diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
index d5b3b9e323a186e920a597242b22ab491e577e2c..6df0316fe12cef1d40a9b83ef1204b0a48990d67 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
@@ -1,6 +1,6 @@
 hdl_lib_name = lofar2_unb2b_adc
 hdl_library_clause_name = lofar2_unb2b_adc_lib
-hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag tech_jesd204b
+hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tr_10GbE diagnostics diag aduh tech_jesd204b
 hdl_lib_uses_sim = 
 hdl_lib_technology = ip_arria10_e1sg
 
@@ -8,12 +8,15 @@ synth_files =
     src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
     src/vhdl/lofar2_unb2b_adc_pkg.vhd
     src/vhdl/mmm_lofar2_unb2b_adc.vhd
+    src/vhdl/node_adc_input_and_timing.vhd
     src/vhdl/lofar2_unb2b_adc.vhd
     
 test_bench_files = 
     tb/vhdl/tb_lofar2_unb2b_adc.vhd
     tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
 
+regression_test_vhdl =
+    tb/vhdl/tb_lofar2_unb2b_adc.vhd
 
 [modelsim_project_file]
 modelsim_copy_files = 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
index c8bc4033c2bf8ff667b777c725560189d68e366d..25835ed8fbfe521845560e0023eabadc1b251454 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
@@ -1,3568 +1,3668 @@
 <?xml version="1.0" ?>
-<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
-  <spirit:vendor>Intel Corporation</spirit:vendor>
-  <spirit:library>qsys_unb2c_minimal_cpu_0</spirit:library>
-  <spirit:name>cpu_0</spirit:name>
-  <spirit:version>18.0</spirit:version>
-  <spirit:busInterfaces>
-    <spirit:busInterface>
-      <spirit:name>clk</spirit:name>
-      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
-      <spirit:slave></spirit:slave>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>clk</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>clk</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>clockRate</spirit:name>
-          <spirit:displayName>Clock rate</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>externallyDriven</spirit:name>
-          <spirit:displayName>Externally driven</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>ptfSchematicName</spirit:name>
-          <spirit:displayName>PTF schematic name</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>custom_instruction_master</spirit:name>
-      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="nios_custom_instruction" spirit:version="18.0"></spirit:busType>
-      <spirit:master></spirit:master>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>readra</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>dummy_ci_port</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>CIName</spirit:name>
-          <spirit:displayName>CIName</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="CIName"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>addressWidth</spirit:name>
-          <spirit:displayName>addressWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="addressWidth">8</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>clockCycle</spirit:name>
-          <spirit:displayName>Clock cycles</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="clockCycle">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>enabled</spirit:name>
-          <spirit:displayName>enabled</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="enabled">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>maxAddressWidth</spirit:name>
-          <spirit:displayName>maxAddressWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="maxAddressWidth">8</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>opcodeExtension</spirit:name>
-          <spirit:displayName>opcodeExtension</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="opcodeExtension">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>sharedCombinationalAndMulticycle</spirit:name>
-          <spirit:displayName>sharedCombinationalAndMulticycle</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="sharedCombinationalAndMulticycle">false</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>data_master</spirit:name>
-      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
-      <spirit:master></spirit:master>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>address</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>d_address</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>byteenable</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>d_byteenable</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>read</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>d_read</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>readdata</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>d_readdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>waitrequest</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>d_waitrequest</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>write</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>d_write</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>writedata</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>d_writedata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>debugaccess</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_mem_slave_debugaccess_to_roms</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>adaptsTo</spirit:name>
-          <spirit:displayName>Adapts to</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="adaptsTo"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>addressGroup</spirit:name>
-          <spirit:displayName>Address group</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="addressGroup">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>addressUnits</spirit:name>
-          <spirit:displayName>Address units</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="addressUnits">SYMBOLS</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>alwaysBurstMaxBurst</spirit:name>
-          <spirit:displayName>Always burst maximum burst</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedClock</spirit:name>
-          <spirit:displayName>Associated clock</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedReset</spirit:name>
-          <spirit:displayName>Associated reset</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>bitsPerSymbol</spirit:name>
-          <spirit:displayName>Bits per symbol</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
-          <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>burstcountUnits</spirit:name>
-          <spirit:displayName>Burstcount units</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>constantBurstBehavior</spirit:name>
-          <spirit:displayName>Constant burst behavior</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dBSBigEndian</spirit:name>
-          <spirit:displayName>dBS big endian</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="dBSBigEndian">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>doStreamReads</spirit:name>
-          <spirit:displayName>Use flow control for read transfers</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="doStreamReads">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>doStreamWrites</spirit:name>
-          <spirit:displayName>Use flow control for write transfers</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="doStreamWrites">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>holdTime</spirit:name>
-          <spirit:displayName>Hold</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>interleaveBursts</spirit:name>
-          <spirit:displayName>Interleave bursts</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isAsynchronous</spirit:name>
-          <spirit:displayName>Is asynchronous</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isAsynchronous">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isBigEndian</spirit:name>
-          <spirit:displayName>Is big endian</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isReadable</spirit:name>
-          <spirit:displayName>Is readable</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isReadable">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isWriteable</spirit:name>
-          <spirit:displayName>Is writeable</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isWriteable">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>linewrapBursts</spirit:name>
-          <spirit:displayName>Linewrap bursts</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>maxAddressWidth</spirit:name>
-          <spirit:displayName>Maximum address width</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="maxAddressWidth">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>maximumPendingReadTransactions</spirit:name>
-          <spirit:displayName>Maximum pending read transactions</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>maximumPendingWriteTransactions</spirit:name>
-          <spirit:displayName>Maximum pending write transactions</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>minimumReadLatency</spirit:name>
-          <spirit:displayName>minimumReadLatency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>minimumResponseLatency</spirit:name>
-          <spirit:displayName>Minimum response latency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>prSafe</spirit:name>
-          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>readLatency</spirit:name>
-          <spirit:displayName>Read latency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>readWaitTime</spirit:name>
-          <spirit:displayName>Read wait</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>registerIncomingSignals</spirit:name>
-          <spirit:displayName>Register incoming signals</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>registerOutgoingSignals</spirit:name>
-          <spirit:displayName>Register outgoing signals</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setupTime</spirit:name>
-          <spirit:displayName>Setup</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>timingUnits</spirit:name>
-          <spirit:displayName>Timing units</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>waitrequestAllowance</spirit:name>
-          <spirit:displayName>Waitrequest allowance</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>writeWaitTime</spirit:name>
-          <spirit:displayName>Write wait</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-      <spirit:vendorExtensions>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>Intel Corporation</ipxact:vendor>
+  <ipxact:library>qsys_lofar2_unb2b_adc_cpu_0</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_cpu_0</ipxact:name>
+  <ipxact:version>19.1</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset_n</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>reset_n</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset_req</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>reset_req</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>clk</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>data_master</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>d_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>byteenable</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>d_byteenable</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>d_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>d_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>waitrequest</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>d_waitrequest</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>d_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>d_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>debugaccess</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_mem_slave_debugaccess_to_roms</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:master></ipxact:master>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="adaptsTo" type="string">
+          <ipxact:name>adaptsTo</ipxact:name>
+          <ipxact:displayName>Adapts to</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>SYMBOLS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>clk</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dBSBigEndian" type="bit">
+          <ipxact:name>dBSBigEndian</ipxact:name>
+          <ipxact:displayName>dBS big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="doStreamReads" type="bit">
+          <ipxact:name>doStreamReads</ipxact:name>
+          <ipxact:displayName>Use flow control for read transfers</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="doStreamWrites" type="bit">
+          <ipxact:name>doStreamWrites</ipxact:name>
+          <ipxact:displayName>Use flow control for write transfers</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isAsynchronous" type="bit">
+          <ipxact:name>isAsynchronous</ipxact:name>
+          <ipxact:displayName>Is asynchronous</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Is big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isReadable" type="bit">
+          <ipxact:name>isReadable</ipxact:name>
+          <ipxact:displayName>Is readable</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isWriteable" type="bit">
+          <ipxact:name>isWriteable</ipxact:name>
+          <ipxact:displayName>Is writeable</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maxAddressWidth" type="int">
+          <ipxact:name>maxAddressWidth</ipxact:name>
+          <ipxact:displayName>Maximum address width</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
         <altera:altera_assignments>
-          <spirit:parameters>
-            <spirit:parameter>
-              <spirit:name>debug.providesServices</spirit:name>
-              <spirit:value spirit:format="string" spirit:id="debug.providesServices">master</spirit:value>
-            </spirit:parameter>
-          </spirit:parameters>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="debug.providesServices" type="string">
+              <ipxact:name>debug.providesServices</ipxact:name>
+              <ipxact:value>master</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
         </altera:altera_assignments>
-      </spirit:vendorExtensions>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>debug_mem_slave</spirit:name>
-      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
-      <spirit:slave></spirit:slave>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>address</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_mem_slave_address</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>byteenable</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_mem_slave_byteenable</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>debugaccess</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_mem_slave_debugaccess</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>read</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_mem_slave_read</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>readdata</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_mem_slave_readdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>waitrequest</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_mem_slave_waitrequest</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>write</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_mem_slave_write</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>writedata</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_mem_slave_writedata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>addressAlignment</spirit:name>
-          <spirit:displayName>Slave addressing</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>addressGroup</spirit:name>
-          <spirit:displayName>Address group</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>addressSpan</spirit:name>
-          <spirit:displayName>Address span</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="addressSpan">2048</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>addressUnits</spirit:name>
-          <spirit:displayName>Address units</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>alwaysBurstMaxBurst</spirit:name>
-          <spirit:displayName>Always burst maximum burst</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedClock</spirit:name>
-          <spirit:displayName>Associated clock</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedReset</spirit:name>
-          <spirit:displayName>Associated reset</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>bitsPerSymbol</spirit:name>
-          <spirit:displayName>Bits per symbol</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>bridgedAddressOffset</spirit:name>
-          <spirit:displayName>Bridged Address Offset</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>bridgesToMaster</spirit:name>
-          <spirit:displayName>Bridges to master</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
-          <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>burstcountUnits</spirit:name>
-          <spirit:displayName>Burstcount units</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>constantBurstBehavior</spirit:name>
-          <spirit:displayName>Constant burst behavior</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>explicitAddressSpan</spirit:name>
-          <spirit:displayName>Explicit address span</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>holdTime</spirit:name>
-          <spirit:displayName>Hold</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>interleaveBursts</spirit:name>
-          <spirit:displayName>Interleave bursts</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isBigEndian</spirit:name>
-          <spirit:displayName>Big endian</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isFlash</spirit:name>
-          <spirit:displayName>Flash memory</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isMemoryDevice</spirit:name>
-          <spirit:displayName>Memory device</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isNonVolatileStorage</spirit:name>
-          <spirit:displayName>Non-volatile storage</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>linewrapBursts</spirit:name>
-          <spirit:displayName>Linewrap bursts</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>maximumPendingReadTransactions</spirit:name>
-          <spirit:displayName>Maximum pending read transactions</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>maximumPendingWriteTransactions</spirit:name>
-          <spirit:displayName>Maximum pending write transactions</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>minimumReadLatency</spirit:name>
-          <spirit:displayName>minimumReadLatency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>minimumResponseLatency</spirit:name>
-          <spirit:displayName>Minimum response latency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>minimumUninterruptedRunLength</spirit:name>
-          <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>prSafe</spirit:name>
-          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>printableDevice</spirit:name>
-          <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>readLatency</spirit:name>
-          <spirit:displayName>Read latency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>readWaitStates</spirit:name>
-          <spirit:displayName>Read wait states</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="readWaitStates">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>readWaitTime</spirit:name>
-          <spirit:displayName>Read wait</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>registerIncomingSignals</spirit:name>
-          <spirit:displayName>Register incoming signals</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>registerOutgoingSignals</spirit:name>
-          <spirit:displayName>Register outgoing signals</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setupTime</spirit:name>
-          <spirit:displayName>Setup</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>timingUnits</spirit:name>
-          <spirit:displayName>Timing units</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>transparentBridge</spirit:name>
-          <spirit:displayName>Transparent bridge</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>waitrequestAllowance</spirit:name>
-          <spirit:displayName>Waitrequest allowance</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>wellBehavedWaitrequest</spirit:name>
-          <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>writeLatency</spirit:name>
-          <spirit:displayName>Write latency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>writeWaitStates</spirit:name>
-          <spirit:displayName>Write wait states</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>writeWaitTime</spirit:name>
-          <spirit:displayName>Write wait</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-      <spirit:vendorExtensions>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>instruction_master</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>i_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>i_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>i_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>waitrequest</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>i_waitrequest</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:master></ipxact:master>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="adaptsTo" type="string">
+          <ipxact:name>adaptsTo</ipxact:name>
+          <ipxact:displayName>Adapts to</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>SYMBOLS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>clk</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dBSBigEndian" type="bit">
+          <ipxact:name>dBSBigEndian</ipxact:name>
+          <ipxact:displayName>dBS big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="doStreamReads" type="bit">
+          <ipxact:name>doStreamReads</ipxact:name>
+          <ipxact:displayName>Use flow control for read transfers</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="doStreamWrites" type="bit">
+          <ipxact:name>doStreamWrites</ipxact:name>
+          <ipxact:displayName>Use flow control for write transfers</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isAsynchronous" type="bit">
+          <ipxact:name>isAsynchronous</ipxact:name>
+          <ipxact:displayName>Is asynchronous</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Is big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isReadable" type="bit">
+          <ipxact:name>isReadable</ipxact:name>
+          <ipxact:displayName>Is readable</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isWriteable" type="bit">
+          <ipxact:name>isWriteable</ipxact:name>
+          <ipxact:displayName>Is writeable</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maxAddressWidth" type="int">
+          <ipxact:name>maxAddressWidth</ipxact:name>
+          <ipxact:displayName>Maximum address width</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>irq</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="interrupt" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="interrupt" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>irq</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>irq</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:master></ipxact:master>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedAddressablePoint" type="string">
+          <ipxact:name>associatedAddressablePoint</ipxact:name>
+          <ipxact:displayName>Associated addressable interface</ipxact:displayName>
+          <ipxact:value>qsys_lofar2_unb2b_adc_cpu_0.data_master</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>clk</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="irqMap" type="string">
+          <ipxact:name>irqMap</ipxact:name>
+          <ipxact:displayName>IRQ Map</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="irqScheme" type="string">
+          <ipxact:name>irqScheme</ipxact:name>
+          <ipxact:displayName>Interrupt scheme</ipxact:displayName>
+          <ipxact:value>INDIVIDUAL_REQUESTS</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>debug_reset_request</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_reset_request</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:master></ipxact:master>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>clk</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedDirectReset" type="string">
+          <ipxact:name>associatedDirectReset</ipxact:name>
+          <ipxact:displayName>Associated direct reset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedResetSinks" type="string">
+          <ipxact:name>associatedResetSinks</ipxact:name>
+          <ipxact:displayName>Associated reset sinks</ipxact:displayName>
+          <ipxact:value>none</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>debug_mem_slave</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_mem_slave_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>byteenable</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_mem_slave_byteenable</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>debugaccess</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_mem_slave_debugaccess</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_mem_slave_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_mem_slave_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>waitrequest</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_mem_slave_waitrequest</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_mem_slave_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>debug_mem_slave_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>2048</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>clk</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
         <altera:altera_assignments>
-          <spirit:parameters>
-            <spirit:parameter>
-              <spirit:name>embeddedsw.configuration.hideDevice</spirit:name>
-              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.hideDevice">1</spirit:value>
-            </spirit:parameter>
-            <spirit:parameter>
-              <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
-              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
-            </spirit:parameter>
-            <spirit:parameter>
-              <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
-              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">1</spirit:value>
-            </spirit:parameter>
-            <spirit:parameter>
-              <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
-              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
-            </spirit:parameter>
-            <spirit:parameter>
-              <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
-              <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
-            </spirit:parameter>
-            <spirit:parameter>
-              <spirit:name>qsys.ui.connect</spirit:name>
-              <spirit:value spirit:format="string" spirit:id="qsys.ui.connect">instruction_master,data_master</spirit:value>
-            </spirit:parameter>
-          </spirit:parameters>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.hideDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.hideDevice</ipxact:name>
+              <ipxact:value>1</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>1</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="qsys.ui.connect" type="string">
+              <ipxact:name>qsys.ui.connect</ipxact:name>
+              <ipxact:value>instruction_master,data_master</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
         </altera:altera_assignments>
-      </spirit:vendorExtensions>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>debug_reset_request</spirit:name>
-      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
-      <spirit:master></spirit:master>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>reset</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>debug_reset_request</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>associatedClock</spirit:name>
-          <spirit:displayName>Associated clock</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedDirectReset</spirit:name>
-          <spirit:displayName>Associated direct reset</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedDirectReset"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedResetSinks</spirit:name>
-          <spirit:displayName>Associated reset sinks</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedResetSinks">none</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>synchronousEdges</spirit:name>
-          <spirit:displayName>Synchronous edges</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>instruction_master</spirit:name>
-      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
-      <spirit:master></spirit:master>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>address</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>i_address</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>read</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>i_read</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>readdata</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>i_readdata</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>waitrequest</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>i_waitrequest</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>adaptsTo</spirit:name>
-          <spirit:displayName>Adapts to</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="adaptsTo"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>addressGroup</spirit:name>
-          <spirit:displayName>Address group</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="addressGroup">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>addressUnits</spirit:name>
-          <spirit:displayName>Address units</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="addressUnits">SYMBOLS</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>alwaysBurstMaxBurst</spirit:name>
-          <spirit:displayName>Always burst maximum burst</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedClock</spirit:name>
-          <spirit:displayName>Associated clock</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedReset</spirit:name>
-          <spirit:displayName>Associated reset</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>bitsPerSymbol</spirit:name>
-          <spirit:displayName>Bits per symbol</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
-          <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>burstcountUnits</spirit:name>
-          <spirit:displayName>Burstcount units</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>constantBurstBehavior</spirit:name>
-          <spirit:displayName>Constant burst behavior</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dBSBigEndian</spirit:name>
-          <spirit:displayName>dBS big endian</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="dBSBigEndian">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>doStreamReads</spirit:name>
-          <spirit:displayName>Use flow control for read transfers</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="doStreamReads">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>doStreamWrites</spirit:name>
-          <spirit:displayName>Use flow control for write transfers</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="doStreamWrites">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>holdTime</spirit:name>
-          <spirit:displayName>Hold</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>interleaveBursts</spirit:name>
-          <spirit:displayName>Interleave bursts</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isAsynchronous</spirit:name>
-          <spirit:displayName>Is asynchronous</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isAsynchronous">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isBigEndian</spirit:name>
-          <spirit:displayName>Is big endian</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isReadable</spirit:name>
-          <spirit:displayName>Is readable</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isReadable">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>isWriteable</spirit:name>
-          <spirit:displayName>Is writeable</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="isWriteable">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>linewrapBursts</spirit:name>
-          <spirit:displayName>Linewrap bursts</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="linewrapBursts">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>maxAddressWidth</spirit:name>
-          <spirit:displayName>Maximum address width</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="maxAddressWidth">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>maximumPendingReadTransactions</spirit:name>
-          <spirit:displayName>Maximum pending read transactions</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>maximumPendingWriteTransactions</spirit:name>
-          <spirit:displayName>Maximum pending write transactions</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>minimumReadLatency</spirit:name>
-          <spirit:displayName>minimumReadLatency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>minimumResponseLatency</spirit:name>
-          <spirit:displayName>Minimum response latency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>prSafe</spirit:name>
-          <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>readLatency</spirit:name>
-          <spirit:displayName>Read latency</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="readLatency">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>readWaitTime</spirit:name>
-          <spirit:displayName>Read wait</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="readWaitTime">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>registerIncomingSignals</spirit:name>
-          <spirit:displayName>Register incoming signals</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>registerOutgoingSignals</spirit:name>
-          <spirit:displayName>Register outgoing signals</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setupTime</spirit:name>
-          <spirit:displayName>Setup</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>timingUnits</spirit:name>
-          <spirit:displayName>Timing units</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>waitrequestAllowance</spirit:name>
-          <spirit:displayName>Waitrequest allowance</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>writeWaitTime</spirit:name>
-          <spirit:displayName>Write wait</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>irq</spirit:name>
-      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="interrupt" spirit:version="18.0"></spirit:busType>
-      <spirit:master></spirit:master>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>irq</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>irq</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>associatedAddressablePoint</spirit:name>
-          <spirit:displayName>Associated addressable interface</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedAddressablePoint">qsys_unb2c_minimal_cpu_0.data_master</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedClock</spirit:name>
-          <spirit:displayName>Associated clock</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>associatedReset</spirit:name>
-          <spirit:displayName>Associated reset</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedReset">reset</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>irqMap</spirit:name>
-          <spirit:displayName>IRQ Map</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="irqMap"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>irqScheme</spirit:name>
-          <spirit:displayName>Interrupt scheme</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="irqScheme">INDIVIDUAL_REQUESTS</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-    <spirit:busInterface>
-      <spirit:name>reset</spirit:name>
-      <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
-      <spirit:slave></spirit:slave>
-      <spirit:portMaps>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>reset_n</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>reset_n</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-        <spirit:portMap>
-          <spirit:logicalPort>
-            <spirit:name>reset_req</spirit:name>
-          </spirit:logicalPort>
-          <spirit:physicalPort>
-            <spirit:name>reset_req</spirit:name>
-          </spirit:physicalPort>
-        </spirit:portMap>
-      </spirit:portMaps>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>associatedClock</spirit:name>
-          <spirit:displayName>Associated clock</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="associatedClock">clk</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>synchronousEdges</spirit:name>
-          <spirit:displayName>Synchronous edges</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
-    </spirit:busInterface>
-  </spirit:busInterfaces>
-  <spirit:model>
-    <spirit:views>
-      <spirit:view>
-        <spirit:name>QUARTUS_SYNTH</spirit:name>
-        <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
-        <spirit:modelName>altera_nios2_gen2</spirit:modelName>
-        <spirit:fileSetRef>
-          <spirit:localName>QUARTUS_SYNTH</spirit:localName>
-        </spirit:fileSetRef>
-      </spirit:view>
-    </spirit:views>
-    <spirit:ports>
-      <spirit:port>
-        <spirit:name>clk</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>dummy_ci_port</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>d_address</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>20</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>d_byteenable</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>3</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>d_read</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>d_readdata</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>31</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>d_waitrequest</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>d_write</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>d_writedata</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>31</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_mem_slave_debugaccess_to_roms</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_mem_slave_address</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>8</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_mem_slave_byteenable</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>3</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_mem_slave_debugaccess</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_mem_slave_read</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_mem_slave_readdata</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>31</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_mem_slave_waitrequest</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_mem_slave_write</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_mem_slave_writedata</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>31</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>debug_reset_request</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>i_address</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>17</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>i_read</spirit:name>
-        <spirit:wire>
-          <spirit:direction>out</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>i_readdata</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>31</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>i_waitrequest</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>irq</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:vector>
-            <spirit:left>0</spirit:left>
-            <spirit:right>31</spirit:right>
-          </spirit:vector>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>reset_n</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-      <spirit:port>
-        <spirit:name>reset_req</spirit:name>
-        <spirit:wire>
-          <spirit:direction>in</spirit:direction>
-          <spirit:wireTypeDefs>
-            <spirit:wireTypeDef>
-              <spirit:typeName>STD_LOGIC</spirit:typeName>
-              <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
-            </spirit:wireTypeDef>
-          </spirit:wireTypeDefs>
-        </spirit:wire>
-      </spirit:port>
-    </spirit:ports>
-  </spirit:model>
-  <spirit:vendorExtensions>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>custom_instruction_master</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="nios_custom_instruction" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="nios_custom_instruction" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readra</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>dummy_ci_port</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:master></ipxact:master>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="CIName" type="string">
+          <ipxact:name>CIName</ipxact:name>
+          <ipxact:displayName>CIName</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressWidth" type="int">
+          <ipxact:name>addressWidth</ipxact:name>
+          <ipxact:displayName>addressWidth</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="clockCycle" type="int">
+          <ipxact:name>clockCycle</ipxact:name>
+          <ipxact:displayName>Clock cycles</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="enabled" type="bit">
+          <ipxact:name>enabled</ipxact:name>
+          <ipxact:displayName>enabled</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maxAddressWidth" type="int">
+          <ipxact:name>maxAddressWidth</ipxact:name>
+          <ipxact:displayName>maxAddressWidth</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="opcodeExtension" type="int">
+          <ipxact:name>opcodeExtension</ipxact:name>
+          <ipxact:displayName>opcodeExtension</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="sharedCombinationalAndMulticycle" type="bit">
+          <ipxact:name>sharedCombinationalAndMulticycle</ipxact:name>
+          <ipxact:displayName>sharedCombinationalAndMulticycle</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>altera_nios2_gen2</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>reset_n</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>reset_req</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>d_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>19</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>d_byteenable</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>3</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>d_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>d_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>d_waitrequest</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>d_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>d_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_mem_slave_debugaccess_to_roms</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>i_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>17</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>i_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>i_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>i_waitrequest</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>irq</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_reset_request</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_mem_slave_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>8</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_mem_slave_byteenable</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>3</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_mem_slave_debugaccess</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_mem_slave_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_mem_slave_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_mem_slave_waitrequest</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_mem_slave_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>debug_mem_slave_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>dummy_ci_port</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
     <altera:entity_info>
-      <spirit:vendor>Intel Corporation</spirit:vendor>
-      <spirit:library>qsys_unb2c_minimal_cpu_0</spirit:library>
-      <spirit:name>altera_nios2_gen2</spirit:name>
-      <spirit:version>18.0</spirit:version>
+      <ipxact:vendor>Intel Corporation</ipxact:vendor>
+      <ipxact:library>qsys_lofar2_unb2b_adc_cpu_0</ipxact:library>
+      <ipxact:name>altera_nios2_gen2</ipxact:name>
+      <ipxact:version>19.1</ipxact:version>
     </altera:entity_info>
     <altera:altera_module_parameters>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>tmr_enabled</spirit:name>
-          <spirit:displayName>Nios II Triple Mode Redundancy</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="tmr_enabled">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_disable_tmr_inj</spirit:name>
-          <spirit:displayName>Disabled TMR Error Injection Port</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_disable_tmr_inj">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_showUnpublishedSettings</spirit:name>
-          <spirit:displayName>Show Unpublished Settings</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_showUnpublishedSettings">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_showInternalSettings</spirit:name>
-          <spirit:displayName>Show Internal Verification Settings</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_showInternalSettings">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_preciseIllegalMemAccessException</spirit:name>
-          <spirit:displayName>Misaligned memory access</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_preciseIllegalMemAccessException">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_exportPCB</spirit:name>
-          <spirit:displayName>setting_exportPCB</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_exportPCB">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_exportdebuginfo</spirit:name>
-          <spirit:displayName>Export Instruction Execution States</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_exportdebuginfo">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_clearXBitsLDNonBypass</spirit:name>
-          <spirit:displayName>Clear X data bits</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_clearXBitsLDNonBypass">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_bigEndian</spirit:name>
-          <spirit:displayName>setting_bigEndian</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_bigEndian">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_export_large_RAMs</spirit:name>
-          <spirit:displayName>Export Large RAMs</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_export_large_RAMs">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_asic_enabled</spirit:name>
-          <spirit:displayName>ASIC enabled</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_asic_enabled">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>register_file_por</spirit:name>
-          <spirit:displayName>Register File POR</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="register_file_por">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_asic_synopsys_translate_on_off</spirit:name>
-          <spirit:displayName>ASIC Synopsys translate</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_asic_synopsys_translate_on_off">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_asic_third_party_synthesis</spirit:name>
-          <spirit:displayName>ASIC third party synthesis</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_asic_third_party_synthesis">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_asic_add_scan_mode_input</spirit:name>
-          <spirit:displayName>ASIC add scan mode input</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_asic_add_scan_mode_input">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_oci_version</spirit:name>
-          <spirit:displayName>Nios II OCI Version</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="setting_oci_version">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_fast_register_read</spirit:name>
-          <spirit:displayName>Fast Register Read</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_fast_register_read">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_exportHostDebugPort</spirit:name>
-          <spirit:displayName>Export Debug Host Slave</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_exportHostDebugPort">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_oci_export_jtag_signals</spirit:name>
-          <spirit:displayName>Export JTAG signals</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_oci_export_jtag_signals">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_avalonDebugPortPresent</spirit:name>
-          <spirit:displayName>Avalon Debug Port Present</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_avalonDebugPortPresent">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_alwaysEncrypt</spirit:name>
-          <spirit:displayName>Always encrypt</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_alwaysEncrypt">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>io_regionbase</spirit:name>
-          <spirit:displayName>Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="io_regionbase">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>io_regionsize</spirit:name>
-          <spirit:displayName>Size</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="io_regionsize">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_support31bitdcachebypass</spirit:name>
-          <spirit:displayName>Use most-significant address bit in processor to bypass data cache</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_support31bitdcachebypass">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_activateTrace</spirit:name>
-          <spirit:displayName>Generate trace file during RTL simulation</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_activateTrace">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_allow_break_inst</spirit:name>
-          <spirit:displayName>Allow Break instructions</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_allow_break_inst">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_activateTestEndChecker</spirit:name>
-          <spirit:displayName>Activate test end checker</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_activateTestEndChecker">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_ecc_sim_test_ports</spirit:name>
-          <spirit:displayName>Enable ECC simulation test ports</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_ecc_sim_test_ports">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_disableocitrace</spirit:name>
-          <spirit:displayName>Disable comptr generation</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_disableocitrace">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_activateMonitors</spirit:name>
-          <spirit:displayName>Activate monitors</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_activateMonitors">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_HDLSimCachesCleared</spirit:name>
-          <spirit:displayName>HDL simulation caches cleared</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_HDLSimCachesCleared">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_HBreakTest</spirit:name>
-          <spirit:displayName>Add HBreak Request port</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_HBreakTest">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_breakslaveoveride</spirit:name>
-          <spirit:displayName>Manually assign break slave</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_breakslaveoveride">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mpu_useLimit</spirit:name>
-          <spirit:displayName>Use Limit for region range</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="mpu_useLimit">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mpu_enabled</spirit:name>
-          <spirit:displayName>Include MPU</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="mpu_enabled">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_enabled</spirit:name>
-          <spirit:displayName>Include MMU</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="mmu_enabled">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_autoAssignTlbPtrSz</spirit:name>
-          <spirit:displayName>Optimize TLB entries base on device family</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="mmu_autoAssignTlbPtrSz">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>cpuReset</spirit:name>
-          <spirit:displayName>Include cpu_resetrequest and cpu_resettaken signals</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="cpuReset">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>resetrequest_enabled</spirit:name>
-          <spirit:displayName>Include reset_req signal for OCI RAM and Multi-Cycle Custom Instructions</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="resetrequest_enabled">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_removeRAMinit</spirit:name>
-          <spirit:displayName>Remove RAM Initialization</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_removeRAMinit">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_tmr_output_disable</spirit:name>
-          <spirit:displayName>Create a signal to disable TMR outputs</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_tmr_output_disable">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_shadowRegisterSets</spirit:name>
-          <spirit:displayName>Number of shadow register sets (0-63)</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="setting_shadowRegisterSets">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mpu_numOfInstRegion</spirit:name>
-          <spirit:displayName>        Number of instruction regions</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mpu_numOfInstRegion">8</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mpu_numOfDataRegion</spirit:name>
-          <spirit:displayName>        Number of data regions</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mpu_numOfDataRegion">8</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_TLBMissExcOffset</spirit:name>
-          <spirit:displayName>Fast TLB Miss Exception vector offset</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mmu_TLBMissExcOffset">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>resetOffset</spirit:name>
-          <spirit:displayName>Reset vector offset</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="resetOffset">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>exceptionOffset</spirit:name>
-          <spirit:displayName>Exception vector offset</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="exceptionOffset">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>cpuID</spirit:name>
-          <spirit:displayName>CPUID control register value</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="cpuID">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>breakOffset</spirit:name>
-          <spirit:displayName>Break vector offset</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="breakOffset">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>userDefinedSettings</spirit:name>
-          <spirit:displayName>User Defined Settings</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="userDefinedSettings"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tracefilename</spirit:name>
-          <spirit:displayName>Trace File Name</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tracefilename"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>resetSlave</spirit:name>
-          <spirit:displayName>Reset vector memory</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="resetSlave">onchip_memory2_0.s1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_TLBMissExcSlave</spirit:name>
-          <spirit:displayName>Fast TLB Miss Exception vector memory</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="mmu_TLBMissExcSlave">None</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>exceptionSlave</spirit:name>
-          <spirit:displayName>Exception vector memory</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="exceptionSlave">onchip_memory2_0.s1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>breakSlave</spirit:name>
-          <spirit:displayName>Break vector memory</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="breakSlave">None</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_interruptControllerType</spirit:name>
-          <spirit:displayName>Interrupt controller</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="setting_interruptControllerType">Internal</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_branchpredictiontype</spirit:name>
-          <spirit:displayName>Branch prediction type</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="setting_branchpredictiontype">Dynamic</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_bhtPtrSz</spirit:name>
-          <spirit:displayName>        Number of entries (2-bits wide)</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="setting_bhtPtrSz">8</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>cpuArchRev</spirit:name>
-          <spirit:displayName>Architecture Revision</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="cpuArchRev">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>stratix_dspblock_shift_mul</spirit:name>
-          <spirit:displayName>stratix_dspblock_shift_mul</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="stratix_dspblock_shift_mul">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>shifterType</spirit:name>
-          <spirit:displayName>shifterType</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="shifterType">medium_le_shift</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>multiplierType</spirit:name>
-          <spirit:displayName>multiplierType</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="multiplierType">no_mul</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mul_shift_choice</spirit:name>
-          <spirit:displayName>Multiply/Shift/Rotate Hardware</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mul_shift_choice">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mul_32_impl</spirit:name>
-          <spirit:displayName>Multiply Implementation</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mul_32_impl">2</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mul_64_impl</spirit:name>
-          <spirit:displayName>Multiply Extended Implementation</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mul_64_impl">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>shift_rot_impl</spirit:name>
-          <spirit:displayName>Shift/Rotate Implementation</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="shift_rot_impl">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dividerType</spirit:name>
-          <spirit:displayName>Divide Hardware</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="dividerType">no_div</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mpu_minInstRegionSize</spirit:name>
-          <spirit:displayName>        Minimum instruction region size</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mpu_minInstRegionSize">12</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mpu_minDataRegionSize</spirit:name>
-          <spirit:displayName>        Minimum data region size</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mpu_minDataRegionSize">12</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_uitlbNumEntries</spirit:name>
-          <spirit:displayName>        Micro ITLB entries</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mmu_uitlbNumEntries">4</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_udtlbNumEntries</spirit:name>
-          <spirit:displayName>        Micro DTLB entries</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mmu_udtlbNumEntries">6</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_tlbPtrSz</spirit:name>
-          <spirit:displayName>        TLB entries</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mmu_tlbPtrSz">7</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_tlbNumWays</spirit:name>
-          <spirit:displayName>        TLB Set-Associativity</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mmu_tlbNumWays">16</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_processIDNumBits</spirit:name>
-          <spirit:displayName>        Process ID (PID) bits</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mmu_processIDNumBits">8</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>impl</spirit:name>
-          <spirit:displayName>Nios II Core</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="impl">Tiny</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>icache_size</spirit:name>
-          <spirit:displayName>Size</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="icache_size">4096</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>fa_cache_line</spirit:name>
-          <spirit:displayName>Number of Cache Lines</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="fa_cache_line">2</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>fa_cache_linesize</spirit:name>
-          <spirit:displayName>Line Size</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="fa_cache_linesize">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>icache_tagramBlockType</spirit:name>
-          <spirit:displayName>Tag RAM block type</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="icache_tagramBlockType">Automatic</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>icache_ramBlockType</spirit:name>
-          <spirit:displayName>Data RAM block type</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="icache_ramBlockType">Automatic</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>icache_numTCIM</spirit:name>
-          <spirit:displayName>Number of tightly coupled instruction master ports</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="icache_numTCIM">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>icache_burstType</spirit:name>
-          <spirit:displayName>Add burstcount signal to instruction_master</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="icache_burstType">None</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dcache_bursts</spirit:name>
-          <spirit:displayName>Add burstcount signal to data_master</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="dcache_bursts">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dcache_victim_buf_impl</spirit:name>
-          <spirit:displayName>Victim buffer implementation</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="dcache_victim_buf_impl">ram</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dcache_size</spirit:name>
-          <spirit:displayName>Size</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="dcache_size">2048</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dcache_tagramBlockType</spirit:name>
-          <spirit:displayName>Tag RAM block type</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="dcache_tagramBlockType">Automatic</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dcache_ramBlockType</spirit:name>
-          <spirit:displayName>Data RAM block type</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="dcache_ramBlockType">Automatic</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dcache_numTCDM</spirit:name>
-          <spirit:displayName>Number of tightly coupled data master ports</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="dcache_numTCDM">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_exportvectors</spirit:name>
-          <spirit:displayName>Export Vectors</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_exportvectors">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_usedesignware</spirit:name>
-          <spirit:displayName>Use Designware Components</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_usedesignware">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_ecc_present</spirit:name>
-          <spirit:displayName>ECC Present</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_ecc_present">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_ic_ecc_present</spirit:name>
-          <spirit:displayName>Instruction Cache ECC Present</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_ic_ecc_present">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_rf_ecc_present</spirit:name>
-          <spirit:displayName>Register File ECC Present</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_rf_ecc_present">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_mmu_ecc_present</spirit:name>
-          <spirit:displayName>MMU ECC Present</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_mmu_ecc_present">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_dc_ecc_present</spirit:name>
-          <spirit:displayName>Data Cache ECC Present</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_dc_ecc_present">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_itcm_ecc_present</spirit:name>
-          <spirit:displayName>Instruction TCM ECC Present</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_itcm_ecc_present">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_dtcm_ecc_present</spirit:name>
-          <spirit:displayName>Data TCM ECC Present</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_dtcm_ecc_present">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>regfile_ramBlockType</spirit:name>
-          <spirit:displayName>RAM block type</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="regfile_ramBlockType">Automatic</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>ocimem_ramBlockType</spirit:name>
-          <spirit:displayName>RAM block type</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="ocimem_ramBlockType">Automatic</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>ocimem_ramInit</spirit:name>
-          <spirit:displayName>Initialized OCI RAM</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="ocimem_ramInit">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_ramBlockType</spirit:name>
-          <spirit:displayName>        MMU RAM block type</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="mmu_ramBlockType">Automatic</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>bht_ramBlockType</spirit:name>
-          <spirit:displayName>BHT RAM Block Type</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="bht_ramBlockType">Automatic</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>cdx_enabled</spirit:name>
-          <spirit:displayName>CDX (Code Density eXtension) Instructions</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="cdx_enabled">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mpx_enabled</spirit:name>
-          <spirit:displayName>mpx_enabled</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="mpx_enabled">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_enabled</spirit:name>
-          <spirit:displayName>Include JTAG Debug</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="debug_enabled">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_triggerArming</spirit:name>
-          <spirit:displayName>Trigger Arming</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="debug_triggerArming">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_debugReqSignals</spirit:name>
-          <spirit:displayName>Include debugreq and debugack Signals</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="debug_debugReqSignals">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_assignJtagInstanceID</spirit:name>
-          <spirit:displayName>Assign JTAG Instance ID for debug core manually</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="debug_assignJtagInstanceID">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_jtagInstanceID</spirit:name>
-          <spirit:displayName>JTAG Instance ID value</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="debug_jtagInstanceID">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_OCIOnchipTrace</spirit:name>
-          <spirit:displayName>Onchip Trace Frame Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="debug_OCIOnchipTrace">_128</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_hwbreakpoint</spirit:name>
-          <spirit:displayName>Hardware Breakpoints</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="debug_hwbreakpoint">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_datatrigger</spirit:name>
-          <spirit:displayName>Data Triggers</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="debug_datatrigger">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_traceType</spirit:name>
-          <spirit:displayName>Trace Types</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="debug_traceType">none</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_traceStorage</spirit:name>
-          <spirit:displayName>Trace Storage</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="debug_traceStorage">onchip_trace</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>master_addr_map</spirit:name>
-          <spirit:displayName>Manually Set Master Base Address and Size</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="master_addr_map">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>instruction_master_paddr_base</spirit:name>
-          <spirit:displayName>Instruction Master Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="instruction_master_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>instruction_master_paddr_size</spirit:name>
-          <spirit:displayName>Instruction Master Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="instruction_master_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>flash_instruction_master_paddr_base</spirit:name>
-          <spirit:displayName>Flash Instruction Master Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="flash_instruction_master_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>flash_instruction_master_paddr_size</spirit:name>
-          <spirit:displayName>Flash Instruction Master Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="flash_instruction_master_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>data_master_paddr_base</spirit:name>
-          <spirit:displayName>Data Master Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="data_master_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>data_master_paddr_size</spirit:name>
-          <spirit:displayName>Data Master Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="data_master_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_instruction_master_0_paddr_base</spirit:name>
-          <spirit:displayName>Tightly coupled Instruction Master 0 Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightly_coupled_instruction_master_0_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_instruction_master_0_paddr_size</spirit:name>
-          <spirit:displayName>Tightly coupled Instruction Master 0 Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightly_coupled_instruction_master_0_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_instruction_master_1_paddr_base</spirit:name>
-          <spirit:displayName>Tightly coupled Instruction Master 1 Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightly_coupled_instruction_master_1_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_instruction_master_1_paddr_size</spirit:name>
-          <spirit:displayName>Tightly coupled Instruction Master 1 Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightly_coupled_instruction_master_1_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_instruction_master_2_paddr_base</spirit:name>
-          <spirit:displayName>Tightly coupled Instruction Master 2 Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightly_coupled_instruction_master_2_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_instruction_master_2_paddr_size</spirit:name>
-          <spirit:displayName>Tightly coupled Instruction Master 2 Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightly_coupled_instruction_master_2_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_instruction_master_3_paddr_base</spirit:name>
-          <spirit:displayName>Tightly coupled Instruction Master 3 Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightly_coupled_instruction_master_3_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_instruction_master_3_paddr_size</spirit:name>
-          <spirit:displayName>Tightly coupled Instruction Master 3 Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightly_coupled_instruction_master_3_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_data_master_0_paddr_base</spirit:name>
-          <spirit:displayName>Tightly coupled Data Master 0 Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightly_coupled_data_master_0_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_data_master_0_paddr_size</spirit:name>
-          <spirit:displayName>Tightly coupled Data Master 0 Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightly_coupled_data_master_0_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_data_master_1_paddr_base</spirit:name>
-          <spirit:displayName>Tightly coupled Data Master 1 Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightly_coupled_data_master_1_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_data_master_1_paddr_size</spirit:name>
-          <spirit:displayName>Tightly coupled Data Master 1 Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightly_coupled_data_master_1_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_data_master_2_paddr_base</spirit:name>
-          <spirit:displayName>Tightly coupled Data Master 2 Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightly_coupled_data_master_2_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_data_master_2_paddr_size</spirit:name>
-          <spirit:displayName>Tightly coupled Data Master 2 Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightly_coupled_data_master_2_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_data_master_3_paddr_base</spirit:name>
-          <spirit:displayName>Tightly coupled Data Master 3 Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightly_coupled_data_master_3_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightly_coupled_data_master_3_paddr_size</spirit:name>
-          <spirit:displayName>Tightly coupled Data Master 3 Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightly_coupled_data_master_3_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>instruction_master_high_performance_paddr_base</spirit:name>
-          <spirit:displayName>Instruction Master High Performance Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="instruction_master_high_performance_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>instruction_master_high_performance_paddr_size</spirit:name>
-          <spirit:displayName>Instruction Master High Performance Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="instruction_master_high_performance_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>data_master_high_performance_paddr_base</spirit:name>
-          <spirit:displayName>Data Master High Performance Base Address</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="data_master_high_performance_paddr_base">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>data_master_high_performance_paddr_size</spirit:name>
-          <spirit:displayName>Data Master High Performance Size</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="data_master_high_performance_paddr_size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>resetAbsoluteAddr</spirit:name>
-          <spirit:displayName>Reset vector</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="resetAbsoluteAddr">131072</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>exceptionAbsoluteAddr</spirit:name>
-          <spirit:displayName>Exception vector</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="exceptionAbsoluteAddr">131104</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>breakAbsoluteAddr</spirit:name>
-          <spirit:displayName>Break vector</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="breakAbsoluteAddr">14368</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>mmu_TLBMissExcAbsAddr</spirit:name>
-          <spirit:displayName>Fast TLB Miss Exception vector</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="mmu_TLBMissExcAbsAddr">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dcache_bursts_derived</spirit:name>
-          <spirit:displayName>dcache_bursts_derived</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="dcache_bursts_derived">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dcache_size_derived</spirit:name>
-          <spirit:displayName>dcache_size_derived</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="dcache_size_derived">2048</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>breakSlave_derived</spirit:name>
-          <spirit:displayName>breakSlave_derived</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="breakSlave_derived">cpu_0.debug_mem_slave</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dcache_lineSize_derived</spirit:name>
-          <spirit:displayName>dcache_lineSize_derived</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="dcache_lineSize_derived">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_ioregionBypassDCache</spirit:name>
-          <spirit:displayName>setting_ioregionBypassDCache</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_ioregionBypassDCache">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>setting_bit31BypassDCache</spirit:name>
-          <spirit:displayName>setting_bit31BypassDCache</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="setting_bit31BypassDCache">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>translate_on</spirit:name>
-          <spirit:displayName>translate_on</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="translate_on"> "synthesis translate_on"  </spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>translate_off</spirit:name>
-          <spirit:displayName>translate_off</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="translate_off"> "synthesis translate_off" </spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_onchiptrace</spirit:name>
-          <spirit:displayName>debug_onchiptrace</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="debug_onchiptrace">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_offchiptrace</spirit:name>
-          <spirit:displayName>debug_offchiptrace</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="debug_offchiptrace">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_insttrace</spirit:name>
-          <spirit:displayName>debug_insttrace</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="debug_insttrace">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>debug_datatrace</spirit:name>
-          <spirit:displayName>debug_datatrace</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="debug_datatrace">false</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>instAddrWidth</spirit:name>
-          <spirit:displayName>instAddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="instAddrWidth">18</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>faAddrWidth</spirit:name>
-          <spirit:displayName>faAddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="faAddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dataAddrWidth</spirit:name>
-          <spirit:displayName>dataAddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="dataAddrWidth">21</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledDataMaster0AddrWidth</spirit:name>
-          <spirit:displayName>tightlyCoupledDataMaster0AddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightlyCoupledDataMaster0AddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledDataMaster1AddrWidth</spirit:name>
-          <spirit:displayName>tightlyCoupledDataMaster1AddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightlyCoupledDataMaster1AddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledDataMaster2AddrWidth</spirit:name>
-          <spirit:displayName>tightlyCoupledDataMaster2AddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightlyCoupledDataMaster2AddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledDataMaster3AddrWidth</spirit:name>
-          <spirit:displayName>tightlyCoupledDataMaster3AddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightlyCoupledDataMaster3AddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledInstructionMaster0AddrWidth</spirit:name>
-          <spirit:displayName>tightlyCoupledInstructionMaster0AddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightlyCoupledInstructionMaster0AddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledInstructionMaster1AddrWidth</spirit:name>
-          <spirit:displayName>tightlyCoupledInstructionMaster1AddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightlyCoupledInstructionMaster1AddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledInstructionMaster2AddrWidth</spirit:name>
-          <spirit:displayName>tightlyCoupledInstructionMaster2AddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightlyCoupledInstructionMaster2AddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledInstructionMaster3AddrWidth</spirit:name>
-          <spirit:displayName>tightlyCoupledInstructionMaster3AddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="tightlyCoupledInstructionMaster3AddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dataMasterHighPerformanceAddrWidth</spirit:name>
-          <spirit:displayName>dataMasterHighPerformanceAddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="dataMasterHighPerformanceAddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>instructionMasterHighPerformanceAddrWidth</spirit:name>
-          <spirit:displayName>instructionMasterHighPerformanceAddrWidth</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="instructionMasterHighPerformanceAddrWidth">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>instSlaveMapParam</spirit:name>
-          <spirit:displayName>instSlaveMapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>faSlaveMapParam</spirit:name>
-          <spirit:displayName>faSlaveMapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="faSlaveMapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dataSlaveMapParam</spirit:name>
-          <spirit:displayName>dataSlaveMapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='jesd204b.mem' start='0x40000' end='0x80000' datawidth='32' /><slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0x100000' datawidth='32' /><slave name='reg_diag_data_buffer_jesd.mem' start='0x100000' end='0x140000' datawidth='32' /></address-map>]]></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
-          <spirit:displayName>tightlyCoupledDataMaster0MapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightlyCoupledDataMaster0MapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledDataMaster1MapParam</spirit:name>
-          <spirit:displayName>tightlyCoupledDataMaster1MapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightlyCoupledDataMaster1MapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledDataMaster2MapParam</spirit:name>
-          <spirit:displayName>tightlyCoupledDataMaster2MapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightlyCoupledDataMaster2MapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledDataMaster3MapParam</spirit:name>
-          <spirit:displayName>tightlyCoupledDataMaster3MapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightlyCoupledDataMaster3MapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledInstructionMaster0MapParam</spirit:name>
-          <spirit:displayName>tightlyCoupledInstructionMaster0MapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightlyCoupledInstructionMaster0MapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledInstructionMaster1MapParam</spirit:name>
-          <spirit:displayName>tightlyCoupledInstructionMaster1MapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightlyCoupledInstructionMaster1MapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledInstructionMaster2MapParam</spirit:name>
-          <spirit:displayName>tightlyCoupledInstructionMaster2MapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightlyCoupledInstructionMaster2MapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>tightlyCoupledInstructionMaster3MapParam</spirit:name>
-          <spirit:displayName>tightlyCoupledInstructionMaster3MapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="tightlyCoupledInstructionMaster3MapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>dataMasterHighPerformanceMapParam</spirit:name>
-          <spirit:displayName>dataMasterHighPerformanceMapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="dataMasterHighPerformanceMapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>instructionMasterHighPerformanceMapParam</spirit:name>
-          <spirit:displayName>instructionMasterHighPerformanceMapParam</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="instructionMasterHighPerformanceMapParam"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>clockFrequency</spirit:name>
-          <spirit:displayName>clockFrequency</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="clockFrequency">100000000</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>deviceFamilyName</spirit:name>
-          <spirit:displayName>deviceFamilyName</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="deviceFamilyName">Arria 10</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>internalIrqMaskSystemInfo</spirit:name>
-          <spirit:displayName>internalIrqMaskSystemInfo</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="internalIrqMaskSystemInfo">7</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>customInstSlavesSystemInfo</spirit:name>
-          <spirit:displayName>customInstSlavesSystemInfo</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>customInstSlavesSystemInfo_nios_a</spirit:name>
-          <spirit:displayName>customInstSlavesSystemInfo_nios_a</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo_nios_a"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>customInstSlavesSystemInfo_nios_b</spirit:name>
-          <spirit:displayName>customInstSlavesSystemInfo_nios_b</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo_nios_b"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>customInstSlavesSystemInfo_nios_c</spirit:name>
-          <spirit:displayName>customInstSlavesSystemInfo_nios_c</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="customInstSlavesSystemInfo_nios_c"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>deviceFeaturesSystemInfo</spirit:name>
-          <spirit:displayName>deviceFeaturesSystemInfo</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="deviceFeaturesSystemInfo">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DISABLE_CRC_ERROR_DETECTION 0 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MISSING_PAD_INFO 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MAC_NEGATE_SUPPORT_DISABLED 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 PINTABLE_OPTIONAL 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_DSP_FROM_PREVIOUS_FAMILY 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_RAM_FROM_PREVIOUS_FAMILY 0 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WORKS_AROUND_MISSING_RED_FLAGS_IN_DSPF_ROUTING_MODELS 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>AUTO_DEVICE</spirit:name>
-          <spirit:displayName>Auto DEVICE</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE">10AX115U2F45E1SG</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>AUTO_DEVICE_SPEEDGRADE</spirit:name>
-          <spirit:displayName>Auto DEVICE_SPEEDGRADE</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE_SPEEDGRADE">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>AUTO_CLK_CLOCK_DOMAIN</spirit:name>
-          <spirit:displayName>Auto CLOCK_DOMAIN</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="AUTO_CLK_CLOCK_DOMAIN">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>AUTO_CLK_RESET_DOMAIN</spirit:name>
-          <spirit:displayName>Auto RESET_DOMAIN</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="AUTO_CLK_RESET_DOMAIN">1</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="tmr_enabled" type="bit">
+          <ipxact:name>tmr_enabled</ipxact:name>
+          <ipxact:displayName>Nios II Triple Mode Redundancy</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_disable_tmr_inj" type="bit">
+          <ipxact:name>setting_disable_tmr_inj</ipxact:name>
+          <ipxact:displayName>Disabled TMR Error Injection Port</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_showUnpublishedSettings" type="bit">
+          <ipxact:name>setting_showUnpublishedSettings</ipxact:name>
+          <ipxact:displayName>Show Unpublished Settings</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_showInternalSettings" type="bit">
+          <ipxact:name>setting_showInternalSettings</ipxact:name>
+          <ipxact:displayName>Show Internal Verification Settings</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_preciseIllegalMemAccessException" type="bit">
+          <ipxact:name>setting_preciseIllegalMemAccessException</ipxact:name>
+          <ipxact:displayName>Misaligned memory access</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_exportPCB" type="bit">
+          <ipxact:name>setting_exportPCB</ipxact:name>
+          <ipxact:displayName>setting_exportPCB</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_exportdebuginfo" type="bit">
+          <ipxact:name>setting_exportdebuginfo</ipxact:name>
+          <ipxact:displayName>Export Instruction Execution States</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_clearXBitsLDNonBypass" type="bit">
+          <ipxact:name>setting_clearXBitsLDNonBypass</ipxact:name>
+          <ipxact:displayName>Clear X data bits</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_bigEndian" type="bit">
+          <ipxact:name>setting_bigEndian</ipxact:name>
+          <ipxact:displayName>setting_bigEndian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_export_large_RAMs" type="bit">
+          <ipxact:name>setting_export_large_RAMs</ipxact:name>
+          <ipxact:displayName>Export Large RAMs</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_asic_enabled" type="bit">
+          <ipxact:name>setting_asic_enabled</ipxact:name>
+          <ipxact:displayName>ASIC enabled</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="register_file_por" type="bit">
+          <ipxact:name>register_file_por</ipxact:name>
+          <ipxact:displayName>Register File POR</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_asic_synopsys_translate_on_off" type="bit">
+          <ipxact:name>setting_asic_synopsys_translate_on_off</ipxact:name>
+          <ipxact:displayName>ASIC Synopsys translate</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_asic_third_party_synthesis" type="bit">
+          <ipxact:name>setting_asic_third_party_synthesis</ipxact:name>
+          <ipxact:displayName>ASIC third party synthesis</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_asic_add_scan_mode_input" type="bit">
+          <ipxact:name>setting_asic_add_scan_mode_input</ipxact:name>
+          <ipxact:displayName>ASIC add scan mode input</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_oci_version" type="int">
+          <ipxact:name>setting_oci_version</ipxact:name>
+          <ipxact:displayName>Nios II OCI Version</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_fast_register_read" type="bit">
+          <ipxact:name>setting_fast_register_read</ipxact:name>
+          <ipxact:displayName>Fast Register Read</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_exportHostDebugPort" type="bit">
+          <ipxact:name>setting_exportHostDebugPort</ipxact:name>
+          <ipxact:displayName>Export Debug Host Slave</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_oci_export_jtag_signals" type="bit">
+          <ipxact:name>setting_oci_export_jtag_signals</ipxact:name>
+          <ipxact:displayName>Export JTAG signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_avalonDebugPortPresent" type="bit">
+          <ipxact:name>setting_avalonDebugPortPresent</ipxact:name>
+          <ipxact:displayName>Avalon Debug Port Present</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_alwaysEncrypt" type="bit">
+          <ipxact:name>setting_alwaysEncrypt</ipxact:name>
+          <ipxact:displayName>Always encrypt</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="io_regionbase" type="int">
+          <ipxact:name>io_regionbase</ipxact:name>
+          <ipxact:displayName>Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="io_regionsize" type="int">
+          <ipxact:name>io_regionsize</ipxact:name>
+          <ipxact:displayName>Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_support31bitdcachebypass" type="bit">
+          <ipxact:name>setting_support31bitdcachebypass</ipxact:name>
+          <ipxact:displayName>Use most-significant address bit in processor to bypass data cache</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_activateTrace" type="bit">
+          <ipxact:name>setting_activateTrace</ipxact:name>
+          <ipxact:displayName>Generate trace file during RTL simulation</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_allow_break_inst" type="bit">
+          <ipxact:name>setting_allow_break_inst</ipxact:name>
+          <ipxact:displayName>Allow Break instructions</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_activateTestEndChecker" type="bit">
+          <ipxact:name>setting_activateTestEndChecker</ipxact:name>
+          <ipxact:displayName>Activate test end checker</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_ecc_sim_test_ports" type="bit">
+          <ipxact:name>setting_ecc_sim_test_ports</ipxact:name>
+          <ipxact:displayName>Enable ECC simulation test ports</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_disableocitrace" type="bit">
+          <ipxact:name>setting_disableocitrace</ipxact:name>
+          <ipxact:displayName>Disable comptr generation</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_activateMonitors" type="bit">
+          <ipxact:name>setting_activateMonitors</ipxact:name>
+          <ipxact:displayName>Activate monitors</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_HDLSimCachesCleared" type="bit">
+          <ipxact:name>setting_HDLSimCachesCleared</ipxact:name>
+          <ipxact:displayName>HDL simulation caches cleared</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_HBreakTest" type="bit">
+          <ipxact:name>setting_HBreakTest</ipxact:name>
+          <ipxact:displayName>Add HBreak Request port</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_breakslaveoveride" type="bit">
+          <ipxact:name>setting_breakslaveoveride</ipxact:name>
+          <ipxact:displayName>Manually assign break slave</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mpu_useLimit" type="bit">
+          <ipxact:name>mpu_useLimit</ipxact:name>
+          <ipxact:displayName>Use Limit for region range</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mpu_enabled" type="bit">
+          <ipxact:name>mpu_enabled</ipxact:name>
+          <ipxact:displayName>Include MPU</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_enabled" type="bit">
+          <ipxact:name>mmu_enabled</ipxact:name>
+          <ipxact:displayName>Include MMU</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_autoAssignTlbPtrSz" type="bit">
+          <ipxact:name>mmu_autoAssignTlbPtrSz</ipxact:name>
+          <ipxact:displayName>Optimize TLB entries base on device family</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="cpuReset" type="bit">
+          <ipxact:name>cpuReset</ipxact:name>
+          <ipxact:displayName>Include cpu_resetrequest and cpu_resettaken signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="resetrequest_enabled" type="bit">
+          <ipxact:name>resetrequest_enabled</ipxact:name>
+          <ipxact:displayName>Include reset_req signal for OCI RAM and Multi-Cycle Custom Instructions</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_removeRAMinit" type="bit">
+          <ipxact:name>setting_removeRAMinit</ipxact:name>
+          <ipxact:displayName>Remove RAM Initialization</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_tmr_output_disable" type="bit">
+          <ipxact:name>setting_tmr_output_disable</ipxact:name>
+          <ipxact:displayName>Create a signal to disable TMR outputs</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_shadowRegisterSets" type="int">
+          <ipxact:name>setting_shadowRegisterSets</ipxact:name>
+          <ipxact:displayName>Number of shadow register sets (0-63)</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mpu_numOfInstRegion" type="int">
+          <ipxact:name>mpu_numOfInstRegion</ipxact:name>
+          <ipxact:displayName>        Number of instruction regions</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mpu_numOfDataRegion" type="int">
+          <ipxact:name>mpu_numOfDataRegion</ipxact:name>
+          <ipxact:displayName>        Number of data regions</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_TLBMissExcOffset" type="int">
+          <ipxact:name>mmu_TLBMissExcOffset</ipxact:name>
+          <ipxact:displayName>Fast TLB Miss Exception vector offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="resetOffset" type="int">
+          <ipxact:name>resetOffset</ipxact:name>
+          <ipxact:displayName>Reset vector offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="exceptionOffset" type="int">
+          <ipxact:name>exceptionOffset</ipxact:name>
+          <ipxact:displayName>Exception vector offset</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="cpuID" type="int">
+          <ipxact:name>cpuID</ipxact:name>
+          <ipxact:displayName>CPUID control register value</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="breakOffset" type="int">
+          <ipxact:name>breakOffset</ipxact:name>
+          <ipxact:displayName>Break vector offset</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="userDefinedSettings" type="string">
+          <ipxact:name>userDefinedSettings</ipxact:name>
+          <ipxact:displayName>User Defined Settings</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tracefilename" type="string">
+          <ipxact:name>tracefilename</ipxact:name>
+          <ipxact:displayName>Trace File Name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="resetSlave" type="string">
+          <ipxact:name>resetSlave</ipxact:name>
+          <ipxact:displayName>Reset vector memory</ipxact:displayName>
+          <ipxact:value>onchip_memory2_0.s1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_TLBMissExcSlave" type="string">
+          <ipxact:name>mmu_TLBMissExcSlave</ipxact:name>
+          <ipxact:displayName>Fast TLB Miss Exception vector memory</ipxact:displayName>
+          <ipxact:value>None</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="exceptionSlave" type="string">
+          <ipxact:name>exceptionSlave</ipxact:name>
+          <ipxact:displayName>Exception vector memory</ipxact:displayName>
+          <ipxact:value>onchip_memory2_0.s1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="breakSlave" type="string">
+          <ipxact:name>breakSlave</ipxact:name>
+          <ipxact:displayName>Break vector memory</ipxact:displayName>
+          <ipxact:value>None</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_interruptControllerType" type="string">
+          <ipxact:name>setting_interruptControllerType</ipxact:name>
+          <ipxact:displayName>Interrupt controller</ipxact:displayName>
+          <ipxact:value>Internal</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_branchpredictiontype" type="string">
+          <ipxact:name>setting_branchpredictiontype</ipxact:name>
+          <ipxact:displayName>Branch prediction type</ipxact:displayName>
+          <ipxact:value>Dynamic</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_bhtPtrSz" type="int">
+          <ipxact:name>setting_bhtPtrSz</ipxact:name>
+          <ipxact:displayName>        Number of entries (2-bits wide)</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="cpuArchRev" type="int">
+          <ipxact:name>cpuArchRev</ipxact:name>
+          <ipxact:displayName>Architecture Revision</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="stratix_dspblock_shift_mul" type="bit">
+          <ipxact:name>stratix_dspblock_shift_mul</ipxact:name>
+          <ipxact:displayName>stratix_dspblock_shift_mul</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="shifterType" type="string">
+          <ipxact:name>shifterType</ipxact:name>
+          <ipxact:displayName>shifterType</ipxact:displayName>
+          <ipxact:value>medium_le_shift</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="multiplierType" type="string">
+          <ipxact:name>multiplierType</ipxact:name>
+          <ipxact:displayName>multiplierType</ipxact:displayName>
+          <ipxact:value>no_mul</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mul_shift_choice" type="int">
+          <ipxact:name>mul_shift_choice</ipxact:name>
+          <ipxact:displayName>Multiply/Shift/Rotate Hardware</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mul_32_impl" type="int">
+          <ipxact:name>mul_32_impl</ipxact:name>
+          <ipxact:displayName>Multiply Implementation</ipxact:displayName>
+          <ipxact:value>2</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mul_64_impl" type="int">
+          <ipxact:name>mul_64_impl</ipxact:name>
+          <ipxact:displayName>Multiply Extended Implementation</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="shift_rot_impl" type="int">
+          <ipxact:name>shift_rot_impl</ipxact:name>
+          <ipxact:displayName>Shift/Rotate Implementation</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dividerType" type="string">
+          <ipxact:name>dividerType</ipxact:name>
+          <ipxact:displayName>Divide Hardware</ipxact:displayName>
+          <ipxact:value>no_div</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mpu_minInstRegionSize" type="int">
+          <ipxact:name>mpu_minInstRegionSize</ipxact:name>
+          <ipxact:displayName>        Minimum instruction region size</ipxact:displayName>
+          <ipxact:value>12</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mpu_minDataRegionSize" type="int">
+          <ipxact:name>mpu_minDataRegionSize</ipxact:name>
+          <ipxact:displayName>        Minimum data region size</ipxact:displayName>
+          <ipxact:value>12</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_uitlbNumEntries" type="int">
+          <ipxact:name>mmu_uitlbNumEntries</ipxact:name>
+          <ipxact:displayName>        Micro ITLB entries</ipxact:displayName>
+          <ipxact:value>4</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_udtlbNumEntries" type="int">
+          <ipxact:name>mmu_udtlbNumEntries</ipxact:name>
+          <ipxact:displayName>        Micro DTLB entries</ipxact:displayName>
+          <ipxact:value>6</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_tlbPtrSz" type="int">
+          <ipxact:name>mmu_tlbPtrSz</ipxact:name>
+          <ipxact:displayName>        TLB entries</ipxact:displayName>
+          <ipxact:value>7</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_tlbNumWays" type="int">
+          <ipxact:name>mmu_tlbNumWays</ipxact:name>
+          <ipxact:displayName>        TLB Set-Associativity</ipxact:displayName>
+          <ipxact:value>16</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_processIDNumBits" type="int">
+          <ipxact:name>mmu_processIDNumBits</ipxact:name>
+          <ipxact:displayName>        Process ID (PID) bits</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="impl" type="string">
+          <ipxact:name>impl</ipxact:name>
+          <ipxact:displayName>Nios II Core</ipxact:displayName>
+          <ipxact:value>Tiny</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="icache_size" type="int">
+          <ipxact:name>icache_size</ipxact:name>
+          <ipxact:displayName>Size</ipxact:displayName>
+          <ipxact:value>4096</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="fa_cache_line" type="int">
+          <ipxact:name>fa_cache_line</ipxact:name>
+          <ipxact:displayName>Number of Cache Lines</ipxact:displayName>
+          <ipxact:value>2</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="fa_cache_linesize" type="int">
+          <ipxact:name>fa_cache_linesize</ipxact:name>
+          <ipxact:displayName>Line Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="icache_tagramBlockType" type="string">
+          <ipxact:name>icache_tagramBlockType</ipxact:name>
+          <ipxact:displayName>Tag RAM block type</ipxact:displayName>
+          <ipxact:value>Automatic</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="icache_ramBlockType" type="string">
+          <ipxact:name>icache_ramBlockType</ipxact:name>
+          <ipxact:displayName>Data RAM block type</ipxact:displayName>
+          <ipxact:value>Automatic</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="icache_numTCIM" type="int">
+          <ipxact:name>icache_numTCIM</ipxact:name>
+          <ipxact:displayName>Number of tightly coupled instruction master ports</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="icache_burstType" type="string">
+          <ipxact:name>icache_burstType</ipxact:name>
+          <ipxact:displayName>Add burstcount signal to instruction_master</ipxact:displayName>
+          <ipxact:value>None</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dcache_bursts" type="string">
+          <ipxact:name>dcache_bursts</ipxact:name>
+          <ipxact:displayName>Add burstcount signal to data_master</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dcache_victim_buf_impl" type="string">
+          <ipxact:name>dcache_victim_buf_impl</ipxact:name>
+          <ipxact:displayName>Victim buffer implementation</ipxact:displayName>
+          <ipxact:value>ram</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dcache_size" type="int">
+          <ipxact:name>dcache_size</ipxact:name>
+          <ipxact:displayName>Size</ipxact:displayName>
+          <ipxact:value>2048</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dcache_tagramBlockType" type="string">
+          <ipxact:name>dcache_tagramBlockType</ipxact:name>
+          <ipxact:displayName>Tag RAM block type</ipxact:displayName>
+          <ipxact:value>Automatic</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dcache_ramBlockType" type="string">
+          <ipxact:name>dcache_ramBlockType</ipxact:name>
+          <ipxact:displayName>Data RAM block type</ipxact:displayName>
+          <ipxact:value>Automatic</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dcache_numTCDM" type="int">
+          <ipxact:name>dcache_numTCDM</ipxact:name>
+          <ipxact:displayName>Number of tightly coupled data master ports</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_exportvectors" type="bit">
+          <ipxact:name>setting_exportvectors</ipxact:name>
+          <ipxact:displayName>Export Vectors</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_usedesignware" type="bit">
+          <ipxact:name>setting_usedesignware</ipxact:name>
+          <ipxact:displayName>Use Designware Components</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_ecc_present" type="bit">
+          <ipxact:name>setting_ecc_present</ipxact:name>
+          <ipxact:displayName>ECC Present</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_ic_ecc_present" type="bit">
+          <ipxact:name>setting_ic_ecc_present</ipxact:name>
+          <ipxact:displayName>Instruction Cache ECC Present</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_rf_ecc_present" type="bit">
+          <ipxact:name>setting_rf_ecc_present</ipxact:name>
+          <ipxact:displayName>Register File ECC Present</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_mmu_ecc_present" type="bit">
+          <ipxact:name>setting_mmu_ecc_present</ipxact:name>
+          <ipxact:displayName>MMU ECC Present</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_dc_ecc_present" type="bit">
+          <ipxact:name>setting_dc_ecc_present</ipxact:name>
+          <ipxact:displayName>Data Cache ECC Present</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_itcm_ecc_present" type="bit">
+          <ipxact:name>setting_itcm_ecc_present</ipxact:name>
+          <ipxact:displayName>Instruction TCM ECC Present</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_dtcm_ecc_present" type="bit">
+          <ipxact:name>setting_dtcm_ecc_present</ipxact:name>
+          <ipxact:displayName>Data TCM ECC Present</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="regfile_ramBlockType" type="string">
+          <ipxact:name>regfile_ramBlockType</ipxact:name>
+          <ipxact:displayName>RAM block type</ipxact:displayName>
+          <ipxact:value>Automatic</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ocimem_ramBlockType" type="string">
+          <ipxact:name>ocimem_ramBlockType</ipxact:name>
+          <ipxact:displayName>RAM block type</ipxact:displayName>
+          <ipxact:value>Automatic</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ocimem_ramInit" type="bit">
+          <ipxact:name>ocimem_ramInit</ipxact:name>
+          <ipxact:displayName>Initialized OCI RAM</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_ramBlockType" type="string">
+          <ipxact:name>mmu_ramBlockType</ipxact:name>
+          <ipxact:displayName>        MMU RAM block type</ipxact:displayName>
+          <ipxact:value>Automatic</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bht_ramBlockType" type="string">
+          <ipxact:name>bht_ramBlockType</ipxact:name>
+          <ipxact:displayName>BHT RAM Block Type</ipxact:displayName>
+          <ipxact:value>Automatic</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="cdx_enabled" type="bit">
+          <ipxact:name>cdx_enabled</ipxact:name>
+          <ipxact:displayName>CDX (Code Density eXtension) Instructions</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mpx_enabled" type="bit">
+          <ipxact:name>mpx_enabled</ipxact:name>
+          <ipxact:displayName>mpx_enabled</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_enabled" type="bit">
+          <ipxact:name>debug_enabled</ipxact:name>
+          <ipxact:displayName>Include JTAG Debug</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_triggerArming" type="bit">
+          <ipxact:name>debug_triggerArming</ipxact:name>
+          <ipxact:displayName>Trigger Arming</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_debugReqSignals" type="bit">
+          <ipxact:name>debug_debugReqSignals</ipxact:name>
+          <ipxact:displayName>Include debugreq and debugack Signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_assignJtagInstanceID" type="bit">
+          <ipxact:name>debug_assignJtagInstanceID</ipxact:name>
+          <ipxact:displayName>Assign JTAG Instance ID for debug core manually</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_jtagInstanceID" type="int">
+          <ipxact:name>debug_jtagInstanceID</ipxact:name>
+          <ipxact:displayName>JTAG Instance ID value</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_OCIOnchipTrace" type="string">
+          <ipxact:name>debug_OCIOnchipTrace</ipxact:name>
+          <ipxact:displayName>Onchip Trace Frame Size</ipxact:displayName>
+          <ipxact:value>_128</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_hwbreakpoint" type="int">
+          <ipxact:name>debug_hwbreakpoint</ipxact:name>
+          <ipxact:displayName>Hardware Breakpoints</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_datatrigger" type="int">
+          <ipxact:name>debug_datatrigger</ipxact:name>
+          <ipxact:displayName>Data Triggers</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_traceType" type="string">
+          <ipxact:name>debug_traceType</ipxact:name>
+          <ipxact:displayName>Trace Types</ipxact:displayName>
+          <ipxact:value>none</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_traceStorage" type="string">
+          <ipxact:name>debug_traceStorage</ipxact:name>
+          <ipxact:displayName>Trace Storage</ipxact:displayName>
+          <ipxact:value>onchip_trace</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="master_addr_map" type="bit">
+          <ipxact:name>master_addr_map</ipxact:name>
+          <ipxact:displayName>Manually Set Master Base Address and Size</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="instruction_master_paddr_base" type="int">
+          <ipxact:name>instruction_master_paddr_base</ipxact:name>
+          <ipxact:displayName>Instruction Master Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="instruction_master_paddr_size" type="longint">
+          <ipxact:name>instruction_master_paddr_size</ipxact:name>
+          <ipxact:displayName>Instruction Master Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="flash_instruction_master_paddr_base" type="int">
+          <ipxact:name>flash_instruction_master_paddr_base</ipxact:name>
+          <ipxact:displayName>Flash Instruction Master Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="flash_instruction_master_paddr_size" type="longint">
+          <ipxact:name>flash_instruction_master_paddr_size</ipxact:name>
+          <ipxact:displayName>Flash Instruction Master Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="data_master_paddr_base" type="int">
+          <ipxact:name>data_master_paddr_base</ipxact:name>
+          <ipxact:displayName>Data Master Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="data_master_paddr_size" type="longint">
+          <ipxact:name>data_master_paddr_size</ipxact:name>
+          <ipxact:displayName>Data Master Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_instruction_master_0_paddr_base" type="int">
+          <ipxact:name>tightly_coupled_instruction_master_0_paddr_base</ipxact:name>
+          <ipxact:displayName>Tightly coupled Instruction Master 0 Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_instruction_master_0_paddr_size" type="longint">
+          <ipxact:name>tightly_coupled_instruction_master_0_paddr_size</ipxact:name>
+          <ipxact:displayName>Tightly coupled Instruction Master 0 Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_instruction_master_1_paddr_base" type="int">
+          <ipxact:name>tightly_coupled_instruction_master_1_paddr_base</ipxact:name>
+          <ipxact:displayName>Tightly coupled Instruction Master 1 Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_instruction_master_1_paddr_size" type="longint">
+          <ipxact:name>tightly_coupled_instruction_master_1_paddr_size</ipxact:name>
+          <ipxact:displayName>Tightly coupled Instruction Master 1 Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_instruction_master_2_paddr_base" type="int">
+          <ipxact:name>tightly_coupled_instruction_master_2_paddr_base</ipxact:name>
+          <ipxact:displayName>Tightly coupled Instruction Master 2 Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_instruction_master_2_paddr_size" type="longint">
+          <ipxact:name>tightly_coupled_instruction_master_2_paddr_size</ipxact:name>
+          <ipxact:displayName>Tightly coupled Instruction Master 2 Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_instruction_master_3_paddr_base" type="int">
+          <ipxact:name>tightly_coupled_instruction_master_3_paddr_base</ipxact:name>
+          <ipxact:displayName>Tightly coupled Instruction Master 3 Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_instruction_master_3_paddr_size" type="longint">
+          <ipxact:name>tightly_coupled_instruction_master_3_paddr_size</ipxact:name>
+          <ipxact:displayName>Tightly coupled Instruction Master 3 Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_data_master_0_paddr_base" type="int">
+          <ipxact:name>tightly_coupled_data_master_0_paddr_base</ipxact:name>
+          <ipxact:displayName>Tightly coupled Data Master 0 Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_data_master_0_paddr_size" type="longint">
+          <ipxact:name>tightly_coupled_data_master_0_paddr_size</ipxact:name>
+          <ipxact:displayName>Tightly coupled Data Master 0 Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_data_master_1_paddr_base" type="int">
+          <ipxact:name>tightly_coupled_data_master_1_paddr_base</ipxact:name>
+          <ipxact:displayName>Tightly coupled Data Master 1 Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_data_master_1_paddr_size" type="longint">
+          <ipxact:name>tightly_coupled_data_master_1_paddr_size</ipxact:name>
+          <ipxact:displayName>Tightly coupled Data Master 1 Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_data_master_2_paddr_base" type="int">
+          <ipxact:name>tightly_coupled_data_master_2_paddr_base</ipxact:name>
+          <ipxact:displayName>Tightly coupled Data Master 2 Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_data_master_2_paddr_size" type="longint">
+          <ipxact:name>tightly_coupled_data_master_2_paddr_size</ipxact:name>
+          <ipxact:displayName>Tightly coupled Data Master 2 Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_data_master_3_paddr_base" type="int">
+          <ipxact:name>tightly_coupled_data_master_3_paddr_base</ipxact:name>
+          <ipxact:displayName>Tightly coupled Data Master 3 Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightly_coupled_data_master_3_paddr_size" type="longint">
+          <ipxact:name>tightly_coupled_data_master_3_paddr_size</ipxact:name>
+          <ipxact:displayName>Tightly coupled Data Master 3 Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="instruction_master_high_performance_paddr_base" type="int">
+          <ipxact:name>instruction_master_high_performance_paddr_base</ipxact:name>
+          <ipxact:displayName>Instruction Master High Performance Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="instruction_master_high_performance_paddr_size" type="longint">
+          <ipxact:name>instruction_master_high_performance_paddr_size</ipxact:name>
+          <ipxact:displayName>Instruction Master High Performance Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="data_master_high_performance_paddr_base" type="int">
+          <ipxact:name>data_master_high_performance_paddr_base</ipxact:name>
+          <ipxact:displayName>Data Master High Performance Base Address</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="data_master_high_performance_paddr_size" type="longint">
+          <ipxact:name>data_master_high_performance_paddr_size</ipxact:name>
+          <ipxact:displayName>Data Master High Performance Size</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="resetAbsoluteAddr" type="int">
+          <ipxact:name>resetAbsoluteAddr</ipxact:name>
+          <ipxact:displayName>Reset vector</ipxact:displayName>
+          <ipxact:value>131072</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="exceptionAbsoluteAddr" type="int">
+          <ipxact:name>exceptionAbsoluteAddr</ipxact:name>
+          <ipxact:displayName>Exception vector</ipxact:displayName>
+          <ipxact:value>131104</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="breakAbsoluteAddr" type="int">
+          <ipxact:name>breakAbsoluteAddr</ipxact:name>
+          <ipxact:displayName>Break vector</ipxact:displayName>
+          <ipxact:value>14368</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="mmu_TLBMissExcAbsAddr" type="int">
+          <ipxact:name>mmu_TLBMissExcAbsAddr</ipxact:name>
+          <ipxact:displayName>Fast TLB Miss Exception vector</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dcache_bursts_derived" type="string">
+          <ipxact:name>dcache_bursts_derived</ipxact:name>
+          <ipxact:displayName>dcache_bursts_derived</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dcache_size_derived" type="int">
+          <ipxact:name>dcache_size_derived</ipxact:name>
+          <ipxact:displayName>dcache_size_derived</ipxact:displayName>
+          <ipxact:value>2048</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="breakSlave_derived" type="string">
+          <ipxact:name>breakSlave_derived</ipxact:name>
+          <ipxact:displayName>breakSlave_derived</ipxact:displayName>
+          <ipxact:value>cpu_0.debug_mem_slave</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dcache_lineSize_derived" type="int">
+          <ipxact:name>dcache_lineSize_derived</ipxact:name>
+          <ipxact:displayName>dcache_lineSize_derived</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_ioregionBypassDCache" type="bit">
+          <ipxact:name>setting_ioregionBypassDCache</ipxact:name>
+          <ipxact:displayName>setting_ioregionBypassDCache</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setting_bit31BypassDCache" type="bit">
+          <ipxact:name>setting_bit31BypassDCache</ipxact:name>
+          <ipxact:displayName>setting_bit31BypassDCache</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="translate_on" type="string">
+          <ipxact:name>translate_on</ipxact:name>
+          <ipxact:displayName>translate_on</ipxact:displayName>
+          <ipxact:value> "synthesis translate_on"  </ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="translate_off" type="string">
+          <ipxact:name>translate_off</ipxact:name>
+          <ipxact:displayName>translate_off</ipxact:displayName>
+          <ipxact:value> "synthesis translate_off" </ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_onchiptrace" type="bit">
+          <ipxact:name>debug_onchiptrace</ipxact:name>
+          <ipxact:displayName>debug_onchiptrace</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_offchiptrace" type="bit">
+          <ipxact:name>debug_offchiptrace</ipxact:name>
+          <ipxact:displayName>debug_offchiptrace</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_insttrace" type="bit">
+          <ipxact:name>debug_insttrace</ipxact:name>
+          <ipxact:displayName>debug_insttrace</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="debug_datatrace" type="bit">
+          <ipxact:name>debug_datatrace</ipxact:name>
+          <ipxact:displayName>debug_datatrace</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="instAddrWidth" type="int">
+          <ipxact:name>instAddrWidth</ipxact:name>
+          <ipxact:displayName>instAddrWidth</ipxact:displayName>
+          <ipxact:value>18</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="faAddrWidth" type="int">
+          <ipxact:name>faAddrWidth</ipxact:name>
+          <ipxact:displayName>faAddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dataAddrWidth" type="int">
+          <ipxact:name>dataAddrWidth</ipxact:name>
+          <ipxact:displayName>dataAddrWidth</ipxact:displayName>
+          <ipxact:value>20</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledDataMaster0AddrWidth" type="int">
+          <ipxact:name>tightlyCoupledDataMaster0AddrWidth</ipxact:name>
+          <ipxact:displayName>tightlyCoupledDataMaster0AddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledDataMaster1AddrWidth" type="int">
+          <ipxact:name>tightlyCoupledDataMaster1AddrWidth</ipxact:name>
+          <ipxact:displayName>tightlyCoupledDataMaster1AddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledDataMaster2AddrWidth" type="int">
+          <ipxact:name>tightlyCoupledDataMaster2AddrWidth</ipxact:name>
+          <ipxact:displayName>tightlyCoupledDataMaster2AddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledDataMaster3AddrWidth" type="int">
+          <ipxact:name>tightlyCoupledDataMaster3AddrWidth</ipxact:name>
+          <ipxact:displayName>tightlyCoupledDataMaster3AddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledInstructionMaster0AddrWidth" type="int">
+          <ipxact:name>tightlyCoupledInstructionMaster0AddrWidth</ipxact:name>
+          <ipxact:displayName>tightlyCoupledInstructionMaster0AddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledInstructionMaster1AddrWidth" type="int">
+          <ipxact:name>tightlyCoupledInstructionMaster1AddrWidth</ipxact:name>
+          <ipxact:displayName>tightlyCoupledInstructionMaster1AddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledInstructionMaster2AddrWidth" type="int">
+          <ipxact:name>tightlyCoupledInstructionMaster2AddrWidth</ipxact:name>
+          <ipxact:displayName>tightlyCoupledInstructionMaster2AddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledInstructionMaster3AddrWidth" type="int">
+          <ipxact:name>tightlyCoupledInstructionMaster3AddrWidth</ipxact:name>
+          <ipxact:displayName>tightlyCoupledInstructionMaster3AddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dataMasterHighPerformanceAddrWidth" type="int">
+          <ipxact:name>dataMasterHighPerformanceAddrWidth</ipxact:name>
+          <ipxact:displayName>dataMasterHighPerformanceAddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="instructionMasterHighPerformanceAddrWidth" type="int">
+          <ipxact:name>instructionMasterHighPerformanceAddrWidth</ipxact:name>
+          <ipxact:displayName>instructionMasterHighPerformanceAddrWidth</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="instSlaveMapParam" type="string">
+          <ipxact:name>instSlaveMapParam</ipxact:name>
+          <ipxact:displayName>instSlaveMapParam</ipxact:displayName>
+          <ipxact:value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="faSlaveMapParam" type="string">
+          <ipxact:name>faSlaveMapParam</ipxact:name>
+          <ipxact:displayName>faSlaveMapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dataSlaveMapParam" type="string">
+          <ipxact:name>dataSlaveMapParam</ipxact:name>
+          <ipxact:displayName>dataSlaveMapParam</ipxact:displayName>
+          <ipxact:value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x40000' end='0x44000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x48000' end='0x48400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x4C000' end='0x4C100' datawidth='32' /&gt;&lt;slave name='reg_bsn_source.mem' start='0x4C100' end='0x4C110' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0x4C110' end='0x4C118' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x4C120' end='0x4C140' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x50000' end='0x60000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_jesd.mem' start='0x60000' end='0x64000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x64000' end='0x68000' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x68000' end='0x68100' datawidth='32' /&gt;&lt;slave name='ram_aduh_monitor.mem' start='0x70000' end='0x74000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0xC0000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0xC0000' end='0x100000' datawidth='32' /&gt;&lt;/address-map&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledDataMaster0MapParam" type="string">
+          <ipxact:name>tightlyCoupledDataMaster0MapParam</ipxact:name>
+          <ipxact:displayName>tightlyCoupledDataMaster0MapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledDataMaster1MapParam" type="string">
+          <ipxact:name>tightlyCoupledDataMaster1MapParam</ipxact:name>
+          <ipxact:displayName>tightlyCoupledDataMaster1MapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledDataMaster2MapParam" type="string">
+          <ipxact:name>tightlyCoupledDataMaster2MapParam</ipxact:name>
+          <ipxact:displayName>tightlyCoupledDataMaster2MapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledDataMaster3MapParam" type="string">
+          <ipxact:name>tightlyCoupledDataMaster3MapParam</ipxact:name>
+          <ipxact:displayName>tightlyCoupledDataMaster3MapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledInstructionMaster0MapParam" type="string">
+          <ipxact:name>tightlyCoupledInstructionMaster0MapParam</ipxact:name>
+          <ipxact:displayName>tightlyCoupledInstructionMaster0MapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledInstructionMaster1MapParam" type="string">
+          <ipxact:name>tightlyCoupledInstructionMaster1MapParam</ipxact:name>
+          <ipxact:displayName>tightlyCoupledInstructionMaster1MapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledInstructionMaster2MapParam" type="string">
+          <ipxact:name>tightlyCoupledInstructionMaster2MapParam</ipxact:name>
+          <ipxact:displayName>tightlyCoupledInstructionMaster2MapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="tightlyCoupledInstructionMaster3MapParam" type="string">
+          <ipxact:name>tightlyCoupledInstructionMaster3MapParam</ipxact:name>
+          <ipxact:displayName>tightlyCoupledInstructionMaster3MapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="dataMasterHighPerformanceMapParam" type="string">
+          <ipxact:name>dataMasterHighPerformanceMapParam</ipxact:name>
+          <ipxact:displayName>dataMasterHighPerformanceMapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="instructionMasterHighPerformanceMapParam" type="string">
+          <ipxact:name>instructionMasterHighPerformanceMapParam</ipxact:name>
+          <ipxact:displayName>instructionMasterHighPerformanceMapParam</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="clockFrequency" type="longint">
+          <ipxact:name>clockFrequency</ipxact:name>
+          <ipxact:displayName>clockFrequency</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamilyName" type="string">
+          <ipxact:name>deviceFamilyName</ipxact:name>
+          <ipxact:displayName>deviceFamilyName</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="internalIrqMaskSystemInfo" type="longint">
+          <ipxact:name>internalIrqMaskSystemInfo</ipxact:name>
+          <ipxact:displayName>internalIrqMaskSystemInfo</ipxact:displayName>
+          <ipxact:value>7</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="customInstSlavesSystemInfo" type="string">
+          <ipxact:name>customInstSlavesSystemInfo</ipxact:name>
+          <ipxact:displayName>customInstSlavesSystemInfo</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="customInstSlavesSystemInfo_nios_a" type="string">
+          <ipxact:name>customInstSlavesSystemInfo_nios_a</ipxact:name>
+          <ipxact:displayName>customInstSlavesSystemInfo_nios_a</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="customInstSlavesSystemInfo_nios_b" type="string">
+          <ipxact:name>customInstSlavesSystemInfo_nios_b</ipxact:name>
+          <ipxact:displayName>customInstSlavesSystemInfo_nios_b</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="customInstSlavesSystemInfo_nios_c" type="string">
+          <ipxact:name>customInstSlavesSystemInfo_nios_c</ipxact:name>
+          <ipxact:displayName>customInstSlavesSystemInfo_nios_c</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFeaturesSystemInfo" type="string">
+          <ipxact:name>deviceFeaturesSystemInfo</ipxact:name>
+          <ipxact:displayName>deviceFeaturesSystemInfo</ipxact:displayName>
+          <ipxact:value>ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 ALLOW_DIFF_SUFFIX_MIGRATION 0 ASSERT_TIMING_ROUTING_DELAYS_HAS_ALL_EXPECTED_DATA 0 ASSERT_TIMING_ROUTING_DELAYS_NO_AUTOFILL 0 BLACKLISTS_HIERARCHIES 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DOES_NOT_SUPPORT_TIMING_MODELS_FOR_ROUTING_WIRES_WITH_ONLY_REDUNDANT_FANOUTS 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_HIGH_SPEED_HSSI 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FM_REVB 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CROSS_FEATURE_VERTICAL_MIGRATION_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_BLOCK 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LAB_LATCHES 0 HAS_LEIM_RES_MERGED_IN_RR_GRAPH 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QHD_INCREMENTAL_TIMING_CLOSURE_SUPPORT 1 HAS_QHD_IP_REUSE_INTEGRATION_SUPPORT 1 HAS_QHD_PARTITIONS_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_REVC_IO 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMPLIFIED_PARTIAL_RECONFIG_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SIP_TILE_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_STATIC_PART 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_DQS_IN_BUFFER_REDUCTION 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_JW_NEW_BINNING_PLAN 0 IS_JZ_NEW_BINNING_PLAN 0 IS_MCP_DEVICE 0 IS_REVE_SILICON 0 IS_SDM_LITE 0 IS_UDM_BASED 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LUTRAM_DATA_IN_FF_MUST_BE_HIPI 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NOT_SUPPORTED_BY_QPA 0 NO_CLOCK_REGION 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PCF 0 NO_PIN_OUT 0 NO_POF 0 NO_ROUTING 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PRE_ND5_L_FINALITY 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 QPA_SUPPORTS_VID_CALC 0 QPA_USES_PAN2 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_ADVANCED_SECURITY 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_PW0 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_MIN_CORNER_DMF_GENERATION 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_PSEUDO_LATCHES_ONLY 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_TIMING_CLOSURE_CORNERS 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HBM_IN_EPE 0 SUPPORT_HIGH_SPEED_HPS 0 SUPPORT_MULTIPLE_PAD_PER_PIN 0 SUPPORT_UIB 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 U2B2_SUPPORT_NOT_READY 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DETAILED_REDTAX_WITH_DSPF_ROUTING_MODELS 0 USES_DEV 1 USES_DSPF_ROUTING_MODELS 0 USES_ESTIMATED_TIMING 0 USES_EXTRACTION_CORNERS_WITH_DSPF_ROUTING_MODELS 0 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_ANNOTATION_FOR_LAB_OUTPUTS 0 USES_LIBERTY_ANNOTATION_FOR_M20K_DSP_OUTPUTS 0 USES_LIBERTY_TIMING 0 USES_MULTIPLE_VID_VOLTAGES 1 USES_PARASITIC_LOADS_WITH_DSPF_ROUTING_MODELS 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_TIMING_ROUTING_DELAYS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SDM_CONFIGURATION 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_DEVICE" type="string">
+          <ipxact:name>AUTO_DEVICE</ipxact:name>
+          <ipxact:displayName>Auto DEVICE</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_DEVICE_SPEEDGRADE" type="string">
+          <ipxact:name>AUTO_DEVICE_SPEEDGRADE</ipxact:name>
+          <ipxact:displayName>Auto DEVICE_SPEEDGRADE</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_CLK_CLOCK_DOMAIN" type="longint">
+          <ipxact:name>AUTO_CLK_CLOCK_DOMAIN</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_DOMAIN</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_CLK_RESET_DOMAIN" type="longint">
+          <ipxact:name>AUTO_CLK_RESET_DOMAIN</ipxact:name>
+          <ipxact:displayName>Auto RESET_DOMAIN</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
     </altera:altera_module_parameters>
     <altera:altera_assignments>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>debug.hostConnection</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="debug.hostConnection">type jtag id 70:34|110:135</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.BIG_ENDIAN</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BIG_ENDIAN">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.BREAK_ADDR</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BREAK_ADDR">0x00003820</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_ARCH_NIOS2_R1"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.CPU_FREQ</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_FREQ">100000000u</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.CPU_ID_SIZE</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_ID_SIZE">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.CPU_ID_VALUE</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_ID_VALUE">0x00000000</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.CPU_IMPLEMENTATION</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.CPU_IMPLEMENTATION">"tiny"</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.DATA_ADDR_WIDTH</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_ADDR_WIDTH">21</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.DCACHE_LINE_SIZE</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DCACHE_LINE_SIZE">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.DCACHE_SIZE</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DCACHE_SIZE">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.EXCEPTION_ADDR</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.EXCEPTION_ADDR">0x00020020</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FLASH_ACCELERATOR_LINES">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.FLUSHDA_SUPPORTED</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FLUSHDA_SUPPORTED"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HARDWARE_MULX_PRESENT">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.HAS_DEBUG_CORE</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_DEBUG_CORE">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.HAS_DEBUG_STUB</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_DEBUG_STUB"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.HAS_JMPI_INSTRUCTION"></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.ICACHE_LINE_SIZE</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ICACHE_LINE_SIZE">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.ICACHE_SIZE</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ICACHE_SIZE">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.INST_ADDR_WIDTH</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.INST_ADDR_WIDTH">18</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.OCI_VERSION</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.OCI_VERSION">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.CMacro.RESET_ADDR</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.RESET_ADDR">0x00020000</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.configuration.DataCacheVictimBufImpl</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.DataCacheVictimBufImpl">ram</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.configuration.HDLSimCachesCleared</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.HDLSimCachesCleared">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.configuration.breakOffset</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.breakOffset">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.configuration.breakSlave</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.breakSlave">cpu_0.debug_mem_slave</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.configuration.cpuArchitecture</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.cpuArchitecture">Nios II</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.configuration.exceptionOffset</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.exceptionOffset">32</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.configuration.exceptionSlave</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.exceptionSlave">onchip_memory2_0.s1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.configuration.resetOffset</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.resetOffset">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.configuration.resetSlave</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.resetSlave">onchip_memory2_0.s1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.compatible</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.compatible">altr,nios2-1.1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.group</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.group">cpu</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.name</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.name">nios2</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.params.altr,exception-addr</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.altr,exception-addr">0x00020020</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.params.altr,implementation</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.altr,implementation">"tiny"</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.params.altr,reset-addr</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.altr,reset-addr">0x00020000</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.params.clock-frequency</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.clock-frequency">100000000u</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.params.dcache-line-size</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.dcache-line-size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.params.dcache-size</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.dcache-size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.params.icache-line-size</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.icache-line-size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.params.icache-size</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.icache-size">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>embeddedsw.dts.vendor</spirit:name>
-          <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.vendor">altr</spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="debug.hostConnection" type="string">
+          <ipxact:name>debug.hostConnection</ipxact:name>
+          <ipxact:value>type jtag id 70:34|110:135</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.BIG_ENDIAN" type="string">
+          <ipxact:name>embeddedsw.CMacro.BIG_ENDIAN</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.BREAK_ADDR" type="string">
+          <ipxact:name>embeddedsw.CMacro.BREAK_ADDR</ipxact:name>
+          <ipxact:value>0x00003820</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.CPU_ARCH_NIOS2_R1" type="string">
+          <ipxact:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</ipxact:name>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.CPU_FREQ" type="string">
+          <ipxact:name>embeddedsw.CMacro.CPU_FREQ</ipxact:name>
+          <ipxact:value>100000000u</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.CPU_ID_SIZE" type="string">
+          <ipxact:name>embeddedsw.CMacro.CPU_ID_SIZE</ipxact:name>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.CPU_ID_VALUE" type="string">
+          <ipxact:name>embeddedsw.CMacro.CPU_ID_VALUE</ipxact:name>
+          <ipxact:value>0x00000000</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.CPU_IMPLEMENTATION" type="string">
+          <ipxact:name>embeddedsw.CMacro.CPU_IMPLEMENTATION</ipxact:name>
+          <ipxact:value>"tiny"</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.DATA_ADDR_WIDTH" type="string">
+          <ipxact:name>embeddedsw.CMacro.DATA_ADDR_WIDTH</ipxact:name>
+          <ipxact:value>20</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.DCACHE_LINE_SIZE" type="string">
+          <ipxact:name>embeddedsw.CMacro.DCACHE_LINE_SIZE</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2" type="string">
+          <ipxact:name>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.DCACHE_SIZE" type="string">
+          <ipxact:name>embeddedsw.CMacro.DCACHE_SIZE</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.EXCEPTION_ADDR" type="string">
+          <ipxact:name>embeddedsw.CMacro.EXCEPTION_ADDR</ipxact:name>
+          <ipxact:value>0x00020020</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.FLASH_ACCELERATOR_LINES" type="string">
+          <ipxact:name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE" type="string">
+          <ipxact:name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.FLUSHDA_SUPPORTED" type="string">
+          <ipxact:name>embeddedsw.CMacro.FLUSHDA_SUPPORTED</ipxact:name>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT" type="string">
+          <ipxact:name>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT" type="string">
+          <ipxact:name>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.HARDWARE_MULX_PRESENT" type="string">
+          <ipxact:name>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.HAS_DEBUG_CORE" type="string">
+          <ipxact:name>embeddedsw.CMacro.HAS_DEBUG_CORE</ipxact:name>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.HAS_DEBUG_STUB" type="string">
+          <ipxact:name>embeddedsw.CMacro.HAS_DEBUG_STUB</ipxact:name>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION" type="string">
+          <ipxact:name>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</ipxact:name>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.HAS_JMPI_INSTRUCTION" type="string">
+          <ipxact:name>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</ipxact:name>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.ICACHE_LINE_SIZE" type="string">
+          <ipxact:name>embeddedsw.CMacro.ICACHE_LINE_SIZE</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2" type="string">
+          <ipxact:name>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.ICACHE_SIZE" type="string">
+          <ipxact:name>embeddedsw.CMacro.ICACHE_SIZE</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.INST_ADDR_WIDTH" type="string">
+          <ipxact:name>embeddedsw.CMacro.INST_ADDR_WIDTH</ipxact:name>
+          <ipxact:value>18</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.OCI_VERSION" type="string">
+          <ipxact:name>embeddedsw.CMacro.OCI_VERSION</ipxact:name>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.CMacro.RESET_ADDR" type="string">
+          <ipxact:name>embeddedsw.CMacro.RESET_ADDR</ipxact:name>
+          <ipxact:value>0x00020000</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.configuration.DataCacheVictimBufImpl" type="string">
+          <ipxact:name>embeddedsw.configuration.DataCacheVictimBufImpl</ipxact:name>
+          <ipxact:value>ram</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.configuration.HDLSimCachesCleared" type="string">
+          <ipxact:name>embeddedsw.configuration.HDLSimCachesCleared</ipxact:name>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.configuration.breakOffset" type="string">
+          <ipxact:name>embeddedsw.configuration.breakOffset</ipxact:name>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.configuration.breakSlave" type="string">
+          <ipxact:name>embeddedsw.configuration.breakSlave</ipxact:name>
+          <ipxact:value>cpu_0.debug_mem_slave</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.configuration.cpuArchitecture" type="string">
+          <ipxact:name>embeddedsw.configuration.cpuArchitecture</ipxact:name>
+          <ipxact:value>Nios II</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.configuration.exceptionOffset" type="string">
+          <ipxact:name>embeddedsw.configuration.exceptionOffset</ipxact:name>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.configuration.exceptionSlave" type="string">
+          <ipxact:name>embeddedsw.configuration.exceptionSlave</ipxact:name>
+          <ipxact:value>onchip_memory2_0.s1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.configuration.resetOffset" type="string">
+          <ipxact:name>embeddedsw.configuration.resetOffset</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.configuration.resetSlave" type="string">
+          <ipxact:name>embeddedsw.configuration.resetSlave</ipxact:name>
+          <ipxact:value>onchip_memory2_0.s1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.compatible" type="string">
+          <ipxact:name>embeddedsw.dts.compatible</ipxact:name>
+          <ipxact:value>altr,nios2-1.1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.group" type="string">
+          <ipxact:name>embeddedsw.dts.group</ipxact:name>
+          <ipxact:value>cpu</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.name" type="string">
+          <ipxact:name>embeddedsw.dts.name</ipxact:name>
+          <ipxact:value>nios2</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.params.altr,exception-addr" type="string">
+          <ipxact:name>embeddedsw.dts.params.altr,exception-addr</ipxact:name>
+          <ipxact:value>0x00020020</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.params.altr,implementation" type="string">
+          <ipxact:name>embeddedsw.dts.params.altr,implementation</ipxact:name>
+          <ipxact:value>"tiny"</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.params.altr,reset-addr" type="string">
+          <ipxact:name>embeddedsw.dts.params.altr,reset-addr</ipxact:name>
+          <ipxact:value>0x00020000</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.params.clock-frequency" type="string">
+          <ipxact:name>embeddedsw.dts.params.clock-frequency</ipxact:name>
+          <ipxact:value>100000000u</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.params.dcache-line-size" type="string">
+          <ipxact:name>embeddedsw.dts.params.dcache-line-size</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.params.dcache-size" type="string">
+          <ipxact:name>embeddedsw.dts.params.dcache-size</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.params.icache-line-size" type="string">
+          <ipxact:name>embeddedsw.dts.params.icache-line-size</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.params.icache-size" type="string">
+          <ipxact:name>embeddedsw.dts.params.icache-size</ipxact:name>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="embeddedsw.dts.vendor" type="string">
+          <ipxact:name>embeddedsw.dts.vendor</ipxact:name>
+          <ipxact:value>altr</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
     </altera:altera_assignments>
     <altera:altera_system_parameters>
-      <spirit:parameters>
-        <spirit:parameter>
-          <spirit:name>device</spirit:name>
-          <spirit:displayName>Device</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>deviceFamily</spirit:name>
-          <spirit:displayName>Device family</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>deviceSpeedGrade</spirit:name>
-          <spirit:displayName>Device Speed Grade</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>generationId</spirit:name>
-          <spirit:displayName>Generation Id</spirit:displayName>
-          <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>bonusData</spirit:name>
-          <spirit:displayName>bonusData</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="bonusData">bonusData 
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element cpu_0
+   {
+      datum _originalVersion
+      {
+         value = "18.0";
+         type = "String";
+      }
+   }
 }
-</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>hideFromIPCatalog</spirit:name>
-          <spirit:displayName>Hide from IP Catalog</spirit:displayName>
-          <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">true</spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>lockedInterfaceDefinition</spirit:name>
-          <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
-    <interfaces>
-        <interface>
-            <name>clk</name>
-            <type>clock</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>ptfSchematicName</key>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>custom_instruction_master</name>
-            <type>nios_custom_instruction</type>
-            <isStart>true</isStart>
-            <ports>
-                <port>
-                    <name>dummy_ci_port</name>
-                    <role>readra</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>CIName</key>
-                        <value></value>
-                    </entry>
-                    <entry>
-                        <key>addressWidth</key>
-                        <value>8</value>
-                    </entry>
-                    <entry>
-                        <key>clockCycle</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>enabled</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>maxAddressWidth</key>
-                        <value>8</value>
-                    </entry>
-                    <entry>
-                        <key>opcodeExtension</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>sharedCombinationalAndMulticycle</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>data_master</name>
-            <type>avalon</type>
-            <isStart>true</isStart>
-            <ports>
-                <port>
-                    <name>d_address</name>
-                    <role>address</role>
-                    <direction>Output</direction>
-                    <width>21</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>d_byteenable</name>
-                    <role>byteenable</role>
-                    <direction>Output</direction>
-                    <width>4</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>d_read</name>
-                    <role>read</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>d_readdata</name>
-                    <role>readdata</role>
-                    <direction>Input</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>d_waitrequest</name>
-                    <role>waitrequest</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>d_write</name>
-                    <role>write</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>d_writedata</name>
-                    <role>writedata</role>
-                    <direction>Output</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>debug_mem_slave_debugaccess_to_roms</name>
-                    <role>debugaccess</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>debug.providesServices</key>
-                        <value>master</value>
-                    </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>adaptsTo</key>
-                    </entry>
-                    <entry>
-                        <key>addressGroup</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>addressUnits</key>
-                        <value>SYMBOLS</value>
-                    </entry>
-                    <entry>
-                        <key>alwaysBurstMaxBurst</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>associatedClock</key>
-                        <value>clk</value>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                        <value>reset</value>
-                    </entry>
-                    <entry>
-                        <key>bitsPerSymbol</key>
-                        <value>8</value>
-                    </entry>
-                    <entry>
-                        <key>burstOnBurstBoundariesOnly</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>burstcountUnits</key>
-                        <value>WORDS</value>
-                    </entry>
-                    <entry>
-                        <key>constantBurstBehavior</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>dBSBigEndian</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>doStreamReads</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>doStreamWrites</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>holdTime</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>interleaveBursts</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isAsynchronous</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isBigEndian</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isReadable</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isWriteable</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>linewrapBursts</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>maxAddressWidth</key>
-                        <value>32</value>
-                    </entry>
-                    <entry>
-                        <key>maximumPendingReadTransactions</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>maximumPendingWriteTransactions</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>minimumReadLatency</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>minimumResponseLatency</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>readLatency</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>readWaitTime</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>registerIncomingSignals</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>registerOutgoingSignals</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>setupTime</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>timingUnits</key>
-                        <value>Cycles</value>
-                    </entry>
-                    <entry>
-                        <key>waitrequestAllowance</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>writeWaitTime</key>
-                        <value>0</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>debug_mem_slave</name>
-            <type>avalon</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>debug_mem_slave_address</name>
-                    <role>address</role>
-                    <direction>Input</direction>
-                    <width>9</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>debug_mem_slave_byteenable</name>
-                    <role>byteenable</role>
-                    <direction>Input</direction>
-                    <width>4</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>debug_mem_slave_debugaccess</name>
-                    <role>debugaccess</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>debug_mem_slave_read</name>
-                    <role>read</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>debug_mem_slave_readdata</name>
-                    <role>readdata</role>
-                    <direction>Output</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>debug_mem_slave_waitrequest</name>
-                    <role>waitrequest</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>debug_mem_slave_write</name>
-                    <role>write</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>debug_mem_slave_writedata</name>
-                    <role>writedata</role>
-                    <direction>Input</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>embeddedsw.configuration.hideDevice</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>embeddedsw.configuration.isFlash</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>qsys.ui.connect</key>
-                        <value>instruction_master,data_master</value>
-                    </entry>
-                </assignmentValueMap>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>addressAlignment</key>
-                        <value>DYNAMIC</value>
-                    </entry>
-                    <entry>
-                        <key>addressGroup</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>addressSpan</key>
-                        <value>2048</value>
-                    </entry>
-                    <entry>
-                        <key>addressUnits</key>
-                        <value>WORDS</value>
-                    </entry>
-                    <entry>
-                        <key>alwaysBurstMaxBurst</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>associatedClock</key>
-                        <value>clk</value>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                        <value>reset</value>
-                    </entry>
-                    <entry>
-                        <key>bitsPerSymbol</key>
-                        <value>8</value>
-                    </entry>
-                    <entry>
-                        <key>bridgedAddressOffset</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>bridgesToMaster</key>
-                    </entry>
-                    <entry>
-                        <key>burstOnBurstBoundariesOnly</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>burstcountUnits</key>
-                        <value>WORDS</value>
-                    </entry>
-                    <entry>
-                        <key>constantBurstBehavior</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>explicitAddressSpan</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>holdTime</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>interleaveBursts</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isBigEndian</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isFlash</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isMemoryDevice</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>isNonVolatileStorage</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>linewrapBursts</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>maximumPendingReadTransactions</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>maximumPendingWriteTransactions</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>minimumReadLatency</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>minimumResponseLatency</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>minimumUninterruptedRunLength</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>printableDevice</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>readLatency</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>readWaitStates</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>readWaitTime</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>registerIncomingSignals</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>registerOutgoingSignals</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>setupTime</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>timingUnits</key>
-                        <value>Cycles</value>
-                    </entry>
-                    <entry>
-                        <key>transparentBridge</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>waitrequestAllowance</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>wellBehavedWaitrequest</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>writeLatency</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>writeWaitStates</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>writeWaitTime</key>
-                        <value>0</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>debug_reset_request</name>
-            <type>reset</type>
-            <isStart>true</isStart>
-            <ports>
-                <port>
-                    <name>debug_reset_request</name>
-                    <role>reset</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                        <value>clk</value>
-                    </entry>
-                    <entry>
-                        <key>associatedDirectReset</key>
-                    </entry>
-                    <entry>
-                        <key>associatedResetSinks</key>
-                        <value>none</value>
-                    </entry>
-                    <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>instruction_master</name>
-            <type>avalon</type>
-            <isStart>true</isStart>
-            <ports>
-                <port>
-                    <name>i_address</name>
-                    <role>address</role>
-                    <direction>Output</direction>
-                    <width>18</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>i_read</name>
-                    <role>read</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>i_readdata</name>
-                    <role>readdata</role>
-                    <direction>Input</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-                <port>
-                    <name>i_waitrequest</name>
-                    <role>waitrequest</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>adaptsTo</key>
-                    </entry>
-                    <entry>
-                        <key>addressGroup</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>addressUnits</key>
-                        <value>SYMBOLS</value>
-                    </entry>
-                    <entry>
-                        <key>alwaysBurstMaxBurst</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>associatedClock</key>
-                        <value>clk</value>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                        <value>reset</value>
-                    </entry>
-                    <entry>
-                        <key>bitsPerSymbol</key>
-                        <value>8</value>
-                    </entry>
-                    <entry>
-                        <key>burstOnBurstBoundariesOnly</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>burstcountUnits</key>
-                        <value>WORDS</value>
-                    </entry>
-                    <entry>
-                        <key>constantBurstBehavior</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>dBSBigEndian</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>doStreamReads</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>doStreamWrites</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>holdTime</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>interleaveBursts</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isAsynchronous</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isBigEndian</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isReadable</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>isWriteable</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>linewrapBursts</key>
-                        <value>true</value>
-                    </entry>
-                    <entry>
-                        <key>maxAddressWidth</key>
-                        <value>32</value>
-                    </entry>
-                    <entry>
-                        <key>maximumPendingReadTransactions</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>maximumPendingWriteTransactions</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>minimumReadLatency</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>minimumResponseLatency</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>readLatency</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>readWaitTime</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>registerIncomingSignals</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>registerOutgoingSignals</key>
-                        <value>false</value>
-                    </entry>
-                    <entry>
-                        <key>setupTime</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>timingUnits</key>
-                        <value>Cycles</value>
-                    </entry>
-                    <entry>
-                        <key>waitrequestAllowance</key>
-                        <value>0</value>
-                    </entry>
-                    <entry>
-                        <key>writeWaitTime</key>
-                        <value>0</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>irq</name>
-            <type>interrupt</type>
-            <isStart>true</isStart>
-            <ports>
-                <port>
-                    <name>irq</name>
-                    <role>irq</role>
-                    <direction>Input</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedAddressablePoint</key>
-                        <value>qsys_unb2c_minimal_cpu_0.data_master</value>
-                    </entry>
-                    <entry>
-                        <key>associatedClock</key>
-                        <value>clk</value>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                        <value>reset</value>
-                    </entry>
-                    <entry>
-                        <key>irqMap</key>
-                    </entry>
-                    <entry>
-                        <key>irqScheme</key>
-                        <value>INDIVIDUAL_REQUESTS</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>reset</name>
-            <type>reset</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>reset_n</name>
-                    <role>reset_n</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-                <port>
-                    <name>reset_req</name>
-                    <role>reset_req</role>
-                    <direction>Input</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                        <value>clk</value>
-                    </entry>
-                    <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-    </interfaces>
-</boundaryDefinition>]]></spirit:value>
-        </spirit:parameter>
-        <spirit:parameter>
-          <spirit:name>systemInfos</spirit:name>
-          <spirit:displayName>systemInfos</spirit:displayName>
-          <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
-    <connPtSystemInfos>
-        <entry>
-            <key>clk</key>
-            <value>
-                <connectionPointName>clk</connectionPointName>
-                <suppliedSystemInfos>
-                    <entry>
-                        <key>CLOCK_DOMAIN</key>
-                        <value>1</value>
-                    </entry>
-                    <entry>
-                        <key>CLOCK_RATE</key>
-                        <value>100000000</value>
-                    </entry>
-                    <entry>
-                        <key>RESET_DOMAIN</key>
-                        <value>1</value>
-                    </entry>
-                </suppliedSystemInfos>
-                <consumedSystemInfos/>
-            </value>
-        </entry>
-        <entry>
-            <key>custom_instruction_master</key>
-            <value>
-                <connectionPointName>custom_instruction_master</connectionPointName>
-                <suppliedSystemInfos>
-                    <entry>
-                        <key>CUSTOM_INSTRUCTION_SLAVES</key>
-                        <value></value>
-                    </entry>
-                </suppliedSystemInfos>
-                <consumedSystemInfos/>
-            </value>
-        </entry>
-        <entry>
-            <key>data_master</key>
-            <value>
-                <connectionPointName>data_master</connectionPointName>
-                <suppliedSystemInfos>
-                    <entry>
-                        <key>ADDRESS_MAP</key>
-                        <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x40000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_jesd.mem' start='0x100000' end='0x140000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
-                    </entry>
-                    <entry>
-                        <key>ADDRESS_WIDTH</key>
-                        <value>21</value>
-                    </entry>
-                </suppliedSystemInfos>
-                <consumedSystemInfos/>
-            </value>
-        </entry>
-        <entry>
-            <key>debug_mem_slave</key>
-            <value>
-                <connectionPointName>debug_mem_slave</connectionPointName>
-                <suppliedSystemInfos/>
-                <consumedSystemInfos>
-                    <entry>
-                        <key>ADDRESS_MAP</key>
-                        <value>&lt;address-map&gt;&lt;slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /&gt;&lt;/address-map&gt;</value>
-                    </entry>
-                    <entry>
-                        <key>ADDRESS_WIDTH</key>
-                        <value>11</value>
-                    </entry>
-                    <entry>
-                        <key>MAX_SLAVE_DATA_WIDTH</key>
-                        <value>32</value>
-                    </entry>
-                </consumedSystemInfos>
-            </value>
-        </entry>
-        <entry>
-            <key>instruction_master</key>
-            <value>
-                <connectionPointName>instruction_master</connectionPointName>
-                <suppliedSystemInfos>
-                    <entry>
-                        <key>ADDRESS_MAP</key>
-                        <value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
-                    </entry>
-                    <entry>
-                        <key>ADDRESS_WIDTH</key>
-                        <value>18</value>
-                    </entry>
-                </suppliedSystemInfos>
-                <consumedSystemInfos/>
-            </value>
-        </entry>
-        <entry>
-            <key>irq</key>
-            <value>
-                <connectionPointName>irq</connectionPointName>
-                <suppliedSystemInfos>
-                    <entry>
-                        <key>INTERRUPTS_USED</key>
-                        <value>7</value>
-                    </entry>
-                </suppliedSystemInfos>
-                <consumedSystemInfos/>
-            </value>
-        </entry>
-    </connPtSystemInfos>
-</systemInfosDefinition>]]></spirit:value>
-        </spirit:parameter>
-      </spirit:parameters>
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>true</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;reset_n&lt;/name&gt;
+                    &lt;role&gt;reset_n&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;reset_req&lt;/name&gt;
+                    &lt;role&gt;reset_req&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;clk&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;data_master&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;true&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;d_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;20&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;d_byteenable&lt;/name&gt;
+                    &lt;role&gt;byteenable&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;4&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;d_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;d_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;d_waitrequest&lt;/name&gt;
+                    &lt;role&gt;waitrequest&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;d_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;d_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_mem_slave_debugaccess_to_roms&lt;/name&gt;
+                    &lt;role&gt;debugaccess&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;debug.providesServices&lt;/key&gt;
+                        &lt;value&gt;master&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;adaptsTo&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;SYMBOLS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;clk&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;true&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;dBSBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;doStreamReads&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;doStreamWrites&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isAsynchronous&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isReadable&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isWriteable&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maxAddressWidth&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;true&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;instruction_master&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;true&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;i_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;18&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;i_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;i_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;i_waitrequest&lt;/name&gt;
+                    &lt;role&gt;waitrequest&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;adaptsTo&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;SYMBOLS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;true&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;clk&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;dBSBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;doStreamReads&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;doStreamWrites&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isAsynchronous&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isReadable&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isWriteable&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;true&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maxAddressWidth&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;irq&lt;/name&gt;
+            &lt;type&gt;interrupt&lt;/type&gt;
+            &lt;isStart&gt;true&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;irq&lt;/name&gt;
+                    &lt;role&gt;irq&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedAddressablePoint&lt;/key&gt;
+                        &lt;value&gt;qsys_lofar2_unb2b_adc_cpu_0.data_master&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;clk&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;irqMap&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;irqScheme&lt;/key&gt;
+                        &lt;value&gt;INDIVIDUAL_REQUESTS&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;debug_reset_request&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;true&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_reset_request&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;clk&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedDirectReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedResetSinks&lt;/key&gt;
+                        &lt;value&gt;none&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;debug_mem_slave&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_mem_slave_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;9&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_mem_slave_byteenable&lt;/name&gt;
+                    &lt;role&gt;byteenable&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;4&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_mem_slave_debugaccess&lt;/name&gt;
+                    &lt;role&gt;debugaccess&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_mem_slave_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_mem_slave_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_mem_slave_waitrequest&lt;/name&gt;
+                    &lt;role&gt;waitrequest&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_mem_slave_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;debug_mem_slave_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.hideDevice&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;qsys.ui.connect&lt;/key&gt;
+                        &lt;value&gt;instruction_master,data_master&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;2048&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;clk&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;true&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;true&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;custom_instruction_master&lt;/name&gt;
+            &lt;type&gt;nios_custom_instruction&lt;/type&gt;
+            &lt;isStart&gt;true&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;dummy_ci_port&lt;/name&gt;
+                    &lt;role&gt;readra&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CIName&lt;/key&gt;
+                        &lt;value&gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressWidth&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockCycle&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;enabled&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maxAddressWidth&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;opcodeExtension&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;sharedCombinationalAndMulticycle&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;clk&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;clk&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_DOMAIN&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;RESET_DOMAIN&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;custom_instruction_master&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;custom_instruction_master&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CUSTOM_INSTRUCTION_SLAVES&lt;/key&gt;
+                        &lt;value&gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;data_master&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;data_master&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&amp;gt;&amp;lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&amp;gt;&amp;lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&amp;gt;&amp;lt;slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /&amp;gt;&amp;lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /&amp;gt;&amp;lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&amp;gt;&amp;lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /&amp;gt;&amp;lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;slave name='jesd204b.mem' start='0x40000' end='0x44000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_monitor_input.mem' start='0x48000' end='0x48400' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_wg.mem' start='0x4C000' end='0x4C100' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_source.mem' start='0x4C100' end='0x4C110' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_bsn_scheduler.mem' start='0x4C110' end='0x4C118' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_dp_shiftram.mem' start='0x4C120' end='0x4C140' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_wg.mem' start='0x50000' end='0x60000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_diag_data_buffer_jesd.mem' start='0x60000' end='0x64000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x64000' end='0x68000' datawidth='32' /&amp;gt;&amp;lt;slave name='reg_aduh_monitor.mem' start='0x68000' end='0x68100' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_aduh_monitor.mem' start='0x70000' end='0x74000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0xC0000' datawidth='32' /&amp;gt;&amp;lt;slave name='ram_diag_data_buffer_bsn.mem' start='0xC0000' end='0x100000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;20&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;debug_mem_slave&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;debug_mem_slave&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;11&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;instruction_master&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;instruction_master&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;18&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;irq&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;irq&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;INTERRUPTS_USED&lt;/key&gt;
+                        &lt;value&gt;7&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="clk" altera:internal="cpu_0.clk" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_cpu_0.clk" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="clk" altera:internal="clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="custom_instruction_master" altera:internal="cpu_0.custom_instruction_master" altera:type="nios_custom_instruction" altera:dir="start">
+      <altera:interface_mapping altera:name="custom_instruction_master" altera:internal="qsys_lofar2_unb2b_adc_cpu_0.custom_instruction_master" altera:type="nios_custom_instruction" altera:dir="start">
         <altera:port_mapping altera:name="dummy_ci_port" altera:internal="dummy_ci_port"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="data_master" altera:internal="cpu_0.data_master" altera:type="avalon" altera:dir="start">
+      <altera:interface_mapping altera:name="data_master" altera:internal="qsys_lofar2_unb2b_adc_cpu_0.data_master" altera:type="avalon" altera:dir="start">
         <altera:port_mapping altera:name="d_address" altera:internal="d_address"></altera:port_mapping>
         <altera:port_mapping altera:name="d_byteenable" altera:internal="d_byteenable"></altera:port_mapping>
         <altera:port_mapping altera:name="d_read" altera:internal="d_read"></altera:port_mapping>
@@ -3572,7 +3672,7 @@
         <altera:port_mapping altera:name="d_writedata" altera:internal="d_writedata"></altera:port_mapping>
         <altera:port_mapping altera:name="debug_mem_slave_debugaccess_to_roms" altera:internal="debug_mem_slave_debugaccess_to_roms"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="debug_mem_slave" altera:internal="cpu_0.debug_mem_slave" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="debug_mem_slave" altera:internal="qsys_lofar2_unb2b_adc_cpu_0.debug_mem_slave" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="debug_mem_slave_address" altera:internal="debug_mem_slave_address"></altera:port_mapping>
         <altera:port_mapping altera:name="debug_mem_slave_byteenable" altera:internal="debug_mem_slave_byteenable"></altera:port_mapping>
         <altera:port_mapping altera:name="debug_mem_slave_debugaccess" altera:internal="debug_mem_slave_debugaccess"></altera:port_mapping>
@@ -3582,24 +3682,24 @@
         <altera:port_mapping altera:name="debug_mem_slave_write" altera:internal="debug_mem_slave_write"></altera:port_mapping>
         <altera:port_mapping altera:name="debug_mem_slave_writedata" altera:internal="debug_mem_slave_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="debug_reset_request" altera:internal="cpu_0.debug_reset_request" altera:type="reset" altera:dir="start">
+      <altera:interface_mapping altera:name="debug_reset_request" altera:internal="qsys_lofar2_unb2b_adc_cpu_0.debug_reset_request" altera:type="reset" altera:dir="start">
         <altera:port_mapping altera:name="debug_reset_request" altera:internal="debug_reset_request"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="instruction_master" altera:internal="cpu_0.instruction_master" altera:type="avalon" altera:dir="start">
+      <altera:interface_mapping altera:name="instruction_master" altera:internal="qsys_lofar2_unb2b_adc_cpu_0.instruction_master" altera:type="avalon" altera:dir="start">
         <altera:port_mapping altera:name="i_address" altera:internal="i_address"></altera:port_mapping>
         <altera:port_mapping altera:name="i_read" altera:internal="i_read"></altera:port_mapping>
         <altera:port_mapping altera:name="i_readdata" altera:internal="i_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="i_waitrequest" altera:internal="i_waitrequest"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="irq" altera:internal="cpu_0.irq" altera:type="interrupt" altera:dir="start">
+      <altera:interface_mapping altera:name="irq" altera:internal="qsys_lofar2_unb2b_adc_cpu_0.irq" altera:type="interrupt" altera:dir="start">
         <altera:port_mapping altera:name="irq" altera:internal="irq"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="cpu_0.reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_cpu_0.reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping>
         <altera:port_mapping altera:name="reset_req" altera:internal="reset_req"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
     <altera:altera_has_warnings>false</altera:altera_has_warnings>
     <altera:altera_has_errors>false</altera:altera_has_errors>
-  </spirit:vendorExtensions>
-</spirit:component>
\ No newline at end of file
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_0.ip
rename to applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
index 24b78eab8573743c9c959518b95e18b963711a97..aa47144a0c1be54cce7e1e509bbd8351262ee44f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg_0</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2b_adc_ram_wg_0</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2b_adc_jesd204b</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_jesd204b</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -139,7 +139,7 @@
         <ipxact:parameter parameterId="addressSpan" type="string">
           <ipxact:name>addressSpan</ipxact:name>
           <ipxact:displayName>Address span</ipxact:displayName>
-          <ipxact:value>4096</ipxact:value>
+          <ipxact:value>16384</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="addressUnits" type="string">
           <ipxact:name>addressUnits</ipxact:name>
@@ -630,6 +630,7 @@
         <ipxact:fileSetRef>
           <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
         </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
       </ipxact:componentInstantiation>
     </ipxact:instantiations>
     <ipxact:ports>
@@ -637,6 +638,7 @@
         <ipxact:name>csi_system_clk</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -649,6 +651,7 @@
         <ipxact:name>csi_system_reset</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -664,7 +667,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>9</ipxact:right>
+              <ipxact:right>11</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -679,6 +682,7 @@
         <ipxact:name>avs_mem_write</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -709,6 +713,7 @@
         <ipxact:name>avs_mem_read</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -739,6 +744,7 @@
         <ipxact:name>coe_reset_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -751,6 +757,7 @@
         <ipxact:name>coe_clk_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -766,7 +773,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>9</ipxact:right>
+              <ipxact:right>11</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -781,6 +788,7 @@
         <ipxact:name>coe_write_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -811,6 +819,7 @@
         <ipxact:name>coe_read_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -842,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg_0</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2b_adc_jesd204b</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -851,7 +860,7 @@
         <ipxact:parameter parameterId="g_adr_w" type="int">
           <ipxact:name>g_adr_w</ipxact:name>
           <ipxact:displayName>g_adr_w</ipxact:displayName>
-          <ipxact:value>10</ipxact:value>
+          <ipxact:value>12</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="g_dat_w" type="int">
           <ipxact:name>g_dat_w</ipxact:name>
@@ -861,7 +870,7 @@
         <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
           <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
           <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
-          <ipxact:value>-1</ipxact:value>
+          <ipxact:value>100000000</ipxact:value>
         </ipxact:parameter>
       </ipxact:parameters>
     </altera:altera_module_parameters>
@@ -892,6 +901,17 @@
           <ipxact:displayName>bonusData</ipxact:displayName>
           <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_jesd204b
+   {
+   }
 }
 </ipxact:value>
         </ipxact:parameter>
@@ -977,7 +997,7 @@
                     &lt;name&gt;avs_mem_address&lt;/name&gt;
                     &lt;role&gt;address&lt;/role&gt;
                     &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;width&gt;12&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1046,7 +1066,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressSpan&lt;/key&gt;
-                        &lt;value&gt;4096&lt;/value&gt;
+                        &lt;value&gt;16384&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressUnits&lt;/key&gt;
@@ -1275,7 +1295,7 @@
                     &lt;name&gt;coe_address_export&lt;/name&gt;
                     &lt;role&gt;export&lt;/role&gt;
                     &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;width&gt;12&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1442,11 +1462,11 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
-                        &lt;value&gt;12&lt;/value&gt;
+                        &lt;value&gt;14&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
@@ -1462,7 +1482,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;-1&lt;/value&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/suppliedSystemInfos&gt;
                 &lt;consumedSystemInfos/&gt;
@@ -1474,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_0.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_jesd204b.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_1.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_1.ip
rename to applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
index 035bf2c50c07bb6ce22cbdb45cc71acdf2f13c02..13dd14c5898df3b8cd453c0ca9ee28c570398a88 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_1.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg_1</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2b_adc_ram_wg_1</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2b_adc_ram_aduh_monitor</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_ram_wg</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -139,7 +139,7 @@
         <ipxact:parameter parameterId="addressSpan" type="string">
           <ipxact:name>addressSpan</ipxact:name>
           <ipxact:displayName>Address span</ipxact:displayName>
-          <ipxact:value>4096</ipxact:value>
+          <ipxact:value>16384</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="addressUnits" type="string">
           <ipxact:name>addressUnits</ipxact:name>
@@ -630,6 +630,7 @@
         <ipxact:fileSetRef>
           <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
         </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
       </ipxact:componentInstantiation>
     </ipxact:instantiations>
     <ipxact:ports>
@@ -637,6 +638,7 @@
         <ipxact:name>csi_system_clk</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -649,6 +651,7 @@
         <ipxact:name>csi_system_reset</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -664,7 +667,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>9</ipxact:right>
+              <ipxact:right>11</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -679,6 +682,7 @@
         <ipxact:name>avs_mem_write</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -709,6 +713,7 @@
         <ipxact:name>avs_mem_read</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -739,6 +744,7 @@
         <ipxact:name>coe_reset_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -751,6 +757,7 @@
         <ipxact:name>coe_clk_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -766,7 +773,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>9</ipxact:right>
+              <ipxact:right>11</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -781,6 +788,7 @@
         <ipxact:name>coe_write_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -811,6 +819,7 @@
         <ipxact:name>coe_read_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -842,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg_1</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2b_adc_ram_aduh_monitor</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -851,7 +860,7 @@
         <ipxact:parameter parameterId="g_adr_w" type="int">
           <ipxact:name>g_adr_w</ipxact:name>
           <ipxact:displayName>g_adr_w</ipxact:displayName>
-          <ipxact:value>10</ipxact:value>
+          <ipxact:value>12</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="g_dat_w" type="int">
           <ipxact:name>g_dat_w</ipxact:name>
@@ -861,7 +870,7 @@
         <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
           <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
           <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
-          <ipxact:value>-1</ipxact:value>
+          <ipxact:value>100000000</ipxact:value>
         </ipxact:parameter>
       </ipxact:parameters>
     </altera:altera_module_parameters>
@@ -892,6 +901,17 @@
           <ipxact:displayName>bonusData</ipxact:displayName>
           <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_ram_wg
+   {
+   }
 }
 </ipxact:value>
         </ipxact:parameter>
@@ -977,7 +997,7 @@
                     &lt;name&gt;avs_mem_address&lt;/name&gt;
                     &lt;role&gt;address&lt;/role&gt;
                     &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;width&gt;12&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1046,7 +1066,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressSpan&lt;/key&gt;
-                        &lt;value&gt;4096&lt;/value&gt;
+                        &lt;value&gt;16384&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressUnits&lt;/key&gt;
@@ -1275,7 +1295,7 @@
                     &lt;name&gt;coe_address_export&lt;/name&gt;
                     &lt;role&gt;export&lt;/role&gt;
                     &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;width&gt;12&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1442,11 +1462,11 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
-                        &lt;value&gt;12&lt;/value&gt;
+                        &lt;value&gt;14&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
@@ -1462,7 +1482,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;-1&lt;/value&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/suppliedSystemInfos&gt;
                 &lt;consumedSystemInfos/&gt;
@@ -1474,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_1.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_3.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
similarity index 96%
rename from applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_3.ip
rename to applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
index 6ae4f8598bf5189019b8d7a65212502220e5ef45..c8cfd35db3c11359524f5f011335176b0a7a17d0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_3.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg_3</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2b_adc_reg_wg_3</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_ram_wg</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -139,7 +139,7 @@
         <ipxact:parameter parameterId="addressSpan" type="string">
           <ipxact:name>addressSpan</ipxact:name>
           <ipxact:displayName>Address span</ipxact:displayName>
-          <ipxact:value>16</ipxact:value>
+          <ipxact:value>262144</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="addressUnits" type="string">
           <ipxact:name>addressUnits</ipxact:name>
@@ -630,6 +630,7 @@
         <ipxact:fileSetRef>
           <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
         </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
       </ipxact:componentInstantiation>
     </ipxact:instantiations>
     <ipxact:ports>
@@ -637,6 +638,7 @@
         <ipxact:name>csi_system_clk</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -649,6 +651,7 @@
         <ipxact:name>csi_system_reset</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -664,7 +667,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>1</ipxact:right>
+              <ipxact:right>15</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -679,6 +682,7 @@
         <ipxact:name>avs_mem_write</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -709,6 +713,7 @@
         <ipxact:name>avs_mem_read</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -739,6 +744,7 @@
         <ipxact:name>coe_reset_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -751,6 +757,7 @@
         <ipxact:name>coe_clk_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -766,7 +773,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>1</ipxact:right>
+              <ipxact:right>15</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -781,6 +788,7 @@
         <ipxact:name>coe_write_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -811,6 +819,7 @@
         <ipxact:name>coe_read_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -842,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg_3</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -851,7 +860,7 @@
         <ipxact:parameter parameterId="g_adr_w" type="int">
           <ipxact:name>g_adr_w</ipxact:name>
           <ipxact:displayName>g_adr_w</ipxact:displayName>
-          <ipxact:value>2</ipxact:value>
+          <ipxact:value>16</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="g_dat_w" type="int">
           <ipxact:name>g_dat_w</ipxact:name>
@@ -861,7 +870,7 @@
         <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
           <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
           <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
-          <ipxact:value>-1</ipxact:value>
+          <ipxact:value>100000000</ipxact:value>
         </ipxact:parameter>
       </ipxact:parameters>
     </altera:altera_module_parameters>
@@ -892,6 +901,17 @@
           <ipxact:displayName>bonusData</ipxact:displayName>
           <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_ram_wg
+   {
+   }
 }
 </ipxact:value>
         </ipxact:parameter>
@@ -977,7 +997,7 @@
                     &lt;name&gt;avs_mem_address&lt;/name&gt;
                     &lt;role&gt;address&lt;/role&gt;
                     &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;2&lt;/width&gt;
+                    &lt;width&gt;16&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1046,7 +1066,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressSpan&lt;/key&gt;
-                        &lt;value&gt;16&lt;/value&gt;
+                        &lt;value&gt;262144&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressUnits&lt;/key&gt;
@@ -1275,7 +1295,7 @@
                     &lt;name&gt;coe_address_export&lt;/name&gt;
                     &lt;role&gt;export&lt;/role&gt;
                     &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;2&lt;/width&gt;
+                    &lt;width&gt;16&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1442,11 +1462,11 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
-                        &lt;value&gt;4&lt;/value&gt;
+                        &lt;value&gt;18&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
@@ -1462,7 +1482,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;-1&lt;/value&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/suppliedSystemInfos&gt;
                 &lt;consumedSystemInfos/&gt;
@@ -1474,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_3.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip
new file mode 100644
index 0000000000000000000000000000000000000000..ce78f0e5d55e90957689e280865f0b02ebec53a4
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>ASTRON</ipxact:vendor>
+  <ipxact:library>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</ipxact:name>
+  <ipxact:version>1.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>system</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>system_reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_reset</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>mem</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>262144</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>system_reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
+        <altera:altera_assignments>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
+        </altera:altera_assignments>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_reset_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_clk_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>address</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_address_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>write</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_write_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>writedata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_writedata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>read</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_read_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>readdata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_readdata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>csi_system_clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>csi_system_reset</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>15</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_reset_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_clk_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_address_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>15</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_write_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_writedata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_read_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_readdata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>ASTRON</ipxact:vendor>
+      <ipxact:library>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</ipxact:library>
+      <ipxact:name>avs_common_mm</ipxact:name>
+      <ipxact:version>1.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="g_adr_w" type="int">
+          <ipxact:name>g_adr_w</ipxact:name>
+          <ipxact:displayName>g_adr_w</ipxact:displayName>
+          <ipxact:value>16</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="g_dat_w" type="int">
+          <ipxact:name>g_dat_w</ipxact:name>
+          <ipxact:displayName>g_dat_w</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element ram_diag_data_buffer_jesd
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system_reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_reset&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;mem&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;16&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;262144&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;system_reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_reset_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_clk_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;address&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_address_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;16&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;write&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_write_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;writedata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_writedata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;read&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_read_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;readdata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_readdata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;mem&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x40000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;18&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;system&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_2.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_2.ip
rename to applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
index 88603f883cd6985b79cb29edb9b036aacfc08af9..41d9dc2113e5e244c8f407ff91762ee34f24b908 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_2.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg_2</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2b_adc_reg_wg_2</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_ram_wg</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -139,7 +139,7 @@
         <ipxact:parameter parameterId="addressSpan" type="string">
           <ipxact:name>addressSpan</ipxact:name>
           <ipxact:displayName>Address span</ipxact:displayName>
-          <ipxact:value>16</ipxact:value>
+          <ipxact:value>65536</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="addressUnits" type="string">
           <ipxact:name>addressUnits</ipxact:name>
@@ -630,6 +630,7 @@
         <ipxact:fileSetRef>
           <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
         </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
       </ipxact:componentInstantiation>
     </ipxact:instantiations>
     <ipxact:ports>
@@ -637,6 +638,7 @@
         <ipxact:name>csi_system_clk</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -649,6 +651,7 @@
         <ipxact:name>csi_system_reset</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -664,7 +667,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>1</ipxact:right>
+              <ipxact:right>13</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -679,6 +682,7 @@
         <ipxact:name>avs_mem_write</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -709,6 +713,7 @@
         <ipxact:name>avs_mem_read</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -739,6 +744,7 @@
         <ipxact:name>coe_reset_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -751,6 +757,7 @@
         <ipxact:name>coe_clk_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -766,7 +773,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>1</ipxact:right>
+              <ipxact:right>13</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -781,6 +788,7 @@
         <ipxact:name>coe_write_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -811,6 +819,7 @@
         <ipxact:name>coe_read_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -842,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg_2</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -851,7 +860,7 @@
         <ipxact:parameter parameterId="g_adr_w" type="int">
           <ipxact:name>g_adr_w</ipxact:name>
           <ipxact:displayName>g_adr_w</ipxact:displayName>
-          <ipxact:value>2</ipxact:value>
+          <ipxact:value>14</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="g_dat_w" type="int">
           <ipxact:name>g_dat_w</ipxact:name>
@@ -861,7 +870,7 @@
         <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
           <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
           <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
-          <ipxact:value>-1</ipxact:value>
+          <ipxact:value>100000000</ipxact:value>
         </ipxact:parameter>
       </ipxact:parameters>
     </altera:altera_module_parameters>
@@ -892,6 +901,17 @@
           <ipxact:displayName>bonusData</ipxact:displayName>
           <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_ram_wg
+   {
+   }
 }
 </ipxact:value>
         </ipxact:parameter>
@@ -977,7 +997,7 @@
                     &lt;name&gt;avs_mem_address&lt;/name&gt;
                     &lt;role&gt;address&lt;/role&gt;
                     &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;2&lt;/width&gt;
+                    &lt;width&gt;14&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1046,7 +1066,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressSpan&lt;/key&gt;
-                        &lt;value&gt;16&lt;/value&gt;
+                        &lt;value&gt;65536&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressUnits&lt;/key&gt;
@@ -1275,7 +1295,7 @@
                     &lt;name&gt;coe_address_export&lt;/name&gt;
                     &lt;role&gt;export&lt;/role&gt;
                     &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;2&lt;/width&gt;
+                    &lt;width&gt;14&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1442,11 +1462,11 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
-                        &lt;value&gt;4&lt;/value&gt;
+                        &lt;value&gt;16&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
@@ -1462,7 +1482,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;-1&lt;/value&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/suppliedSystemInfos&gt;
                 &lt;consumedSystemInfos/&gt;
@@ -1474,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_2.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_2.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
similarity index 96%
rename from applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_2.ip
rename to applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
index f2e4d6c7311d868a8a8b2a7404009bf63a791f6c..fe170758eae9f13fb9653add6e6c0669a8d1ca27 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_2.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg_2</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2b_adc_ram_wg_2</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2b_adc_reg_aduh_monitor</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_ram_wg</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -139,7 +139,7 @@
         <ipxact:parameter parameterId="addressSpan" type="string">
           <ipxact:name>addressSpan</ipxact:name>
           <ipxact:displayName>Address span</ipxact:displayName>
-          <ipxact:value>4096</ipxact:value>
+          <ipxact:value>256</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="addressUnits" type="string">
           <ipxact:name>addressUnits</ipxact:name>
@@ -630,6 +630,7 @@
         <ipxact:fileSetRef>
           <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
         </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
       </ipxact:componentInstantiation>
     </ipxact:instantiations>
     <ipxact:ports>
@@ -637,6 +638,7 @@
         <ipxact:name>csi_system_clk</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -649,6 +651,7 @@
         <ipxact:name>csi_system_reset</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -664,7 +667,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>9</ipxact:right>
+              <ipxact:right>5</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -679,6 +682,7 @@
         <ipxact:name>avs_mem_write</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -709,6 +713,7 @@
         <ipxact:name>avs_mem_read</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -739,6 +744,7 @@
         <ipxact:name>coe_reset_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -751,6 +757,7 @@
         <ipxact:name>coe_clk_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -766,7 +773,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>9</ipxact:right>
+              <ipxact:right>5</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -781,6 +788,7 @@
         <ipxact:name>coe_write_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -811,6 +819,7 @@
         <ipxact:name>coe_read_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -842,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg_2</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2b_adc_reg_aduh_monitor</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -851,7 +860,7 @@
         <ipxact:parameter parameterId="g_adr_w" type="int">
           <ipxact:name>g_adr_w</ipxact:name>
           <ipxact:displayName>g_adr_w</ipxact:displayName>
-          <ipxact:value>10</ipxact:value>
+          <ipxact:value>6</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="g_dat_w" type="int">
           <ipxact:name>g_dat_w</ipxact:name>
@@ -861,7 +870,7 @@
         <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
           <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
           <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
-          <ipxact:value>-1</ipxact:value>
+          <ipxact:value>100000000</ipxact:value>
         </ipxact:parameter>
       </ipxact:parameters>
     </altera:altera_module_parameters>
@@ -892,6 +901,17 @@
           <ipxact:displayName>bonusData</ipxact:displayName>
           <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_ram_wg
+   {
+   }
 }
 </ipxact:value>
         </ipxact:parameter>
@@ -977,7 +997,7 @@
                     &lt;name&gt;avs_mem_address&lt;/name&gt;
                     &lt;role&gt;address&lt;/role&gt;
                     &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;width&gt;6&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1046,7 +1066,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressSpan&lt;/key&gt;
-                        &lt;value&gt;4096&lt;/value&gt;
+                        &lt;value&gt;256&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressUnits&lt;/key&gt;
@@ -1275,7 +1295,7 @@
                     &lt;name&gt;coe_address_export&lt;/name&gt;
                     &lt;role&gt;export&lt;/role&gt;
                     &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;width&gt;6&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1442,11 +1462,11 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
-                        &lt;value&gt;12&lt;/value&gt;
+                        &lt;value&gt;8&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
@@ -1462,7 +1482,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;-1&lt;/value&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/suppliedSystemInfos&gt;
                 &lt;consumedSystemInfos/&gt;
@@ -1474,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_2.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
index 2df9312500bc97f54bf5ba731047f4885cd3708d..d05336eb146441f2506b5e128dc5e5afeb24e775 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
@@ -630,6 +630,7 @@
         <ipxact:fileSetRef>
           <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
         </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
       </ipxact:componentInstantiation>
     </ipxact:instantiations>
     <ipxact:ports>
@@ -637,6 +638,7 @@
         <ipxact:name>csi_system_clk</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -649,6 +651,7 @@
         <ipxact:name>csi_system_reset</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -679,6 +682,7 @@
         <ipxact:name>avs_mem_write</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -709,6 +713,7 @@
         <ipxact:name>avs_mem_read</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -739,6 +744,7 @@
         <ipxact:name>coe_reset_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -751,6 +757,7 @@
         <ipxact:name>coe_clk_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -781,6 +788,7 @@
         <ipxact:name>coe_write_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -811,6 +819,7 @@
         <ipxact:name>coe_read_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -861,7 +870,7 @@
         <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
           <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
           <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
-          <ipxact:value>-1</ipxact:value>
+          <ipxact:value>100000000</ipxact:value>
         </ipxact:parameter>
       </ipxact:parameters>
     </altera:altera_module_parameters>
@@ -892,6 +901,17 @@
           <ipxact:displayName>bonusData</ipxact:displayName>
           <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_reg_bsn_monitor_input
+   {
+   }
 }
 </ipxact:value>
         </ipxact:parameter>
@@ -1462,7 +1482,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;-1&lt;/value&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/suppliedSystemInfos&gt;
                 &lt;consumedSystemInfos/&gt;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_3.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
similarity index 96%
rename from applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_3.ip
rename to applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
index 0cb927249768eea4ca56a587406a51656c30ef53..068d24058254482a0edfc378a6189bebc1f3d217 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_3.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg_3</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2b_adc_ram_wg_3</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -139,7 +139,7 @@
         <ipxact:parameter parameterId="addressSpan" type="string">
           <ipxact:name>addressSpan</ipxact:name>
           <ipxact:displayName>Address span</ipxact:displayName>
-          <ipxact:value>4096</ipxact:value>
+          <ipxact:value>8</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="addressUnits" type="string">
           <ipxact:name>addressUnits</ipxact:name>
@@ -630,6 +630,7 @@
         <ipxact:fileSetRef>
           <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
         </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
       </ipxact:componentInstantiation>
     </ipxact:instantiations>
     <ipxact:ports>
@@ -637,6 +638,7 @@
         <ipxact:name>csi_system_clk</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -649,6 +651,7 @@
         <ipxact:name>csi_system_reset</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -661,12 +664,7 @@
         <ipxact:name>avs_mem_address</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
-          <ipxact:vectors>
-            <ipxact:vector>
-              <ipxact:left>0</ipxact:left>
-              <ipxact:right>9</ipxact:right>
-            </ipxact:vector>
-          </ipxact:vectors>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
@@ -679,6 +677,7 @@
         <ipxact:name>avs_mem_write</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -709,6 +708,7 @@
         <ipxact:name>avs_mem_read</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -739,6 +739,7 @@
         <ipxact:name>coe_reset_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -751,6 +752,7 @@
         <ipxact:name>coe_clk_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -763,12 +765,7 @@
         <ipxact:name>coe_address_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
-          <ipxact:vectors>
-            <ipxact:vector>
-              <ipxact:left>0</ipxact:left>
-              <ipxact:right>9</ipxact:right>
-            </ipxact:vector>
-          </ipxact:vectors>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
@@ -781,6 +778,7 @@
         <ipxact:name>coe_write_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -811,6 +809,7 @@
         <ipxact:name>coe_read_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -842,7 +841,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2b_adc_ram_wg_3</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -851,7 +850,7 @@
         <ipxact:parameter parameterId="g_adr_w" type="int">
           <ipxact:name>g_adr_w</ipxact:name>
           <ipxact:displayName>g_adr_w</ipxact:displayName>
-          <ipxact:value>10</ipxact:value>
+          <ipxact:value>1</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="g_dat_w" type="int">
           <ipxact:name>g_dat_w</ipxact:name>
@@ -861,7 +860,7 @@
         <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
           <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
           <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
-          <ipxact:value>-1</ipxact:value>
+          <ipxact:value>100000000</ipxact:value>
         </ipxact:parameter>
       </ipxact:parameters>
     </altera:altera_module_parameters>
@@ -892,6 +891,17 @@
           <ipxact:displayName>bonusData</ipxact:displayName>
           <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_reg_bsn_scheduler
+   {
+   }
 }
 </ipxact:value>
         </ipxact:parameter>
@@ -977,7 +987,7 @@
                     &lt;name&gt;avs_mem_address&lt;/name&gt;
                     &lt;role&gt;address&lt;/role&gt;
                     &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;width&gt;1&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1046,7 +1056,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressSpan&lt;/key&gt;
-                        &lt;value&gt;4096&lt;/value&gt;
+                        &lt;value&gt;8&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressUnits&lt;/key&gt;
@@ -1275,7 +1285,7 @@
                     &lt;name&gt;coe_address_export&lt;/name&gt;
                     &lt;role&gt;export&lt;/role&gt;
                     &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;10&lt;/width&gt;
+                    &lt;width&gt;1&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1442,11 +1452,11 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
-                        &lt;value&gt;12&lt;/value&gt;
+                        &lt;value&gt;3&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
@@ -1462,7 +1472,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;-1&lt;/value&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/suppliedSystemInfos&gt;
                 &lt;consumedSystemInfos/&gt;
@@ -1474,38 +1484,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_ram_wg_3.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_scheduler.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_0.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
similarity index 97%
rename from applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_0.ip
rename to applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
index 1a62f4c1a54956faf18d589bad53d9f3437de9b1..eff2d436dd0eea413932dec84821ef107d3759c0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_0.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
@@ -1,8 +1,8 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg_0</ipxact:library>
-  <ipxact:name>qsys_lofar2_unb2b_adc_reg_wg_0</ipxact:name>
+  <ipxact:library>qsys_lofar2_unb2b_adc_reg_bsn_source</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_reg_bsn_source</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
     <ipxact:busInterface>
@@ -630,6 +630,7 @@
         <ipxact:fileSetRef>
           <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
         </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
       </ipxact:componentInstantiation>
     </ipxact:instantiations>
     <ipxact:ports>
@@ -637,6 +638,7 @@
         <ipxact:name>csi_system_clk</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -649,6 +651,7 @@
         <ipxact:name>csi_system_reset</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -679,6 +682,7 @@
         <ipxact:name>avs_mem_write</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -709,6 +713,7 @@
         <ipxact:name>avs_mem_read</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -739,6 +744,7 @@
         <ipxact:name>coe_reset_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -751,6 +757,7 @@
         <ipxact:name>coe_clk_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -781,6 +788,7 @@
         <ipxact:name>coe_write_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -811,6 +819,7 @@
         <ipxact:name>coe_read_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -842,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg_0</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2b_adc_reg_bsn_source</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -861,7 +870,7 @@
         <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
           <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
           <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
-          <ipxact:value>-1</ipxact:value>
+          <ipxact:value>100000000</ipxact:value>
         </ipxact:parameter>
       </ipxact:parameters>
     </altera:altera_module_parameters>
@@ -892,6 +901,17 @@
           <ipxact:displayName>bonusData</ipxact:displayName>
           <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_reg_bsn_source
+   {
+   }
 }
 </ipxact:value>
         </ipxact:parameter>
@@ -1462,7 +1482,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;-1&lt;/value&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/suppliedSystemInfos&gt;
                 &lt;consumedSystemInfos/&gt;
@@ -1474,38 +1494,38 @@
       </ipxact:parameters>
     </altera:altera_system_parameters>
     <altera:altera_interface_boundary>
-      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.address" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.address" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.clk" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.clk" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.mem" altera:type="avalon" altera:dir="end">
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.mem" altera:type="avalon" altera:dir="end">
         <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
         <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.read" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.read" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.readdata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.readdata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.reset" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.reset" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.system" altera:type="clock" altera:dir="end">
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.system" altera:type="clock" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.system_reset" altera:type="reset" altera:dir="end">
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.system_reset" altera:type="reset" altera:dir="end">
         <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.write" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.write" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
       </altera:interface_mapping>
-      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_reg_wg_0.writedata" altera:type="conduit" altera:dir="end">
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_reg_bsn_source.writedata" altera:type="conduit" altera:dir="end">
         <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
       </altera:interface_mapping>
     </altera:altera_interface_boundary>
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
new file mode 100644
index 0000000000000000000000000000000000000000..b2220e0d2e6e3deb141c064bb81207fd3123cbf6
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>ASTRON</ipxact:vendor>
+  <ipxact:library>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</ipxact:name>
+  <ipxact:version>1.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>system</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>system_reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_reset</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>mem</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>16384</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>system_reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
+        <altera:altera_assignments>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
+        </altera:altera_assignments>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_reset_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_clk_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>address</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_address_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>write</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_write_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>writedata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_writedata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>read</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_read_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>readdata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_readdata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>csi_system_clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>csi_system_reset</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>11</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_reset_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_clk_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_address_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>11</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_write_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_writedata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_read_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_readdata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>ASTRON</ipxact:vendor>
+      <ipxact:library>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn</ipxact:library>
+      <ipxact:name>avs_common_mm</ipxact:name>
+      <ipxact:version>1.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="g_adr_w" type="int">
+          <ipxact:name>g_adr_w</ipxact:name>
+          <ipxact:displayName>g_adr_w</ipxact:displayName>
+          <ipxact:value>12</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="g_dat_w" type="int">
+          <ipxact:name>g_dat_w</ipxact:name>
+          <ipxact:displayName>g_dat_w</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system_reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_reset&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;mem&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;12&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;16384&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;system_reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_reset_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_clk_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;address&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_address_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;12&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;write&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_write_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;writedata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_writedata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;read&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_read_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;readdata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_readdata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;mem&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;14&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;system&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.ip
new file mode 100644
index 0000000000000000000000000000000000000000..d4d5677707e4c859b0e86d7246a89cf0a0f252a5
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>ASTRON</ipxact:vendor>
+  <ipxact:library>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</ipxact:name>
+  <ipxact:version>1.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>system</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>system_reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_reset</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>mem</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>16384</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>system_reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
+        <altera:altera_assignments>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
+        </altera:altera_assignments>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_reset_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_clk_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>address</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_address_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>write</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_write_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>writedata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_writedata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>read</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_read_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>readdata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_readdata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>csi_system_clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>csi_system_reset</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>11</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_reset_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_clk_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_address_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>11</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_write_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_writedata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_read_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_readdata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>ASTRON</ipxact:vendor>
+      <ipxact:library>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</ipxact:library>
+      <ipxact:name>avs_common_mm</ipxact:name>
+      <ipxact:version>1.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="g_adr_w" type="int">
+          <ipxact:name>g_adr_w</ipxact:name>
+          <ipxact:displayName>g_adr_w</ipxact:displayName>
+          <ipxact:value>12</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="g_dat_w" type="int">
+          <ipxact:name>g_dat_w</ipxact:name>
+          <ipxact:displayName>g_dat_w</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system_reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_reset&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;mem&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;12&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;16384&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;system_reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_reset_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_clk_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;address&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_address_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;12&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;write&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_write_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;writedata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_writedata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;read&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_read_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;readdata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_readdata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;mem&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;14&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;system&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
new file mode 100644
index 0000000000000000000000000000000000000000..9515fa078f02da6f6e25e1e86ee177f880bac698
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
@@ -0,0 +1,1535 @@
+<?xml version="1.0" ?>
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+  <ipxact:vendor>ASTRON</ipxact:vendor>
+  <ipxact:library>qsys_lofar2_unb2b_adc_reg_dp_shiftram</ipxact:library>
+  <ipxact:name>qsys_lofar2_unb2b_adc_reg_dp_shiftram</ipxact:name>
+  <ipxact:version>1.0</ipxact:version>
+  <ipxact:busInterfaces>
+    <ipxact:busInterface>
+      <ipxact:name>system</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="clock" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="clock" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>clk</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_clk</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="clockRate" type="longint">
+          <ipxact:name>clockRate</ipxact:name>
+          <ipxact:displayName>Clock rate</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="externallyDriven" type="bit">
+          <ipxact:name>externallyDriven</ipxact:name>
+          <ipxact:displayName>Externally driven</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="ptfSchematicName" type="string">
+          <ipxact:name>ptfSchematicName</ipxact:name>
+          <ipxact:displayName>PTF schematic name</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>system_reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="reset" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="reset" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>reset</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>csi_system_reset</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="synchronousEdges" type="string">
+          <ipxact:name>synchronousEdges</ipxact:name>
+          <ipxact:displayName>Synchronous edges</ipxact:displayName>
+          <ipxact:value>DEASSERT</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>mem</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="avalon" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>address</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_address</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>write</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_write</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>writedata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_writedata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>read</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_read</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>readdata</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>avs_mem_readdata</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="addressAlignment" type="string">
+          <ipxact:name>addressAlignment</ipxact:name>
+          <ipxact:displayName>Slave addressing</ipxact:displayName>
+          <ipxact:value>DYNAMIC</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressGroup" type="int">
+          <ipxact:name>addressGroup</ipxact:name>
+          <ipxact:displayName>Address group</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressSpan" type="string">
+          <ipxact:name>addressSpan</ipxact:name>
+          <ipxact:displayName>Address span</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="addressUnits" type="string">
+          <ipxact:name>addressUnits</ipxact:name>
+          <ipxact:displayName>Address units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="alwaysBurstMaxBurst" type="bit">
+          <ipxact:name>alwaysBurstMaxBurst</ipxact:name>
+          <ipxact:displayName>Always burst maximum burst</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>Associated clock</ipxact:displayName>
+          <ipxact:value>system</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>Associated reset</ipxact:displayName>
+          <ipxact:value>system_reset</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bitsPerSymbol" type="int">
+          <ipxact:name>bitsPerSymbol</ipxact:name>
+          <ipxact:displayName>Bits per symbol</ipxact:displayName>
+          <ipxact:value>8</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgedAddressOffset" type="string">
+          <ipxact:name>bridgedAddressOffset</ipxact:name>
+          <ipxact:displayName>Bridged Address Offset</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bridgesToMaster" type="string">
+          <ipxact:name>bridgesToMaster</ipxact:name>
+          <ipxact:displayName>Bridges to master</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstOnBurstBoundariesOnly" type="bit">
+          <ipxact:name>burstOnBurstBoundariesOnly</ipxact:name>
+          <ipxact:displayName>Burst on burst boundaries only</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="burstcountUnits" type="string">
+          <ipxact:name>burstcountUnits</ipxact:name>
+          <ipxact:displayName>Burstcount units</ipxact:displayName>
+          <ipxact:value>WORDS</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="constantBurstBehavior" type="bit">
+          <ipxact:name>constantBurstBehavior</ipxact:name>
+          <ipxact:displayName>Constant burst behavior</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="explicitAddressSpan" type="string">
+          <ipxact:name>explicitAddressSpan</ipxact:name>
+          <ipxact:displayName>Explicit address span</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="holdTime" type="int">
+          <ipxact:name>holdTime</ipxact:name>
+          <ipxact:displayName>Hold</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="interleaveBursts" type="bit">
+          <ipxact:name>interleaveBursts</ipxact:name>
+          <ipxact:displayName>Interleave bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isBigEndian" type="bit">
+          <ipxact:name>isBigEndian</ipxact:name>
+          <ipxact:displayName>Big endian</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isFlash" type="bit">
+          <ipxact:name>isFlash</ipxact:name>
+          <ipxact:displayName>Flash memory</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isMemoryDevice" type="bit">
+          <ipxact:name>isMemoryDevice</ipxact:name>
+          <ipxact:displayName>Memory device</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="isNonVolatileStorage" type="bit">
+          <ipxact:name>isNonVolatileStorage</ipxact:name>
+          <ipxact:displayName>Non-volatile storage</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="linewrapBursts" type="bit">
+          <ipxact:name>linewrapBursts</ipxact:name>
+          <ipxact:displayName>Linewrap bursts</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingReadTransactions" type="int">
+          <ipxact:name>maximumPendingReadTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending read transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="maximumPendingWriteTransactions" type="int">
+          <ipxact:name>maximumPendingWriteTransactions</ipxact:name>
+          <ipxact:displayName>Maximum pending write transactions</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumReadLatency" type="int">
+          <ipxact:name>minimumReadLatency</ipxact:name>
+          <ipxact:displayName>minimumReadLatency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumResponseLatency" type="int">
+          <ipxact:name>minimumResponseLatency</ipxact:name>
+          <ipxact:displayName>Minimum response latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="minimumUninterruptedRunLength" type="int">
+          <ipxact:name>minimumUninterruptedRunLength</ipxact:name>
+          <ipxact:displayName>Minimum uninterrupted run length</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="printableDevice" type="bit">
+          <ipxact:name>printableDevice</ipxact:name>
+          <ipxact:displayName>Can receive stdout/stderr</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readLatency" type="int">
+          <ipxact:name>readLatency</ipxact:name>
+          <ipxact:displayName>Read latency</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitStates" type="int">
+          <ipxact:name>readWaitStates</ipxact:name>
+          <ipxact:displayName>Read wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="readWaitTime" type="int">
+          <ipxact:name>readWaitTime</ipxact:name>
+          <ipxact:displayName>Read wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerIncomingSignals" type="bit">
+          <ipxact:name>registerIncomingSignals</ipxact:name>
+          <ipxact:displayName>Register incoming signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="registerOutgoingSignals" type="bit">
+          <ipxact:name>registerOutgoingSignals</ipxact:name>
+          <ipxact:displayName>Register outgoing signals</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="setupTime" type="int">
+          <ipxact:name>setupTime</ipxact:name>
+          <ipxact:displayName>Setup</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="timingUnits" type="string">
+          <ipxact:name>timingUnits</ipxact:name>
+          <ipxact:displayName>Timing units</ipxact:displayName>
+          <ipxact:value>Cycles</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="transparentBridge" type="bit">
+          <ipxact:name>transparentBridge</ipxact:name>
+          <ipxact:displayName>Transparent bridge</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="waitrequestAllowance" type="int">
+          <ipxact:name>waitrequestAllowance</ipxact:name>
+          <ipxact:displayName>Waitrequest allowance</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="wellBehavedWaitrequest" type="bit">
+          <ipxact:name>wellBehavedWaitrequest</ipxact:name>
+          <ipxact:displayName>Well-behaved waitrequest</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeLatency" type="int">
+          <ipxact:name>writeLatency</ipxact:name>
+          <ipxact:displayName>Write latency</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitStates" type="int">
+          <ipxact:name>writeWaitStates</ipxact:name>
+          <ipxact:displayName>Write wait states</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="writeWaitTime" type="int">
+          <ipxact:name>writeWaitTime</ipxact:name>
+          <ipxact:displayName>Write wait</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+      <ipxact:vendorExtensions>
+        <altera:altera_assignments>
+          <ipxact:parameters>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isFlash" type="string">
+              <ipxact:name>embeddedsw.configuration.isFlash</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isMemoryDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isMemoryDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isNonVolatileStorage" type="string">
+              <ipxact:name>embeddedsw.configuration.isNonVolatileStorage</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+            <ipxact:parameter parameterId="embeddedsw.configuration.isPrintableDevice" type="string">
+              <ipxact:name>embeddedsw.configuration.isPrintableDevice</ipxact:name>
+              <ipxact:value>0</ipxact:value>
+            </ipxact:parameter>
+          </ipxact:parameters>
+        </altera:altera_assignments>
+      </ipxact:vendorExtensions>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>reset</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_reset_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>clk</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_clk_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>address</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_address_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>write</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_write_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>writedata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_writedata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>read</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_read_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+    <ipxact:busInterface>
+      <ipxact:name>readdata</ipxact:name>
+      <ipxact:busType vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:busType>
+      <ipxact:abstractionTypes>
+        <ipxact:abstractionType>
+          <ipxact:abstractionRef vendor="altera" library="altera" name="conduit" version="19.4"></ipxact:abstractionRef>
+          <ipxact:portMaps>
+            <ipxact:portMap>
+              <ipxact:logicalPort>
+                <ipxact:name>export</ipxact:name>
+              </ipxact:logicalPort>
+              <ipxact:physicalPort>
+                <ipxact:name>coe_readdata_export</ipxact:name>
+              </ipxact:physicalPort>
+            </ipxact:portMap>
+          </ipxact:portMaps>
+        </ipxact:abstractionType>
+      </ipxact:abstractionTypes>
+      <ipxact:slave></ipxact:slave>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="associatedClock" type="string">
+          <ipxact:name>associatedClock</ipxact:name>
+          <ipxact:displayName>associatedClock</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="associatedReset" type="string">
+          <ipxact:name>associatedReset</ipxact:name>
+          <ipxact:displayName>associatedReset</ipxact:displayName>
+          <ipxact:value></ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="prSafe" type="bit">
+          <ipxact:name>prSafe</ipxact:name>
+          <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </ipxact:busInterface>
+  </ipxact:busInterfaces>
+  <ipxact:model>
+    <ipxact:views>
+      <ipxact:view>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+        <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+      </ipxact:view>
+    </ipxact:views>
+    <ipxact:instantiations>
+      <ipxact:componentInstantiation>
+        <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+        <ipxact:moduleName>avs_common_mm</ipxact:moduleName>
+        <ipxact:fileSetRef>
+          <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+        </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
+      </ipxact:componentInstantiation>
+    </ipxact:instantiations>
+    <ipxact:ports>
+      <ipxact:port>
+        <ipxact:name>csi_system_clk</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>csi_system_reset</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_address</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>2</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_write</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_writedata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_read</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>avs_mem_readdata</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_reset_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_clk_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_address_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>2</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_write_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_writedata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_read_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+      <ipxact:port>
+        <ipxact:name>coe_readdata_export</ipxact:name>
+        <ipxact:wire>
+          <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors>
+            <ipxact:vector>
+              <ipxact:left>0</ipxact:left>
+              <ipxact:right>31</ipxact:right>
+            </ipxact:vector>
+          </ipxact:vectors>
+          <ipxact:wireTypeDefs>
+            <ipxact:wireTypeDef>
+              <ipxact:typeName>STD_LOGIC_VECTOR</ipxact:typeName>
+              <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+            </ipxact:wireTypeDef>
+          </ipxact:wireTypeDefs>
+        </ipxact:wire>
+      </ipxact:port>
+    </ipxact:ports>
+  </ipxact:model>
+  <ipxact:vendorExtensions>
+    <altera:entity_info>
+      <ipxact:vendor>ASTRON</ipxact:vendor>
+      <ipxact:library>qsys_lofar2_unb2b_adc_reg_dp_shiftram</ipxact:library>
+      <ipxact:name>avs_common_mm</ipxact:name>
+      <ipxact:version>1.0</ipxact:version>
+    </altera:entity_info>
+    <altera:altera_module_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="g_adr_w" type="int">
+          <ipxact:name>g_adr_w</ipxact:name>
+          <ipxact:displayName>g_adr_w</ipxact:displayName>
+          <ipxact:value>3</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="g_dat_w" type="int">
+          <ipxact:name>g_dat_w</ipxact:name>
+          <ipxact:displayName>g_dat_w</ipxact:displayName>
+          <ipxact:value>32</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
+          <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
+          <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
+          <ipxact:value>100000000</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_module_parameters>
+    <altera:altera_system_parameters>
+      <ipxact:parameters>
+        <ipxact:parameter parameterId="device" type="string">
+          <ipxact:name>device</ipxact:name>
+          <ipxact:displayName>Device</ipxact:displayName>
+          <ipxact:value>10AX115U2F45E1SG</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceFamily" type="string">
+          <ipxact:name>deviceFamily</ipxact:name>
+          <ipxact:displayName>Device family</ipxact:displayName>
+          <ipxact:value>Arria 10</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+          <ipxact:name>deviceSpeedGrade</ipxact:name>
+          <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+          <ipxact:value>1</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="generationId" type="int">
+          <ipxact:name>generationId</ipxact:name>
+          <ipxact:displayName>Generation Id</ipxact:displayName>
+          <ipxact:value>0</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="bonusData" type="string">
+          <ipxact:name>bonusData</ipxact:name>
+          <ipxact:displayName>bonusData</ipxact:displayName>
+          <ipxact:value>bonusData 
+{
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_reg_dp_shiftram
+   {
+   }
+}
+</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+          <ipxact:name>hideFromIPCatalog</ipxact:name>
+          <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+          <ipxact:value>false</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+          <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+          <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+          <ipxact:value>&lt;boundaryDefinition&gt;
+    &lt;interfaces&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system&lt;/name&gt;
+            &lt;type&gt;clock&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_clk&lt;/name&gt;
+                    &lt;role&gt;clk&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;clockRate&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;externallyDriven&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;system_reset&lt;/name&gt;
+            &lt;type&gt;reset&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;csi_system_reset&lt;/name&gt;
+                    &lt;role&gt;reset&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;synchronousEdges&lt;/key&gt;
+                        &lt;value&gt;DEASSERT&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;mem&lt;/name&gt;
+            &lt;type&gt;avalon&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_address&lt;/name&gt;
+                    &lt;role&gt;address&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;3&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_write&lt;/name&gt;
+                    &lt;role&gt;write&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_writedata&lt;/name&gt;
+                    &lt;role&gt;writedata&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_read&lt;/name&gt;
+                    &lt;role&gt;read&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+                &lt;port&gt;
+                    &lt;name&gt;avs_mem_readdata&lt;/name&gt;
+                    &lt;role&gt;readdata&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isFlash&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;embeddedsw.configuration.isPrintableDevice&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/assignmentValueMap&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressAlignment&lt;/key&gt;
+                        &lt;value&gt;DYNAMIC&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressGroup&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressSpan&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;addressUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;alwaysBurstMaxBurst&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                        &lt;value&gt;system&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                        &lt;value&gt;system_reset&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bitsPerSymbol&lt;/key&gt;
+                        &lt;value&gt;8&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgedAddressOffset&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;bridgesToMaster&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstOnBurstBoundariesOnly&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;burstcountUnits&lt;/key&gt;
+                        &lt;value&gt;WORDS&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;constantBurstBehavior&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;explicitAddressSpan&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;holdTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;interleaveBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isBigEndian&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isFlash&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isMemoryDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;isNonVolatileStorage&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;linewrapBursts&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingReadTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;maximumPendingWriteTransactions&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumReadLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumResponseLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;minimumUninterruptedRunLength&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;printableDevice&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readLatency&lt;/key&gt;
+                        &lt;value&gt;1&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;readWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerIncomingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;registerOutgoingSignals&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;setupTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;timingUnits&lt;/key&gt;
+                        &lt;value&gt;Cycles&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;transparentBridge&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;waitrequestAllowance&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;wellBehavedWaitrequest&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeLatency&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitStates&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;writeWaitTime&lt;/key&gt;
+                        &lt;value&gt;0&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;reset&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_reset_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;clk&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_clk_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;address&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_address_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;3&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;write&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_write_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;writedata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_writedata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;read&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_read_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Output&lt;/direction&gt;
+                    &lt;width&gt;1&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+        &lt;interface&gt;
+            &lt;name&gt;readdata&lt;/name&gt;
+            &lt;type&gt;conduit&lt;/type&gt;
+            &lt;isStart&gt;false&lt;/isStart&gt;
+            &lt;ports&gt;
+                &lt;port&gt;
+                    &lt;name&gt;coe_readdata_export&lt;/name&gt;
+                    &lt;role&gt;export&lt;/role&gt;
+                    &lt;direction&gt;Input&lt;/direction&gt;
+                    &lt;width&gt;32&lt;/width&gt;
+                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
+                    &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
+                &lt;/port&gt;
+            &lt;/ports&gt;
+            &lt;assignments&gt;
+                &lt;assignmentValueMap/&gt;
+            &lt;/assignments&gt;
+            &lt;parameters&gt;
+                &lt;parameterValueMap&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedClock&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;associatedReset&lt;/key&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;prSafe&lt;/key&gt;
+                        &lt;value&gt;false&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/parameterValueMap&gt;
+            &lt;/parameters&gt;
+        &lt;/interface&gt;
+    &lt;/interfaces&gt;
+&lt;/boundaryDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+        <ipxact:parameter parameterId="systemInfos" type="string">
+          <ipxact:name>systemInfos</ipxact:name>
+          <ipxact:displayName>systemInfos</ipxact:displayName>
+          <ipxact:value>&lt;systemInfosDefinition&gt;
+    &lt;connPtSystemInfos&gt;
+        &lt;entry&gt;
+            &lt;key&gt;mem&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;mem&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos/&gt;
+                &lt;consumedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
+                        &lt;value&gt;5&lt;/value&gt;
+                    &lt;/entry&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
+                        &lt;value&gt;32&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/consumedSystemInfos&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+        &lt;entry&gt;
+            &lt;key&gt;system&lt;/key&gt;
+            &lt;value&gt;
+                &lt;connectionPointName&gt;system&lt;/connectionPointName&gt;
+                &lt;suppliedSystemInfos&gt;
+                    &lt;entry&gt;
+                        &lt;key&gt;CLOCK_RATE&lt;/key&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
+                    &lt;/entry&gt;
+                &lt;/suppliedSystemInfos&gt;
+                &lt;consumedSystemInfos/&gt;
+            &lt;/value&gt;
+        &lt;/entry&gt;
+    &lt;/connPtSystemInfos&gt;
+&lt;/systemInfosDefinition&gt;</ipxact:value>
+        </ipxact:parameter>
+      </ipxact:parameters>
+    </altera:altera_system_parameters>
+    <altera:altera_interface_boundary>
+      <altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.address" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.clk" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.mem" altera:type="avalon" altera:dir="end">
+        <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+        <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.read" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.readdata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.reset" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.system" altera:type="clock" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.system_reset" altera:type="reset" altera:dir="end">
+        <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.write" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+      </altera:interface_mapping>
+      <altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_adc_reg_dp_shiftram.writedata" altera:type="conduit" altera:dir="end">
+        <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+      </altera:interface_mapping>
+    </altera:altera_interface_boundary>
+    <altera:altera_has_warnings>false</altera:altera_has_warnings>
+    <altera:altera_has_errors>false</altera:altera_has_errors>
+  </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_1.ip b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
similarity index 98%
rename from applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_1.ip
rename to applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
index 56cfc913a0f8646557c2123986f9221dcf4229fc..b1f9a8d101879e73dfe32f88f7aa2ebbe0f84aa3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_1.ip
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
@@ -1,7 +1,7 @@
 <?xml version="1.0" ?>
 <ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
   <ipxact:vendor>ASTRON</ipxact:vendor>
-  <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg_1</ipxact:library>
+  <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg</ipxact:library>
   <ipxact:name>qsys_lofar2_unb2b_adc_reg_wg_1</ipxact:name>
   <ipxact:version>1.0</ipxact:version>
   <ipxact:busInterfaces>
@@ -139,7 +139,7 @@
         <ipxact:parameter parameterId="addressSpan" type="string">
           <ipxact:name>addressSpan</ipxact:name>
           <ipxact:displayName>Address span</ipxact:displayName>
-          <ipxact:value>16</ipxact:value>
+          <ipxact:value>256</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="addressUnits" type="string">
           <ipxact:name>addressUnits</ipxact:name>
@@ -630,6 +630,7 @@
         <ipxact:fileSetRef>
           <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
         </ipxact:fileSetRef>
+        <ipxact:parameters></ipxact:parameters>
       </ipxact:componentInstantiation>
     </ipxact:instantiations>
     <ipxact:ports>
@@ -637,6 +638,7 @@
         <ipxact:name>csi_system_clk</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -649,6 +651,7 @@
         <ipxact:name>csi_system_reset</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -664,7 +667,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>1</ipxact:right>
+              <ipxact:right>5</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -679,6 +682,7 @@
         <ipxact:name>avs_mem_write</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -709,6 +713,7 @@
         <ipxact:name>avs_mem_read</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>in</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -739,6 +744,7 @@
         <ipxact:name>coe_reset_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -751,6 +757,7 @@
         <ipxact:name>coe_clk_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -766,7 +773,7 @@
           <ipxact:vectors>
             <ipxact:vector>
               <ipxact:left>0</ipxact:left>
-              <ipxact:right>1</ipxact:right>
+              <ipxact:right>5</ipxact:right>
             </ipxact:vector>
           </ipxact:vectors>
           <ipxact:wireTypeDefs>
@@ -781,6 +788,7 @@
         <ipxact:name>coe_write_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -811,6 +819,7 @@
         <ipxact:name>coe_read_export</ipxact:name>
         <ipxact:wire>
           <ipxact:direction>out</ipxact:direction>
+          <ipxact:vectors></ipxact:vectors>
           <ipxact:wireTypeDefs>
             <ipxact:wireTypeDef>
               <ipxact:typeName>STD_LOGIC</ipxact:typeName>
@@ -842,7 +851,7 @@
   <ipxact:vendorExtensions>
     <altera:entity_info>
       <ipxact:vendor>ASTRON</ipxact:vendor>
-      <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg_1</ipxact:library>
+      <ipxact:library>qsys_lofar2_unb2b_adc_reg_wg</ipxact:library>
       <ipxact:name>avs_common_mm</ipxact:name>
       <ipxact:version>1.0</ipxact:version>
     </altera:entity_info>
@@ -851,7 +860,7 @@
         <ipxact:parameter parameterId="g_adr_w" type="int">
           <ipxact:name>g_adr_w</ipxact:name>
           <ipxact:displayName>g_adr_w</ipxact:displayName>
-          <ipxact:value>2</ipxact:value>
+          <ipxact:value>6</ipxact:value>
         </ipxact:parameter>
         <ipxact:parameter parameterId="g_dat_w" type="int">
           <ipxact:name>g_dat_w</ipxact:name>
@@ -861,7 +870,7 @@
         <ipxact:parameter parameterId="AUTO_SYSTEM_CLOCK_RATE" type="longint">
           <ipxact:name>AUTO_SYSTEM_CLOCK_RATE</ipxact:name>
           <ipxact:displayName>Auto CLOCK_RATE</ipxact:displayName>
-          <ipxact:value>-1</ipxact:value>
+          <ipxact:value>100000000</ipxact:value>
         </ipxact:parameter>
       </ipxact:parameters>
     </altera:altera_module_parameters>
@@ -892,6 +901,17 @@
           <ipxact:displayName>bonusData</ipxact:displayName>
           <ipxact:value>bonusData 
 {
+   element $system
+   {
+      datum _originalDeviceFamily
+      {
+         value = "Arria 10";
+         type = "String";
+      }
+   }
+   element qsys_lofar2_unb2b_adc_reg_wg_1
+   {
+   }
 }
 </ipxact:value>
         </ipxact:parameter>
@@ -977,7 +997,7 @@
                     &lt;name&gt;avs_mem_address&lt;/name&gt;
                     &lt;role&gt;address&lt;/role&gt;
                     &lt;direction&gt;Input&lt;/direction&gt;
-                    &lt;width&gt;2&lt;/width&gt;
+                    &lt;width&gt;6&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1046,7 +1066,7 @@
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressSpan&lt;/key&gt;
-                        &lt;value&gt;16&lt;/value&gt;
+                        &lt;value&gt;256&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;addressUnits&lt;/key&gt;
@@ -1275,7 +1295,7 @@
                     &lt;name&gt;coe_address_export&lt;/name&gt;
                     &lt;role&gt;export&lt;/role&gt;
                     &lt;direction&gt;Output&lt;/direction&gt;
-                    &lt;width&gt;2&lt;/width&gt;
+                    &lt;width&gt;6&lt;/width&gt;
                     &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                     &lt;vhdlType&gt;STD_LOGIC_VECTOR&lt;/vhdlType&gt;
                 &lt;/port&gt;
@@ -1442,11 +1462,11 @@
                 &lt;consumedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_MAP&lt;/key&gt;
-                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
+                        &lt;value&gt;&amp;lt;address-map&amp;gt;&amp;lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&amp;gt;&amp;lt;/address-map&amp;gt;&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;ADDRESS_WIDTH&lt;/key&gt;
-                        &lt;value&gt;4&lt;/value&gt;
+                        &lt;value&gt;8&lt;/value&gt;
                     &lt;/entry&gt;
                     &lt;entry&gt;
                         &lt;key&gt;MAX_SLAVE_DATA_WIDTH&lt;/key&gt;
@@ -1462,7 +1482,7 @@
                 &lt;suppliedSystemInfos&gt;
                     &lt;entry&gt;
                         &lt;key&gt;CLOCK_RATE&lt;/key&gt;
-                        &lt;value&gt;-1&lt;/value&gt;
+                        &lt;value&gt;100000000&lt;/value&gt;
                     &lt;/entry&gt;
                 &lt;/suppliedSystemInfos&gt;
                 &lt;consumedSystemInfos/&gt;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
index 2b3054541887dd3eca88e9422b06efe06f36a312..e60b7a1addebff53a70392b8f86cdc5a0ec10b58 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/qsys_lofar2_unb2b_adc.qsys
@@ -70,7 +70,7 @@
    {
       datum _sortIndex
       {
-         value = "23";
+         value = "21";
          type = "int";
       }
    }
@@ -185,44 +185,63 @@
          type = "String";
       }
    }
-   element ram_diag_data_buffer_jesd
+   element ram_aduh_monitor
    {
       datum _sortIndex
       {
-         value = "22";
+         value = "31";
          type = "int";
       }
-      datum sopceditor_expanded
+   }
+   element ram_aduh_monitor.mem
+   {
+      datum baseAddress
       {
-         value = "0";
-         type = "boolean";
+         value = "458752";
+         type = "String";
       }
    }
-   element ram_diag_data_buffer_jesd.mem
+   element ram_diag_data_buffer_bsn
+   {
+      datum _sortIndex
+      {
+         value = "29";
+         type = "int";
+      }
+   }
+   element ram_diag_data_buffer_bsn.mem
    {
       datum baseAddress
       {
-         value = "524288";
+         value = "786432";
          type = "String";
       }
    }
-   element ram_diag_data_buffer_jesd.reset
+   element ram_diag_data_buffer_jesd
    {
-      datum _tags
+      datum _sortIndex
       {
-         value = "";
+         value = "33";
+         type = "int";
+      }
+   }
+   element ram_diag_data_buffer_jesd.mem
+   {
+      datum baseAddress
+      {
+         value = "524288";
          type = "String";
       }
    }
-   element ram_wg_0
+   element ram_wg
    {
       datum _sortIndex
       {
-         value = "29";
+         value = "27";
          type = "int";
       }
    }
-   element ram_wg_0.mem
+   element ram_wg.mem
    {
       datum baseAddress
       {
@@ -230,7 +249,7 @@
          type = "String";
       }
    }
-   element ram_wg_1
+   element reg_aduh_monitor
    {
       datum _sortIndex
       {
@@ -238,47 +257,47 @@
          type = "int";
       }
    }
-   element ram_wg_1.mem
+   element reg_aduh_monitor.mem
    {
       datum baseAddress
       {
-         value = "331776";
+         value = "425984";
          type = "String";
       }
    }
-   element ram_wg_2
+   element reg_bsn_monitor_input
    {
       datum _sortIndex
       {
-         value = "31";
+         value = "22";
          type = "int";
       }
    }
-   element ram_wg_2.mem
+   element reg_bsn_monitor_input.mem
    {
       datum baseAddress
       {
-         value = "335872";
+         value = "294912";
          type = "String";
       }
    }
-   element ram_wg_3
+   element reg_bsn_scheduler
    {
       datum _sortIndex
       {
-         value = "32";
+         value = "25";
          type = "int";
       }
    }
-   element ram_wg_3.mem
+   element reg_bsn_scheduler.mem
    {
       datum baseAddress
       {
-         value = "339968";
+         value = "311568";
          type = "String";
       }
    }
-   element reg_bsn_monitor_input
+   element reg_bsn_source
    {
       datum _sortIndex
       {
@@ -286,32 +305,59 @@
          type = "int";
       }
    }
-   element reg_bsn_monitor_input.mem
+   element reg_bsn_source.mem
    {
       datum baseAddress
       {
-         value = "294912";
+         value = "311552";
          type = "String";
       }
    }
-   element reg_diag_data_buffer_jesd
+   element reg_diag_data_buffer_bsn
    {
       datum _sortIndex
       {
-         value = "21";
+         value = "28";
          type = "int";
       }
-      datum sopceditor_expanded
+   }
+   element reg_diag_data_buffer_bsn.mem
+   {
+      datum baseAddress
       {
-         value = "0";
-         type = "boolean";
+         value = "409600";
+         type = "String";
+      }
+   }
+   element reg_diag_data_buffer_jesd
+   {
+      datum _sortIndex
+      {
+         value = "32";
+         type = "int";
       }
    }
    element reg_diag_data_buffer_jesd.mem
    {
       datum baseAddress
       {
-         value = "1048576";
+         value = "393216";
+         type = "String";
+      }
+   }
+   element reg_dp_shiftram
+   {
+      datum _sortIndex
+      {
+         value = "26";
+         type = "int";
+      }
+   }
+   element reg_dp_shiftram.mem
+   {
+      datum baseAddress
+      {
+         value = "311584";
          type = "String";
       }
    }
@@ -536,15 +582,15 @@
          type = "String";
       }
    }
-   element reg_wg_0
+   element reg_wg
    {
       datum _sortIndex
       {
-         value = "25";
+         value = "23";
          type = "int";
       }
    }
-   element reg_wg_0.mem
+   element reg_wg.mem
    {
       datum baseAddress
       {
@@ -552,54 +598,6 @@
          type = "String";
       }
    }
-   element reg_wg_1
-   {
-      datum _sortIndex
-      {
-         value = "26";
-         type = "int";
-      }
-   }
-   element reg_wg_1.mem
-   {
-      datum baseAddress
-      {
-         value = "311312";
-         type = "String";
-      }
-   }
-   element reg_wg_2
-   {
-      datum _sortIndex
-      {
-         value = "27";
-         type = "int";
-      }
-   }
-   element reg_wg_2.mem
-   {
-      datum baseAddress
-      {
-         value = "311328";
-         type = "String";
-      }
-   }
-   element reg_wg_3
-   {
-      datum _sortIndex
-      {
-         value = "28";
-         type = "int";
-      }
-   }
-   element reg_wg_3.mem
-   {
-      datum baseAddress
-      {
-         value = "311344";
-         type = "String";
-      }
-   }
    element rom_system_info
    {
       datum _sortIndex
@@ -872,162 +870,162 @@
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buf_jesd_address"
-   internal="ram_diag_data_buffer_jesd.address"
+   name="ram_aduh_monitor_address"
+   internal="ram_aduh_monitor.address"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buf_jesd_clk"
-   internal="ram_diag_data_buffer_jesd.clk"
+   name="ram_aduh_monitor_clk"
+   internal="ram_aduh_monitor.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buf_jesd_read"
-   internal="ram_diag_data_buffer_jesd.read"
+   name="ram_aduh_monitor_read"
+   internal="ram_aduh_monitor.read"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buf_jesd_readdata"
-   internal="ram_diag_data_buffer_jesd.readdata"
+   name="ram_aduh_monitor_readdata"
+   internal="ram_aduh_monitor.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buf_jesd_reset"
-   internal="ram_diag_data_buffer_jesd.reset"
+   name="ram_aduh_monitor_reset"
+   internal="ram_aduh_monitor.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buf_jesd_write"
-   internal="ram_diag_data_buffer_jesd.write"
+   name="ram_aduh_monitor_write"
+   internal="ram_aduh_monitor.write"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_diag_data_buf_jesd_writedata"
-   internal="ram_diag_data_buffer_jesd.writedata"
+   name="ram_aduh_monitor_writedata"
+   internal="ram_aduh_monitor.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_0_address"
-   internal="ram_wg_0.address"
+   name="ram_diag_data_buf_bsn_address"
+   internal="ram_diag_data_buffer_bsn.address"
    type="conduit"
    dir="end" />
- <interface name="ram_wg_0_clk" internal="ram_wg_0.clk" type="conduit" dir="end" />
  <interface
-   name="ram_wg_0_read"
-   internal="ram_wg_0.read"
+   name="ram_diag_data_buf_bsn_clk"
+   internal="ram_diag_data_buffer_bsn.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_0_readdata"
-   internal="ram_wg_0.readdata"
+   name="ram_diag_data_buf_bsn_read"
+   internal="ram_diag_data_buffer_bsn.read"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_0_reset"
-   internal="ram_wg_0.reset"
+   name="ram_diag_data_buf_bsn_readdata"
+   internal="ram_diag_data_buffer_bsn.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_0_write"
-   internal="ram_wg_0.write"
+   name="ram_diag_data_buf_bsn_reset"
+   internal="ram_diag_data_buffer_bsn.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_0_writedata"
-   internal="ram_wg_0.writedata"
+   name="ram_diag_data_buf_bsn_write"
+   internal="ram_diag_data_buffer_bsn.write"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_1_address"
-   internal="ram_wg_1.address"
+   name="ram_diag_data_buf_bsn_writedata"
+   internal="ram_diag_data_buffer_bsn.writedata"
    type="conduit"
    dir="end" />
- <interface name="ram_wg_1_clk" internal="ram_wg_1.clk" type="conduit" dir="end" />
  <interface
-   name="ram_wg_1_read"
-   internal="ram_wg_1.read"
+   name="ram_diag_data_buf_jesd_address"
+   internal="ram_diag_data_buffer_jesd.address"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_1_readdata"
-   internal="ram_wg_1.readdata"
+   name="ram_diag_data_buf_jesd_clk"
+   internal="ram_diag_data_buffer_jesd.clk"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_1_reset"
-   internal="ram_wg_1.reset"
+   name="ram_diag_data_buf_jesd_read"
+   internal="ram_diag_data_buffer_jesd.read"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_1_write"
-   internal="ram_wg_1.write"
+   name="ram_diag_data_buf_jesd_readdata"
+   internal="ram_diag_data_buffer_jesd.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_1_writedata"
-   internal="ram_wg_1.writedata"
+   name="ram_diag_data_buf_jesd_reset"
+   internal="ram_diag_data_buffer_jesd.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_2_address"
-   internal="ram_wg_2.address"
+   name="ram_diag_data_buf_jesd_write"
+   internal="ram_diag_data_buffer_jesd.write"
    type="conduit"
    dir="end" />
- <interface name="ram_wg_2_clk" internal="ram_wg_2.clk" type="conduit" dir="end" />
  <interface
-   name="ram_wg_2_read"
-   internal="ram_wg_2.read"
+   name="ram_diag_data_buf_jesd_writedata"
+   internal="ram_diag_data_buffer_jesd.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_2_readdata"
-   internal="ram_wg_2.readdata"
+   name="ram_wg_address"
+   internal="ram_wg.address"
    type="conduit"
    dir="end" />
+ <interface name="ram_wg_clk" internal="ram_wg.clk" type="conduit" dir="end" />
+ <interface name="ram_wg_read" internal="ram_wg.read" type="conduit" dir="end" />
  <interface
-   name="ram_wg_2_reset"
-   internal="ram_wg_2.reset"
+   name="ram_wg_readdata"
+   internal="ram_wg.readdata"
    type="conduit"
    dir="end" />
+ <interface name="ram_wg_reset" internal="ram_wg.reset" type="conduit" dir="end" />
+ <interface name="ram_wg_write" internal="ram_wg.write" type="conduit" dir="end" />
  <interface
-   name="ram_wg_2_write"
-   internal="ram_wg_2.write"
+   name="ram_wg_writedata"
+   internal="ram_wg.writedata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_2_writedata"
-   internal="ram_wg_2.writedata"
+   name="reg_aduh_monitor_address"
+   internal="reg_aduh_monitor.address"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_3_address"
-   internal="ram_wg_3.address"
+   name="reg_aduh_monitor_clk"
+   internal="reg_aduh_monitor.clk"
    type="conduit"
    dir="end" />
- <interface name="ram_wg_3_clk" internal="ram_wg_3.clk" type="conduit" dir="end" />
  <interface
-   name="ram_wg_3_read"
-   internal="ram_wg_3.read"
+   name="reg_aduh_monitor_read"
+   internal="reg_aduh_monitor.read"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_3_readdata"
-   internal="ram_wg_3.readdata"
+   name="reg_aduh_monitor_readdata"
+   internal="reg_aduh_monitor.readdata"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_3_reset"
-   internal="ram_wg_3.reset"
+   name="reg_aduh_monitor_reset"
+   internal="reg_aduh_monitor.reset"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_3_write"
-   internal="ram_wg_3.write"
+   name="reg_aduh_monitor_write"
+   internal="reg_aduh_monitor.write"
    type="conduit"
    dir="end" />
  <interface
-   name="ram_wg_3_writedata"
-   internal="ram_wg_3.writedata"
+   name="reg_aduh_monitor_writedata"
+   internal="reg_aduh_monitor.writedata"
    type="conduit"
    dir="end" />
  <interface
@@ -1065,6 +1063,111 @@
    internal="reg_bsn_monitor_input.writedata"
    type="conduit"
    dir="end" />
+ <interface
+   name="reg_bsn_scheduler_address"
+   internal="reg_bsn_scheduler.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_scheduler_clk"
+   internal="reg_bsn_scheduler.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_scheduler_read"
+   internal="reg_bsn_scheduler.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_scheduler_readdata"
+   internal="reg_bsn_scheduler.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_scheduler_reset"
+   internal="reg_bsn_scheduler.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_scheduler_write"
+   internal="reg_bsn_scheduler.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_scheduler_writedata"
+   internal="reg_bsn_scheduler.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_source_address"
+   internal="reg_bsn_source.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_source_clk"
+   internal="reg_bsn_source.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_source_read"
+   internal="reg_bsn_source.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_source_readdata"
+   internal="reg_bsn_source.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_source_reset"
+   internal="reg_bsn_source.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_source_write"
+   internal="reg_bsn_source.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_bsn_source_writedata"
+   internal="reg_bsn_source.writedata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buf_bsn_address"
+   internal="reg_diag_data_buffer_bsn.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buf_bsn_clk"
+   internal="reg_diag_data_buffer_bsn.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buf_bsn_read"
+   internal="reg_diag_data_buffer_bsn.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buf_bsn_readdata"
+   internal="reg_diag_data_buffer_bsn.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buf_bsn_reset"
+   internal="reg_diag_data_buffer_bsn.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buf_bsn_write"
+   internal="reg_diag_data_buffer_bsn.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_diag_data_buf_bsn_writedata"
+   internal="reg_diag_data_buffer_bsn.writedata"
+   type="conduit"
+   dir="end" />
  <interface
    name="reg_diag_data_buf_jesd_address"
    internal="reg_diag_data_buffer_jesd.address"
@@ -1100,6 +1203,41 @@
    internal="reg_diag_data_buffer_jesd.writedata"
    type="conduit"
    dir="end" />
+ <interface
+   name="reg_dp_shiftram_address"
+   internal="reg_dp_shiftram.address"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_shiftram_clk"
+   internal="reg_dp_shiftram.clk"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_shiftram_read"
+   internal="reg_dp_shiftram.read"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_shiftram_readdata"
+   internal="reg_dp_shiftram.readdata"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_shiftram_reset"
+   internal="reg_dp_shiftram.reset"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_shiftram_write"
+   internal="reg_dp_shiftram.write"
+   type="conduit"
+   dir="end" />
+ <interface
+   name="reg_dp_shiftram_writedata"
+   internal="reg_dp_shiftram.writedata"
+   type="conduit"
+   dir="end" />
  <interface
    name="reg_dpmm_ctrl_address"
    internal="reg_dpmm_ctrl.address"
@@ -1470,127 +1608,22 @@
    type="conduit"
    dir="end" />
  <interface
-   name="reg_wg_0_address"
-   internal="reg_wg_0.address"
-   type="conduit"
-   dir="end" />
- <interface name="reg_wg_0_clk" internal="reg_wg_0.clk" type="conduit" dir="end" />
- <interface
-   name="reg_wg_0_read"
-   internal="reg_wg_0.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_0_readdata"
-   internal="reg_wg_0.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_0_reset"
-   internal="reg_wg_0.reset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_0_write"
-   internal="reg_wg_0.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_0_writedata"
-   internal="reg_wg_0.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_1_address"
-   internal="reg_wg_1.address"
-   type="conduit"
-   dir="end" />
- <interface name="reg_wg_1_clk" internal="reg_wg_1.clk" type="conduit" dir="end" />
- <interface
-   name="reg_wg_1_read"
-   internal="reg_wg_1.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_1_readdata"
-   internal="reg_wg_1.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_1_reset"
-   internal="reg_wg_1.reset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_1_write"
-   internal="reg_wg_1.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_1_writedata"
-   internal="reg_wg_1.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_2_address"
-   internal="reg_wg_2.address"
-   type="conduit"
-   dir="end" />
- <interface name="reg_wg_2_clk" internal="reg_wg_2.clk" type="conduit" dir="end" />
- <interface
-   name="reg_wg_2_read"
-   internal="reg_wg_2.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_2_readdata"
-   internal="reg_wg_2.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_2_reset"
-   internal="reg_wg_2.reset"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_2_write"
-   internal="reg_wg_2.write"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_2_writedata"
-   internal="reg_wg_2.writedata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_3_address"
-   internal="reg_wg_3.address"
-   type="conduit"
-   dir="end" />
- <interface name="reg_wg_3_clk" internal="reg_wg_3.clk" type="conduit" dir="end" />
- <interface
-   name="reg_wg_3_read"
-   internal="reg_wg_3.read"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_3_readdata"
-   internal="reg_wg_3.readdata"
-   type="conduit"
-   dir="end" />
- <interface
-   name="reg_wg_3_reset"
-   internal="reg_wg_3.reset"
+   name="reg_wg_address"
+   internal="reg_wg.address"
    type="conduit"
    dir="end" />
+ <interface name="reg_wg_clk" internal="reg_wg.clk" type="conduit" dir="end" />
+ <interface name="reg_wg_read" internal="reg_wg.read" type="conduit" dir="end" />
  <interface
-   name="reg_wg_3_write"
-   internal="reg_wg_3.write"
+   name="reg_wg_readdata"
+   internal="reg_wg.readdata"
    type="conduit"
    dir="end" />
+ <interface name="reg_wg_reset" internal="reg_wg.reset" type="conduit" dir="end" />
+ <interface name="reg_wg_write" internal="reg_wg.write" type="conduit" dir="end" />
  <interface
-   name="reg_wg_3_writedata"
-   internal="reg_wg_3.writedata"
+   name="reg_wg_writedata"
+   internal="reg_wg.writedata"
    type="conduit"
    dir="end" />
  <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
@@ -3140,292 +3173,94 @@
             </entry>
         </connPtSystemInfos>
     </systemInfos>
-</componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
-  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_avs_eth_0</hdlLibraryName>
-    <fileSets>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetFixedName>
-            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetFixedName>
-            <fileSetKind>SIM_VERILOG</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetFixedName>
-            <fileSetKind>SIM_VHDL</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-    </fileSets>
-</generationInfoDefinition>]]></parameter>
-  <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip</parameter>
-  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
-    <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
-  <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
-   name="clk_0"
-   kind="altera_generic_component"
-   version="1.0"
-   enabled="1">
-  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
-    <boundary>
-        <interfaces>
-            <interface>
-                <name>clk</name>
-                <type>clock</type>
-                <isStart>true</isStart>
-                <ports>
-                    <port>
-                        <name>clk_out</name>
-                        <role>clk</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedDirectClock</key>
-                            <value>clk_in</value>
-                        </entry>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>100000000</value>
-                        </entry>
-                        <entry>
-                            <key>clockRateKnown</key>
-                            <value>true</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>true</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>clk_in</name>
-                <type>clock</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>in_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap>
-                        <entry>
-                            <key>qsys.ui.export_name</key>
-                            <value>clk</value>
-                        </entry>
-                    </assignmentValueMap>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>100000000</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>clk_in_reset</name>
-                <type>reset</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>reset_n</name>
-                        <role>reset_n</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap>
-                        <entry>
-                            <key>qsys.ui.export_name</key>
-                            <value>reset</value>
-                        </entry>
-                    </assignmentValueMap>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>NONE</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>clk_reset</name>
-                <type>reset</type>
-                <isStart>true</isStart>
-                <ports>
-                    <port>
-                        <name>reset_n_out</name>
-                        <role>reset_n</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedDirectReset</key>
-                            <value>clk_in_reset</value>
-                        </entry>
-                        <entry>
-                            <key>associatedResetSinks</key>
-                            <value>clk_in_reset</value>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>NONE</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-        </interfaces>
-    </boundary>
-    <originalModuleInfo>
-        <className>clock_source</className>
-        <displayName>Clock Source</displayName>
-    </originalModuleInfo>
-    <systemInfoParameterDescriptors>
-        <descriptors>
-            <descriptor>
-                <parameterDefaultValue>0</parameterDefaultValue>
-                <parameterName>inputClockFrequency</parameterName>
-                <parameterType>java.lang.Long</parameterType>
-                <systemInfoArgs>clk_in</systemInfoArgs>
-                <systemInfotype>CLOCK_RATE</systemInfotype>
-            </descriptor>
-        </descriptors>
-    </systemInfoParameterDescriptors>
-    <systemInfos>
-        <connPtSystemInfos>
-            <entry>
-                <key>clk</key>
-                <value>
-                    <connectionPointName>clk</connectionPointName>
-                    <suppliedSystemInfos>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>100000000</value>
-                        </entry>
-                    </suppliedSystemInfos>
-                    <consumedSystemInfos/>
-                </value>
-            </entry>
-            <entry>
-                <key>clk_in</key>
-                <value>
-                    <connectionPointName>clk_in</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>0</value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
-        </connPtSystemInfos>
-    </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>clk_in</name>
-            <type>clock</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>in_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
                     <entry>
-                        <key>qsys.ui.export_name</key>
-                        <value>clk</value>
+                        <key>associatedClock</key>
                     </entry>
-                </assignmentValueMap>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>interrupt</name>
+            <type>interrupt</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>ins_interrupt_irq</name>
+                    <role>irq</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
             </assignments>
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>100000000</value>
+                        <key>associatedAddressablePoint</key>
+                        <value>avs_eth_0.mms_reg</value>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedClock</key>
+                        <value>mm</value>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>associatedReset</key>
+                        <value>mm_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedReceiverOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToReceiver</key>
+                    </entry>
+                    <entry>
+                        <key>irqScheme</key>
+                        <value>NONE</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk_in_reset</name>
-            <type>reset</type>
+            <name>irq</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>reset_n</name>
-                    <role>reset_n</role>
+                    <name>coe_irq_export</name>
+                    <role>export</role>
                     <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
@@ -3433,12 +3268,7 @@
                 </port>
             </ports>
             <assignments>
-                <assignmentValueMap>
-                    <entry>
-                        <key>qsys.ui.export_name</key>
-                        <value>reset</value>
-                    </entry>
-                </assignmentValueMap>
+                <assignmentValueMap/>
             </assignments>
             <parameters>
                 <parameterValueMap>
@@ -3446,21 +3276,24 @@
                         <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>NONE</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>mm</name>
             <type>clock</type>
-            <isStart>true</isStart>
+            <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>clk_out</name>
+                    <name>csi_mm_clk</name>
                     <role>clk</role>
-                    <direction>Output</direction>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -3471,21 +3304,13 @@
             </assignments>
             <parameters>
                 <parameterValueMap>
-                    <entry>
-                        <key>associatedDirectClock</key>
-                        <value>clk_in</value>
-                    </entry>
                     <entry>
                         <key>clockRate</key>
-                        <value>100000000</value>
-                    </entry>
-                    <entry>
-                        <key>clockRateKnown</key>
-                        <value>true</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>externallyDriven</key>
-                        <value>true</value>
+                        <value>false</value>
                     </entry>
                     <entry>
                         <key>ptfSchematicName</key>
@@ -3494,14 +3319,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk_reset</name>
+            <name>mm_reset</name>
             <type>reset</type>
-            <isStart>true</isStart>
+            <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>reset_n_out</name>
-                    <role>reset_n</role>
-                    <direction>Output</direction>
+                    <name>csi_mm_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -3514,235 +3339,4185 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedDirectReset</key>
-                        <value>clk_in_reset</value>
-                    </entry>
-                    <entry>
-                        <key>associatedResetSinks</key>
-                        <value>clk_in_reset</value>
+                        <value>mm</value>
                     </entry>
                     <entry>
                         <key>synchronousEdges</key>
-                        <value>NONE</value>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
-    </interfaces>
-</boundaryDefinition>]]></parameter>
-  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_clk_0</hdlLibraryName>
-    <fileSets>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_clk_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_clk_0</fileSetFixedName>
-            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_clk_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_clk_0</fileSetFixedName>
-            <fileSetKind>SIM_VERILOG</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_clk_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_clk_0</fileSetFixedName>
-            <fileSetKind>SIM_VHDL</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-    </fileSets>
-</generationInfoDefinition>]]></parameter>
-  <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip</parameter>
-  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
-    <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
-  <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
-   name="cpu_0"
-   kind="altera_generic_component"
-   version="1.0"
-   enabled="1">
-  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
-    <boundary>
-        <interfaces>
-            <interface>
-                <name>clk</name>
-                <type>clock</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>custom_instruction_master</name>
-                <type>nios_custom_instruction</type>
-                <isStart>true</isStart>
-                <ports>
-                    <port>
-                        <name>dummy_ci_port</name>
-                        <role>readra</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>CIName</key>
-                            <value></value>
-                        </entry>
-                        <entry>
-                            <key>addressWidth</key>
-                            <value>8</value>
-                        </entry>
-                        <entry>
-                            <key>clockCycle</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>enabled</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>maxAddressWidth</key>
-                            <value>8</value>
-                        </entry>
-                        <entry>
-                            <key>opcodeExtension</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>sharedCombinationalAndMulticycle</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>data_master</name>
-                <type>avalon</type>
-                <isStart>true</isStart>
-                <ports>
-                    <port>
-                        <name>d_waitrequest</name>
-                        <role>waitrequest</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                    <port>
-                        <name>d_byteenable</name>
-                        <role>byteenable</role>
-                        <direction>Output</direction>
-                        <width>4</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                    <port>
-                        <name>d_read</name>
-                        <role>read</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                    <port>
-                        <name>d_write</name>
-                        <role>write</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                    <port>
-                        <name>d_address</name>
-                        <role>address</role>
-                        <direction>Output</direction>
-                        <width>21</width>
+        <interface>
+            <name>mms_ram</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>mms_ram_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>10</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>mms_ram_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>mms_ram_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>mms_ram_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>mms_ram_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>4096</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>mm</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>mm_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>2</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mms_reg</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>mms_reg_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>mms_reg_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>mms_reg_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>mms_reg_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>mms_reg_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>64</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>mm</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>mm_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mms_tse</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>mms_tse_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>10</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>mms_tse_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>mms_tse_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>mms_tse_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>mms_tse_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>mms_tse_waitrequest</name>
+                    <role>waitrequest</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>4096</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>mm</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>mm_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>ram_address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_ram_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>10</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>ram_read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_ram_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>ram_readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_ram_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>ram_write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_ram_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>ram_writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_ram_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reg_address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reg_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reg_read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reg_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reg_readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reg_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reg_write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reg_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reg_writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reg_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>tse_address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_tse_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>10</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>tse_read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_tse_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>tse_readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_tse_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>tse_waitrequest</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_tse_waitrequest_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>tse_write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_tse_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>tse_writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_tse_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_avs_eth_0</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_eth_0</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="clk_0"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>clk</name>
+                <type>clock</type>
+                <isStart>true</isStart>
+                <ports>
+                    <port>
+                        <name>clk_out</name>
+                        <role>clk</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedDirectClock</key>
+                            <value>clk_in</value>
+                        </entry>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>100000000</value>
+                        </entry>
+                        <entry>
+                            <key>clockRateKnown</key>
+                            <value>true</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>true</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk_in</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>in_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>qsys.ui.export_name</key>
+                            <value>clk</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>100000000</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk_in_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>reset_n</name>
+                        <role>reset_n</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>qsys.ui.export_name</key>
+                            <value>reset</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>NONE</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk_reset</name>
+                <type>reset</type>
+                <isStart>true</isStart>
+                <ports>
+                    <port>
+                        <name>reset_n_out</name>
+                        <role>reset_n</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedDirectReset</key>
+                            <value>clk_in_reset</value>
+                        </entry>
+                        <entry>
+                            <key>associatedResetSinks</key>
+                            <value>clk_in_reset</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>NONE</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>clock_source</className>
+        <displayName>Clock Source</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>0</parameterDefaultValue>
+                <parameterName>inputClockFrequency</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>clk_in</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>clk</key>
+                <value>
+                    <connectionPointName>clk</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>clk_in</key>
+                <value>
+                    <connectionPointName>clk_in</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>0</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>clk</name>
+            <type>clock</type>
+            <isStart>true</isStart>
+            <ports>
+                <port>
+                    <name>clk_out</name>
+                    <role>clk</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedDirectClock</key>
+                        <value>clk_in</value>
+                    </entry>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>100000000</value>
+                    </entry>
+                    <entry>
+                        <key>clockRateKnown</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk_in</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>in_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>qsys.ui.export_name</key>
+                        <value>clk</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>100000000</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk_in_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>reset_n</name>
+                    <role>reset_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>qsys.ui.export_name</key>
+                        <value>reset</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>NONE</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk_reset</name>
+            <type>reset</type>
+            <isStart>true</isStart>
+            <ports>
+                <port>
+                    <name>reset_n_out</name>
+                    <role>reset_n</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedDirectReset</key>
+                        <value>clk_in_reset</value>
+                    </entry>
+                    <entry>
+                        <key>associatedResetSinks</key>
+                        <value>clk_in_reset</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>NONE</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_clk_0</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_clk_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_clk_0</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_clk_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_clk_0</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_clk_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_clk_0</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="cpu_0"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>clk</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>custom_instruction_master</name>
+                <type>nios_custom_instruction</type>
+                <isStart>true</isStart>
+                <ports>
+                    <port>
+                        <name>dummy_ci_port</name>
+                        <role>readra</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>CIName</key>
+                            <value></value>
+                        </entry>
+                        <entry>
+                            <key>addressWidth</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>clockCycle</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>enabled</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maxAddressWidth</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>opcodeExtension</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>sharedCombinationalAndMulticycle</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>data_master</name>
+                <type>avalon</type>
+                <isStart>true</isStart>
+                <ports>
+                    <port>
+                        <name>d_waitrequest</name>
+                        <role>waitrequest</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>d_byteenable</name>
+                        <role>byteenable</role>
+                        <direction>Output</direction>
+                        <width>4</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>d_read</name>
+                        <role>read</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>d_write</name>
+                        <role>write</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>d_address</name>
+                        <role>address</role>
+                        <direction>Output</direction>
+                        <width>20</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>d_readdata</name>
+                        <role>readdata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>d_writedata</name>
+                        <role>writedata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>debug_mem_slave_debugaccess_to_roms</name>
+                        <role>debugaccess</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>debug.providesServices</key>
+                            <value>master</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>adaptsTo</key>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>SYMBOLS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>clk</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>true</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>dBSBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>doStreamReads</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>doStreamWrites</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isAsynchronous</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isReadable</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isWriteable</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maxAddressWidth</key>
+                            <value>32</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>true</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>debug_mem_slave</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>debug_mem_slave_writedata</name>
+                        <role>writedata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>debug_mem_slave_byteenable</name>
+                        <role>byteenable</role>
+                        <direction>Input</direction>
+                        <width>4</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>debug_mem_slave_address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>9</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>debug_mem_slave_debugaccess</name>
+                        <role>debugaccess</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>debug_mem_slave_readdata</name>
+                        <role>readdata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>debug_mem_slave_waitrequest</name>
+                        <role>waitrequest</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>debug_mem_slave_read</name>
+                        <role>read</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>debug_mem_slave_write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>embeddedsw.configuration.hideDevice</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>qsys.ui.connect</key>
+                            <value>instruction_master,data_master</value>
+                        </entry>
+                    </assignmentValueMap>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>addressAlignment</key>
+                            <value>DYNAMIC</value>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>2048</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>clk</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToMaster</key>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isFlash</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isMemoryDevice</key>
+                            <value>true</value>
+                        </entry>
+                        <entry>
+                            <key>isNonVolatileStorage</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>printableDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>true</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>transparentBridge</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>debug_reset_request</name>
+                <type>reset</type>
+                <isStart>true</isStart>
+                <ports>
+                    <port>
+                        <name>debug_reset_request</name>
+                        <role>reset</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>clk</value>
+                        </entry>
+                        <entry>
+                            <key>associatedDirectReset</key>
+                        </entry>
+                        <entry>
+                            <key>associatedResetSinks</key>
+                            <value>none</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>instruction_master</name>
+                <type>avalon</type>
+                <isStart>true</isStart>
+                <ports>
+                    <port>
+                        <name>i_readdata</name>
+                        <role>readdata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>i_address</name>
+                        <role>address</role>
+                        <direction>Output</direction>
+                        <width>18</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>i_read</name>
+                        <role>read</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>i_waitrequest</name>
+                        <role>waitrequest</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>adaptsTo</key>
+                        </entry>
+                        <entry>
+                            <key>addressGroup</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>addressUnits</key>
+                            <value>SYMBOLS</value>
+                        </entry>
+                        <entry>
+                            <key>alwaysBurstMaxBurst</key>
+                            <value>true</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>clk</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>reset</value>
+                        </entry>
+                        <entry>
+                            <key>bitsPerSymbol</key>
+                            <value>8</value>
+                        </entry>
+                        <entry>
+                            <key>burstOnBurstBoundariesOnly</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
+                        </entry>
+                        <entry>
+                            <key>constantBurstBehavior</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>dBSBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>doStreamReads</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>doStreamWrites</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isAsynchronous</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isBigEndian</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isReadable</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isWriteable</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>true</value>
+                        </entry>
+                        <entry>
+                            <key>maxAddressWidth</key>
+                            <value>32</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>irq</name>
+                <type>interrupt</type>
+                <isStart>true</isStart>
+                <ports>
+                    <port>
+                        <name>irq</name>
+                        <role>irq</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedAddressablePoint</key>
+                            <value>cpu_0.data_master</value>
+                        </entry>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>clk</value>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                            <value>reset</value>
+                        </entry>
+                        <entry>
+                            <key>irqMap</key>
+                        </entry>
+                        <entry>
+                            <key>irqScheme</key>
+                            <value>INDIVIDUAL_REQUESTS</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>reset_n</name>
+                        <role>reset_n</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>reset_req</name>
+                        <role>reset_req</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>clk</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>altera_nios2_gen2</className>
+        <version>19.1</version>
+        <displayName>Nios II Processor</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_CLK_CLOCK_DOMAIN</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>clk</systemInfoArgs>
+                <systemInfotype>CLOCK_DOMAIN</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_CLK_RESET_DOMAIN</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>clk</systemInfoArgs>
+                <systemInfotype>RESET_DOMAIN</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>AUTO_DEVICE</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfotype>DEVICE</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>50000000</parameterDefaultValue>
+                <parameterName>clockFrequency</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>clk</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>customInstSlavesSystemInfo</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>custom_instruction_master</systemInfoArgs>
+                <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>customInstSlavesSystemInfo_nios_a</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>custom_instruction_master_a</systemInfoArgs>
+                <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>customInstSlavesSystemInfo_nios_b</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>custom_instruction_master_b</systemInfoArgs>
+                <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>customInstSlavesSystemInfo_nios_c</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>custom_instruction_master_c</systemInfoArgs>
+                <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>dataAddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>data_master</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>dataMasterHighPerformanceAddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>data_master_high_performance</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>dataMasterHighPerformanceMapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>data_master_high_performance</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>dataSlaveMapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>data_master</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>STRATIXIV</parameterDefaultValue>
+                <parameterName>deviceFamilyName</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfotype>DEVICE_FAMILY</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>deviceFeaturesSystemInfo</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfotype>DEVICE_FEATURES</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>faAddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>flash_instruction_master</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>faSlaveMapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>flash_instruction_master</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>instAddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>instruction_master</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>instSlaveMapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>instruction_master</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>instructionMasterHighPerformanceAddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>instruction_master_high_performance</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>instructionMasterHighPerformanceMapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>instruction_master_high_performance</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>0</parameterDefaultValue>
+                <parameterName>internalIrqMaskSystemInfo</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>irq</systemInfoArgs>
+                <systemInfotype>INTERRUPTS_USED</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>tightlyCoupledDataMaster0AddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>tightlyCoupledDataMaster0MapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>tightlyCoupledDataMaster1AddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>tightlyCoupledDataMaster1MapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>tightlyCoupledDataMaster2AddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>tightlyCoupledDataMaster2MapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>tightlyCoupledDataMaster3AddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>tightlyCoupledDataMaster3MapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>tightlyCoupledInstructionMaster0AddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>tightlyCoupledInstructionMaster0MapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>tightlyCoupledInstructionMaster1AddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>tightlyCoupledInstructionMaster1MapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>tightlyCoupledInstructionMaster2AddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>tightlyCoupledInstructionMaster2MapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>1</parameterDefaultValue>
+                <parameterName>tightlyCoupledInstructionMaster3AddrWidth</parameterName>
+                <parameterType>java.lang.Integer</parameterType>
+                <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs>
+                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>tightlyCoupledInstructionMaster3MapParam</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs>
+                <systemInfotype>ADDRESS_MAP</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>clk</key>
+                <value>
+                    <connectionPointName>clk</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_DOMAIN</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                        <entry>
+                            <key>RESET_DOMAIN</key>
+                            <value>1</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+            <entry>
+                <key>custom_instruction_master</key>
+                <value>
+                    <connectionPointName>custom_instruction_master</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CUSTOM_INSTRUCTION_SLAVES</key>
+                            <value></value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+            <entry>
+                <key>data_master</key>
+                <value>
+                    <connectionPointName>data_master</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value></value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>1</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+            <entry>
+                <key>debug_mem_slave</key>
+                <value>
+                    <connectionPointName>debug_mem_slave</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>11</value>
+                        </entry>
+                        <entry>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>32</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>instruction_master</key>
+                <value>
+                    <connectionPointName>instruction_master</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value></value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>1</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+            <entry>
+                <key>irq</key>
+                <value>
+                    <connectionPointName>irq</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>INTERRUPTS_USED</key>
+                            <value>7</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>clk</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>reset_n</name>
+                    <role>reset_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>reset_req</name>
+                    <role>reset_req</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>data_master</name>
+            <type>avalon</type>
+            <isStart>true</isStart>
+            <ports>
+                <port>
+                    <name>d_address</name>
+                    <role>address</role>
+                    <direction>Output</direction>
+                    <width>20</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>d_byteenable</name>
+                    <role>byteenable</role>
+                    <direction>Output</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>d_read</name>
+                    <role>read</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>d_readdata</name>
+                    <role>readdata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>d_waitrequest</name>
+                    <role>waitrequest</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>d_write</name>
+                    <role>write</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>d_writedata</name>
+                    <role>writedata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>debug_mem_slave_debugaccess_to_roms</name>
+                    <role>debugaccess</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>debug.providesServices</key>
+                        <value>master</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>adaptsTo</key>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>SYMBOLS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>dBSBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>doStreamReads</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>doStreamWrites</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isAsynchronous</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isReadable</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isWriteable</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maxAddressWidth</key>
+                        <value>32</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>instruction_master</name>
+            <type>avalon</type>
+            <isStart>true</isStart>
+            <ports>
+                <port>
+                    <name>i_address</name>
+                    <role>address</role>
+                    <direction>Output</direction>
+                    <width>18</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>i_read</name>
+                    <role>read</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>i_readdata</name>
+                    <role>readdata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>i_waitrequest</name>
+                    <role>waitrequest</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>adaptsTo</key>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>SYMBOLS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>dBSBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>doStreamReads</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>doStreamWrites</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isAsynchronous</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isReadable</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isWriteable</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>maxAddressWidth</key>
+                        <value>32</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>irq</name>
+            <type>interrupt</type>
+            <isStart>true</isStart>
+            <ports>
+                <port>
+                    <name>irq</name>
+                    <role>irq</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedAddressablePoint</key>
+                        <value>qsys_lofar2_unb2b_adc_cpu_0.data_master</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>reset</value>
+                    </entry>
+                    <entry>
+                        <key>irqMap</key>
+                    </entry>
+                    <entry>
+                        <key>irqScheme</key>
+                        <value>INDIVIDUAL_REQUESTS</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>debug_reset_request</name>
+            <type>reset</type>
+            <isStart>true</isStart>
+            <ports>
+                <port>
+                    <name>debug_reset_request</name>
+                    <role>reset</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedDirectReset</key>
+                    </entry>
+                    <entry>
+                        <key>associatedResetSinks</key>
+                        <value>none</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>debug_mem_slave</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>debug_mem_slave_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>9</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>debug_mem_slave_byteenable</name>
+                    <role>byteenable</role>
+                    <direction>Input</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>debug_mem_slave_debugaccess</name>
+                    <role>debugaccess</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>debug_mem_slave_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>debug_mem_slave_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>debug_mem_slave_waitrequest</name>
+                    <role>waitrequest</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>debug_mem_slave_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>debug_mem_slave_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.hideDevice</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>qsys.ui.connect</key>
+                        <value>instruction_master,data_master</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>2048</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>custom_instruction_master</name>
+            <type>nios_custom_instruction</type>
+            <isStart>true</isStart>
+            <ports>
+                <port>
+                    <name>dummy_ci_port</name>
+                    <role>readra</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>CIName</key>
+                        <value></value>
+                    </entry>
+                    <entry>
+                        <key>addressWidth</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>clockCycle</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>enabled</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maxAddressWidth</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>opcodeExtension</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>sharedCombinationalAndMulticycle</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_cpu_0</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_cpu_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_cpu_0</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_cpu_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_cpu_0</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_cpu_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_cpu_0</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap>
+        <entry>
+            <key>debug.hostConnection</key>
+            <value>type jtag id 70:34|110:135</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.BIG_ENDIAN</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.BREAK_ADDR</key>
+            <value>0x00003820</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
+            <value></value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.CPU_FREQ</key>
+            <value>100000000u</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.CPU_ID_SIZE</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.CPU_ID_VALUE</key>
+            <value>0x00000000</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.CPU_IMPLEMENTATION</key>
+            <value>"tiny"</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.DATA_ADDR_WIDTH</key>
+            <value>20</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.DCACHE_LINE_SIZE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.DCACHE_SIZE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.EXCEPTION_ADDR</key>
+            <value>0x00020020</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.FLUSHDA_SUPPORTED</key>
+            <value></value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HAS_DEBUG_CORE</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HAS_DEBUG_STUB</key>
+            <value></value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</key>
+            <value></value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</key>
+            <value></value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.ICACHE_LINE_SIZE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.ICACHE_SIZE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.INST_ADDR_WIDTH</key>
+            <value>18</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.OCI_VERSION</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.RESET_ADDR</key>
+            <value>0x00020000</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.configuration.DataCacheVictimBufImpl</key>
+            <value>ram</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.configuration.HDLSimCachesCleared</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.configuration.breakOffset</key>
+            <value>32</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.configuration.breakSlave</key>
+            <value>cpu_0.debug_mem_slave</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.configuration.cpuArchitecture</key>
+            <value>Nios II</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.configuration.exceptionOffset</key>
+            <value>32</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.configuration.exceptionSlave</key>
+            <value>onchip_memory2_0.s1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.configuration.resetOffset</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.configuration.resetSlave</key>
+            <value>onchip_memory2_0.s1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.compatible</key>
+            <value>altr,nios2-1.1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.group</key>
+            <value>cpu</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.name</key>
+            <value>nios2</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.altr,exception-addr</key>
+            <value>0x00020020</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.altr,implementation</key>
+            <value>"tiny"</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.altr,reset-addr</key>
+            <value>0x00020000</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.clock-frequency</key>
+            <value>100000000u</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.dcache-line-size</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.dcache-size</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.icache-line-size</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.icache-size</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.vendor</key>
+            <value>altr</value>
+        </entry>
+    </assignmentValueMap>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="jesd204b"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
+            <interface>
+                <name>address</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
                     <port>
-                        <name>d_readdata</name>
-                        <role>readdata</role>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>mem</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
                         <direction>Input</direction>
-                        <width>32</width>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>avs_mem_address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>d_writedata</name>
-                        <role>writedata</role>
+                        <name>avs_mem_readdata</name>
+                        <role>readdata</role>
                         <direction>Output</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>debug_mem_slave_debugaccess_to_roms</name>
-                        <role>debugaccess</role>
-                        <direction>Output</direction>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
+                    <port>
+                        <name>avs_mem_writedata</name>
+                        <role>writedata</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
                 </ports>
                 <assignments>
                     <assignmentValueMap>
                         <entry>
-                            <key>debug.providesServices</key>
-                            <value>master</value>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>0</value>
                         </entry>
                     </assignmentValueMap>
                 </assignments>
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>adaptsTo</key>
+                            <key>addressAlignment</key>
+                            <value>DYNAMIC</value>
                         </entry>
                         <entry>
                             <key>addressGroup</key>
-                            <value>1</value>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>16384</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
-                            <value>SYMBOLS</value>
+                            <value>WORDS</value>
                         </entry>
                         <entry>
                             <key>alwaysBurstMaxBurst</key>
@@ -3750,19 +7525,26 @@
                         </entry>
                         <entry>
                             <key>associatedClock</key>
-                            <value>clk</value>
+                            <value>system</value>
                         </entry>
                         <entry>
                             <key>associatedReset</key>
-                            <value>reset</value>
+                            <value>system_reset</value>
                         </entry>
                         <entry>
                             <key>bitsPerSymbol</key>
                             <value>8</value>
                         </entry>
+                        <entry>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToMaster</key>
+                        </entry>
                         <entry>
                             <key>burstOnBurstBoundariesOnly</key>
-                            <value>true</value>
+                            <value>false</value>
                         </entry>
                         <entry>
                             <key>burstcountUnits</key>
@@ -3773,464 +7555,1066 @@
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>dBSBigEndian</key>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>holdTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>interleaveBursts</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>doStreamReads</key>
+                            <key>isBigEndian</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>doStreamWrites</key>
+                            <key>isFlash</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>holdTime</key>
+                            <key>isMemoryDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>isNonVolatileStorage</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>linewrapBursts</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>maximumPendingReadTransactions</key>
                             <value>0</value>
                         </entry>
                         <entry>
-                            <key>interleaveBursts</key>
+                            <key>maximumPendingWriteTransactions</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>minimumReadLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumResponseLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>isAsynchronous</key>
+                            <key>printableDevice</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>isBigEndian</key>
+                            <key>readLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>isReadable</key>
+                            <key>registerOutgoingSignals</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>isWriteable</key>
+                            <key>setupTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
+                        </entry>
+                        <entry>
+                            <key>transparentBridge</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>linewrapBursts</key>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>maxAddressWidth</key>
-                            <value>32</value>
+                            <key>ptfSchematicName</key>
                         </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
                         <entry>
-                            <key>maximumPendingReadTransactions</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>maximumPendingWriteTransactions</key>
-                            <value>0</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
                         <entry>
-                            <key>minimumReadLatency</key>
-                            <value>1</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>minimumResponseLatency</key>
-                            <value>1</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
                             <key>prSafe</key>
                             <value>false</value>
                         </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
                         <entry>
-                            <key>readLatency</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>readWaitTime</key>
-                            <value>1</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>registerIncomingSignals</key>
-                            <value>true</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>registerOutgoingSignals</key>
+                            <key>prSafe</key>
                             <value>false</value>
                         </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>mem</key>
+                <value>
+                    <connectionPointName>mem</connectionPointName>
+                    <suppliedSystemInfos>
                         <entry>
-                            <key>setupTime</key>
-                            <value>0</value>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
-                            <key>timingUnits</key>
-                            <value>Cycles</value>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>14</value>
                         </entry>
                         <entry>
-                            <key>waitrequestAllowance</key>
-                            <value>0</value>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>32</value>
                         </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
                         <entry>
-                            <key>writeWaitTime</key>
-                            <value>0</value>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
                         </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>12</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>12</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>16384</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
+  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_jesd204b</hdlLibraryName>
+    <fileSets>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_jesd204b</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_jesd204b</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_jesd204b</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_jesd204b</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_jesd204b</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_jesd204b</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+  <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+   name="jtag_uart_0"
+   kind="altera_generic_component"
+   version="1.0"
+   enabled="1">
+  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+    <boundary>
+        <interfaces>
             <interface>
-                <name>debug_mem_slave</name>
+                <name>avalon_jtag_slave</name>
                 <type>avalon</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>debug_mem_slave_writedata</name>
-                        <role>writedata</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                    <port>
-                        <name>debug_mem_slave_byteenable</name>
-                        <role>byteenable</role>
-                        <direction>Input</direction>
-                        <width>4</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                    <port>
-                        <name>debug_mem_slave_address</name>
-                        <role>address</role>
-                        <direction>Input</direction>
-                        <width>9</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                    <port>
-                        <name>debug_mem_slave_debugaccess</name>
-                        <role>debugaccess</role>
+                        <name>av_chipselect</name>
+                        <role>chipselect</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>debug_mem_slave_readdata</name>
-                        <role>readdata</role>
-                        <direction>Output</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                    <port>
-                        <name>debug_mem_slave_waitrequest</name>
-                        <role>waitrequest</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                    <port>
-                        <name>debug_mem_slave_read</name>
-                        <role>read</role>
+                        <name>av_address</name>
+                        <role>address</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>debug_mem_slave_write</name>
-                        <role>write</role>
+                        <name>av_read_n</name>
+                        <role>read_n</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap>
-                        <entry>
-                            <key>embeddedsw.configuration.hideDevice</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>embeddedsw.configuration.isFlash</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>embeddedsw.configuration.isMemoryDevice</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>embeddedsw.configuration.isPrintableDevice</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>qsys.ui.connect</key>
-                            <value>instruction_master,data_master</value>
-                        </entry>
-                    </assignmentValueMap>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>addressAlignment</key>
-                            <value>DYNAMIC</value>
-                        </entry>
-                        <entry>
-                            <key>addressGroup</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>addressSpan</key>
-                            <value>2048</value>
-                        </entry>
-                        <entry>
-                            <key>addressUnits</key>
-                            <value>WORDS</value>
-                        </entry>
-                        <entry>
-                            <key>alwaysBurstMaxBurst</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>associatedClock</key>
-                            <value>clk</value>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                            <value>reset</value>
-                        </entry>
-                        <entry>
-                            <key>bitsPerSymbol</key>
-                            <value>8</value>
-                        </entry>
-                        <entry>
-                            <key>bridgedAddressOffset</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>bridgesToMaster</key>
-                        </entry>
-                        <entry>
-                            <key>burstOnBurstBoundariesOnly</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>burstcountUnits</key>
-                            <value>WORDS</value>
-                        </entry>
-                        <entry>
-                            <key>constantBurstBehavior</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>explicitAddressSpan</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>holdTime</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>interleaveBursts</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>isBigEndian</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>isFlash</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>isMemoryDevice</key>
-                            <value>true</value>
-                        </entry>
-                        <entry>
-                            <key>isNonVolatileStorage</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>linewrapBursts</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>maximumPendingReadTransactions</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>maximumPendingWriteTransactions</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>minimumReadLatency</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>minimumResponseLatency</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>minimumUninterruptedRunLength</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>printableDevice</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>readLatency</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>readWaitStates</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>readWaitTime</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>registerIncomingSignals</key>
-                            <value>true</value>
-                        </entry>
-                        <entry>
-                            <key>registerOutgoingSignals</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>setupTime</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>timingUnits</key>
-                            <value>Cycles</value>
-                        </entry>
-                        <entry>
-                            <key>transparentBridge</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>waitrequestAllowance</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>wellBehavedWaitrequest</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>writeLatency</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>writeWaitStates</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>writeWaitTime</key>
-                            <value>0</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>debug_reset_request</name>
-                <type>reset</type>
-                <isStart>true</isStart>
-                <ports>
-                    <port>
-                        <name>debug_reset_request</name>
-                        <role>reset</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                            <value>clk</value>
-                        </entry>
-                        <entry>
-                            <key>associatedDirectReset</key>
-                        </entry>
-                        <entry>
-                            <key>associatedResetSinks</key>
-                            <value>none</value>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>instruction_master</name>
-                <type>avalon</type>
-                <isStart>true</isStart>
-                <ports>
                     <port>
-                        <name>i_readdata</name>
+                        <name>av_readdata</name>
                         <role>readdata</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                    <port>
-                        <name>i_address</name>
-                        <role>address</role>
                         <direction>Output</direction>
-                        <width>18</width>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>i_read</name>
-                        <role>read</role>
-                        <direction>Output</direction>
+                        <name>av_write_n</name>
+                        <role>write_n</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>i_waitrequest</name>
-                        <role>waitrequest</role>
+                        <name>av_writedata</name>
+                        <role>writedata</role>
                         <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>av_waitrequest</name>
+                        <role>waitrequest</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
-                    <assignmentValueMap/>
+                    <assignmentValueMap>
+                        <entry>
+                            <key>embeddedsw.configuration.isFlash</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isMemoryDevice</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>embeddedsw.configuration.isPrintableDevice</key>
+                            <value>1</value>
+                        </entry>
+                    </assignmentValueMap>
                 </assignments>
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>adaptsTo</key>
+                            <key>addressAlignment</key>
+                            <value>NATIVE</value>
                         </entry>
                         <entry>
                             <key>addressGroup</key>
-                            <value>1</value>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>addressSpan</key>
+                            <value>2</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
-                            <value>SYMBOLS</value>
+                            <value>WORDS</value>
                         </entry>
                         <entry>
                             <key>alwaysBurstMaxBurst</key>
-                            <value>true</value>
+                            <value>false</value>
                         </entry>
                         <entry>
                             <key>associatedClock</key>
@@ -4245,28 +8629,27 @@
                             <value>8</value>
                         </entry>
                         <entry>
-                            <key>burstOnBurstBoundariesOnly</key>
-                            <value>false</value>
+                            <key>bridgedAddressOffset</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>burstcountUnits</key>
-                            <value>WORDS</value>
+                            <key>bridgesToMaster</key>
                         </entry>
                         <entry>
-                            <key>constantBurstBehavior</key>
+                            <key>burstOnBurstBoundariesOnly</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>dBSBigEndian</key>
-                            <value>false</value>
+                            <key>burstcountUnits</key>
+                            <value>WORDS</value>
                         </entry>
                         <entry>
-                            <key>doStreamReads</key>
+                            <key>constantBurstBehavior</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>doStreamWrites</key>
-                            <value>false</value>
+                            <key>explicitAddressSpan</key>
+                            <value>0</value>
                         </entry>
                         <entry>
                             <key>holdTime</key>
@@ -4277,28 +8660,24 @@
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>isAsynchronous</key>
+                            <key>isBigEndian</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>isBigEndian</key>
+                            <key>isFlash</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>isReadable</key>
+                            <key>isMemoryDevice</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>isWriteable</key>
+                            <key>isNonVolatileStorage</key>
                             <value>false</value>
                         </entry>
                         <entry>
                             <key>linewrapBursts</key>
-                            <value>true</value>
-                        </entry>
-                        <entry>
-                            <key>maxAddressWidth</key>
-                            <value>32</value>
+                            <value>false</value>
                         </entry>
                         <entry>
                             <key>maximumPendingReadTransactions</key>
@@ -4316,14 +8695,26 @@
                             <key>minimumResponseLatency</key>
                             <value>1</value>
                         </entry>
+                        <entry>
+                            <key>minimumUninterruptedRunLength</key>
+                            <value>1</value>
+                        </entry>
                         <entry>
                             <key>prSafe</key>
                             <value>false</value>
                         </entry>
+                        <entry>
+                            <key>printableDevice</key>
+                            <value>true</value>
+                        </entry>
                         <entry>
                             <key>readLatency</key>
                             <value>0</value>
                         </entry>
+                        <entry>
+                            <key>readWaitStates</key>
+                            <value>1</value>
+                        </entry>
                         <entry>
                             <key>readWaitTime</key>
                             <value>1</value>
@@ -4344,29 +8735,175 @@
                             <key>timingUnits</key>
                             <value>Cycles</value>
                         </entry>
+                        <entry>
+                            <key>transparentBridge</key>
+                            <value>false</value>
+                        </entry>
                         <entry>
                             <key>waitrequestAllowance</key>
                             <value>0</value>
                         </entry>
+                        <entry>
+                            <key>wellBehavedWaitrequest</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>writeLatency</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
+                        </entry>
                         <entry>
                             <key>writeWaitTime</key>
                             <value>0</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
+                <cmsisInfo>
+                    <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;    
+&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
+  &lt;peripherals&gt;
+   &lt;peripheral&gt;
+      &lt;name&gt;altera_avalon_jtag_uart&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; 
+      &lt;addressBlock&gt;
+        &lt;offset&gt;0x0&lt;/offset&gt;
+        &lt;size&gt;8&lt;/size&gt;
+        &lt;usage&gt;registers&lt;/usage&gt;
+      &lt;/addressBlock&gt;
+      &lt;registers&gt;
+        &lt;register&gt;     
+         &lt;name&gt;DATA&lt;/name&gt;  
+         &lt;displayName&gt;Data&lt;/displayName&gt;
+         &lt;description&gt;Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.&lt;/description&gt;
+         &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;data&lt;/name&gt;
+           &lt;description&gt;The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;8&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;rvalid&lt;/name&gt;
+           &lt;description&gt;Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.&lt;/description&gt;
+            &lt;bitOffset&gt;0xf&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;ravail&lt;/name&gt;
+           &lt;description&gt;The number of characters remaining in the read FIFO (after the current read).&lt;/description&gt;
+            &lt;bitOffset&gt;0x10&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;16&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;CONTROL&lt;/name&gt;  
+         &lt;displayName&gt;Control&lt;/displayName&gt;
+         &lt;description&gt;Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.&lt;/description&gt;
+         &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;re&lt;/name&gt;
+            &lt;description&gt;Interrupt-enable bit for read interrupts.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;we&lt;/name&gt;
+            &lt;description&gt;Interrupt-enable bit for write interrupts&lt;/description&gt;
+            &lt;bitOffset&gt;0x1&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;ri&lt;/name&gt;
+            &lt;description&gt;Indicates that the read interrupt is pending.&lt;/description&gt;
+            &lt;bitOffset&gt;0x8&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;wi&lt;/name&gt;
+            &lt;description&gt;Indicates that the write interrupt is pending.&lt;/description&gt;
+            &lt;bitOffset&gt;0x9&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;ac&lt;/name&gt;
+            &lt;description&gt;Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.&lt;/description&gt;
+            &lt;bitOffset&gt;0xa&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;wspace&lt;/name&gt;
+            &lt;description&gt;The number of spaces available in the write FIFO&lt;/description&gt;
+            &lt;bitOffset&gt;0x10&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;16&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt;            
+    &lt;/registers&gt;
+   &lt;/peripheral&gt;
+  &lt;/peripherals&gt;
+&lt;/device&gt; </cmsisSrcFileContents>
+                    <addressGroup></addressGroup>
+                    <cmsisVars/>
+                </cmsisInfo>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
             </interface>
             <interface>
                 <name>irq</name>
                 <type>interrupt</type>
-                <isStart>true</isStart>
+                <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>irq</name>
+                        <name>av_irq</name>
                         <role>irq</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -4376,7 +8913,7 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedAddressablePoint</key>
-                            <value>cpu_0.data_master</value>
+                            <value>jtag_uart_0.avalon_jtag_slave</value>
                         </entry>
                         <entry>
                             <key>associatedClock</key>
@@ -4387,11 +8924,15 @@
                             <value>reset</value>
                         </entry>
                         <entry>
-                            <key>irqMap</key>
+                            <key>bridgedReceiverOffset</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>bridgesToReceiver</key>
                         </entry>
                         <entry>
                             <key>irqScheme</key>
-                            <value>INDIVIDUAL_REQUESTS</value>
+                            <value>NONE</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -4402,21 +8943,13 @@
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>reset_n</name>
+                        <name>rst_n</name>
                         <role>reset_n</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
-                    <port>
-                        <name>reset_req</name>
-                        <role>reset_req</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
                 </ports>
                 <assignments>
                     <assignmentValueMap/>
@@ -4437,341 +8970,41 @@
         </interfaces>
     </boundary>
     <originalModuleInfo>
-        <className>altera_nios2_gen2</className>
-        <version>18.0</version>
-        <displayName>Nios II Processor</displayName>
-    </originalModuleInfo>
-    <systemInfoParameterDescriptors>
-        <descriptors>
-            <descriptor>
-                <parameterDefaultValue>-1</parameterDefaultValue>
-                <parameterName>AUTO_CLK_CLOCK_DOMAIN</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>clk</systemInfoArgs>
-                <systemInfotype>CLOCK_DOMAIN</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>-1</parameterDefaultValue>
-                <parameterName>AUTO_CLK_RESET_DOMAIN</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>clk</systemInfoArgs>
-                <systemInfotype>RESET_DOMAIN</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>AUTO_DEVICE</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>DEVICE</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>AUTO_DEVICE_SPEEDGRADE</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>DEVICE_SPEEDGRADE</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>50000000</parameterDefaultValue>
-                <parameterName>clockFrequency</parameterName>
-                <parameterType>java.lang.Long</parameterType>
-                <systemInfoArgs>clk</systemInfoArgs>
-                <systemInfotype>CLOCK_RATE</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>customInstSlavesSystemInfo</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>custom_instruction_master</systemInfoArgs>
-                <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>customInstSlavesSystemInfo_nios_a</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>custom_instruction_master_a</systemInfoArgs>
-                <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>customInstSlavesSystemInfo_nios_b</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>custom_instruction_master_b</systemInfoArgs>
-                <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>customInstSlavesSystemInfo_nios_c</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>custom_instruction_master_c</systemInfoArgs>
-                <systemInfotype>CUSTOM_INSTRUCTION_SLAVES</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>dataAddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>data_master</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>dataMasterHighPerformanceAddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>data_master_high_performance</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>dataMasterHighPerformanceMapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>data_master_high_performance</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>dataSlaveMapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>data_master</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>STRATIXIV</parameterDefaultValue>
-                <parameterName>deviceFamilyName</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>DEVICE_FAMILY</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>deviceFeaturesSystemInfo</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>DEVICE_FEATURES</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>faAddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>flash_instruction_master</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>faSlaveMapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>flash_instruction_master</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>instAddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>instruction_master</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>instSlaveMapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>instruction_master</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>instructionMasterHighPerformanceAddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>instruction_master_high_performance</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>instructionMasterHighPerformanceMapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>instruction_master_high_performance</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>0</parameterDefaultValue>
-                <parameterName>internalIrqMaskSystemInfo</parameterName>
-                <parameterType>java.lang.Long</parameterType>
-                <systemInfoArgs>irq</systemInfoArgs>
-                <systemInfotype>INTERRUPTS_USED</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>tightlyCoupledDataMaster0AddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>tightlyCoupledDataMaster0MapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>tightly_coupled_data_master_0</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>tightlyCoupledDataMaster1AddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>tightlyCoupledDataMaster1MapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>tightly_coupled_data_master_1</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>tightlyCoupledDataMaster2AddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>tightlyCoupledDataMaster2MapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>tightly_coupled_data_master_2</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>tightlyCoupledDataMaster3AddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>tightlyCoupledDataMaster3MapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>tightly_coupled_data_master_3</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>tightlyCoupledInstructionMaster0AddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>tightlyCoupledInstructionMaster0MapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>tightly_coupled_instruction_master_0</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>tightlyCoupledInstructionMaster1AddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>tightlyCoupledInstructionMaster1MapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>tightly_coupled_instruction_master_1</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>tightlyCoupledInstructionMaster2AddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
-            </descriptor>
+        <className>altera_avalon_jtag_uart</className>
+        <version>19.1.0</version>
+        <displayName>JTAG UART Intel FPGA IP</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
             <descriptor>
                 <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>tightlyCoupledInstructionMaster2MapParam</parameterName>
+                <parameterName>avalonSpec</parameterName>
                 <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>tightly_coupled_instruction_master_2</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>1</parameterDefaultValue>
-                <parameterName>tightlyCoupledInstructionMaster3AddrWidth</parameterName>
-                <parameterType>java.lang.Integer</parameterType>
-                <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs>
-                <systemInfotype>ADDRESS_WIDTH</systemInfotype>
+                <systemInfotype>AVALON_SPEC</systemInfotype>
             </descriptor>
             <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>tightlyCoupledInstructionMaster3MapParam</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfoArgs>tightly_coupled_instruction_master_3</systemInfoArgs>
-                <systemInfotype>ADDRESS_MAP</systemInfotype>
+                <parameterDefaultValue>0</parameterDefaultValue>
+                <parameterName>clkFreq</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>clk</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
             </descriptor>
         </descriptors>
     </systemInfoParameterDescriptors>
     <systemInfos>
         <connPtSystemInfos>
             <entry>
-                <key>clk</key>
-                <value>
-                    <connectionPointName>clk</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>CLOCK_DOMAIN</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>100000000</value>
-                        </entry>
-                        <entry>
-                            <key>RESET_DOMAIN</key>
-                            <value>1</value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
-            <entry>
-                <key>custom_instruction_master</key>
-                <value>
-                    <connectionPointName>custom_instruction_master</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>CUSTOM_INSTRUCTION_SLAVES</key>
-                            <value></value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
-            <entry>
-                <key>data_master</key>
-                <value>
-                    <connectionPointName>data_master</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0x40000' end='0x44000' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x48000' end='0x48400' datawidth='32' /&gt;&lt;slave name='reg_wg_0.mem' start='0x4C000' end='0x4C010' datawidth='32' /&gt;&lt;slave name='reg_wg_1.mem' start='0x4C010' end='0x4C020' datawidth='32' /&gt;&lt;slave name='reg_wg_2.mem' start='0x4C020' end='0x4C030' datawidth='32' /&gt;&lt;slave name='reg_wg_3.mem' start='0x4C030' end='0x4C040' datawidth='32' /&gt;&lt;slave name='ram_wg_0.mem' start='0x50000' end='0x51000' datawidth='32' /&gt;&lt;slave name='ram_wg_1.mem' start='0x51000' end='0x52000' datawidth='32' /&gt;&lt;slave name='ram_wg_2.mem' start='0x52000' end='0x53000' datawidth='32' /&gt;&lt;slave name='ram_wg_3.mem' start='0x53000' end='0x54000' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_jesd.mem' start='0x80000' end='0x100000' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_jesd.mem' start='0x100000' end='0x104000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
-                        </entry>
-                        <entry>
-                            <key>ADDRESS_WIDTH</key>
-                            <value>21</value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
-            <entry>
-                <key>debug_mem_slave</key>
+                <key>avalon_jtag_slave</key>
                 <value>
-                    <connectionPointName>debug_mem_slave</connectionPointName>
+                    <connectionPointName>avalon_jtag_slave</connectionPointName>
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='debug_mem_slave' start='0x0' end='0x800' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>11</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -4782,31 +9015,14 @@
                 </value>
             </entry>
             <entry>
-                <key>instruction_master</key>
-                <value>
-                    <connectionPointName>instruction_master</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
-                        </entry>
-                        <entry>
-                            <key>ADDRESS_WIDTH</key>
-                            <value>18</value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
-            <entry>
-                <key>irq</key>
+                <key>clk</key>
                 <value>
-                    <connectionPointName>irq</connectionPointName>
+                    <connectionPointName>clk</connectionPointName>
                     <suppliedSystemInfos/>
                     <consumedSystemInfos>
                         <entry>
-                            <key>INTERRUPTS_USED</key>
-                            <value>7</value>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
                         </entry>
                     </consumedSystemInfos>
                 </value>
@@ -4814,229 +9030,519 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>avalon_jtag_slave</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>av_chipselect</name>
+                    <role>chipselect</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>av_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>av_read_n</name>
+                    <role>read_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>av_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>av_write_n</name>
+                    <role>write_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>av_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>av_waitrequest</name>
+                    <role>waitrequest</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>1</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>NATIVE</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>2</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>true</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+            <cmsisInfo>
+                <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;    
+&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
+  &lt;peripherals&gt;
+   &lt;peripheral&gt;
+      &lt;name&gt;altera_avalon_jtag_uart&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; 
+      &lt;addressBlock&gt;
+        &lt;offset&gt;0x0&lt;/offset&gt;
+        &lt;size&gt;8&lt;/size&gt;
+        &lt;usage&gt;registers&lt;/usage&gt;
+      &lt;/addressBlock&gt;
+      &lt;registers&gt;
+        &lt;register&gt;     
+         &lt;name&gt;DATA&lt;/name&gt;  
+         &lt;displayName&gt;Data&lt;/displayName&gt;
+         &lt;description&gt;Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.&lt;/description&gt;
+         &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;data&lt;/name&gt;
+           &lt;description&gt;The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;8&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;rvalid&lt;/name&gt;
+           &lt;description&gt;Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.&lt;/description&gt;
+            &lt;bitOffset&gt;0xf&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;ravail&lt;/name&gt;
+           &lt;description&gt;The number of characters remaining in the read FIFO (after the current read).&lt;/description&gt;
+            &lt;bitOffset&gt;0x10&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;16&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;CONTROL&lt;/name&gt;  
+         &lt;displayName&gt;Control&lt;/displayName&gt;
+         &lt;description&gt;Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.&lt;/description&gt;
+         &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;re&lt;/name&gt;
+            &lt;description&gt;Interrupt-enable bit for read interrupts.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;we&lt;/name&gt;
+            &lt;description&gt;Interrupt-enable bit for write interrupts&lt;/description&gt;
+            &lt;bitOffset&gt;0x1&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;ri&lt;/name&gt;
+            &lt;description&gt;Indicates that the read interrupt is pending.&lt;/description&gt;
+            &lt;bitOffset&gt;0x8&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;wi&lt;/name&gt;
+            &lt;description&gt;Indicates that the write interrupt is pending.&lt;/description&gt;
+            &lt;bitOffset&gt;0x9&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;ac&lt;/name&gt;
+            &lt;description&gt;Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.&lt;/description&gt;
+            &lt;bitOffset&gt;0xa&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+           &lt;field&gt;&lt;name&gt;wspace&lt;/name&gt;
+            &lt;description&gt;The number of spaces available in the write FIFO&lt;/description&gt;
+            &lt;bitOffset&gt;0x10&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;16&lt;/bitWidth&gt;
+            &lt;access&gt;read-only&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt;            
+    &lt;/registers&gt;
+   &lt;/peripheral&gt;
+  &lt;/peripherals&gt;
+&lt;/device&gt; </cmsisSrcFileContents>
+                <addressGroup></addressGroup>
+                <cmsisVars/>
+            </cmsisInfo>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>irq</name>
+            <type>interrupt</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>av_irq</name>
+                    <role>irq</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedAddressablePoint</key>
+                        <value>jtag_uart_0.avalon_jtag_slave</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>reset</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedReceiverOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToReceiver</key>
+                    </entry>
+                    <entry>
+                        <key>irqScheme</key>
+                        <value>NONE</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>rst_n</name>
+                    <role>reset_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_cpu_0</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_jtag_uart_0</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_cpu_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_cpu_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_cpu_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_cpu_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_cpu_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_cpu_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap>
         <entry>
-            <key>debug.hostConnection</key>
-            <value>type jtag id 70:34|110:135</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.BIG_ENDIAN</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.BREAK_ADDR</key>
-            <value>0x00003820</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
-            <value></value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.CPU_FREQ</key>
-            <value>100000000u</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.CPU_ID_SIZE</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.CPU_ID_VALUE</key>
-            <value>0x00000000</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.CPU_IMPLEMENTATION</key>
-            <value>"tiny"</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.DATA_ADDR_WIDTH</key>
-            <value>21</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.DCACHE_LINE_SIZE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.DCACHE_SIZE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.EXCEPTION_ADDR</key>
-            <value>0x00020020</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.FLUSHDA_SUPPORTED</key>
-            <value></value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HAS_DEBUG_CORE</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HAS_DEBUG_STUB</key>
-            <value></value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</key>
-            <value></value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</key>
-            <value></value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.ICACHE_LINE_SIZE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.ICACHE_SIZE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.INST_ADDR_WIDTH</key>
-            <value>18</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.OCI_VERSION</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.RESET_ADDR</key>
-            <value>0x00020000</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.configuration.DataCacheVictimBufImpl</key>
-            <value>ram</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.configuration.HDLSimCachesCleared</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.configuration.breakOffset</key>
-            <value>32</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.configuration.breakSlave</key>
-            <value>cpu_0.debug_mem_slave</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.configuration.cpuArchitecture</key>
-            <value>Nios II</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.configuration.exceptionOffset</key>
-            <value>32</value>
+            <key>embeddedsw.CMacro.READ_DEPTH</key>
+            <value>64</value>
         </entry>
         <entry>
-            <key>embeddedsw.configuration.exceptionSlave</key>
-            <value>onchip_memory2_0.s1</value>
+            <key>embeddedsw.CMacro.READ_THRESHOLD</key>
+            <value>8</value>
         </entry>
         <entry>
-            <key>embeddedsw.configuration.resetOffset</key>
-            <value>0</value>
+            <key>embeddedsw.CMacro.WRITE_DEPTH</key>
+            <value>64</value>
         </entry>
         <entry>
-            <key>embeddedsw.configuration.resetSlave</key>
-            <value>onchip_memory2_0.s1</value>
+            <key>embeddedsw.CMacro.WRITE_THRESHOLD</key>
+            <value>8</value>
         </entry>
         <entry>
             <key>embeddedsw.dts.compatible</key>
-            <value>altr,nios2-1.1</value>
+            <value>altr,juart-1.0</value>
         </entry>
         <entry>
             <key>embeddedsw.dts.group</key>
-            <value>cpu</value>
+            <value>serial</value>
         </entry>
         <entry>
             <key>embeddedsw.dts.name</key>
-            <value>nios2</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.altr,exception-addr</key>
-            <value>0x00020020</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.altr,implementation</key>
-            <value>"tiny"</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.altr,reset-addr</key>
-            <value>0x00020000</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.clock-frequency</key>
-            <value>100000000u</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.dcache-line-size</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.dcache-size</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.icache-line-size</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.icache-size</key>
-            <value>0</value>
+            <value>juart</value>
         </entry>
         <entry>
             <key>embeddedsw.dts.vendor</key>
@@ -5047,7 +9553,7 @@
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="jesd204b"
+   name="onchip_memory2_0"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -5055,17 +9561,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>clk1</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>12</width>
+                        <name>clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -5074,27 +9580,36 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>reset1</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>reset_req</name>
+                        <role>reset_req</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -5107,40 +9622,54 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>clk1</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>mem</name>
+                <name>s1</name>
                 <type>avalon</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>avs_mem_read</name>
-                        <role>read</role>
+                        <name>address</name>
+                        <role>address</role>
+                        <direction>Input</direction>
+                        <width>15</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                    <port>
+                        <name>clken</name>
+                        <role>clken</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>avs_mem_address</name>
-                        <role>address</role>
+                        <name>chipselect</name>
+                        <role>chipselect</role>
                         <direction>Input</direction>
-                        <width>12</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>avs_mem_readdata</name>
+                        <name>write</name>
+                        <role>write</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                    <port>
+                        <name>readdata</name>
                         <role>readdata</role>
                         <direction>Output</direction>
                         <width>32</width>
@@ -5148,18 +9677,18 @@
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>avs_mem_write</name>
-                        <role>write</role>
+                        <name>writedata</name>
+                        <role>writedata</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>avs_mem_writedata</name>
-                        <role>writedata</role>
+                        <name>byteenable</name>
+                        <role>byteenable</role>
                         <direction>Input</direction>
-                        <width>32</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -5172,7 +9701,7 @@
                         </entry>
                         <entry>
                             <key>embeddedsw.configuration.isMemoryDevice</key>
-                            <value>0</value>
+                            <value>1</value>
                         </entry>
                         <entry>
                             <key>embeddedsw.configuration.isNonVolatileStorage</key>
@@ -5196,7 +9725,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16384</value>
+                            <value>131072</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -5208,11 +9737,11 @@
                         </entry>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
+                            <value>clk1</value>
                         </entry>
                         <entry>
                             <key>associatedReset</key>
-                            <value>system_reset</value>
+                            <value>reset1</value>
                         </entry>
                         <entry>
                             <key>bitsPerSymbol</key>
@@ -5239,7 +9768,7 @@
                         </entry>
                         <entry>
                             <key>explicitAddressSpan</key>
-                            <value>0</value>
+                            <value>131072</value>
                         </entry>
                         <entry>
                             <key>holdTime</key>
@@ -5259,7 +9788,7 @@
                         </entry>
                         <entry>
                             <key>isMemoryDevice</key>
-                            <value>false</value>
+                            <value>true</value>
                         </entry>
                         <entry>
                             <key>isNonVolatileStorage</key>
@@ -5291,286 +9820,63 @@
                         </entry>
                         <entry>
                             <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>printableDevice</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>readLatency</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>readWaitStates</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>readWaitTime</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>registerIncomingSignals</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>registerOutgoingSignals</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>setupTime</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>timingUnits</key>
-                            <value>Cycles</value>
-                        </entry>
-                        <entry>
-                            <key>transparentBridge</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>waitrequestAllowance</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>wellBehavedWaitrequest</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>writeLatency</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>writeWaitStates</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>writeWaitTime</key>
-                            <value>0</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>read</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_read_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>reset</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_reset_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>system</name>
-                <type>clock</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
+                            <value>false</value>
+                        </entry>
                         <entry>
-                            <key>clockRate</key>
+                            <key>printableDevice</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>readLatency</key>
+                            <value>1</value>
+                        </entry>
+                        <entry>
+                            <key>readWaitStates</key>
                             <value>0</value>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
+                            <key>readWaitTime</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>registerIncomingSignals</key>
                             <value>false</value>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>registerOutgoingSignals</key>
+                            <value>false</value>
                         </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>system_reset</name>
-                <type>reset</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
-                            <value>system</value>
+                            <key>setupTime</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>timingUnits</key>
+                            <value>Cycles</value>
                         </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>write</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>transparentBridge</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>waitrequestAllowance</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
+                            <key>wellBehavedWaitrequest</key>
                             <value>false</value>
                         </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>writedata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_writedata_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>writeLatency</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>writeWaitStates</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>writeWaitTime</key>
+                            <value>0</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -5578,35 +9884,46 @@
         </interfaces>
     </boundary>
     <originalModuleInfo>
-        <className>avs_common_mm</className>
-        <version>1.0</version>
-        <displayName>avs_common_mm</displayName>
+        <className>altera_avalon_onchip_memory2</className>
+        <version>19.2.0</version>
+        <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
     </originalModuleInfo>
     <systemInfoParameterDescriptors>
         <descriptors>
             <descriptor>
-                <parameterDefaultValue>-1</parameterDefaultValue>
-                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
-                <parameterType>java.lang.Long</parameterType>
-                <systemInfoArgs>system</systemInfoArgs>
-                <systemInfotype>CLOCK_RATE</systemInfotype>
+                <parameterDefaultValue></parameterDefaultValue>
+                <parameterName>autoInitializationFileName</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfotype>UNIQUE_ID</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>NONE</parameterDefaultValue>
+                <parameterName>deviceFamily</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfotype>DEVICE_FAMILY</systemInfotype>
+            </descriptor>
+            <descriptor>
+                <parameterDefaultValue>NONE</parameterDefaultValue>
+                <parameterName>deviceFeatures</parameterName>
+                <parameterType>java.lang.String</parameterType>
+                <systemInfotype>DEVICE_FEATURES</systemInfotype>
             </descriptor>
         </descriptors>
     </systemInfoParameterDescriptors>
     <systemInfos>
         <connPtSystemInfos>
             <entry>
-                <key>mem</key>
+                <key>s1</key>
                 <value>
-                    <connectionPointName>mem</connectionPointName>
+                    <connectionPointName>s1</connectionPointName>
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x20000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>14</value>
+                            <value>17</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -5616,31 +9933,18 @@
                     <consumedSystemInfos/>
                 </value>
             </entry>
-            <entry>
-                <key>system</key>
-                <value>
-                    <connectionPointName>system</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>100000000</value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
+            <name>clk1</name>
             <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
+                    <name>clk</name>
                     <role>clk</role>
                     <direction>Input</direction>
                     <width>1</width>
@@ -5668,18 +9972,26 @@
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
+            <name>reset1</name>
             <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
+                    <name>reset</name>
                     <role>reset</role>
                     <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
                 </port>
+                <port>
+                    <name>reset_req</name>
+                    <role>reset_req</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
             </ports>
             <assignments>
                 <assignmentValueMap/>
@@ -5688,7 +10000,7 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
+                        <value>clk1</value>
                     </entry>
                     <entry>
                         <key>synchronousEdges</key>
@@ -5698,64 +10010,84 @@
             </parameters>
         </interface>
         <interface>
-            <name>mem</name>
+            <name>s1</name>
             <type>avalon</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>avs_mem_address</name>
+                    <name>address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>12</width>
+                    <width>15</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
                 <port>
-                    <name>avs_mem_write</name>
-                    <role>write</role>
+                    <name>clken</name>
+                    <role>clken</role>
                     <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
                 </port>
                 <port>
-                    <name>avs_mem_writedata</name>
-                    <role>writedata</role>
+                    <name>chipselect</name>
+                    <role>chipselect</role>
                     <direction>Input</direction>
-                    <width>32</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
                 <port>
-                    <name>avs_mem_read</name>
-                    <role>read</role>
+                    <name>write</name>
+                    <role>write</role>
                     <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
                 </port>
                 <port>
-                    <name>avs_mem_readdata</name>
+                    <name>readdata</name>
                     <role>readdata</role>
                     <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
+                <port>
+                    <name>writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>byteenable</name>
+                    <role>byteenable</role>
+                    <direction>Input</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>1</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -5771,7 +10103,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16384</value>
+                        <value>131072</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -5783,11 +10115,11 @@
                     </entry>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
+                        <value>clk1</value>
                     </entry>
                     <entry>
                         <key>associatedReset</key>
-                        <value>system_reset</value>
+                        <value>reset1</value>
                     </entry>
                     <entry>
                         <key>bitsPerSymbol</key>
@@ -5795,6 +10127,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -5813,7 +10146,7 @@
                     </entry>
                     <entry>
                         <key>explicitAddressSpan</key>
-                        <value>0</value>
+                        <value>131072</value>
                     </entry>
                     <entry>
                         <key>holdTime</key>
@@ -5833,7 +10166,7 @@
                     </entry>
                     <entry>
                         <key>isMemoryDevice</key>
-                        <value>false</value>
+                        <value>true</value>
                     </entry>
                     <entry>
                         <key>isNonVolatileStorage</key>
@@ -5926,264 +10259,137 @@
                 </parameterValueMap>
             </parameters>
         </interface>
-        <interface>
-            <name>reset</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_reset_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>clk</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_clk_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>address</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_address_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>12</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>write</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>writedata</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>read</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_read_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
-        <interface>
-            <name>readdata</name>
-            <type>conduit</type>
-            <isStart>false</isStart>
-            <ports>
-                <port>
-                    <name>coe_readdata_export</name>
-                    <role>export</role>
-                    <direction>Input</direction>
-                    <width>32</width>
-                    <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                </port>
-            </ports>
-            <assignments>
-                <assignmentValueMap/>
-            </assignments>
-            <parameters>
-                <parameterValueMap>
-                    <entry>
-                        <key>associatedClock</key>
-                    </entry>
-                    <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
-                    </entry>
-                </parameterValueMap>
-            </parameters>
-        </interface>
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_avs_common_mm_0</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_onchip_memory2_0</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
-    <assignmentValueMap/>
+    <assignmentValueMap>
+        <entry>
+            <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.CONTENTS_INFO</key>
+            <value>""</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.DUAL_PORT</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key>
+            <value>AUTO</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key>
+            <value>onchip_memory2_0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.INSTANCE_ID</key>
+            <value>NONE</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key>
+            <value>AUTO</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key>
+            <value>DONT_CARE</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.SIZE_MULTIPLE</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.SIZE_VALUE</key>
+            <value>131072</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.WRITABLE</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key>
+            <value>SIM_DIR</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.memoryInfo.GENERATE_HEX</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key>
+            <value>QPF_DIR</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key>
+            <value>32</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key>
+            <value>onchip_memory2_0</value>
+        </entry>
+        <entry>
+            <key>postgeneration.simulation.init_file.param_name</key>
+            <value>INIT_FILE</value>
+        </entry>
+        <entry>
+            <key>postgeneration.simulation.init_file.type</key>
+            <value>MEM_INIT</value>
+        </entry>
+    </assignmentValueMap>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="jtag_uart_0"
+   name="pio_pps"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -6191,52 +10397,92 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>avalon_jtag_slave</name>
-                <type>avalon</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>av_chipselect</name>
-                        <role>chipselect</role>
-                        <direction>Input</direction>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>clk</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
                     <port>
-                        <name>av_address</name>
-                        <role>address</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>mem</name>
+                <type>avalon</type>
+                <isStart>false</isStart>
+                <ports>
                     <port>
-                        <name>av_read_n</name>
-                        <role>read_n</role>
+                        <name>avs_mem_address</name>
+                        <role>address</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                    <port>
-                        <name>av_readdata</name>
-                        <role>readdata</role>
-                        <direction>Output</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>av_write_n</name>
-                        <role>write_n</role>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>av_writedata</name>
+                        <name>avs_mem_writedata</name>
                         <role>writedata</role>
                         <direction>Input</direction>
                         <width>32</width>
@@ -6244,13 +10490,21 @@
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>av_waitrequest</name>
-                        <role>waitrequest</role>
-                        <direction>Output</direction>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
+                    <port>
+                        <name>avs_mem_readdata</name>
+                        <role>readdata</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
                 </ports>
                 <assignments>
                     <assignmentValueMap>
@@ -6268,7 +10522,7 @@
                         </entry>
                         <entry>
                             <key>embeddedsw.configuration.isPrintableDevice</key>
-                            <value>1</value>
+                            <value>0</value>
                         </entry>
                     </assignmentValueMap>
                 </assignments>
@@ -6276,7 +10530,7 @@
                     <parameterValueMap>
                         <entry>
                             <key>addressAlignment</key>
-                            <value>NATIVE</value>
+                            <value>DYNAMIC</value>
                         </entry>
                         <entry>
                             <key>addressGroup</key>
@@ -6284,7 +10538,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>2</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -6296,11 +10550,11 @@
                         </entry>
                         <entry>
                             <key>associatedClock</key>
-                            <value>clk</value>
+                            <value>system</value>
                         </entry>
                         <entry>
                             <key>associatedReset</key>
-                            <value>reset</value>
+                            <value>system_reset</value>
                         </entry>
                         <entry>
                             <key>bitsPerSymbol</key>
@@ -6383,19 +10637,19 @@
                         </entry>
                         <entry>
                             <key>printableDevice</key>
-                            <value>true</value>
+                            <value>false</value>
                         </entry>
                         <entry>
                             <key>readLatency</key>
-                            <value>0</value>
+                            <value>1</value>
                         </entry>
                         <entry>
                             <key>readWaitStates</key>
-                            <value>1</value>
+                            <value>0</value>
                         </entry>
                         <entry>
                             <key>readWaitTime</key>
-                            <value>1</value>
+                            <value>0</value>
                         </entry>
                         <entry>
                             <key>registerIncomingSignals</key>
@@ -6439,113 +10693,16 @@
                         </entry>
                     </parameterValueMap>
                 </parameters>
-                <cmsisInfo>
-                    <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;    
-&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
-  &lt;peripherals&gt;
-   &lt;peripheral&gt;
-      &lt;name&gt;altera_avalon_jtag_uart&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; 
-      &lt;addressBlock&gt;
-        &lt;offset&gt;0x0&lt;/offset&gt;
-        &lt;size&gt;8&lt;/size&gt;
-        &lt;usage&gt;registers&lt;/usage&gt;
-      &lt;/addressBlock&gt;
-      &lt;registers&gt;
-        &lt;register&gt;     
-         &lt;name&gt;DATA&lt;/name&gt;  
-         &lt;displayName&gt;Data&lt;/displayName&gt;
-         &lt;description&gt;Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.&lt;/description&gt;
-         &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
-         &lt;size&gt;32&lt;/size&gt;
-         &lt;access&gt;read-write&lt;/access&gt;
-         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
-         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
-         &lt;fields&gt;
-           &lt;field&gt;&lt;name&gt;data&lt;/name&gt;
-           &lt;description&gt;The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.&lt;/description&gt;
-            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;8&lt;/bitWidth&gt;
-            &lt;access&gt;read-write&lt;/access&gt;
-        &lt;/field&gt;
-           &lt;field&gt;&lt;name&gt;rvalid&lt;/name&gt;
-           &lt;description&gt;Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.&lt;/description&gt;
-            &lt;bitOffset&gt;0xf&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
-            &lt;access&gt;read-only&lt;/access&gt;
-        &lt;/field&gt;
-           &lt;field&gt;&lt;name&gt;ravail&lt;/name&gt;
-           &lt;description&gt;The number of characters remaining in the read FIFO (after the current read).&lt;/description&gt;
-            &lt;bitOffset&gt;0x10&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;16&lt;/bitWidth&gt;
-            &lt;access&gt;read-only&lt;/access&gt;
-        &lt;/field&gt;
-       &lt;/fields&gt;
-     &lt;/register&gt; 
-        &lt;register&gt;     
-         &lt;name&gt;CONTROL&lt;/name&gt;  
-         &lt;displayName&gt;Control&lt;/displayName&gt;
-         &lt;description&gt;Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.&lt;/description&gt;
-         &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
-         &lt;size&gt;32&lt;/size&gt;
-         &lt;access&gt;read-write&lt;/access&gt;
-         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
-         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
-         &lt;fields&gt;
-           &lt;field&gt;&lt;name&gt;re&lt;/name&gt;
-            &lt;description&gt;Interrupt-enable bit for read interrupts.&lt;/description&gt;
-            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
-            &lt;access&gt;read-write&lt;/access&gt;
-        &lt;/field&gt;
-           &lt;field&gt;&lt;name&gt;we&lt;/name&gt;
-            &lt;description&gt;Interrupt-enable bit for write interrupts&lt;/description&gt;
-            &lt;bitOffset&gt;0x1&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
-            &lt;access&gt;read-write&lt;/access&gt;
-        &lt;/field&gt;
-           &lt;field&gt;&lt;name&gt;ri&lt;/name&gt;
-            &lt;description&gt;Indicates that the read interrupt is pending.&lt;/description&gt;
-            &lt;bitOffset&gt;0x8&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
-            &lt;access&gt;read-only&lt;/access&gt;
-        &lt;/field&gt;
-           &lt;field&gt;&lt;name&gt;wi&lt;/name&gt;
-            &lt;description&gt;Indicates that the write interrupt is pending.&lt;/description&gt;
-            &lt;bitOffset&gt;0x9&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
-            &lt;access&gt;read-only&lt;/access&gt;
-        &lt;/field&gt;
-           &lt;field&gt;&lt;name&gt;ac&lt;/name&gt;
-            &lt;description&gt;Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.&lt;/description&gt;
-            &lt;bitOffset&gt;0xa&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;1&lt;/bitWidth&gt;
-            &lt;access&gt;read-write&lt;/access&gt;
-        &lt;/field&gt;
-           &lt;field&gt;&lt;name&gt;wspace&lt;/name&gt;
-            &lt;description&gt;The number of spaces available in the write FIFO&lt;/description&gt;
-            &lt;bitOffset&gt;0x10&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;16&lt;/bitWidth&gt;
-            &lt;access&gt;read-only&lt;/access&gt;
-        &lt;/field&gt;
-       &lt;/fields&gt;
-     &lt;/register&gt;            
-    &lt;/registers&gt;
-   &lt;/peripheral&gt;
-  &lt;/peripherals&gt;
-&lt;/device&gt; </cmsisSrcFileContents>
-                    <addressGroup></addressGroup>
-                    <cmsisVars/>
-                </cmsisInfo>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>clock</type>
+                <name>read</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -6557,27 +10714,58 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
                             <value>false</value>
                         </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>irq</name>
-                <type>interrupt</type>
+                <name>reset</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>av_irq</name>
-                        <role>irq</role>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
@@ -6589,40 +10777,60 @@
                 </assignments>
                 <parameters>
                     <parameterValueMap>
-                        <entry>
-                            <key>associatedAddressablePoint</key>
-                            <value>jtag_uart_0.avalon_jtag_slave</value>
-                        </entry>
                         <entry>
                             <key>associatedClock</key>
-                            <value>clk</value>
                         </entry>
                         <entry>
                             <key>associatedReset</key>
-                            <value>reset</value>
                         </entry>
                         <entry>
-                            <key>bridgedReceiverOffset</key>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
                             <value>0</value>
                         </entry>
                         <entry>
-                            <key>bridgesToReceiver</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>irqScheme</key>
-                            <value>NONE</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>system_reset</name>
                 <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>rst_n</name>
-                        <role>reset_n</role>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
@@ -6636,7 +10844,7 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>clk</value>
+                            <value>system</value>
                         </entry>
                         <entry>
                             <key>synchronousEdges</key>
@@ -6645,26 +10853,84 @@
                     </parameterValueMap>
                 </parameters>
             </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
         </interfaces>
     </boundary>
     <originalModuleInfo>
-        <className>altera_avalon_jtag_uart</className>
-        <version>18.0</version>
-        <displayName>JTAG UART Intel FPGA IP</displayName>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
     </originalModuleInfo>
     <systemInfoParameterDescriptors>
         <descriptors>
             <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>avalonSpec</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>AVALON_SPEC</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>0</parameterDefaultValue>
-                <parameterName>clkFreq</parameterName>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
                 <parameterType>java.lang.Long</parameterType>
-                <systemInfoArgs>clk</systemInfoArgs>
+                <systemInfoArgs>system</systemInfoArgs>
                 <systemInfotype>CLOCK_RATE</systemInfotype>
             </descriptor>
         </descriptors>
@@ -6672,13 +10938,13 @@
     <systemInfos>
         <connPtSystemInfos>
             <entry>
-                <key>avalon_jtag_slave</key>
+                <key>mem</key>
                 <value>
-                    <connectionPointName>avalon_jtag_slave</connectionPointName>
+                    <connectionPointName>mem</connectionPointName>
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='avalon_jtag_slave' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
@@ -6693,9 +10959,9 @@
                 </value>
             </entry>
             <entry>
-                <key>clk</key>
+                <key>system</key>
                 <value>
-                    <connectionPointName>clk</connectionPointName>
+                    <connectionPointName>system</connectionPointName>
                     <suppliedSystemInfos/>
                     <consumedSystemInfos>
                         <entry>
@@ -6708,72 +10974,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_jtag_uart_0</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_pio_pps</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_pio_pps</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_pps</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_pio_pps</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_pps</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_jtag_uart_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_pio_pps</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_pps</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-    </fileSets>
-</generationInfoDefinition>]]></parameter>
-  <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip</parameter>
-  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
-    <assignmentValueMap>
-        <entry>
-            <key>embeddedsw.CMacro.READ_DEPTH</key>
-            <value>64</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.READ_THRESHOLD</key>
-            <value>8</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.WRITE_DEPTH</key>
-            <value>64</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.WRITE_THRESHOLD</key>
-            <value>8</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.compatible</key>
-            <value>altr,juart-1.0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.group</key>
-            <value>serial</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.name</key>
-            <value>juart</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.vendor</key>
-            <value>altr</value>
-        </entry>
-    </assignmentValueMap>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="onchip_memory2_0"
+   name="pio_system_info"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -6781,17 +11538,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>clk1</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -6800,36 +11557,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>reset1</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                    <port>
-                        <name>reset_req</name>
-                        <role>reset_req</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -6842,76 +11590,62 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>clk1</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>s1</name>
+                <name>mem</name>
                 <type>avalon</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>address</name>
+                        <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>15</width>
+                        <width>5</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>clken</name>
-                        <role>clken</role>
+                        <name>avs_mem_write</name>
+                        <role>write</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>chipselect</name>
-                        <role>chipselect</role>
+                        <name>avs_mem_writedata</name>
+                        <role>writedata</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>write</name>
-                        <role>write</role>
+                        <name>avs_mem_read</name>
+                        <role>read</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>readdata</name>
+                        <name>avs_mem_readdata</name>
                         <role>readdata</role>
                         <direction>Output</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
-                    <port>
-                        <name>writedata</name>
-                        <role>writedata</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                    <port>
-                        <name>byteenable</name>
-                        <role>byteenable</role>
-                        <direction>Input</direction>
-                        <width>4</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
                 </ports>
                 <assignments>
                     <assignmentValueMap>
@@ -6921,7 +11655,7 @@
                         </entry>
                         <entry>
                             <key>embeddedsw.configuration.isMemoryDevice</key>
-                            <value>1</value>
+                            <value>0</value>
                         </entry>
                         <entry>
                             <key>embeddedsw.configuration.isNonVolatileStorage</key>
@@ -6945,7 +11679,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>131072</value>
+                            <value>128</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -6957,11 +11691,11 @@
                         </entry>
                         <entry>
                             <key>associatedClock</key>
-                            <value>clk1</value>
+                            <value>system</value>
                         </entry>
                         <entry>
                             <key>associatedReset</key>
-                            <value>reset1</value>
+                            <value>system_reset</value>
                         </entry>
                         <entry>
                             <key>bitsPerSymbol</key>
@@ -6988,7 +11722,7 @@
                         </entry>
                         <entry>
                             <key>explicitAddressSpan</key>
-                            <value>131072</value>
+                            <value>0</value>
                         </entry>
                         <entry>
                             <key>holdTime</key>
@@ -7008,7 +11742,7 @@
                         </entry>
                         <entry>
                             <key>isMemoryDevice</key>
-                            <value>true</value>
+                            <value>false</value>
                         </entry>
                         <entry>
                             <key>isNonVolatileStorage</key>
@@ -7101,49 +11835,261 @@
                     </parameterValueMap>
                 </parameters>
             </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>reset</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_reset_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
         </interfaces>
     </boundary>
     <originalModuleInfo>
-        <className>altera_avalon_onchip_memory2</className>
-        <version>18.0</version>
-        <displayName>On-Chip Memory (RAM or ROM) Intel FPGA IP</displayName>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
     </originalModuleInfo>
     <systemInfoParameterDescriptors>
         <descriptors>
             <descriptor>
-                <parameterDefaultValue></parameterDefaultValue>
-                <parameterName>autoInitializationFileName</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>UNIQUE_ID</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>NONE</parameterDefaultValue>
-                <parameterName>deviceFamily</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>DEVICE_FAMILY</systemInfotype>
-            </descriptor>
-            <descriptor>
-                <parameterDefaultValue>NONE</parameterDefaultValue>
-                <parameterName>deviceFeatures</parameterName>
-                <parameterType>java.lang.String</parameterType>
-                <systemInfotype>DEVICE_FEATURES</systemInfotype>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
             </descriptor>
         </descriptors>
     </systemInfoParameterDescriptors>
     <systemInfos>
         <connPtSystemInfos>
             <entry>
-                <key>s1</key>
+                <key>mem</key>
                 <value>
-                    <connectionPointName>s1</connectionPointName>
+                    <connectionPointName>mem</connectionPointName>
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x20000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>17</value>
+                            <value>7</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -7153,139 +12099,579 @@
                     <consumedSystemInfos/>
                 </value>
             </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>5</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>5</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>128</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_onchip_memory2_0</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_pio_system_info</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetFixedName>
-            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetFixedName>
-            <fileSetKind>SIM_VERILOG</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_onchip_memory2_0</fileSetFixedName>
-            <fileSetKind>SIM_VHDL</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-    </fileSets>
-</generationInfoDefinition>]]></parameter>
-  <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip</parameter>
-  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
-    <assignmentValueMap>
-        <entry>
-            <key>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.CONTENTS_INFO</key>
-            <value>""</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.DUAL_PORT</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</key>
-            <value>AUTO</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.INIT_CONTENTS_FILE</key>
-            <value>onchip_memory2_0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.INIT_MEM_CONTENT</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.INSTANCE_ID</key>
-            <value>NONE</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.RAM_BLOCK_TYPE</key>
-            <value>AUTO</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.READ_DURING_WRITE_MODE</key>
-            <value>DONT_CARE</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.SINGLE_CLOCK_OP</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.SIZE_MULTIPLE</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.SIZE_VALUE</key>
-            <value>131072</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.WRITABLE</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</key>
-            <value>SIM_DIR</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.memoryInfo.GENERATE_DAT_SYM</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.memoryInfo.GENERATE_HEX</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.memoryInfo.HAS_BYTE_LANE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.memoryInfo.HEX_INSTALL_DIR</key>
-            <value>QPF_DIR</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</key>
-            <value>32</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.memoryInfo.MEM_INIT_FILENAME</key>
-            <value>onchip_memory2_0</value>
-        </entry>
-        <entry>
-            <key>postgeneration.simulation.init_file.param_name</key>
-            <value>INIT_FILE</value>
-        </entry>
-        <entry>
-            <key>postgeneration.simulation.init_file.type</key>
-            <value>MEM_INIT</value>
-        </entry>
-    </assignmentValueMap>
+            <fileSetName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetFixedName>
+            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetFixedName>
+            <fileSetKind>SIM_VERILOG</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+        <fileSet>
+            <fileSetName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetFixedName>
+            <fileSetKind>SIM_VHDL</fileSetKind>
+            <fileSetFiles/>
+        </fileSet>
+    </fileSets>
+</generationInfoDefinition>]]></parameter>
+  <parameter name="hlsFile" value="" />
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip</parameter>
+  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+    <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="pio_pps"
+   name="pio_wdi"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -7293,17 +12679,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>clk</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -7312,25 +12698,26 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
+                <name>external_connection</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
+                        <name>out_port</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -7357,28 +12744,58 @@
                 </parameters>
             </interface>
             <interface>
-                <name>mem</name>
+                <name>reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>reset_n</name>
+                        <role>reset_n</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>clk</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>s1</name>
                 <type>avalon</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>avs_mem_address</name>
+                        <name>address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>avs_mem_write</name>
-                        <role>write</role>
+                        <name>write_n</name>
+                        <role>write_n</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>avs_mem_writedata</name>
+                        <name>writedata</name>
                         <role>writedata</role>
                         <direction>Input</direction>
                         <width>32</width>
@@ -7386,15 +12803,15 @@
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                     <port>
-                        <name>avs_mem_read</name>
-                        <role>read</role>
+                        <name>chipselect</name>
+                        <role>chipselect</role>
                         <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                     <port>
-                        <name>avs_mem_readdata</name>
+                        <name>readdata</name>
                         <role>readdata</role>
                         <direction>Output</direction>
                         <width>32</width>
@@ -7426,7 +12843,7 @@
                     <parameterValueMap>
                         <entry>
                             <key>addressAlignment</key>
-                            <value>DYNAMIC</value>
+                            <value>NATIVE</value>
                         </entry>
                         <entry>
                             <key>addressGroup</key>
@@ -7434,7 +12851,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>4</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -7446,11 +12863,11 @@
                         </entry>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
+                            <value>clk</value>
                         </entry>
                         <entry>
                             <key>associatedReset</key>
-                            <value>system_reset</value>
+                            <value>reset</value>
                         </entry>
                         <entry>
                             <key>bitsPerSymbol</key>
@@ -7537,15 +12954,15 @@
                         </entry>
                         <entry>
                             <key>readLatency</key>
-                            <value>1</value>
+                            <value>0</value>
                         </entry>
                         <entry>
                             <key>readWaitStates</key>
-                            <value>0</value>
+                            <value>1</value>
                         </entry>
                         <entry>
                             <key>readWaitTime</key>
-                            <value>0</value>
+                            <value>1</value>
                         </entry>
                         <entry>
                             <key>registerIncomingSignals</key>
@@ -7589,244 +13006,148 @@
                         </entry>
                     </parameterValueMap>
                 </parameters>
-            </interface>
-            <interface>
-                <name>read</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_read_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>reset</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_reset_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>system</name>
-                <type>clock</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>system_reset</name>
-                <type>reset</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                            <value>system</value>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>write</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>writedata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_writedata_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
+                <cmsisInfo>
+                    <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;    
+&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
+  &lt;peripherals&gt;
+   &lt;peripheral&gt;
+      &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; 
+      &lt;addressBlock&gt;
+        &lt;offset&gt;0x0&lt;/offset&gt;
+        &lt;size&gt;32&lt;/size&gt;
+        &lt;usage&gt;registers&lt;/usage&gt;
+      &lt;/addressBlock&gt;
+      &lt;registers&gt;
+        &lt;register&gt;     
+         &lt;name&gt;DATA&lt;/name&gt;  
+         &lt;displayName&gt;Data&lt;/displayName&gt;
+         &lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt;
+         &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;data&lt;/name&gt;
+           &lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;DIRECTION&lt;/name&gt;  
+         &lt;displayName&gt;Direction&lt;/displayName&gt;
+         &lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt;
+         &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;direction&lt;/name&gt;
+            &lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;IRQ_MASK&lt;/name&gt;  
+         &lt;displayName&gt;Interrupt mask&lt;/displayName&gt;
+         &lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt;
+         &lt;addressOffset&gt;0x8&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt;
+            &lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;EDGE_CAP&lt;/name&gt;  
+         &lt;displayName&gt;Edge capture&lt;/displayName&gt;
+         &lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt;
+         &lt;addressOffset&gt;0xc&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt;
+            &lt;description&gt;Edge detection for each input port.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;
+         &lt;name&gt;SET_BIT&lt;/name&gt;  
+         &lt;displayName&gt;Outset&lt;/displayName&gt;
+         &lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
+         &lt;addressOffset&gt;0x10&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;write-only&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;outset&lt;/name&gt;
+            &lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;write-only&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;CLEAR_BITS&lt;/name&gt;  
+         &lt;displayName&gt;Outclear&lt;/displayName&gt;
+         &lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
+         &lt;addressOffset&gt;0x14&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;write-only&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;outclear&lt;/name&gt;
+            &lt;description&gt;Specifies which output bit to clear.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;write-only&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt;            
+    &lt;/registers&gt;
+   &lt;/peripheral&gt;
+  &lt;/peripherals&gt;
+&lt;/device&gt; </cmsisSrcFileContents>
+                    <addressGroup></addressGroup>
+                    <cmsisVars/>
+                </cmsisInfo>
             </interface>
         </interfaces>
     </boundary>
     <originalModuleInfo>
-        <className>avs_common_mm</className>
-        <version>1.0</version>
-        <displayName>avs_common_mm</displayName>
+        <className>altera_avalon_pio</className>
+        <version>19.1.0</version>
+        <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
     </originalModuleInfo>
     <systemInfoParameterDescriptors>
         <descriptors>
             <descriptor>
-                <parameterDefaultValue>-1</parameterDefaultValue>
-                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+                <parameterDefaultValue>0</parameterDefaultValue>
+                <parameterName>clockRate</parameterName>
                 <parameterType>java.lang.Long</parameterType>
-                <systemInfoArgs>system</systemInfoArgs>
+                <systemInfoArgs>clk</systemInfoArgs>
                 <systemInfotype>CLOCK_RATE</systemInfotype>
             </descriptor>
         </descriptors>
@@ -7834,17 +13155,30 @@
     <systemInfos>
         <connPtSystemInfos>
             <entry>
-                <key>mem</key>
+                <key>clk</key>
                 <value>
-                    <connectionPointName>mem</connectionPointName>
+                    <connectionPointName>clk</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+            <entry>
+                <key>s1</key>
+                <value>
+                    <connectionPointName>s1</connectionPointName>
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>4</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -7854,55 +13188,578 @@
                     <consumedSystemInfos/>
                 </value>
             </entry>
-            <entry>
-                <key>system</key>
-                <value>
-                    <connectionPointName>system</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>100000000</value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>clk</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>external_connection</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>out_port</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>reset_n</name>
+                    <role>reset_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>s1</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>2</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>write_n</name>
+                    <role>write_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>chipselect</name>
+                    <role>chipselect</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>NATIVE</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>4</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+            <cmsisInfo>
+                <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;    
+&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
+  &lt;peripherals&gt;
+   &lt;peripheral&gt;
+      &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; 
+      &lt;addressBlock&gt;
+        &lt;offset&gt;0x0&lt;/offset&gt;
+        &lt;size&gt;32&lt;/size&gt;
+        &lt;usage&gt;registers&lt;/usage&gt;
+      &lt;/addressBlock&gt;
+      &lt;registers&gt;
+        &lt;register&gt;     
+         &lt;name&gt;DATA&lt;/name&gt;  
+         &lt;displayName&gt;Data&lt;/displayName&gt;
+         &lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt;
+         &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;data&lt;/name&gt;
+           &lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;DIRECTION&lt;/name&gt;  
+         &lt;displayName&gt;Direction&lt;/displayName&gt;
+         &lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt;
+         &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;direction&lt;/name&gt;
+            &lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;IRQ_MASK&lt;/name&gt;  
+         &lt;displayName&gt;Interrupt mask&lt;/displayName&gt;
+         &lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt;
+         &lt;addressOffset&gt;0x8&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt;
+            &lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;EDGE_CAP&lt;/name&gt;  
+         &lt;displayName&gt;Edge capture&lt;/displayName&gt;
+         &lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt;
+         &lt;addressOffset&gt;0xc&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;read-write&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt;
+            &lt;description&gt;Edge detection for each input port.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;
+         &lt;name&gt;SET_BIT&lt;/name&gt;  
+         &lt;displayName&gt;Outset&lt;/displayName&gt;
+         &lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
+         &lt;addressOffset&gt;0x10&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;write-only&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;outset&lt;/name&gt;
+            &lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;write-only&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt; 
+        &lt;register&gt;     
+         &lt;name&gt;CLEAR_BITS&lt;/name&gt;  
+         &lt;displayName&gt;Outclear&lt;/displayName&gt;
+         &lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
+         &lt;addressOffset&gt;0x14&lt;/addressOffset&gt;
+         &lt;size&gt;32&lt;/size&gt;
+         &lt;access&gt;write-only&lt;/access&gt;
+         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
+         &lt;fields&gt;
+           &lt;field&gt;&lt;name&gt;outclear&lt;/name&gt;
+            &lt;description&gt;Specifies which output bit to clear.&lt;/description&gt;
+            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
+            &lt;access&gt;write-only&lt;/access&gt;
+        &lt;/field&gt;
+       &lt;/fields&gt;
+     &lt;/register&gt;            
+    &lt;/registers&gt;
+   &lt;/peripheral&gt;
+  &lt;/peripherals&gt;
+&lt;/device&gt; </cmsisSrcFileContents>
+                <addressGroup></addressGroup>
+                <cmsisVars/>
+            </cmsisInfo>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_pio_pps</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_pio_wdi</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_pio_pps</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_pps</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_pio_pps</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_pps</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_pio_pps</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_pps</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
-    <assignmentValueMap/>
+    <assignmentValueMap>
+        <entry>
+            <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.CAPTURE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.DATA_WIDTH</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.EDGE_TYPE</key>
+            <value>NONE</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.FREQ</key>
+            <value>100000000</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HAS_IN</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HAS_OUT</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.HAS_TRI</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.IRQ_TYPE</key>
+            <value>NONE</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.CMacro.RESET_VALUE</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.compatible</key>
+            <value>altr,pio-1.0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.group</key>
+            <value>gpio</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.name</key>
+            <value>pio</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.altr,gpio-bank-width</key>
+            <value>1</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.params.resetvalue</key>
+            <value>0</value>
+        </entry>
+        <entry>
+            <key>embeddedsw.dts.vendor</key>
+            <value>altr</value>
+        </entry>
+    </assignmentValueMap>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="pio_system_info"
+   name="ram_aduh_monitor"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -7918,7 +13775,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>5</width>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -7982,7 +13839,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>5</width>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -8051,7 +13908,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>128</value>
+                            <value>16384</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -8333,669 +14190,117 @@
                         <entry>
                             <key>ptfSchematicName</key>
                         </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>system_reset</name>
-                <type>reset</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                            <value>system</value>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>write</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>writedata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_writedata_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-        </interfaces>
-    </boundary>
-    <originalModuleInfo>
-        <className>avs_common_mm</className>
-        <version>1.0</version>
-        <displayName>avs_common_mm</displayName>
-    </originalModuleInfo>
-    <systemInfoParameterDescriptors>
-        <descriptors>
-            <descriptor>
-                <parameterDefaultValue>-1</parameterDefaultValue>
-                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
-                <parameterType>java.lang.Long</parameterType>
-                <systemInfoArgs>system</systemInfoArgs>
-                <systemInfotype>CLOCK_RATE</systemInfotype>
-            </descriptor>
-        </descriptors>
-    </systemInfoParameterDescriptors>
-    <systemInfos>
-        <connPtSystemInfos>
-            <entry>
-                <key>mem</key>
-                <value>
-                    <connectionPointName>mem</connectionPointName>
-                    <suppliedSystemInfos>
-                        <entry>
-                            <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;/address-map&gt;</value>
-                        </entry>
-                        <entry>
-                            <key>ADDRESS_WIDTH</key>
-                            <value>7</value>
-                        </entry>
-                        <entry>
-                            <key>MAX_SLAVE_DATA_WIDTH</key>
-                            <value>32</value>
-                        </entry>
-                    </suppliedSystemInfos>
-                    <consumedSystemInfos/>
-                </value>
-            </entry>
-            <entry>
-                <key>system</key>
-                <value>
-                    <connectionPointName>system</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>100000000</value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
-        </connPtSystemInfos>
-    </systemInfos>
-</componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
-  <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_pio_system_info</hdlLibraryName>
-    <fileSets>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetFixedName>
-            <fileSetKind>QUARTUS_SYNTH</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetFixedName>
-            <fileSetKind>SIM_VERILOG</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-        <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_system_info</fileSetFixedName>
-            <fileSetKind>SIM_VHDL</fileSetKind>
-            <fileSetFiles/>
-        </fileSet>
-    </fileSets>
-</generationInfoDefinition>]]></parameter>
-  <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip</parameter>
-  <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
-    <assignmentValueMap/>
-</assignmentDefinition>]]></parameter>
-  <parameter name="svInterfaceDefinition" value="" />
- </module>
- <module
-   name="pio_wdi"
-   kind="altera_generic_component"
-   version="1.0"
-   enabled="1">
-  <parameter name="componentDefinition"><![CDATA[<componentDefinition>
-    <boundary>
-        <interfaces>
-            <interface>
-                <name>clk</name>
-                <type>clock</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>ptfSchematicName</key>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>external_connection</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>out_port</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>reset</name>
-                <type>reset</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>reset_n</name>
-                        <role>reset_n</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                            <value>clk</value>
-                        </entry>
-                        <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>s1</name>
-                <type>avalon</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>address</name>
-                        <role>address</role>
-                        <direction>Input</direction>
-                        <width>2</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                    <port>
-                        <name>write_n</name>
-                        <role>write_n</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                    <port>
-                        <name>writedata</name>
-                        <role>writedata</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                    <port>
-                        <name>chipselect</name>
-                        <role>chipselect</role>
-                        <direction>Input</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                    <port>
-                        <name>readdata</name>
-                        <role>readdata</role>
-                        <direction>Output</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap>
-                        <entry>
-                            <key>embeddedsw.configuration.isFlash</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>embeddedsw.configuration.isMemoryDevice</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>embeddedsw.configuration.isPrintableDevice</key>
-                            <value>0</value>
-                        </entry>
-                    </assignmentValueMap>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>addressAlignment</key>
-                            <value>NATIVE</value>
-                        </entry>
-                        <entry>
-                            <key>addressGroup</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>addressSpan</key>
-                            <value>4</value>
-                        </entry>
-                        <entry>
-                            <key>addressUnits</key>
-                            <value>WORDS</value>
-                        </entry>
-                        <entry>
-                            <key>alwaysBurstMaxBurst</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>associatedClock</key>
-                            <value>clk</value>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                            <value>reset</value>
-                        </entry>
-                        <entry>
-                            <key>bitsPerSymbol</key>
-                            <value>8</value>
-                        </entry>
-                        <entry>
-                            <key>bridgedAddressOffset</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>bridgesToMaster</key>
-                        </entry>
-                        <entry>
-                            <key>burstOnBurstBoundariesOnly</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>burstcountUnits</key>
-                            <value>WORDS</value>
-                        </entry>
-                        <entry>
-                            <key>constantBurstBehavior</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>explicitAddressSpan</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>holdTime</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>interleaveBursts</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>isBigEndian</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>isFlash</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>isMemoryDevice</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>isNonVolatileStorage</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>linewrapBursts</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>maximumPendingReadTransactions</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>maximumPendingWriteTransactions</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>minimumReadLatency</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>minimumResponseLatency</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>minimumUninterruptedRunLength</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>printableDevice</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>readLatency</key>
-                            <value>0</value>
-                        </entry>
-                        <entry>
-                            <key>readWaitStates</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>readWaitTime</key>
-                            <value>1</value>
-                        </entry>
-                        <entry>
-                            <key>registerIncomingSignals</key>
-                            <value>false</value>
-                        </entry>
-                        <entry>
-                            <key>registerOutgoingSignals</key>
-                            <value>false</value>
-                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
                         <entry>
-                            <key>setupTime</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>timingUnits</key>
-                            <value>Cycles</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
                         <entry>
-                            <key>transparentBridge</key>
-                            <value>false</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>waitrequestAllowance</key>
-                            <value>0</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>wellBehavedWaitrequest</key>
+                            <key>prSafe</key>
                             <value>false</value>
                         </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
                         <entry>
-                            <key>writeLatency</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>writeWaitStates</key>
-                            <value>0</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>writeWaitTime</key>
-                            <value>0</value>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
-                <cmsisInfo>
-                    <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;    
-&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
-  &lt;peripherals&gt;
-   &lt;peripheral&gt;
-      &lt;name&gt;altera_avalon_pio&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; 
-      &lt;addressBlock&gt;
-        &lt;offset&gt;0x0&lt;/offset&gt;
-        &lt;size&gt;32&lt;/size&gt;
-        &lt;usage&gt;registers&lt;/usage&gt;
-      &lt;/addressBlock&gt;
-      &lt;registers&gt;
-        &lt;register&gt;     
-         &lt;name&gt;DATA&lt;/name&gt;  
-         &lt;displayName&gt;Data&lt;/displayName&gt;
-         &lt;description&gt;Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).&lt;/description&gt;
-         &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
-         &lt;size&gt;32&lt;/size&gt;
-         &lt;access&gt;read-write&lt;/access&gt;
-         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
-         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
-         &lt;fields&gt;
-           &lt;field&gt;&lt;name&gt;data&lt;/name&gt;
-           &lt;description&gt;Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.&lt;/description&gt;
-            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
-            &lt;access&gt;read-write&lt;/access&gt;
-        &lt;/field&gt;
-       &lt;/fields&gt;
-     &lt;/register&gt; 
-        &lt;register&gt;     
-         &lt;name&gt;DIRECTION&lt;/name&gt;  
-         &lt;displayName&gt;Direction&lt;/displayName&gt;
-         &lt;description&gt;The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.&lt;/description&gt;
-         &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
-         &lt;size&gt;32&lt;/size&gt;
-         &lt;access&gt;read-write&lt;/access&gt;
-         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
-         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
-         &lt;fields&gt;
-           &lt;field&gt;&lt;name&gt;direction&lt;/name&gt;
-            &lt;description&gt;Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.&lt;/description&gt;
-            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
-            &lt;access&gt;read-write&lt;/access&gt;
-        &lt;/field&gt;
-       &lt;/fields&gt;
-     &lt;/register&gt; 
-        &lt;register&gt;     
-         &lt;name&gt;IRQ_MASK&lt;/name&gt;  
-         &lt;displayName&gt;Interrupt mask&lt;/displayName&gt;
-         &lt;description&gt;Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.&lt;/description&gt;
-         &lt;addressOffset&gt;0x8&lt;/addressOffset&gt;
-         &lt;size&gt;32&lt;/size&gt;
-         &lt;access&gt;read-write&lt;/access&gt;
-         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
-         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
-         &lt;fields&gt;
-           &lt;field&gt;&lt;name&gt;interruptmask&lt;/name&gt;
-            &lt;description&gt;IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.&lt;/description&gt;
-            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
-            &lt;access&gt;read-write&lt;/access&gt;
-        &lt;/field&gt;
-       &lt;/fields&gt;
-     &lt;/register&gt; 
-        &lt;register&gt;     
-         &lt;name&gt;EDGE_CAP&lt;/name&gt;  
-         &lt;displayName&gt;Edge capture&lt;/displayName&gt;
-         &lt;description&gt;Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.&lt;/description&gt;
-         &lt;addressOffset&gt;0xc&lt;/addressOffset&gt;
-         &lt;size&gt;32&lt;/size&gt;
-         &lt;access&gt;read-write&lt;/access&gt;
-         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
-         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
-         &lt;fields&gt;
-           &lt;field&gt;&lt;name&gt;edgecapture&lt;/name&gt;
-            &lt;description&gt;Edge detection for each input port.&lt;/description&gt;
-            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
-            &lt;access&gt;read-write&lt;/access&gt;
-        &lt;/field&gt;
-       &lt;/fields&gt;
-     &lt;/register&gt; 
-        &lt;register&gt;
-         &lt;name&gt;SET_BIT&lt;/name&gt;  
-         &lt;displayName&gt;Outset&lt;/displayName&gt;
-         &lt;description&gt;You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
-         &lt;addressOffset&gt;0x10&lt;/addressOffset&gt;
-         &lt;size&gt;32&lt;/size&gt;
-         &lt;access&gt;write-only&lt;/access&gt;
-         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
-         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
-         &lt;fields&gt;
-           &lt;field&gt;&lt;name&gt;outset&lt;/name&gt;
-            &lt;description&gt;Specifies which bit of the output port to set.&lt;/description&gt;
-            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
-            &lt;access&gt;write-only&lt;/access&gt;
-        &lt;/field&gt;
-       &lt;/fields&gt;
-     &lt;/register&gt; 
-        &lt;register&gt;     
-         &lt;name&gt;CLEAR_BITS&lt;/name&gt;  
-         &lt;displayName&gt;Outclear&lt;/displayName&gt;
-         &lt;description&gt;You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.&lt;/description&gt;
-         &lt;addressOffset&gt;0x14&lt;/addressOffset&gt;
-         &lt;size&gt;32&lt;/size&gt;
-         &lt;access&gt;write-only&lt;/access&gt;
-         &lt;resetValue&gt;0x0&lt;/resetValue&gt;
-         &lt;resetMask&gt;0xffffffff&lt;/resetMask&gt; 
-         &lt;fields&gt;
-           &lt;field&gt;&lt;name&gt;outclear&lt;/name&gt;
-            &lt;description&gt;Specifies which output bit to clear.&lt;/description&gt;
-            &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
-            &lt;bitWidth&gt;32&lt;/bitWidth&gt;
-            &lt;access&gt;write-only&lt;/access&gt;
-        &lt;/field&gt;
-       &lt;/fields&gt;
-     &lt;/register&gt;            
-    &lt;/registers&gt;
-   &lt;/peripheral&gt;
-  &lt;/peripherals&gt;
-&lt;/device&gt; </cmsisSrcFileContents>
-                    <addressGroup></addressGroup>
-                    <cmsisVars/>
-                </cmsisInfo>
             </interface>
         </interfaces>
     </boundary>
     <originalModuleInfo>
-        <className>altera_avalon_pio</className>
-        <version>18.0</version>
-        <displayName>PIO (Parallel I/O) Intel FPGA IP</displayName>
+        <className>avs_common_mm</className>
+        <version>1.0</version>
+        <displayName>avs_common_mm</displayName>
     </originalModuleInfo>
     <systemInfoParameterDescriptors>
         <descriptors>
             <descriptor>
-                <parameterDefaultValue>0</parameterDefaultValue>
-                <parameterName>clockRate</parameterName>
+                <parameterDefaultValue>-1</parameterDefaultValue>
+                <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
                 <parameterType>java.lang.Long</parameterType>
-                <systemInfoArgs>clk</systemInfoArgs>
+                <systemInfoArgs>system</systemInfoArgs>
                 <systemInfotype>CLOCK_RATE</systemInfotype>
             </descriptor>
         </descriptors>
@@ -9003,30 +14308,17 @@
     <systemInfos>
         <connPtSystemInfos>
             <entry>
-                <key>clk</key>
-                <value>
-                    <connectionPointName>clk</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>100000000</value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
-            <entry>
-                <key>s1</key>
+                <key>mem</key>
                 <value>
-                    <connectionPointName>s1</connectionPointName>
+                    <connectionPointName>mem</connectionPointName>
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>14</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -9036,119 +14328,579 @@
                     <consumedSystemInfos/>
                 </value>
             </entry>
+            <entry>
+                <key>system</key>
+                <value>
+                    <connectionPointName>system</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>12</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>12</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>16384</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_pio_wdi</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_ram_aduh_monitor</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_aduh_monitor</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_aduh_monitor</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_aduh_monitor</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_aduh_monitor</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_pio_wdi</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_aduh_monitor</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_aduh_monitor</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
-    <assignmentValueMap>
-        <entry>
-            <key>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.CAPTURE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.DATA_WIDTH</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.DRIVEN_SIM_VALUE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.EDGE_TYPE</key>
-            <value>NONE</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.FREQ</key>
-            <value>100000000</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HAS_IN</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HAS_OUT</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.HAS_TRI</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.IRQ_TYPE</key>
-            <value>NONE</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.CMacro.RESET_VALUE</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.compatible</key>
-            <value>altr,pio-1.0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.group</key>
-            <value>gpio</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.name</key>
-            <value>pio</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.altr,gpio-bank-width</key>
-            <value>1</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.params.resetvalue</key>
-            <value>0</value>
-        </entry>
-        <entry>
-            <key>embeddedsw.dts.vendor</key>
-            <value>altr</value>
-        </entry>
-    </assignmentValueMap>
+    <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_diag_data_buffer_jesd"
+   name="ram_diag_data_buffer_bsn"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -9164,7 +14916,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>17</width>
+                        <width>16</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -9228,7 +14980,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>17</width>
+                        <width>16</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -9297,7 +15049,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>524288</value>
+                            <value>262144</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -9703,11 +15455,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x80000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>19</value>
+                            <value>18</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -9807,7 +15559,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>17</width>
+                    <width>16</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -9872,7 +15624,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>524288</value>
+                        <value>262144</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -10100,7 +15852,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>17</width>
+                    <width>16</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -10254,37 +16006,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_avs_common_mm_1</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_1</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_wg_0"
+   name="ram_diag_data_buffer_jesd"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -10292,17 +16044,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>16</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -10311,28 +16063,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -10345,11 +16096,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -10363,7 +16116,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>10</width>
+                        <width>16</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -10432,7 +16185,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>4096</value>
+                            <value>262144</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -10589,108 +16342,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_reset_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>clk</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>address</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>10</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>write</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -10717,14 +16374,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -10749,12 +16406,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -10781,14 +16438,109 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>system</name>
+                <type>clock</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>clockRate</key>
+                            <value>0</value>
+                        </entry>
+                        <entry>
+                            <key>externallyDriven</key>
+                            <value>false</value>
+                        </entry>
+                        <entry>
+                            <key>ptfSchematicName</key>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_write_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>writedata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -10839,11 +16591,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>12</value>
+                            <value>18</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -10943,7 +16695,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>10</width>
+                    <width>16</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -11008,7 +16760,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>4096</value>
+                        <value>262144</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -11236,7 +16988,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>10</width>
+                    <width>16</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -11390,37 +17142,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_ram_wg_0</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_0.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_wg_1"
+   name="ram_wg"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -11499,7 +17251,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>10</width>
+                        <width>14</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -11568,7 +17320,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>4096</value>
+                            <value>65536</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -11797,7 +17549,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>10</width>
+                        <width>14</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -11975,11 +17727,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>12</value>
+                            <value>16</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12079,7 +17831,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>10</width>
+                    <width>14</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -12118,17 +17870,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -12144,7 +17900,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>4096</value>
+                        <value>65536</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -12168,6 +17924,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -12372,7 +18129,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>10</width>
+                    <width>14</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -12526,37 +18283,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_ram_wg_1</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_ram_wg</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_1</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_1</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_1</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_1</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_1</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_1</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_1.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_wg_2"
+   name="reg_aduh_monitor"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -12564,17 +18321,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -12583,28 +18340,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -12617,11 +18373,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -12635,7 +18393,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>10</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -12704,7 +18462,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>4096</value>
+                            <value>256</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -12861,12 +18619,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -12893,17 +18651,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
+                        <direction>Input</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -12925,17 +18683,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>10</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -12957,14 +18715,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -12976,30 +18734,31 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>32</width>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -13009,24 +18768,22 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>write</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_write_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -13053,14 +18810,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_writedata_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
+                        <direction>Output</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -13111,11 +18868,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>12</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -13144,17 +18901,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -13163,28 +18920,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -13197,11 +18953,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -13215,7 +18973,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>10</width>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -13254,17 +19012,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -13280,7 +19042,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>4096</value>
+                        <value>256</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -13304,6 +19066,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -13436,12 +19199,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -13468,17 +19231,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
+                    <direction>Input</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -13500,17 +19263,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>address</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>10</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -13532,14 +19295,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -13551,30 +19314,31 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -13584,24 +19348,22 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -13628,14 +19390,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>writedata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_writedata_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -13662,37 +19424,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_ram_wg_2</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_aduh_monitor</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_aduh_monitor</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_aduh_monitor</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_aduh_monitor</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_aduh_monitor</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_aduh_monitor</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_aduh_monitor</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_2.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="ram_wg_3"
+   name="reg_bsn_monitor_input"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -13771,7 +19533,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>10</width>
+                        <width>8</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -13840,7 +19602,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>4096</value>
+                            <value>1024</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -14069,7 +19831,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>10</width>
+                        <width>8</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -14247,11 +20009,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x1000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>12</value>
+                            <value>10</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -14351,7 +20113,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>10</width>
+                    <width>8</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -14390,17 +20152,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -14416,7 +20182,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>4096</value>
+                        <value>1024</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -14440,6 +20206,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -14644,7 +20411,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>10</width>
+                    <width>8</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -14798,37 +20565,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_ram_wg_3</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_3</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_3</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_3</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_3</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_ram_wg_3</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_ram_wg_3</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_3.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_bsn_monitor_input"
+   name="reg_bsn_scheduler"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -14907,7 +20674,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>8</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -14976,7 +20743,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>1024</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -15205,7 +20972,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>8</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -15383,11 +21150,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x400' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>10</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -15487,7 +21254,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>8</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -15526,17 +21293,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -15552,7 +21323,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>1024</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -15576,6 +21347,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -15780,7 +21552,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>8</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -15934,37 +21706,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_monitor_input</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_scheduler</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_diag_data_buffer_jesd"
+   name="reg_bsn_source"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -15972,17 +21744,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>12</width>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -15991,27 +21763,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -16024,13 +21797,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -16044,7 +21815,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>12</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -16113,7 +21884,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16384</value>
+                            <value>16</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -16270,12 +22041,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -16302,17 +22073,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -16334,17 +22105,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>address</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>2</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -16366,14 +22137,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>write</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -16385,31 +22156,30 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>writedata</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -16419,22 +22189,24 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -16461,14 +22233,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -16519,11 +22291,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>14</value>
+                            <value>4</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -16623,7 +22395,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>12</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -16662,17 +22434,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -16688,7 +22464,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16384</value>
+                        <value>16</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -16712,6 +22488,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -16916,7 +22693,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>12</width>
+                    <width>2</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -17070,37 +22847,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_avs_common_mm_0</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_bsn_source</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_source</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_source</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_source</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_source</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_avs_common_mm_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_bsn_source</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_bsn_source</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dpmm_ctrl"
+   name="reg_diag_data_buffer_bsn"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -17116,7 +22893,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -17180,7 +22957,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -17249,7 +23026,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>16384</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -17655,11 +23432,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>14</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -17685,39 +23462,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>12</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>12</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>16384</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_dpmm_data"
+   name="reg_diag_data_buffer_jesd"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -17733,7 +24034,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -17797,7 +24098,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>12</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -17866,7 +24167,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>16384</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -18272,11 +24573,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x4000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>14</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -18302,39 +24603,558 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>12</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>false</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>16384</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>12</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_dpmm_data</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_epcs"
+   name="reg_dp_shiftram"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -18342,17 +25162,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>3</width>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -18361,27 +25181,28 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -18394,13 +25215,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -18640,12 +25459,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -18672,17 +25491,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>clk</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_clk_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
+                        <direction>Output</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -18704,17 +25523,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>address</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -18736,14 +25555,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>write</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_write_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -18755,31 +25574,30 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>writedata</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_writedata_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -18789,22 +25607,24 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -18831,14 +25651,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
+                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -18919,39 +25739,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>32</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_epcs</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_dp_shiftram</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_dp_shiftram</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dp_shiftram</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_dp_shiftram</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dp_shiftram</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_dp_shiftram</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dp_shiftram</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_fpga_temp_sens"
+   name="reg_dpmm_ctrl"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -18967,7 +26311,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -19031,7 +26375,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -19100,7 +26444,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -19506,11 +26850,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -19536,39 +26880,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_fpga_voltage_sens"
+   name="reg_dpmm_data"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -19584,7 +27452,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>4</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -19648,7 +27516,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>4</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -19717,7 +27585,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>64</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -20123,11 +27991,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>6</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -20156,17 +28024,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -20175,28 +28043,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -20209,11 +28076,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -20227,7 +28096,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>4</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -20266,17 +28135,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -20292,7 +28165,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>64</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -20316,6 +28189,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -20448,12 +28322,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -20480,17 +28354,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
+                    <direction>Input</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -20512,17 +28386,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>address</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>4</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -20544,14 +28418,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -20563,30 +28437,31 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -20596,24 +28471,22 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -20640,14 +28513,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>writedata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_writedata_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -20674,37 +28547,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_dpmm_data</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_dpmm_data</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_mmdp_ctrl"
+   name="reg_epcs"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -20720,7 +28593,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -20784,7 +28657,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -20853,7 +28726,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -21259,11 +29132,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21289,39 +29162,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>32</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_epcs</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_epcs</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_mmdp_data"
+   name="reg_fpga_temp_sens"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -21337,7 +29734,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -21401,7 +29798,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -21470,7 +29867,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -21876,11 +30273,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -21906,39 +30303,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>32</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_mmdp_data</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_temp_sens</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_remu"
+   name="reg_fpga_voltage_sens"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -21954,7 +30875,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>3</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -22018,7 +30939,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>3</width>
+                        <width>4</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -22087,7 +31008,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>32</value>
+                            <value>64</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -22493,11 +31414,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
+                            <value>6</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -22523,39 +31444,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>4</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>64</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_remu</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_remu</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_remu</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_remu</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_remu</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_remu</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_remu</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_unb_pmbus"
+   name="reg_mmdp_ctrl"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -22571,7 +32016,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>6</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -22635,7 +32080,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>6</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -22704,7 +32149,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>256</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -23110,11 +32555,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>8</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23140,39 +32585,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_ctrl</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_unb_sens"
+   name="reg_mmdp_data"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -23188,7 +33157,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>6</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -23252,7 +33221,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>6</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -23321,7 +33290,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>256</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -23727,11 +33696,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>8</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -23757,39 +33726,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_unb_sens</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_mmdp_data</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_mmdp_data</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_wdi"
+   name="reg_remu"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -23805,7 +34298,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -23869,7 +34362,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>1</width>
+                        <width>3</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -23938,7 +34431,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>8</value>
+                            <value>32</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -24344,11 +34837,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x20' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>3</value>
+                            <value>5</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24374,39 +34867,563 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>32</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_wdi</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_remu</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_remu</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_remu</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_remu</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_remu</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_remu</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_remu</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_wg_0"
+   name="reg_unb_pmbus"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -24414,17 +35431,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -24433,28 +35450,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -24467,11 +35483,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -24485,7 +35503,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -24554,7 +35572,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>256</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -24711,12 +35729,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -24743,17 +35761,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
+                        <direction>Input</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -24775,17 +35793,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -24807,14 +35825,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -24826,30 +35844,31 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>32</width>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -24859,24 +35878,22 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>write</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_write_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -24903,14 +35920,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>readdata</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_readdata_export</name>
+                        <name>coe_writedata_export</name>
                         <role>export</role>
-                        <direction>Input</direction>
+                        <direction>Output</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -24961,11 +35978,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -24994,17 +36011,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -25013,28 +36030,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -25047,11 +36063,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -25065,7 +36083,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>2</width>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -25104,17 +36122,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -25130,7 +36152,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16</value>
+                        <value>256</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -25154,6 +36176,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -25286,12 +36309,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -25318,17 +36341,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
+                    <direction>Input</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -25350,17 +36373,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>address</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>2</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -25382,14 +36405,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -25401,30 +36424,31 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -25434,24 +36458,22 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -25478,14 +36500,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>writedata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_writedata_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -25512,37 +36534,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_wg_0</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_0</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_0</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_pmbus</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_0.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_wg_1"
+   name="reg_unb_sens"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -25550,17 +36572,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
-                        <width>1</width>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -25569,28 +36591,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -25603,11 +36624,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -25621,7 +36644,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -25690,7 +36713,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>256</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -25847,12 +36870,12 @@
                 </parameters>
             </interface>
             <interface>
-                <name>reset</name>
+                <name>read</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_reset_export</name>
+                        <name>coe_read_export</name>
                         <role>export</role>
                         <direction>Output</direction>
                         <width>1</width>
@@ -25879,17 +36902,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
+                <name>readdata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
+                        <name>coe_readdata_export</name>
                         <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
+                        <direction>Input</direction>
+                        <width>32</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -25911,17 +36934,17 @@
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
+                <name>reset</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
+                        <name>coe_reset_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -25943,14 +36966,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>write</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_write_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -25962,30 +36985,61 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>writedata</name>
+                <name>system_reset</name>
+                <type>reset</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                            <value>system</value>
+                        </entry>
+                        <entry>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>write</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_writedata_export</name>
+                        <name>coe_write_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>32</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -26007,46 +37061,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>read</name>
+                <name>writedata</name>
                 <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_read_export</name>
+                        <name>coe_writedata_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
                         <width>32</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -26097,11 +37119,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -26130,17 +37152,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
-                    <width>1</width>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -26149,28 +37171,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -26183,11 +37204,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -26201,7 +37224,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>2</width>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -26240,17 +37263,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -26266,7 +37293,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16</value>
+                        <value>256</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -26290,6 +37317,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -26422,12 +37450,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -26454,17 +37482,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
+                    <direction>Input</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -26486,17 +37514,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>address</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>2</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -26518,14 +37546,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -26537,30 +37565,31 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -26570,24 +37599,22 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -26614,14 +37641,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>writedata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_writedata_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -26648,37 +37675,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_wg_1</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_unb_sens</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_1</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_1</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_1</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_1</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_1</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_1</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_unb_sens</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_1.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_wg_2"
+   name="reg_wdi"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -26686,17 +37713,17 @@
     <boundary>
         <interfaces>
             <interface>
-                <name>system</name>
-                <type>clock</type>
+                <name>address</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_clk</name>
-                        <role>clk</role>
-                        <direction>Input</direction>
+                        <name>coe_address_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -26705,28 +37732,27 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>clockRate</key>
-                            <value>0</value>
+                            <key>associatedClock</key>
                         </entry>
                         <entry>
-                            <key>externallyDriven</key>
-                            <value>false</value>
+                            <key>associatedReset</key>
                         </entry>
                         <entry>
-                            <key>ptfSchematicName</key>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>system_reset</name>
-                <type>reset</type>
+                <name>clk</name>
+                <type>conduit</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>csi_system_reset</name>
-                        <role>reset</role>
-                        <direction>Input</direction>
+                        <name>coe_clk_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -26739,11 +37765,13 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
-                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>synchronousEdges</key>
-                            <value>DEASSERT</value>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -26757,7 +37785,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -26826,7 +37854,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -26982,6 +38010,70 @@
                     </parameterValueMap>
                 </parameters>
             </interface>
+            <interface>
+                <name>read</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_read_export</name>
+                        <role>export</role>
+                        <direction>Output</direction>
+                        <width>1</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
+            <interface>
+                <name>readdata</name>
+                <type>conduit</type>
+                <isStart>false</isStart>
+                <ports>
+                    <port>
+                        <name>coe_readdata_export</name>
+                        <role>export</role>
+                        <direction>Input</direction>
+                        <width>32</width>
+                        <lowerBound>0</lowerBound>
+                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    </port>
+                </ports>
+                <assignments>
+                    <assignmentValueMap/>
+                </assignments>
+                <parameters>
+                    <parameterValueMap>
+                        <entry>
+                            <key>associatedClock</key>
+                        </entry>
+                        <entry>
+                            <key>associatedReset</key>
+                        </entry>
+                        <entry>
+                            <key>prSafe</key>
+                            <value>false</value>
+                        </entry>
+                    </parameterValueMap>
+                </parameters>
+            </interface>
             <interface>
                 <name>reset</name>
                 <type>conduit</type>
@@ -27015,14 +38107,14 @@
                 </parameters>
             </interface>
             <interface>
-                <name>clk</name>
-                <type>conduit</type>
+                <name>system</name>
+                <type>clock</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_clk_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
+                        <name>csi_system_clk</name>
+                        <role>clk</role>
+                        <direction>Input</direction>
                         <width>1</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC</vhdlType>
@@ -27034,30 +38126,31 @@
                 <parameters>
                     <parameterValueMap>
                         <entry>
-                            <key>associatedClock</key>
+                            <key>clockRate</key>
+                            <value>0</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
+                            <key>externallyDriven</key>
+                            <value>false</value>
                         </entry>
                         <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>ptfSchematicName</key>
                         </entry>
                     </parameterValueMap>
                 </parameters>
             </interface>
             <interface>
-                <name>address</name>
-                <type>conduit</type>
+                <name>system_reset</name>
+                <type>reset</type>
                 <isStart>false</isStart>
                 <ports>
                     <port>
-                        <name>coe_address_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>2</width>
+                        <name>csi_system_reset</name>
+                        <role>reset</role>
+                        <direction>Input</direction>
+                        <width>1</width>
                         <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                        <vhdlType>STD_LOGIC</vhdlType>
                     </port>
                 </ports>
                 <assignments>
@@ -27067,13 +38160,11 @@
                     <parameterValueMap>
                         <entry>
                             <key>associatedClock</key>
+                            <value>system</value>
                         </entry>
                         <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
+                            <key>synchronousEdges</key>
+                            <value>DEASSERT</value>
                         </entry>
                     </parameterValueMap>
                 </parameters>
@@ -27142,70 +38233,6 @@
                     </parameterValueMap>
                 </parameters>
             </interface>
-            <interface>
-                <name>read</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_read_export</name>
-                        <role>export</role>
-                        <direction>Output</direction>
-                        <width>1</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
-            <interface>
-                <name>readdata</name>
-                <type>conduit</type>
-                <isStart>false</isStart>
-                <ports>
-                    <port>
-                        <name>coe_readdata_export</name>
-                        <role>export</role>
-                        <direction>Input</direction>
-                        <width>32</width>
-                        <lowerBound>0</lowerBound>
-                        <vhdlType>STD_LOGIC_VECTOR</vhdlType>
-                    </port>
-                </ports>
-                <assignments>
-                    <assignmentValueMap/>
-                </assignments>
-                <parameters>
-                    <parameterValueMap>
-                        <entry>
-                            <key>associatedClock</key>
-                        </entry>
-                        <entry>
-                            <key>associatedReset</key>
-                        </entry>
-                        <entry>
-                            <key>prSafe</key>
-                            <value>false</value>
-                        </entry>
-                    </parameterValueMap>
-                </parameters>
-            </interface>
         </interfaces>
     </boundary>
     <originalModuleInfo>
@@ -27233,11 +38260,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>3</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -27266,17 +38293,17 @@
   <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
     <interfaces>
         <interface>
-            <name>system</name>
-            <type>clock</type>
+            <name>address</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_clk</name>
-                    <role>clk</role>
-                    <direction>Input</direction>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -27285,28 +38312,27 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>clockRate</key>
-                        <value>0</value>
+                        <key>associatedClock</key>
                     </entry>
                     <entry>
-                        <key>externallyDriven</key>
-                        <value>false</value>
+                        <key>associatedReset</key>
                     </entry>
                     <entry>
-                        <key>ptfSchematicName</key>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>system_reset</name>
-            <type>reset</type>
+            <name>clk</name>
+            <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>csi_system_reset</name>
-                    <role>reset</role>
-                    <direction>Input</direction>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -27319,11 +38345,13 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
-                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>synchronousEdges</key>
-                        <value>DEASSERT</value>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
@@ -27337,7 +38365,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>2</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -27376,17 +38404,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -27402,7 +38434,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16</value>
+                        <value>8</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -27426,6 +38458,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -27558,12 +38591,12 @@
             </parameters>
         </interface>
         <interface>
-            <name>reset</name>
+            <name>read</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_reset_export</name>
+                    <name>coe_read_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -27590,17 +38623,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>clk</name>
+            <name>readdata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_clk_export</name>
+                    <name>coe_readdata_export</name>
                     <role>export</role>
-                    <direction>Output</direction>
-                    <width>1</width>
+                    <direction>Input</direction>
+                    <width>32</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC</vhdlType>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -27622,17 +38655,17 @@
             </parameters>
         </interface>
         <interface>
-            <name>address</name>
+            <name>reset</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_address_export</name>
+                    <name>coe_reset_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>2</width>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -27654,14 +38687,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>write</name>
-            <type>conduit</type>
+            <name>system</name>
+            <type>clock</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_write_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
                     <width>1</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC</vhdlType>
@@ -27673,30 +38706,31 @@
             <parameters>
                 <parameterValueMap>
                     <entry>
-                        <key>associatedClock</key>
+                        <key>clockRate</key>
+                        <value>0</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
+                        <key>externallyDriven</key>
+                        <value>false</value>
                     </entry>
                     <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>ptfSchematicName</key>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>writedata</name>
-            <type>conduit</type>
+            <name>system_reset</name>
+            <type>reset</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_writedata_export</name>
-                    <role>export</role>
-                    <direction>Output</direction>
-                    <width>32</width>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
                     <lowerBound>0</lowerBound>
-                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                    <vhdlType>STD_LOGIC</vhdlType>
                 </port>
             </ports>
             <assignments>
@@ -27706,24 +38740,22 @@
                 <parameterValueMap>
                     <entry>
                         <key>associatedClock</key>
+                        <value>system</value>
                     </entry>
                     <entry>
-                        <key>associatedReset</key>
-                    </entry>
-                    <entry>
-                        <key>prSafe</key>
-                        <value>false</value>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
                     </entry>
                 </parameterValueMap>
             </parameters>
         </interface>
         <interface>
-            <name>read</name>
+            <name>write</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_read_export</name>
+                    <name>coe_write_export</name>
                     <role>export</role>
                     <direction>Output</direction>
                     <width>1</width>
@@ -27750,14 +38782,14 @@
             </parameters>
         </interface>
         <interface>
-            <name>readdata</name>
+            <name>writedata</name>
             <type>conduit</type>
             <isStart>false</isStart>
             <ports>
                 <port>
-                    <name>coe_readdata_export</name>
+                    <name>coe_writedata_export</name>
                     <role>export</role>
-                    <direction>Input</direction>
+                    <direction>Output</direction>
                     <width>32</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
@@ -27784,37 +38816,37 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_wg_2</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_wdi</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_2</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_2</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wdi</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_2.ip</parameter>
+  <parameter name="logicalView">../../../../../build/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
   <parameter name="svInterfaceDefinition" value="" />
  </module>
  <module
-   name="reg_wg_3"
+   name="reg_wg"
    kind="altera_generic_component"
    version="1.0"
    enabled="1">
@@ -27893,7 +38925,7 @@
                         <name>avs_mem_address</name>
                         <role>address</role>
                         <direction>Input</direction>
-                        <width>2</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -27962,7 +38994,7 @@
                         </entry>
                         <entry>
                             <key>addressSpan</key>
-                            <value>16</value>
+                            <value>256</value>
                         </entry>
                         <entry>
                             <key>addressUnits</key>
@@ -28191,7 +39223,7 @@
                         <name>coe_address_export</name>
                         <role>export</role>
                         <direction>Output</direction>
-                        <width>2</width>
+                        <width>6</width>
                         <lowerBound>0</lowerBound>
                         <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                     </port>
@@ -28369,11 +39401,11 @@
                     <suppliedSystemInfos>
                         <entry>
                             <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x10' datawidth='32' /&gt;&lt;/address-map&gt;</value>
+                            <value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x100' datawidth='32' /&gt;&lt;/address-map&gt;</value>
                         </entry>
                         <entry>
                             <key>ADDRESS_WIDTH</key>
-                            <value>4</value>
+                            <value>8</value>
                         </entry>
                         <entry>
                             <key>MAX_SLAVE_DATA_WIDTH</key>
@@ -28473,7 +39505,7 @@
                     <name>avs_mem_address</name>
                     <role>address</role>
                     <direction>Input</direction>
-                    <width>2</width>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -28512,17 +39544,21 @@
             </ports>
             <assignments>
                 <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
                     <entry>
                         <key>embeddedsw.configuration.isMemoryDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isNonVolatileStorage</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>embeddedsw.configuration.isPrintableDevice</key>
-                        <value>false</value>
+                        <value>0</value>
                     </entry>
                 </assignmentValueMap>
             </assignments>
@@ -28538,7 +39574,7 @@
                     </entry>
                     <entry>
                         <key>addressSpan</key>
-                        <value>16</value>
+                        <value>256</value>
                     </entry>
                     <entry>
                         <key>addressUnits</key>
@@ -28562,6 +39598,7 @@
                     </entry>
                     <entry>
                         <key>bridgedAddressOffset</key>
+                        <value>0</value>
                     </entry>
                     <entry>
                         <key>bridgesToMaster</key>
@@ -28766,7 +39803,7 @@
                     <name>coe_address_export</name>
                     <role>export</role>
                     <direction>Output</direction>
-                    <width>2</width>
+                    <width>6</width>
                     <lowerBound>0</lowerBound>
                     <vhdlType>STD_LOGIC_VECTOR</vhdlType>
                 </port>
@@ -28920,30 +39957,30 @@
     </interfaces>
 </boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
-    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_wg_3</hdlLibraryName>
+    <hdlLibraryName>qsys_lofar2_unb2b_adc_reg_wg</hdlLibraryName>
     <fileSets>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_3</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_3</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg</fileSetFixedName>
             <fileSetKind>QUARTUS_SYNTH</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_3</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_3</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg</fileSetFixedName>
             <fileSetKind>SIM_VERILOG</fileSetKind>
             <fileSetFiles/>
         </fileSet>
         <fileSet>
-            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg_3</fileSetName>
-            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg_3</fileSetFixedName>
+            <fileSetName>qsys_lofar2_unb2b_adc_reg_wg</fileSetName>
+            <fileSetFixedName>qsys_lofar2_unb2b_adc_reg_wg</fileSetFixedName>
             <fileSetKind>SIM_VHDL</fileSetKind>
             <fileSetFiles/>
         </fileSet>
     </fileSets>
 </generationInfoDefinition>]]></parameter>
   <parameter name="hlsFile" value="" />
-  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_3.ip</parameter>
+  <parameter name="logicalView">ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip</parameter>
   <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
     <assignmentValueMap/>
 </assignmentDefinition>]]></parameter>
@@ -29535,7 +40572,531 @@
         </connPtSystemInfos>
     </systemInfos>
 </componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>address</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_address_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>10</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>clk</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_clk_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>mem</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>avs_mem_address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>10</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_write</name>
+                    <role>write</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_read</name>
+                    <role>read</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>avs_mem_readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>DYNAMIC</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>4096</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>system_reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>read</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_read_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>readdata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_readdata_export</name>
+                    <role>export</role>
+                    <direction>Input</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_reset_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>system_reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>csi_system_reset</name>
+                    <role>reset</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>system</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>write</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_write_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>writedata</name>
+            <type>conduit</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>coe_writedata_export</name>
+                    <role>export</role>
+                    <direction>Output</direction>
+                    <width>32</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
     <hdlLibraryName>qsys_lofar2_unb2b_adc_rom_system_info</hdlLibraryName>
     <fileSets>
@@ -30097,117 +41658,696 @@
    &lt;/peripheral&gt;
   &lt;/peripherals&gt;
 &lt;/device&gt; </cmsisSrcFileContents>
-                    <addressGroup></addressGroup>
-                    <cmsisVars>
-                        <entry>
-                            <key>period_name_1_reset_value</key>
-                            <value>0x1</value>
-                        </entry>
-                        <entry>
-                            <key>snap_0</key>
-                            <value>Reserved</value>
-                        </entry>
-                        <entry>
-                            <key>period_name_0_reset_value</key>
-                            <value>0x869f</value>
-                        </entry>
-                        <entry>
-                            <key>snap_2</key>
-                            <value>Reserved</value>
-                        </entry>
-                        <entry>
-                            <key>snap_1</key>
-                            <value>Reserved</value>
-                        </entry>
-                        <entry>
-                            <key>snap_3</key>
-                            <value>Reserved</value>
-                        </entry>
-                        <entry>
-                            <key>period_name_0</key>
-                            <value>periodl</value>
-                        </entry>
-                        <entry>
-                            <key>period_name_1</key>
-                            <value>periodh</value>
-                        </entry>
-                        <entry>
-                            <key>period_snap_1</key>
-                            <value>snaph</value>
-                        </entry>
-                        <entry>
-                            <key>period_snap_1_reset_value</key>
-                            <value>0x0</value>
-                        </entry>
-                        <entry>
-                            <key>period_snap_0_reset_value</key>
-                            <value>0x0</value>
-                        </entry>
-                        <entry>
-                            <key>period_snap_0</key>
-                            <value>snapl</value>
-                        </entry>
-                    </cmsisVars>
-                </cmsisInfo>
-            </interface>
-        </interfaces>
-    </boundary>
-    <originalModuleInfo>
-        <className>altera_avalon_timer</className>
-        <version>18.0</version>
-        <displayName>Interval Timer Intel FPGA IP</displayName>
-    </originalModuleInfo>
-    <systemInfoParameterDescriptors>
-        <descriptors>
-            <descriptor>
-                <parameterDefaultValue>0</parameterDefaultValue>
-                <parameterName>systemFrequency</parameterName>
-                <parameterType>java.lang.Long</parameterType>
-                <systemInfoArgs>clk</systemInfoArgs>
-                <systemInfotype>CLOCK_RATE</systemInfotype>
-            </descriptor>
-        </descriptors>
-    </systemInfoParameterDescriptors>
-    <systemInfos>
-        <connPtSystemInfos>
-            <entry>
-                <key>clk</key>
-                <value>
-                    <connectionPointName>clk</connectionPointName>
-                    <suppliedSystemInfos/>
-                    <consumedSystemInfos>
-                        <entry>
-                            <key>CLOCK_RATE</key>
-                            <value>100000000</value>
-                        </entry>
-                    </consumedSystemInfos>
-                </value>
-            </entry>
-            <entry>
-                <key>s1</key>
-                <value>
-                    <connectionPointName>s1</connectionPointName>
-                    <suppliedSystemInfos>
-                        <entry>
-                            <key>ADDRESS_MAP</key>
-                            <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x20' datawidth='16' /&gt;&lt;/address-map&gt;</value>
-                        </entry>
-                        <entry>
-                            <key>ADDRESS_WIDTH</key>
-                            <value>5</value>
-                        </entry>
-                        <entry>
-                            <key>MAX_SLAVE_DATA_WIDTH</key>
-                            <value>16</value>
-                        </entry>
-                    </suppliedSystemInfos>
-                    <consumedSystemInfos/>
-                </value>
-            </entry>
-        </connPtSystemInfos>
-    </systemInfos>
-</componentDefinition>]]></parameter>
-  <parameter name="defaultBoundary" value="" />
+                    <addressGroup></addressGroup>
+                    <cmsisVars>
+                        <entry>
+                            <key>period_name_1_reset_value</key>
+                            <value>0x1</value>
+                        </entry>
+                        <entry>
+                            <key>snap_0</key>
+                            <value>Reserved</value>
+                        </entry>
+                        <entry>
+                            <key>period_name_0_reset_value</key>
+                            <value>0x869f</value>
+                        </entry>
+                        <entry>
+                            <key>snap_2</key>
+                            <value>Reserved</value>
+                        </entry>
+                        <entry>
+                            <key>snap_1</key>
+                            <value>Reserved</value>
+                        </entry>
+                        <entry>
+                            <key>snap_3</key>
+                            <value>Reserved</value>
+                        </entry>
+                        <entry>
+                            <key>period_name_0</key>
+                            <value>periodl</value>
+                        </entry>
+                        <entry>
+                            <key>period_name_1</key>
+                            <value>periodh</value>
+                        </entry>
+                        <entry>
+                            <key>period_snap_1</key>
+                            <value>snaph</value>
+                        </entry>
+                        <entry>
+                            <key>period_snap_1_reset_value</key>
+                            <value>0x0</value>
+                        </entry>
+                        <entry>
+                            <key>period_snap_0_reset_value</key>
+                            <value>0x0</value>
+                        </entry>
+                        <entry>
+                            <key>period_snap_0</key>
+                            <value>snapl</value>
+                        </entry>
+                    </cmsisVars>
+                </cmsisInfo>
+            </interface>
+        </interfaces>
+    </boundary>
+    <originalModuleInfo>
+        <className>altera_avalon_timer</className>
+        <version>19.1.0</version>
+        <displayName>Interval Timer Intel FPGA IP</displayName>
+    </originalModuleInfo>
+    <systemInfoParameterDescriptors>
+        <descriptors>
+            <descriptor>
+                <parameterDefaultValue>0</parameterDefaultValue>
+                <parameterName>systemFrequency</parameterName>
+                <parameterType>java.lang.Long</parameterType>
+                <systemInfoArgs>clk</systemInfoArgs>
+                <systemInfotype>CLOCK_RATE</systemInfotype>
+            </descriptor>
+        </descriptors>
+    </systemInfoParameterDescriptors>
+    <systemInfos>
+        <connPtSystemInfos>
+            <entry>
+                <key>clk</key>
+                <value>
+                    <connectionPointName>clk</connectionPointName>
+                    <suppliedSystemInfos/>
+                    <consumedSystemInfos>
+                        <entry>
+                            <key>CLOCK_RATE</key>
+                            <value>100000000</value>
+                        </entry>
+                    </consumedSystemInfos>
+                </value>
+            </entry>
+            <entry>
+                <key>s1</key>
+                <value>
+                    <connectionPointName>s1</connectionPointName>
+                    <suppliedSystemInfos>
+                        <entry>
+                            <key>ADDRESS_MAP</key>
+                            <value>&lt;address-map&gt;&lt;slave name='s1' start='0x0' end='0x20' datawidth='16' /&gt;&lt;/address-map&gt;</value>
+                        </entry>
+                        <entry>
+                            <key>ADDRESS_WIDTH</key>
+                            <value>5</value>
+                        </entry>
+                        <entry>
+                            <key>MAX_SLAVE_DATA_WIDTH</key>
+                            <value>16</value>
+                        </entry>
+                    </suppliedSystemInfos>
+                    <consumedSystemInfos/>
+                </value>
+            </entry>
+        </connPtSystemInfos>
+    </systemInfos>
+</componentDefinition>]]></parameter>
+  <parameter name="defaultBoundary"><![CDATA[<boundaryDefinition>
+    <interfaces>
+        <interface>
+            <name>clk</name>
+            <type>clock</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>clk</name>
+                    <role>clk</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>clockRate</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>externallyDriven</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>ptfSchematicName</key>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>irq</name>
+            <type>interrupt</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>irq</name>
+                    <role>irq</role>
+                    <direction>Output</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedAddressablePoint</key>
+                        <value>timer_0.s1</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>reset</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedReceiverOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToReceiver</key>
+                    </entry>
+                    <entry>
+                        <key>irqScheme</key>
+                        <value>NONE</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>reset</name>
+            <type>reset</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>reset_n</name>
+                    <role>reset_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap/>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>synchronousEdges</key>
+                        <value>DEASSERT</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+        </interface>
+        <interface>
+            <name>s1</name>
+            <type>avalon</type>
+            <isStart>false</isStart>
+            <ports>
+                <port>
+                    <name>address</name>
+                    <role>address</role>
+                    <direction>Input</direction>
+                    <width>3</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>writedata</name>
+                    <role>writedata</role>
+                    <direction>Input</direction>
+                    <width>16</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>readdata</name>
+                    <role>readdata</role>
+                    <direction>Output</direction>
+                    <width>16</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+                </port>
+                <port>
+                    <name>chipselect</name>
+                    <role>chipselect</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+                <port>
+                    <name>write_n</name>
+                    <role>write_n</role>
+                    <direction>Input</direction>
+                    <width>1</width>
+                    <lowerBound>0</lowerBound>
+                    <vhdlType>STD_LOGIC</vhdlType>
+                </port>
+            </ports>
+            <assignments>
+                <assignmentValueMap>
+                    <entry>
+                        <key>embeddedsw.configuration.isFlash</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isMemoryDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isNonVolatileStorage</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isPrintableDevice</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>embeddedsw.configuration.isTimerDevice</key>
+                        <value>1</value>
+                    </entry>
+                </assignmentValueMap>
+            </assignments>
+            <parameters>
+                <parameterValueMap>
+                    <entry>
+                        <key>addressAlignment</key>
+                        <value>NATIVE</value>
+                    </entry>
+                    <entry>
+                        <key>addressGroup</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>addressSpan</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>addressUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>alwaysBurstMaxBurst</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>associatedClock</key>
+                        <value>clk</value>
+                    </entry>
+                    <entry>
+                        <key>associatedReset</key>
+                        <value>reset</value>
+                    </entry>
+                    <entry>
+                        <key>bitsPerSymbol</key>
+                        <value>8</value>
+                    </entry>
+                    <entry>
+                        <key>bridgedAddressOffset</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>bridgesToMaster</key>
+                    </entry>
+                    <entry>
+                        <key>burstOnBurstBoundariesOnly</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>burstcountUnits</key>
+                        <value>WORDS</value>
+                    </entry>
+                    <entry>
+                        <key>constantBurstBehavior</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>explicitAddressSpan</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>holdTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>interleaveBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isBigEndian</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isFlash</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isMemoryDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>isNonVolatileStorage</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>linewrapBursts</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingReadTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>maximumPendingWriteTransactions</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>minimumReadLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumResponseLatency</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>minimumUninterruptedRunLength</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>prSafe</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>printableDevice</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>readLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitStates</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>readWaitTime</key>
+                        <value>1</value>
+                    </entry>
+                    <entry>
+                        <key>registerIncomingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>registerOutgoingSignals</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>setupTime</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>timingUnits</key>
+                        <value>Cycles</value>
+                    </entry>
+                    <entry>
+                        <key>transparentBridge</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>waitrequestAllowance</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>wellBehavedWaitrequest</key>
+                        <value>false</value>
+                    </entry>
+                    <entry>
+                        <key>writeLatency</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitStates</key>
+                        <value>0</value>
+                    </entry>
+                    <entry>
+                        <key>writeWaitTime</key>
+                        <value>0</value>
+                    </entry>
+                </parameterValueMap>
+            </parameters>
+            <cmsisInfo>
+                <cmsisSrcFileContents>&lt;?xml version="1.0" encoding="utf-8"?&gt;    
+&lt;device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd" &gt;
+  &lt;peripherals&gt;
+   &lt;peripheral&gt;
+      &lt;name&gt;altera_avalon_timer&lt;/name&gt;&lt;baseAddress&gt;0x00000000&lt;/baseAddress&gt; 
+      &lt;addressBlock&gt;
+        &lt;offset&gt;0x0&lt;/offset&gt;
+        &lt;size&gt;16&lt;/size&gt;
+        &lt;usage&gt;registers&lt;/usage&gt;
+      &lt;/addressBlock&gt;
+       &lt;registers&gt;
+         &lt;register&gt;     
+          &lt;name&gt;status&lt;/name&gt;  
+          &lt;displayName&gt;Status&lt;/displayName&gt;
+          &lt;description&gt;The status register has two defined bits. TO (timeout), RUN&lt;/description&gt;
+          &lt;addressOffset&gt;0x0&lt;/addressOffset&gt;
+          &lt;size&gt;16&lt;/size&gt;
+          &lt;access&gt;read-write&lt;/access&gt;
+          &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+          &lt;resetMask&gt;0xffff&lt;/resetMask&gt;
+          &lt;fields&gt;
+            &lt;field&gt;&lt;name&gt;TO&lt;/name&gt;
+            &lt;description&gt;The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.&lt;/description&gt;
+             &lt;bitOffset&gt;0x0&lt;/bitOffset&gt;
+             &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+             &lt;access&gt;read-only&lt;/access&gt;
+             &lt;readAction&gt;clear&lt;/readAction&gt;
+            &lt;/field&gt;
+            &lt;field&gt;&lt;name&gt;RUN&lt;/name&gt;
+            &lt;description&gt;The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
+ a write operation to the status register.&lt;/description&gt;
+             &lt;bitOffset&gt;1&lt;/bitOffset&gt;
+             &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+             &lt;access&gt;read-only&lt;/access&gt;
+            &lt;/field&gt;
+            &lt;field&gt;
+             &lt;name&gt;Reserved&lt;/name&gt;
+             &lt;description&gt;Reserved&lt;/description&gt;
+             &lt;bitOffset&gt;2&lt;/bitOffset&gt;
+             &lt;bitWidth&gt;14&lt;/bitWidth&gt;
+             &lt;access&gt;read-write&lt;/access&gt;
+             &lt;parameters&gt;
+                 &lt;parameter&gt;
+                 &lt;name&gt;Reserved&lt;/name&gt;
+                 &lt;value&gt;true&lt;/value&gt;
+                 &lt;/parameter&gt;
+             &lt;/parameters&gt;
+            &lt;/field&gt;
+          &lt;/fields&gt;
+        &lt;/register&gt; 
+        &lt;register&gt;
+            &lt;name&gt;control&lt;/name&gt;
+            &lt;description&gt;The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP&lt;/description&gt;
+            &lt;addressOffset&gt;0x1&lt;/addressOffset&gt;
+            &lt;size&gt;16&lt;/size&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+            &lt;reset&gt;
+                &lt;value&gt;0x0&lt;/value&gt;
+            &lt;/reset&gt;
+            &lt;field&gt;
+                &lt;name&gt;ITO&lt;/name&gt;
+                &lt;description&gt;If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.&lt;/description&gt;
+                &lt;bitOffset&gt;0&lt;/bitOffset&gt;
+                &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+                &lt;access&gt;read-write&lt;/access&gt;
+            &lt;/field&gt;
+            &lt;field&gt;
+                &lt;name&gt;CONT&lt;/name&gt;
+                &lt;description&gt;The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.&lt;/description&gt;
+                &lt;bitOffset&gt;1&lt;/bitOffset&gt;
+                &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+                &lt;access&gt;read-write&lt;/access&gt;
+            &lt;/field&gt;
+            &lt;field&gt;
+                &lt;name&gt;START&lt;/name&gt;
+                &lt;description&gt;Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.&lt;/description&gt;
+                &lt;bitOffset&gt;2&lt;/bitOffset&gt;
+                &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+                &lt;access&gt;write-only&lt;/access&gt;
+            &lt;/field&gt;
+            &lt;field&gt;
+                &lt;name&gt;STOP&lt;/name&gt;
+                &lt;description&gt;Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.&lt;/description&gt;
+                &lt;bitOffset&gt;3&lt;/bitOffset&gt;
+                &lt;bitWidth&gt;1&lt;/bitWidth&gt;
+                &lt;access&gt;write-only&lt;/access&gt;
+            &lt;/field&gt;
+            &lt;field&gt;
+                &lt;name&gt;Reserved&lt;/name&gt;
+                &lt;description&gt;Reserved&lt;/description&gt;
+                &lt;bitOffset&gt;4&lt;/bitOffset&gt;
+                &lt;bitWidth&gt;12&lt;/bitWidth&gt;
+                &lt;access&gt;read-write&lt;/access&gt;
+                &lt;parameters&gt;
+                    &lt;parameter&gt;
+                    &lt;name&gt;Reserved&lt;/name&gt;
+                    &lt;value&gt;true&lt;/value&gt;
+                    &lt;/parameter&gt;
+                &lt;/parameters&gt;
+            &lt;/field&gt;
+        &lt;/register&gt;
+        &lt;register&gt;
+            &lt;name&gt;${period_name_0}&lt;/name&gt;
+            &lt;description&gt;The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.&lt;/description&gt;
+            &lt;addressOffset&gt;0x2&lt;/addressOffset&gt;
+            &lt;size&gt;16&lt;/size&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+            &lt;resetValue&gt;${period_name_0_reset_value}&lt;/resetValue&gt;
+            &lt;resetMask&gt;0xffff&lt;/resetMask&gt;
+        &lt;/register&gt;
+        &lt;register&gt;
+            &lt;name&gt;${period_name_1}&lt;/name&gt;
+            &lt;description&gt;&lt;/description&gt;
+            &lt;addressOffset&gt;0x3&lt;/addressOffset&gt;
+            &lt;size&gt;16&lt;/size&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+            &lt;resetValue&gt;${period_name_1_reset_value}&lt;/resetValue&gt;
+            &lt;resetMask&gt;0xffff&lt;/resetMask&gt;
+        &lt;/register&gt;
+        &lt;register&gt;
+            &lt;name&gt;${period_snap_0}&lt;/name&gt;
+            &lt;description&gt;&lt;/description&gt;
+            &lt;addressOffset&gt;0x4&lt;/addressOffset&gt;
+            &lt;size&gt;16&lt;/size&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+            &lt;resetValue&gt;${period_snap_0_reset_value}&lt;/resetValue&gt;
+            &lt;resetMask&gt;0xffff&lt;/resetMask&gt;
+        &lt;/register&gt;
+        &lt;register&gt;
+            &lt;name&gt;${period_snap_1}&lt;/name&gt;
+            &lt;description&gt;&lt;/description&gt;
+            &lt;addressOffset&gt;0x5&lt;/addressOffset&gt;
+            &lt;size&gt;16&lt;/size&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+            &lt;resetValue&gt;${period_snap_1_reset_value}&lt;/resetValue&gt;
+            &lt;resetMask&gt;0xffff&lt;/resetMask&gt;
+        &lt;/register&gt;
+        &lt;register&gt;
+            &lt;name&gt;${snap_0}&lt;/name&gt;
+            &lt;description&gt;A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.&lt;/description&gt;
+            &lt;addressOffset&gt;0x6&lt;/addressOffset&gt;
+            &lt;size&gt;16&lt;/size&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+            &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+            &lt;resetMask&gt;0xffff&lt;/resetMask&gt;
+        &lt;/register&gt;
+        &lt;register&gt;
+            &lt;name&gt;${snap_1}&lt;/name&gt;
+            &lt;description&gt;&lt;/description&gt;
+            &lt;addressOffset&gt;0x7&lt;/addressOffset&gt;
+            &lt;size&gt;16&lt;/size&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+            &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+            &lt;resetMask&gt;0xffff&lt;/resetMask&gt;
+        &lt;/register&gt;
+        &lt;register&gt;
+            &lt;name&gt;${snap_2}&lt;/name&gt;
+            &lt;description&gt;&lt;/description&gt;
+            &lt;addressOffset&gt;0x8&lt;/addressOffset&gt;
+            &lt;size&gt;16&lt;/size&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+            &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+            &lt;resetMask&gt;0xffff&lt;/resetMask&gt;
+        &lt;/register&gt;
+        &lt;register&gt;
+            &lt;name&gt;${snap_3}&lt;/name&gt;
+            &lt;description&gt;&lt;/description&gt;
+            &lt;addressOffset&gt;0x9&lt;/addressOffset&gt;
+            &lt;size&gt;16&lt;/size&gt;
+            &lt;access&gt;read-write&lt;/access&gt;
+            &lt;resetValue&gt;0x0&lt;/resetValue&gt;
+            &lt;resetMask&gt;0xffff&lt;/resetMask&gt;
+        &lt;/register&gt;
+    &lt;/registers&gt;
+   &lt;/peripheral&gt;
+  &lt;/peripherals&gt;
+&lt;/device&gt; </cmsisSrcFileContents>
+                <addressGroup></addressGroup>
+                <cmsisVars>
+                    <entry>
+                        <key>period_name_1_reset_value</key>
+                        <value>0x1</value>
+                    </entry>
+                    <entry>
+                        <key>snap_0</key>
+                        <value>Reserved</value>
+                    </entry>
+                    <entry>
+                        <key>period_name_0_reset_value</key>
+                        <value>0x869f</value>
+                    </entry>
+                    <entry>
+                        <key>snap_2</key>
+                        <value>Reserved</value>
+                    </entry>
+                    <entry>
+                        <key>snap_1</key>
+                        <value>Reserved</value>
+                    </entry>
+                    <entry>
+                        <key>snap_3</key>
+                        <value>Reserved</value>
+                    </entry>
+                    <entry>
+                        <key>period_name_0</key>
+                        <value>periodl</value>
+                    </entry>
+                    <entry>
+                        <key>period_name_1</key>
+                        <value>periodh</value>
+                    </entry>
+                    <entry>
+                        <key>period_snap_1</key>
+                        <value>snaph</value>
+                    </entry>
+                    <entry>
+                        <key>period_snap_1_reset_value</key>
+                        <value>0x0</value>
+                    </entry>
+                    <entry>
+                        <key>period_snap_0_reset_value</key>
+                        <value>0x0</value>
+                    </entry>
+                    <entry>
+                        <key>period_snap_0</key>
+                        <value>snapl</value>
+                    </entry>
+                </cmsisVars>
+            </cmsisInfo>
+        </interface>
+    </interfaces>
+</boundaryDefinition>]]></parameter>
   <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
     <hdlLibraryName>qsys_lofar2_unb2b_adc_timer_0</hdlLibraryName>
     <fileSets>
@@ -30615,9 +42755,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_diag_data_buffer_jesd.mem">
+   end="jesd204b.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00100000" />
+  <parameter name="baseAddress" value="0x00040000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30635,9 +42775,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="ram_diag_data_buffer_jesd.mem">
+   end="reg_bsn_monitor_input.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00080000" />
+  <parameter name="baseAddress" value="0x00048000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30655,9 +42795,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="jesd204b.mem">
+   end="reg_bsn_source.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00040000" />
+  <parameter name="baseAddress" value="0x0004c100" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30675,9 +42815,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_bsn_monitor_input.mem">
+   end="reg_bsn_scheduler.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00048000" />
+  <parameter name="baseAddress" value="0x0004c110" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30695,9 +42835,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_wg_0.mem">
+   end="reg_dp_shiftram.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0004c000" />
+  <parameter name="baseAddress" value="0x0004c120" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30715,9 +42855,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_wg_1.mem">
+   end="ram_wg.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0004c010" />
+  <parameter name="baseAddress" value="0x00050000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30735,9 +42875,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_wg_2.mem">
+   end="reg_diag_data_buffer_bsn.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0004c020" />
+  <parameter name="baseAddress" value="0x00064000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30755,9 +42895,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="reg_wg_3.mem">
+   end="ram_diag_data_buffer_bsn.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0004c030" />
+  <parameter name="baseAddress" value="0x000c0000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30775,9 +42915,29 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="ram_wg_0.mem">
+   end="reg_aduh_monitor.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00050000" />
+  <parameter name="baseAddress" value="0x00068000" />
+  <parameter name="defaultConnection" value="false" />
+  <parameter name="domainAlias" value="" />
+  <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
+  <parameter name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+  <parameter name="qsys_mm.enableEccProtection" value="FALSE" />
+  <parameter name="qsys_mm.enableInstrumentation" value="FALSE" />
+  <parameter name="qsys_mm.insertDefaultSlave" value="FALSE" />
+  <parameter name="qsys_mm.interconnectResetSource" value="DEFAULT" />
+  <parameter name="qsys_mm.interconnectType" value="STANDARD" />
+  <parameter name="qsys_mm.maxAdditionalLatency" value="1" />
+  <parameter name="qsys_mm.syncResets" value="FALSE" />
+  <parameter name="qsys_mm.widthAdapterImplementation" value="GENERIC_CONVERTER" />
+ </connection>
+ <connection
+   kind="avalon"
+   version="19.4"
+   start="cpu_0.data_master"
+   end="ram_aduh_monitor.mem">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x00070000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30795,9 +42955,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="ram_wg_1.mem">
+   end="reg_wg.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00051000" />
+  <parameter name="baseAddress" value="0x0004c000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30815,9 +42975,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="ram_wg_2.mem">
+   end="reg_diag_data_buffer_jesd.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00052000" />
+  <parameter name="baseAddress" value="0x00060000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -30835,9 +42995,9 @@
    kind="avalon"
    version="19.4"
    start="cpu_0.data_master"
-   end="ram_wg_3.mem">
+   end="ram_diag_data_buffer_jesd.mem">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x00053000" />
+  <parameter name="baseAddress" value="0x00080000" />
   <parameter name="defaultConnection" value="false" />
   <parameter name="domainAlias" value="" />
   <parameter name="qsys_mm.burstAdapterImplementation" value="GENERIC_CONVERTER" />
@@ -31075,30 +43235,59 @@
    version="19.4"
    start="clk_0.clk"
    end="reg_fpga_voltage_sens.system" />
+ <connection kind="clock" version="19.4" start="clk_0.clk" end="jesd204b.system" />
  <connection
    kind="clock"
    version="19.4"
    start="clk_0.clk"
-   end="reg_diag_data_buffer_jesd.system" />
+   end="reg_bsn_monitor_input.system" />
  <connection
    kind="clock"
    version="19.4"
    start="clk_0.clk"
-   end="ram_diag_data_buffer_jesd.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="jesd204b.system" />
+   end="reg_bsn_source.system" />
  <connection
    kind="clock"
    version="19.4"
    start="clk_0.clk"
-   end="reg_bsn_monitor_input.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_wg_0.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_wg_1.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_wg_2.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_wg_3.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="ram_wg_0.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="ram_wg_1.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="ram_wg_2.system" />
- <connection kind="clock" version="19.4" start="clk_0.clk" end="ram_wg_3.system" />
+   end="reg_bsn_scheduler.system" />
+ <connection
+   kind="clock"
+   version="19.4"
+   start="clk_0.clk"
+   end="reg_dp_shiftram.system" />
+ <connection kind="clock" version="19.4" start="clk_0.clk" end="ram_wg.system" />
+ <connection
+   kind="clock"
+   version="19.4"
+   start="clk_0.clk"
+   end="reg_diag_data_buffer_bsn.system" />
+ <connection
+   kind="clock"
+   version="19.4"
+   start="clk_0.clk"
+   end="ram_diag_data_buffer_bsn.system" />
+ <connection
+   kind="clock"
+   version="19.4"
+   start="clk_0.clk"
+   end="reg_aduh_monitor.system" />
+ <connection
+   kind="clock"
+   version="19.4"
+   start="clk_0.clk"
+   end="ram_aduh_monitor.system" />
+ <connection kind="clock" version="19.4" start="clk_0.clk" end="reg_wg.system" />
+ <connection
+   kind="clock"
+   version="19.4"
+   start="clk_0.clk"
+   end="reg_diag_data_buffer_jesd.system" />
+ <connection
+   kind="clock"
+   version="19.4"
+   start="clk_0.clk"
+   end="ram_diag_data_buffer_jesd.system" />
  <connection
    kind="interrupt"
    version="19.4"
@@ -31216,62 +43405,67 @@
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_diag_data_buffer_jesd.system_reset" />
+   end="jesd204b.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="ram_diag_data_buffer_jesd.system_reset" />
+   end="reg_bsn_monitor_input.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="jesd204b.system_reset" />
+   end="reg_bsn_source.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_bsn_monitor_input.system_reset" />
+   end="reg_bsn_scheduler.system_reset" />
+ <connection
+   kind="reset"
+   version="19.4"
+   start="clk_0.clk_reset"
+   end="reg_dp_shiftram.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_wg_0.system_reset" />
+   end="ram_wg.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_wg_1.system_reset" />
+   end="reg_diag_data_buffer_bsn.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_wg_2.system_reset" />
+   end="ram_diag_data_buffer_bsn.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="reg_wg_3.system_reset" />
+   end="reg_aduh_monitor.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="ram_wg_0.system_reset" />
+   end="ram_aduh_monitor.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="ram_wg_1.system_reset" />
+   end="reg_wg.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="ram_wg_2.system_reset" />
+   end="reg_diag_data_buffer_jesd.system_reset" />
  <connection
    kind="reset"
    version="19.4"
    start="clk_0.clk_reset"
-   end="ram_wg_3.system_reset" />
+   end="ram_diag_data_buffer_jesd.system_reset" />
  <connection
    kind="reset"
    version="19.4"
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
index 481256624f3b1de3eb77f3272fcddbd6f4f0a047..0527dc52a1de92830b38cd4998ef114604e6fc76 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
@@ -14,11 +14,12 @@ hdl_lib_technology = ip_arria10_e1sg
 test_bench_files = 
     tb_lofar2_unb2b_adc_full.vhd
 
+regression_test_vhdl =
+    tb_lofar2_unb2b_adc_full.vhd
 
 
 [modelsim_project_file]
 modelsim_copy_files =
-# Pinning design only intended for synthesis
 
 
 [quartus_project_file]
@@ -69,13 +70,17 @@ quartus_ip_files =
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
     $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg_3.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_0.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_1.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_2.ip
-    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg_3.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_jesd.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_jesd.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
+    $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
 
 nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index 64bac09ec83470590b82bfef651030ab49b01993..6289c73f28f7bd582e4b3493277575dd6341fa29 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -1,25 +1,31 @@
 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2015
+-- Copyright 2020
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+--     http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -------------------------------------------------------------------------------
 
+-- Author : J Hargreaves
+-- Purpose:  
+--   Wrapper for full adc input test design
+-- Description:
+--   Unb2b version for lab testing
+--   Contains complete AIT input stage with 12 ADC streams
+
+
 LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
@@ -33,7 +39,7 @@ USE dp_lib.dp_stream_pkg.ALL;
 ENTITY lofar2_unb2b_adc_full IS
   GENERIC (
     g_design_name      : STRING  := "lofar2_unb2b_adc_full";
-    g_design_note      : STRING  := "Lofar2 adc with one node";
+    g_design_note      : STRING  := "Lofar2 adc with all streams";
     g_sim              : BOOLEAN := FALSE; --Overridden by TB
     g_sim_unb_nr       : NATURAL := 0;
     g_sim_node_nr      : NATURAL := 0;
@@ -76,14 +82,14 @@ ENTITY lofar2_unb2b_adc_full IS
  
     -- jesd204b syncronization signals (2 syncs)
     JESD204B_SYSREF : IN    STD_LOGIC;
-    JESD204B_SYNC   : OUT   STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+    JESD204B_SYNC_N : OUT   STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
   );
 END lofar2_unb2b_adc_full;
  
 ARCHITECTURE str OF lofar2_unb2b_adc_full IS
 
   SIGNAL JESD204B_SERIAL_DATA       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
-  SIGNAL jesd204b_sync_arr          : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
+  SIGNAL jesd204b_sync_n_arr        : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
   SIGNAL JESD204B_REFCLK            : STD_LOGIC;
 
 
@@ -103,7 +109,7 @@ BEGIN
   JESD204B_SERIAL_DATA(9) <= '0';
   JESD204B_SERIAL_DATA(10) <= '0';
   JESD204B_SERIAL_DATA(11) <= '0';
-  JESD204B_SYNC(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+  JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
 
 
   u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
@@ -152,6 +158,6 @@ BEGIN
   
     -- jesd204b syncronization signals
     JESD204B_SYSREF        => JESD204B_SYSREF,
-    JESD204B_SYNC          => jesd204b_sync_arr
+    JESD204B_SYNC_N        => jesd204b_sync_n_arr
   );
 END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
index db3b93892959ce06d7c4d62761b3aceca67d1daa..f2a51e01f0cb82287b2ac7649359cff34842cc91 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
@@ -1,25 +1,24 @@
 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2018
+-- Copyright 2020
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+--     http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -------------------------------------------------------------------------------
 
+
 -- Author: Jonathan Hargreaves
 -- Purpose: Tb to show that lofar2_unb2b_adc_full can simulate
 -- Description:
@@ -82,7 +81,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_full IS
 
   -- jesd204b syncronization signals
   SIGNAL jesd204b_sysref     : STD_LOGIC;
-  SIGNAL jesd204b_sync       : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_sync_n     : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
 
 
 BEGIN
@@ -153,7 +152,7 @@ BEGIN
   
     -- jesd204b syncronization signals
     JESD204B_SYSREF => jesd204b_sysref,
-    JESD204B_SYNC   => jesd204b_sync
+    JESD204B_SYNC_N => jesd204b_sync_n
   );
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
index 1d2a4835d5ece5aafd05140e6ba10604d0b77a57..de14b2bf00654f3d3d2df4a28a75943ee42108f4 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
@@ -14,6 +14,8 @@ hdl_lib_technology = ip_arria10_e1sg
 test_bench_files = 
     tb_lofar2_unb2b_adc_one_node.vhd
 
+regression_test_vhdl =
+    tb_lofar2_unb2b_adc_one_node.vhd
 
 [modelsim_project_file]
 modelsim_copy_files =
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 6cab5a830ddee67eb9792ef8aa440fbc4cb3bf29..0992d5502238a45f1a2a5cf989d91d22fe51d272 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -1,24 +1,30 @@
 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2015
+-- Copyright 2020
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+--     http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------\
+
+
+-- Author : J Hargreaves
+-- Purpose:  
+--   Wrapper for one node adc input test design
+-- Description:
+--   Unb2b version for lab testing
+--   Contains complete AIT input stage with 1 ADC stream
 
 LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -76,7 +82,7 @@ ENTITY lofar2_unb2b_adc_one_node IS
  
     -- jesd204b syncronization signals (2 syncs)
     JESD204B_SYSREF : IN    STD_LOGIC;
-    JESD204B_SYNC   : OUT   STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
+    JESD204B_SYNC_N : OUT   STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0)
   );
 END lofar2_unb2b_adc_one_node;
 
@@ -84,7 +90,7 @@ END lofar2_unb2b_adc_one_node;
 ARCHITECTURE str OF lofar2_unb2b_adc_one_node IS
 
   SIGNAL JESD204B_SERIAL_DATA       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
-  SIGNAL jesd204b_sync_arr          : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
+  SIGNAL jesd204b_sync_n_arr        : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1  downto 0);
   SIGNAL JESD204B_REFCLK            : STD_LOGIC;
 
 BEGIN
@@ -103,7 +109,7 @@ BEGIN
   JESD204B_SERIAL_DATA(9) <= '0';
   JESD204B_SERIAL_DATA(10) <= '0';
   JESD204B_SERIAL_DATA(11) <= '0';
-  JESD204B_SYNC(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+  JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
 
   u_revision : ENTITY lofar2_unb2b_adc_lib.lofar2_unb2b_adc
   GENERIC MAP (
@@ -151,6 +157,6 @@ BEGIN
   
     -- jesd204b syncronization signals
     JESD204B_SYSREF        => JESD204B_SYSREF,
-    JESD204B_SYNC          => jesd204b_sync_arr
+    JESD204B_SYNC_N        => jesd204b_sync_n_arr
   );
 END str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
index ead898fe060cced8b372db29479362f9631a7b1c..05e205179d19289848f8ecfec9564aefcb632fa3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
@@ -1,22 +1,20 @@
 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2018
+-- Copyright 2020
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+--     http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -------------------------------------------------------------------------------
 
@@ -82,7 +80,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_one_node IS
 
   -- jesd204b syncronization signals
   SIGNAL jesd204b_sysref     : STD_LOGIC;
-  SIGNAL jesd204b_sync       : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_sync_n     : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
 
 
 BEGIN
@@ -153,7 +151,7 @@ BEGIN
   
     -- jesd204b syncronization signals
     JESD204B_SYSREF => jesd204b_sysref,
-    JESD204B_SYNC   => jesd204b_sync
+    JESD204B_SYNC_N => jesd204b_sync_n
   );
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index c879826d0efdced6c772f3ea2622ce02201242ea..e9804142486e8b8942567ae8ea5a913163848140 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -1,25 +1,31 @@
 -------------------------------------------------------------------------------
 --
--- Copyright (C) 2015
+-- Copyright 2020
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
 --
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--- GNU General Public License for more details.
+--     http://www.apache.org/licenses/LICENSE-2.0
 --
--- You should have received a copy of the GNU General Public License
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
 --
 -------------------------------------------------------------------------------
 
+
+-- Author : J Hargreaves
+-- Purpose:  
+--   Core design for Lofar2 ADC input stage
+-- Description:
+--   Unb2b version for lab testing
+--   Use revisions to select one_node or full versions
+
 LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, dp_lib, tech_jesd204b_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
@@ -37,7 +43,7 @@ ENTITY lofar2_unb2b_adc IS
     g_design_name      : STRING  := "lofar2_unb2b_adc";
     g_design_note      : STRING  := "UNUSED";
     g_technology       : NATURAL := c_tech_arria10_e1sg;
-    g_buf_nof_data     : NATURAL := 8192;
+    g_buf_nof_data     : NATURAL := 1024;
     g_sim              : BOOLEAN := FALSE; --Overridden by TB
     g_sim_unb_nr       : NATURAL := 0;
     g_sim_node_nr      : NATURAL := 0;
@@ -84,7 +90,7 @@ ENTITY lofar2_unb2b_adc IS
  
     -- jesd204b syncronization signals
     JESD204B_SYSREF            : IN    STD_LOGIC;
-    JESD204B_SYNC              : OUT   STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0)
+    JESD204B_SYNC_N            : OUT   STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0)
   );
 END lofar2_unb2b_adc;
 
@@ -93,30 +99,13 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
 
   -- Revision parameters
   CONSTANT c_revision_select        : t_lofar2_unb2b_adc_config := func_sel_revision_rec(g_design_name);
-  CONSTANT c_nof_streams_jesd204b   : NATURAL := c_revision_select.nof_streams_jesd204b; -- IP is set up for 12 streams
-  CONSTANT c_nof_streams_db         : NATURAL := c_revision_select.nof_streams_db;       -- Streams of raw samples to record in db
-  CONSTANT c_nof_streams_input      : NATURAL := c_revision_select.nof_streams_input;    -- Streams actually passed through for processing
+  CONSTANT c_nof_streams            : NATURAL := c_revision_select.nof_streams_input;    -- Streams actually passed through for processing
 
   -- Firmware version x.y
   CONSTANT c_fw_version             : t_unb2b_board_fw_version := (1, 1);
   CONSTANT c_mm_clk_freq            : NATURAL := c_unb2b_board_mm_clk_freq_100M;
   CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6;  -- alternate 160MHz. TODO: Use to check PPS
 
-  -- Waveform Generator
-  CONSTANT c_wg_buf_directory       : STRING := "data/";
-  CONSTANT c_wg_buf_dat_w           : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
-  CONSTANT c_wg_buf_addr_w          : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
-  SIGNAL wg_out_ovr                 : STD_LOGIC_VECTOR(c_nof_streams_input-1 DOWNTO 0);    
-  SIGNAL wg_out_val                 : STD_LOGIC_VECTOR(c_nof_streams_input-1 DOWNTO 0);    
-  SIGNAL wg_out_data                : STD_LOGIC_VECTOR(c_nof_streams_input*c_wg_buf_dat_w-1 DOWNTO 0);    
-  SIGNAL wg_out_sync                : STD_LOGIC_VECTOR(c_nof_streams_input-1 DOWNTO 0);    
-  SIGNAL wg_sosi_arr                : t_dp_sosi_arr(c_nof_streams_input-1 DOWNTO 0);    
-  SIGNAL mux_sosi_arr               : t_dp_sosi_arr(c_nof_streams_input-1 DOWNTO 0);         
-  SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(c_nof_streams_input-1 DOWNTO 0);
-
-  -- bsn monitor
-  SIGNAL bsn_sosi_arr               : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0) := (others => c_dp_sosi_rst);
-
   -- System
   SIGNAL cs_sim                     : STD_LOGIC;
   SIGNAL xo_ethclk                  : STD_LOGIC;
@@ -125,10 +114,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
   SIGNAL mm_clk                     : STD_LOGIC;
   SIGNAL mm_rst                     : STD_LOGIC := '0';
   
-  SIGNAL st_rst                     : STD_LOGIC;
-  SIGNAL st_clk                     : STD_LOGIC;
-  SIGNAL st_pps                     : STD_LOGIC;
-
+  SIGNAL dp_pps                     : STD_LOGIC;
   SIGNAL dp_rst                     : STD_LOGIC;
   SIGNAL dp_clk                     : STD_LOGIC;
 
@@ -197,36 +183,51 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
   SIGNAL jesd204b_mosi              : t_mem_mosi := c_mem_mosi_rst;
   SIGNAL jesd204b_miso              : t_mem_miso := c_mem_miso_rst;
 
+  -- Shiftram (applies per-antenna delay)
+  SIGNAL reg_dp_shiftram_mosi       : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_dp_shiftram_miso       : t_mem_miso := c_mem_miso_rst;
+
+  -- bsn source
+  SIGNAL reg_bsn_source_mosi        : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_bsn_source_miso        : t_mem_miso := c_mem_miso_rst;
+
+  -- bsn scheduler
+  SIGNAL reg_bsn_scheduler_wg_mosi  : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_bsn_scheduler_wg_miso  : t_mem_miso := c_mem_miso_rst;
+
   -- WG
-  SIGNAL reg_wg_mosi_arr            : t_mem_mosi_arr(12-1 DOWNTO 0);
-  SIGNAL reg_wg_miso_arr            : t_mem_miso_arr(12-1 DOWNTO 0);
-  SIGNAL ram_wg_mosi_arr            : t_mem_mosi_arr(12-1 DOWNTO 0);
-  SIGNAL ram_wg_miso_arr            : t_mem_miso_arr(12-1 DOWNTO 0);
+  SIGNAL reg_wg_mosi                : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_wg_miso                : t_mem_miso := c_mem_miso_rst;
+  SIGNAL ram_wg_mosi                : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL ram_wg_miso                : t_mem_miso := c_mem_miso_rst;
 
   -- BSN MONITOR
   SIGNAL reg_bsn_monitor_input_mosi : t_mem_mosi;
   SIGNAL reg_bsn_monitor_input_miso : t_mem_miso;
 
+  -- Data buffer raw
+  SIGNAL ram_diag_data_buf_jesd_mosi: t_mem_mosi;
+  SIGNAL ram_diag_data_buf_jesd_miso: t_mem_miso;
+  SIGNAL reg_diag_data_buf_jesd_mosi: t_mem_mosi;
+  SIGNAL reg_diag_data_buf_jesd_miso: t_mem_miso;
+
+  -- Data buffer bsn
+  SIGNAL ram_diag_data_buf_bsn_mosi : t_mem_mosi;
+  SIGNAL ram_diag_data_buf_bsn_miso : t_mem_miso;
+  SIGNAL reg_diag_data_buf_bsn_mosi : t_mem_mosi;
+  SIGNAL reg_diag_data_buf_bsn_miso : t_mem_miso;
+
+  -- Aduh statistics monitor
+  SIGNAL ram_aduh_monitor_mosi      : t_mem_mosi;
+  SIGNAL ram_aduh_monitor_miso      : t_mem_miso;
+  SIGNAL reg_aduh_monitor_mosi      : t_mem_mosi;
+  SIGNAL reg_aduh_monitor_miso      : t_mem_miso;
+
   -- QSFP leds
   SIGNAL qsfp_green_led_arr         : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
   SIGNAL qsfp_red_led_arr           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
 
-  -- JESD signals
-  SIGNAL ram_diag_data_buf_jesd_mosi    : t_mem_mosi;
-  SIGNAL ram_diag_data_buf_jesd_miso    : t_mem_miso;
-  SIGNAL reg_diag_data_buf_jesd_mosi    : t_mem_mosi;
-  SIGNAL reg_diag_data_buf_jesd_miso    : t_mem_miso;
-  SIGNAL diag_data_buf_snk_in_arr       : t_dp_sosi_arr(c_nof_streams_db-1 DOWNTO 0);
-  SIGNAL jesd204b_rx_src_out_arr        : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
-  SIGNAL jesd204b_frame_clk             : STD_LOGIC;
-
-  -------------------------------------------------------------------------------
-  -- DP sync checker / insert
-  -------------------------------------------------------------------------------
-  CONSTANT c_nof_clk_per_blk         : NATURAL := 1024;
-  CONSTANT c_nof_blk_per_sync        : NATURAL := 800000;
-  CONSTANT c_nof_clk_per_sync        : NATURAL := c_nof_blk_per_sync * 256;  -- = 800000 * 256
-  CONSTANT c_bsn_sync_timeout        : NATURAL := (c_nof_clk_per_sync * 10)/8; -- *10/8 as margin
+  SIGNAL alt_sosi_arr               : t_dp_sosi_arr(c_nof_streams-1 DOWNTO 0);         
 
 
 
@@ -264,9 +265,9 @@ BEGIN
 
     dp_rst                   => dp_rst,
     dp_clk                   => dp_clk,              -- Can be external 200MHz, or PLL generated
-    dp_pps                   => st_pps,
-    dp_rst_in                => st_rst,
-    dp_clk_in                => jesd204b_frame_clk,
+    dp_pps                   => dp_pps,
+    dp_rst_in                => dp_rst,
+    dp_clk_in                => dp_clk,
     
     -- Toggle WDI
     pout_wdi                 => pout_wdi,
@@ -328,10 +329,13 @@ BEGIN
     eth1g_reg_interrupt      => eth1g_reg_interrupt,
     eth1g_ram_mosi           => eth1g_ram_mosi,
     eth1g_ram_miso           => eth1g_ram_miso,
-        
+ 
+    ram_scrap_mosi           => c_mem_mosi_rst,
+    ram_scrap_miso           => open,
+   
     -- FPGA pins
     -- . General
-    CLK                      => jesd204b_frame_clk,
+    CLK                      => CLK,
     PPS                      => PPS,
     WDI                      => WDI,
     INTA                     => INTA,
@@ -370,34 +374,23 @@ BEGIN
     -- PIOs
     pout_wdi                 => pout_wdi,
 
-    -- Manual WDI override
+    -- mm interfaces for control
     reg_wdi_mosi             => reg_wdi_mosi,
     reg_wdi_miso             => reg_wdi_miso,
-
-    -- system_info
     reg_unb_system_info_mosi => reg_unb_system_info_mosi,
     reg_unb_system_info_miso => reg_unb_system_info_miso,
     rom_unb_system_info_mosi => rom_unb_system_info_mosi,
     rom_unb_system_info_miso => rom_unb_system_info_miso, 
-
-    -- UniBoard I2C sensors
     reg_unb_sens_mosi        => reg_unb_sens_mosi,
     reg_unb_sens_miso        => reg_unb_sens_miso, 
-
     reg_unb_pmbus_mosi       => reg_unb_pmbus_mosi,
     reg_unb_pmbus_miso       => reg_unb_pmbus_miso,
- 
-    -- FPGA sensors
     reg_fpga_temp_sens_mosi  => reg_fpga_temp_sens_mosi,
     reg_fpga_temp_sens_miso  => reg_fpga_temp_sens_miso,
     reg_fpga_voltage_sens_mosi  => reg_fpga_voltage_sens_mosi,
     reg_fpga_voltage_sens_miso  => reg_fpga_voltage_sens_miso,
-
-    -- PPSH
     reg_ppsh_mosi            => reg_ppsh_mosi,
     reg_ppsh_miso            => reg_ppsh_miso, 
-  
-    -- eth1g
     eth1g_mm_rst             => eth1g_mm_rst,
     eth1g_tse_mosi           => eth1g_tse_mosi,
     eth1g_tse_miso           => eth1g_tse_miso,
@@ -406,225 +399,105 @@ BEGIN
     eth1g_reg_interrupt      => eth1g_reg_interrupt,
     eth1g_ram_mosi           => eth1g_ram_mosi,
     eth1g_ram_miso           => eth1g_ram_miso,
-
-    -- EPCS read
     reg_dpmm_data_mosi       => reg_dpmm_data_mosi,
     reg_dpmm_data_miso       => reg_dpmm_data_miso,
     reg_dpmm_ctrl_mosi       => reg_dpmm_ctrl_mosi,
     reg_dpmm_ctrl_miso       => reg_dpmm_ctrl_miso,
-
-    -- EPCS write
     reg_mmdp_data_mosi       => reg_mmdp_data_mosi,
     reg_mmdp_data_miso       => reg_mmdp_data_miso,
     reg_mmdp_ctrl_mosi       => reg_mmdp_ctrl_mosi,
     reg_mmdp_ctrl_miso       => reg_mmdp_ctrl_miso,
-
-    -- EPCS status/control
     reg_epcs_mosi            => reg_epcs_mosi,
     reg_epcs_miso            => reg_epcs_miso,
-
-    -- Remote Update
     reg_remu_mosi            => reg_remu_mosi,
     reg_remu_miso            => reg_remu_miso,
 
-    --
+    -- mm buses for signal flow blocks
+    -- Jesd ip status/control
+    jesd204b_mosi               => jesd204b_mosi,
+    jesd204b_miso               => jesd204b_miso,
+    reg_dp_shiftram_mosi        => reg_dp_shiftram_mosi,
+    reg_dp_shiftram_miso        => reg_dp_shiftram_miso,
+    reg_bsn_source_mosi         => reg_bsn_source_mosi,
+    reg_bsn_source_miso         => reg_bsn_source_miso,
+    reg_bsn_scheduler_mosi      => reg_bsn_scheduler_wg_mosi,
+    reg_bsn_scheduler_miso      => reg_bsn_scheduler_wg_miso,
+    reg_wg_mosi                 => reg_wg_mosi,
+    reg_wg_miso                 => reg_wg_miso,
+    ram_wg_mosi                 => ram_wg_mosi,
+    ram_wg_miso                 => ram_wg_miso,
+    reg_bsn_monitor_input_mosi  => reg_bsn_monitor_input_mosi,
+    reg_bsn_monitor_input_miso  => reg_bsn_monitor_input_miso,
     ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
     ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
     reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
     reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
-
-    -- BSN Monitor
-    reg_bsn_monitor_input_mosi => reg_bsn_monitor_input_mosi,
-    reg_bsn_monitor_input_miso => reg_bsn_monitor_input_miso,
-
-    -- WGs 
-    reg_wg_mosi_arr          => reg_wg_mosi_arr,
-    reg_wg_miso_arr          => reg_wg_miso_arr,
-    ram_wg_mosi_arr          => ram_wg_mosi_arr,
-    ram_wg_miso_arr          => ram_wg_miso_arr,
- 
-    -- Jesd ip status/control
-    jesd204b_mosi            => jesd204b_mosi,
-    jesd204b_miso            => jesd204b_miso
+    ram_diag_data_buf_bsn_mosi  => ram_diag_data_buf_bsn_mosi,
+    ram_diag_data_buf_bsn_miso  => ram_diag_data_buf_bsn_miso,
+    reg_diag_data_buf_bsn_mosi  => reg_diag_data_buf_bsn_mosi,
+    reg_diag_data_buf_bsn_miso  => reg_diag_data_buf_bsn_miso,
+    ram_aduh_monitor_mosi       => ram_aduh_monitor_mosi,
+    ram_aduh_monitor_miso       => ram_aduh_monitor_miso,
+    reg_aduh_monitor_mosi       => reg_aduh_monitor_mosi,
+    reg_aduh_monitor_miso       => reg_aduh_monitor_miso
   );
 
   
   -----------------------------------------------------------------------------
-  -- JESD204B IP (ADC Handler)
+  -- node_adc_input_and_timing (AIT)
+  --   .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
   -----------------------------------------------------------------------------
   
-  u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 
+  u_ait: ENTITY work.node_adc_input_and_timing
   GENERIC MAP(
-    g_sim                => g_sim,                
-    g_nof_channels       => c_nof_streams_jesd204b,
-    g_nof_syncs          => c_nof_streams_jesd204b/3        -- Three ADCs per RCU share a sync
+    g_technology                => g_technology,
+    g_nof_streams               => c_nof_streams,
+    g_sim                       => g_sim                
   )
   PORT MAP(
-    jesd204b_refclk      => JESD204B_REFCLK,   
-    jesd204b_sysref      => JESD204B_SYSREF,   
-    jesd204b_sync_n_arr  => JESD204B_SYNC,   
-  
-    rx_src_out_arr       => jesd204b_rx_src_out_arr,          
-    jesd204b_frame_clk   => jesd204b_frame_clk,          
-  
-    -- MM
-    mm_clk               => mm_clk,           
-    mm_rst               => mm_rst,           
-  
-    jesd204b_mosi        => jesd204b_mosi,         
-    jesd204b_miso        => jesd204b_miso,         
-  
-     -- Serial
-    serial_tx_arr        => open,
-    serial_rx_arr        => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b-1 downto 0)
-  );
-
-
-  gen_jesd_mon_in : FOR i IN 0 TO c_nof_streams_db-1 GENERATE
-    diag_data_buf_snk_in_arr(i).data(15 downto 0) <= jesd204b_rx_src_out_arr(i).data(15 downto 0);
-    diag_data_buf_snk_in_arr(i).valid <= jesd204b_rx_src_out_arr(i).valid;
-    diag_data_buf_snk_in_arr(i).sop   <= '0';
-    diag_data_buf_snk_in_arr(i).eop   <= '0';
-    diag_data_buf_snk_in_arr(i).err   <= (OTHERS=>'0');
-  END GENERATE;
-
-
-  -----------------------------------------------------------------------------
-  -- Diagnostic Data Buffer (Records 8192 raw ADC samples after the PPS)
-  -----------------------------------------------------------------------------
-
-  u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
-  GENERIC MAP (
-    g_technology   => g_technology,
-    g_nof_streams  => c_nof_streams_db,
-    g_data_w       => 16,
-    g_buf_nof_data => g_buf_nof_data,
-    g_buf_use_sync => TRUE, -- when TRUE start filling the buffer at the in_sync, else after the last word was read
-    g_use_rx_seq   => FALSE
-  )
-  PORT MAP (
-    mm_rst            => mm_rst,
-    mm_clk            => mm_clk,
-    dp_rst            => st_rst,
-    dp_clk            => jesd204b_frame_clk,
-
-    ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
-    ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
-    reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
-    reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
-
-    in_sosi_arr       => diag_data_buf_snk_in_arr,
-    in_sync           => st_pps
-  );
-
-  -----------------------------------------------------------------------------
-  -- WG (Test Signal Generator)
-  -----------------------------------------------------------------------------
-
-  gen_wg : FOR I IN 0 TO c_nof_streams_input-1 GENERATE
-    u_sp : ENTITY diag_lib.mms_diag_wg_wideband
-    GENERIC MAP (
-      g_cross_clock_domain => TRUE,
-      g_buf_dir            => c_wg_buf_directory,
-
-      -- Wideband parameters
-      g_wideband_factor    => 1, 
-
-      -- Basic WG parameters, see diag_wg.vhd for their meaning
-      g_buf_dat_w          => c_wg_buf_dat_w,
-      g_buf_addr_w         => c_wg_buf_addr_w,
-      g_calc_support       => TRUE,
-      g_calc_gain_w        => 1,
-      g_calc_dat_w         => c_wg_buf_dat_w
-    )
-    PORT MAP (
-      -- Memory-mapped clock domain
-      mm_rst              => mm_rst,
-      mm_clk              => mm_clk,
-
-      reg_mosi            => reg_wg_mosi_arr(I),
-      reg_miso            => reg_wg_miso_arr(I),
-
-      buf_mosi            => ram_wg_mosi_arr(I),
-      buf_miso            => ram_wg_miso_arr(I),
-
-      -- Streaming clock domain
-      st_rst              => dp_rst,
-      st_clk              => jesd204b_frame_clk,
-      st_restart          => st_pps,
-
-      out_ovr             => wg_out_ovr(I downto I),
-      out_val             => wg_out_val(I downto I),
-      out_dat             => wg_out_data((I+1)*c_wg_buf_dat_w-1 downto I*c_wg_buf_dat_w),
-      out_sync            => wg_out_sync(I downto I)
-    );
-
-    wg_sosi_arr(I).err(0) <= wg_out_ovr(I);
-    wg_sosi_arr(I).valid <= wg_out_val(I);
-    wg_sosi_arr(I).data(c_wg_buf_dat_w-1 downto 0) <= wg_out_data((I+1)*c_wg_buf_dat_w-1 downto I*c_wg_buf_dat_w);
-    wg_sosi_arr(I).sync <= wg_out_sync(I);
-
-  END GENERATE;
-
-
-
-  -----------------------------------------------------------------------------
-  -- ADC/WG Mux (Input Select)
-  -----------------------------------------------------------------------------
+    -- clocks and resets
+    mm_clk                      => mm_clk,           
+    mm_rst                      => mm_rst,           
+    dp_clk                      => dp_clk,           
+    dp_rst                      => dp_rst,           
+ 
+    -- mm control buses 
+    jesd204b_mosi               => jesd204b_mosi,         
+    jesd204b_miso               => jesd204b_miso,         
+    reg_dp_shiftram_mosi        => reg_dp_shiftram_mosi,
+    reg_dp_shiftram_miso        => reg_dp_shiftram_miso,
+    reg_bsn_source_mosi         => reg_bsn_source_mosi,
+    reg_bsn_source_miso         => reg_bsn_source_miso,
+    reg_bsn_scheduler_wg_mosi   => reg_bsn_scheduler_wg_mosi,
+    reg_bsn_scheduler_wg_miso   => reg_bsn_scheduler_wg_miso,
+    reg_wg_mosi                 => reg_wg_mosi,
+    reg_wg_miso                 => reg_wg_miso,
+    ram_wg_mosi                 => ram_wg_mosi,
+    ram_wg_miso                 => ram_wg_miso,
+    reg_bsn_monitor_input_mosi  => reg_bsn_monitor_input_mosi,
+    reg_bsn_monitor_input_miso  => reg_bsn_monitor_input_miso,
+    ram_diag_data_buf_jesd_mosi => ram_diag_data_buf_jesd_mosi,
+    ram_diag_data_buf_jesd_miso => ram_diag_data_buf_jesd_miso,
+    reg_diag_data_buf_jesd_mosi => reg_diag_data_buf_jesd_mosi,
+    reg_diag_data_buf_jesd_miso => reg_diag_data_buf_jesd_miso,
+    ram_diag_data_buf_bsn_mosi  => ram_diag_data_buf_bsn_mosi,
+    ram_diag_data_buf_bsn_miso  => ram_diag_data_buf_bsn_miso,
+    reg_diag_data_buf_bsn_mosi  => reg_diag_data_buf_bsn_mosi,
+    reg_diag_data_buf_bsn_miso  => reg_diag_data_buf_bsn_miso,
+    ram_aduh_monitor_mosi       => ram_aduh_monitor_mosi,
+    ram_aduh_monitor_miso       => ram_aduh_monitor_miso,
+    reg_aduh_monitor_mosi       => reg_aduh_monitor_mosi,
+    reg_aduh_monitor_miso       => reg_aduh_monitor_miso,
   
-  gen_mux : FOR I IN 0 TO c_nof_streams_input-1 GENERATE
-    p_sosi : PROCESS(jesd204b_rx_src_out_arr, wg_sosi_arr)
-    BEGIN
-      -- Valid is forced to '1' here for dp_shiftram.
-      nxt_mux_sosi_arr(I).valid <= '1';
-
-      -- Default use the ADUH data
-      nxt_mux_sosi_arr(I).data  <= jesd204b_rx_src_out_arr(I).data;
-      IF wg_sosi_arr(I).valid='1' THEN
-        -- Valid WG data overrules ADUH data
-        nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
-      END IF;
-    END PROCESS;
-  END GENERATE;
-
-  p_reg_mux : PROCESS(st_rst, jesd204b_frame_clk)
-  BEGIN
-    IF st_rst='1' THEN
-      mux_sosi_arr  <= (OTHERS=>c_dp_sosi_rst);
-    ELSIF rising_edge(jesd204b_frame_clk) THEN
-      mux_sosi_arr  <= nxt_mux_sosi_arr;
-    END IF;
-  END PROCESS;
-
-
-  ---------------------------------------------------------------------------------------
-  -- BSN monitor (Block Checker)
-  ---------------------------------------------------------------------------------------
-  u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
-  GENERIC MAP (
-    g_nof_streams        => c_nof_streams_jesd204b,
-    g_sync_timeout       => c_bsn_sync_timeout,
-    g_bsn_w              => 51, --c_apertif_bsn_w,
-    g_log_first_bsn      => FALSE
-  )
-  PORT MAP (
-    -- Memory-mapped clock domain
-    mm_rst      => mm_rst,
-    mm_clk      => mm_clk,
-    reg_mosi    => reg_bsn_monitor_input_mosi,
-    reg_miso    => reg_bsn_monitor_input_miso,
-
-    -- Streaming clock domain
-    dp_rst      => dp_rst,
-    dp_clk      => dp_clk,
-    in_siso_arr => (OTHERS=>c_dp_siso_rdy),
-    in_sosi_arr => bsn_sosi_arr
+     -- Jesd external IOs
+    jesd204b_serial_data       => JESD204B_SERIAL_DATA,
+    jesd204b_refclk            => JESD204B_REFCLK,   
+    jesd204b_sysref            => JESD204B_SYSREF,   
+    jesd204b_sync_n            => JESD204B_SYNC_N,   
+ 
+    -- Streaming data output
+    out_sosi_arr               => alt_sosi_arr        
   );
 
-  -- only connect the channels actually used
-
-  gen_bsn_monitor_inputs : FOR I IN 0 TO c_nof_streams_input-1 GENERATE
-    bsn_sosi_arr(I) <= mux_sosi_arr(I);
-  END GENERATE;
 
-END str;
+END str;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index 8607fd49d5cc643d3a5881d7b1e619bada432d5b..b4a3e724ac15b1dbb00e8375c1ae0e431b58153f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -103,21 +103,45 @@ ENTITY mmm_lofar2_unb2b_adc IS
     jesd204b_mosi            : OUT t_mem_mosi;
     jesd204b_miso            : IN  t_mem_miso;
 
+    -- Dp shiftram
+    reg_dp_shiftram_mosi     : OUT t_mem_mosi;
+    reg_dp_shiftram_miso     : IN  t_mem_miso;
+
+    -- Bsn source
+    reg_bsn_source_mosi      : OUT t_mem_mosi;
+    reg_bsn_source_miso      : IN  t_mem_miso;
+
+    -- bsn schduler for wg trigger
+    reg_bsn_scheduler_mosi   : OUT t_mem_mosi;
+    reg_bsn_scheduler_miso   : IN  t_mem_miso;
+
     -- BSN Monitor
     reg_bsn_monitor_input_mosi : OUT t_mem_mosi := c_mem_mosi_rst;
     reg_bsn_monitor_input_miso : IN  t_mem_miso := c_mem_miso_rst;
 
     -- MM wideband waveform generator registers [0,1,2,3] for signal paths [A,B,C,D]
-    reg_wg_mosi_arr               : OUT t_mem_mosi_arr(11 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);  
-    reg_wg_miso_arr               : IN  t_mem_miso_arr(11 DOWNTO 0);
-    ram_wg_mosi_arr               : OUT t_mem_mosi_arr(11 DOWNTO 0) := (OTHERS=>c_mem_mosi_rst);  
-    ram_wg_miso_arr               : IN  t_mem_miso_arr(11 DOWNTO 0);
+    reg_wg_mosi                   : OUT t_mem_mosi;  
+    reg_wg_miso                   : IN  t_mem_miso;
+    ram_wg_mosi                   : OUT t_mem_mosi;  
+    ram_wg_miso                   : IN  t_mem_miso;
     
     -- JESD databuffer
     ram_diag_data_buf_jesd_mosi   : OUT t_mem_mosi;
     ram_diag_data_buf_jesd_miso   : IN  t_mem_miso;
     reg_diag_data_buf_jesd_mosi   : OUT t_mem_mosi;
-    reg_diag_data_buf_jesd_miso   : IN  t_mem_miso
+    reg_diag_data_buf_jesd_miso   : IN  t_mem_miso;
+
+    -- Bsn databuffer
+    ram_diag_data_buf_bsn_mosi    : OUT t_mem_mosi;
+    ram_diag_data_buf_bsn_miso    : IN  t_mem_miso;
+    reg_diag_data_buf_bsn_mosi    : OUT t_mem_mosi;
+    reg_diag_data_buf_bsn_miso    : IN  t_mem_miso;
+
+    -- Aduh
+    ram_aduh_monitor_mosi         : OUT t_mem_mosi;
+    ram_aduh_monitor_miso         : IN  t_mem_miso;
+    reg_aduh_monitor_mosi         : OUT t_mem_mosi;
+    reg_aduh_monitor_miso         : IN  t_mem_miso
   );
 END mmm_lofar2_unb2b_adc;
 
@@ -293,198 +317,46 @@ BEGIN
       reg_bsn_monitor_input_write_export        => reg_bsn_monitor_input_mosi.wr,
       reg_bsn_monitor_input_writedata_export    => reg_bsn_monitor_input_mosi.wrdata(c_word_w-1 DOWNTO 0),
 
-      -- waveform generators, just use 4 of 12 instances for now
-      reg_wg_0_clk_export                       => OPEN,
-      reg_wg_0_reset_export                     => OPEN,
-      reg_wg_0_address_export                   => reg_wg_mosi_arr(0).address(1 DOWNTO 0),
-      reg_wg_0_read_export                      => reg_wg_mosi_arr(0).rd,
-      reg_wg_0_readdata_export                  => reg_wg_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
-      reg_wg_0_write_export                     => reg_wg_mosi_arr(0).wr,
-      reg_wg_0_writedata_export                 => reg_wg_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-
-      reg_wg_1_clk_export                       => OPEN,
-      reg_wg_1_reset_export                     => OPEN,
-      reg_wg_1_address_export                   => reg_wg_mosi_arr(1).address(1 DOWNTO 0),
-      reg_wg_1_read_export                      => reg_wg_mosi_arr(1).rd,
-      reg_wg_1_readdata_export                  => reg_wg_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
-      reg_wg_1_write_export                     => reg_wg_mosi_arr(1).wr,
-      reg_wg_1_writedata_export                 => reg_wg_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-
-      reg_wg_2_clk_export                       => OPEN,
-      reg_wg_2_reset_export                     => OPEN,
-      reg_wg_2_address_export                   => reg_wg_mosi_arr(2).address(1 DOWNTO 0),
-      reg_wg_2_read_export                      => reg_wg_mosi_arr(2).rd,
-      reg_wg_2_readdata_export                  => reg_wg_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
-      reg_wg_2_write_export                     => reg_wg_mosi_arr(2).wr,
-      reg_wg_2_writedata_export                 => reg_wg_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
-
-      reg_wg_3_clk_export                       => OPEN,
-      reg_wg_3_reset_export                     => OPEN,
-      reg_wg_3_address_export                   => reg_wg_mosi_arr(3).address(1 DOWNTO 0),
-      reg_wg_3_read_export                      => reg_wg_mosi_arr(3).rd,
-      reg_wg_3_readdata_export                  => reg_wg_miso_arr(3).rddata(c_word_w-1 DOWNTO 0),
-      reg_wg_3_write_export                     => reg_wg_mosi_arr(3).wr,
-      reg_wg_3_writedata_export                 => reg_wg_mosi_arr(3).wrdata(c_word_w-1 DOWNTO 0),
-
-      --reg_wg_4_clk_export                       => OPEN,
-      --reg_wg_4_reset_export                     => OPEN,
-      --reg_wg_4_address_export                   => reg_wg_mosi_arr(4).address(1 DOWNTO 0),
-      --reg_wg_4_read_export                      => reg_wg_mosi_arr(4).rd,
-      --reg_wg_4_readdata_export                  => reg_wg_miso_arr(4).rddata(c_word_w-1 DOWNTO 0),
-      --reg_wg_4_write_export                     => reg_wg_mosi_arr(4).wr,
-      --reg_wg_4_writedata_export                 => reg_wg_mosi_arr(4).wrdata(c_word_w-1 DOWNTO 0),
-
-      --reg_wg_5_clk_export                       => OPEN,
-      --reg_wg_5_reset_export                     => OPEN,
-      --reg_wg_5_address_export                   => reg_wg_mosi_arr(5).address(1 DOWNTO 0),
-      --reg_wg_5_read_export                      => reg_wg_mosi_arr(5).rd,
-      --reg_wg_5_readdata_export                  => reg_wg_miso_arr(5).rddata(c_word_w-1 DOWNTO 0),
-      --reg_wg_5_write_export                     => reg_wg_mosi_arr(5).wr,
-      --reg_wg_5_writedata_export                 => reg_wg_mosi_arr(5).wrdata(c_word_w-1 DOWNTO 0),
-
-      --reg_wg_6_clk_export                       => OPEN,
-      --reg_wg_6_reset_export                     => OPEN,
-      --reg_wg_6_address_export                   => reg_wg_mosi_arr(6).address(1 DOWNTO 0),
-      --reg_wg_6_read_export                      => reg_wg_mosi_arr(6).rd,
-      --reg_wg_6_readdata_export                  => reg_wg_miso_arr(6).rddata(c_word_w-1 DOWNTO 0),
-      --reg_wg_6_write_export                     => reg_wg_mosi_arr(6).wr,
-      --reg_wg_6_writedata_export                 => reg_wg_mosi_arr(6).wrdata(c_word_w-1 DOWNTO 0),
-
-      --reg_wg_7_clk_export                       => OPEN,
-      --reg_wg_7_reset_export                     => OPEN,
-      --reg_wg_7_address_export                   => reg_wg_mosi_arr(7).address(1 DOWNTO 0),
-      --reg_wg_7_read_export                      => reg_wg_mosi_arr(7).rd,
-      --reg_wg_7_readdata_export                  => reg_wg_miso_arr(7).rddata(c_word_w-1 DOWNTO 0),
-      --reg_wg_7_write_export                     => reg_wg_mosi_arr(7).wr,
-      --reg_wg_7_writedata_export                 => reg_wg_mosi_arr(7).wrdata(c_word_w-1 DOWNTO 0),
-
-      --reg_wg_8_clk_export                       => OPEN,
-      --reg_wg_8_reset_export                     => OPEN,
-      --reg_wg_8_address_export                   => reg_wg_mosi_arr(8).address(1 DOWNTO 0),
-      --reg_wg_8_read_export                      => reg_wg_mosi_arr(8).rd,
-      --reg_wg_8_readdata_export                  => reg_wg_miso_arr(8).rddata(c_word_w-1 DOWNTO 0),
-      --reg_wg_8_write_export                     => reg_wg_mosi_arr(8).wr,
-      --reg_wg_8_writedata_export                 => reg_wg_mosi_arr(8).wrdata(c_word_w-1 DOWNTO 0),
-
-      --reg_wg_9_clk_export                       => OPEN,
-      --reg_wg_9_reset_export                     => OPEN,
-      --reg_wg_9_address_export                   => reg_wg_mosi_arr(9).address(1 DOWNTO 0),
-      --reg_wg_9_read_export                      => reg_wg_mosi_arr(9).rd,
-      --reg_wg_9_readdata_export                  => reg_wg_miso_arr(9).rddata(c_word_w-1 DOWNTO 0),
-      --reg_wg_9_write_export                     => reg_wg_mosi_arr(9).wr,
-      --reg_wg_9_writedata_export                 => reg_wg_mosi_arr(9).wrdata(c_word_w-1 DOWNTO 0),
-
-      --reg_wg_10_clk_export                       => OPEN,
-      --reg_wg_10_reset_export                     => OPEN,
-      --reg_wg_10_address_export                   => reg_wg_mosi_arr(10).address(1 DOWNTO 0),
-      --reg_wg_10_read_export                      => reg_wg_mosi_arr(10).rd,
-      --reg_wg_10_readdata_export                  => reg_wg_miso_arr(10).rddata(c_word_w-1 DOWNTO 0),
-      --reg_wg_10_write_export                     => reg_wg_mosi_arr(10).wr,
-      --reg_wg_10_writedata_export                 => reg_wg_mosi_arr(10).wrdata(c_word_w-1 DOWNTO 0),
-
-      --reg_wg_11_clk_export                       => OPEN,
-      --reg_wg_11_reset_export                     => OPEN,
-      --reg_wg_11_address_export                   => reg_wg_mosi_arr(11).address(1 DOWNTO 0),
-      --reg_wg_11_read_export                      => reg_wg_mosi_arr(11).rd,
-      --reg_wg_11_readdata_export                  => reg_wg_miso_arr(11).rddata(c_word_w-1 DOWNTO 0),
-      --reg_wg_11_write_export                     => reg_wg_mosi_arr(11).wr,
-      --reg_wg_11_writedata_export                 => reg_wg_mosi_arr(11).wrdata(c_word_w-1 DOWNTO 0),
-
-      ram_wg_0_clk_export                       => OPEN,
-      ram_wg_0_reset_export                     => OPEN,
-      ram_wg_0_address_export                   => ram_wg_mosi_arr(0).address(9 DOWNTO 0),
-      ram_wg_0_read_export                      => ram_wg_mosi_arr(0).rd,
-      ram_wg_0_readdata_export                  => ram_wg_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
-      ram_wg_0_write_export                     => ram_wg_mosi_arr(0).wr,
-      ram_wg_0_writedata_export                 => ram_wg_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-
-      ram_wg_1_clk_export                       => OPEN,
-      ram_wg_1_reset_export                     => OPEN,
-      ram_wg_1_address_export                   => ram_wg_mosi_arr(1).address(9 DOWNTO 0),
-      ram_wg_1_read_export                      => ram_wg_mosi_arr(1).rd,
-      ram_wg_1_readdata_export                  => ram_wg_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
-      ram_wg_1_write_export                     => ram_wg_mosi_arr(1).wr,
-      ram_wg_1_writedata_export                 => ram_wg_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-
-      ram_wg_2_clk_export                       => OPEN,
-      ram_wg_2_reset_export                     => OPEN,
-      ram_wg_2_address_export                   => ram_wg_mosi_arr(2).address(9 DOWNTO 0),
-      ram_wg_2_read_export                      => ram_wg_mosi_arr(2).rd,
-      ram_wg_2_readdata_export                  => ram_wg_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
-      ram_wg_2_write_export                     => ram_wg_mosi_arr(2).wr,
-      ram_wg_2_writedata_export                 => ram_wg_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
-
-      ram_wg_3_clk_export                       => OPEN,
-      ram_wg_3_reset_export                     => OPEN,
-      ram_wg_3_address_export                   => ram_wg_mosi_arr(3).address(9 DOWNTO 0),
-      ram_wg_3_read_export                      => ram_wg_mosi_arr(3).rd,
-      ram_wg_3_readdata_export                  => ram_wg_miso_arr(3).rddata(c_word_w-1 DOWNTO 0),
-      ram_wg_3_write_export                     => ram_wg_mosi_arr(3).wr,
-      ram_wg_3_writedata_export                 => ram_wg_mosi_arr(3).wrdata(c_word_w-1 DOWNTO 0),
-
-      --ram_wg_4_clk_export                       => OPEN,
-      --ram_wg_4_reset_export                     => OPEN,
-      --ram_wg_4_address_export                   => ram_wg_mosi_arr(4).address(9 DOWNTO 0),
-      --ram_wg_4_read_export                      => ram_wg_mosi_arr(4).rd,
-      --ram_wg_4_readdata_export                  => ram_wg_miso_arr(4).rddata(c_word_w-1 DOWNTO 0),
-      --ram_wg_4_write_export                     => ram_wg_mosi_arr(4).wr,
-      --ram_wg_4_writedata_export                 => ram_wg_mosi_arr(4).wrdata(c_word_w-1 DOWNTO 0),
-
-      --ram_wg_5_clk_export                       => OPEN,
-      --ram_wg_5_reset_export                     => OPEN,
-      --ram_wg_5_address_export                   => ram_wg_mosi_arr(5).address(9 DOWNTO 0),
-      --ram_wg_5_read_export                      => ram_wg_mosi_arr(5).rd,
-      --ram_wg_5_readdata_export                  => ram_wg_miso_arr(5).rddata(c_word_w-1 DOWNTO 0),
-      --ram_wg_5_write_export                     => ram_wg_mosi_arr(5).wr,
-      --ram_wg_5_writedata_export                 => ram_wg_mosi_arr(5).wrdata(c_word_w-1 DOWNTO 0),
-
-      --ram_wg_6_clk_export                       => OPEN,
-      --ram_wg_6_reset_export                     => OPEN,
-      --ram_wg_6_address_export                   => ram_wg_mosi_arr(6).address(9 DOWNTO 0),
-      --ram_wg_6_read_export                      => ram_wg_mosi_arr(6).rd,
-      --ram_wg_6_readdata_export                  => ram_wg_miso_arr(6).rddata(c_word_w-1 DOWNTO 0),
-      --ram_wg_6_write_export                     => ram_wg_mosi_arr(6).wr,
-      --ram_wg_6_writedata_export                 => ram_wg_mosi_arr(6).wrdata(c_word_w-1 DOWNTO 0),
-
-      --ram_wg_7_clk_export                       => OPEN,
-      --ram_wg_7_reset_export                     => OPEN,
-      --ram_wg_7_address_export                   => ram_wg_mosi_arr(7).address(9 DOWNTO 0),
-      --ram_wg_7_read_export                      => ram_wg_mosi_arr(7).rd,
-      --ram_wg_7_readdata_export                  => ram_wg_miso_arr(7).rddata(c_word_w-1 DOWNTO 0),
-      --ram_wg_7_write_export                     => ram_wg_mosi_arr(7).wr,
-      --ram_wg_7_writedata_export                 => ram_wg_mosi_arr(7).wrdata(c_word_w-1 DOWNTO 0),
-
-      --ram_wg_8_clk_export                       => OPEN,
-      --ram_wg_8_reset_export                     => OPEN,
-      --ram_wg_8_address_export                   => ram_wg_mosi_arr(8).address(9 DOWNTO 0),
-      --ram_wg_8_read_export                      => ram_wg_mosi_arr(8).rd,
-      --ram_wg_8_readdata_export                  => ram_wg_miso_arr(8).rddata(c_word_w-1 DOWNTO 0),
-      --ram_wg_8_write_export                     => ram_wg_mosi_arr(8).wr,
-      --ram_wg_8_writedata_export                 => ram_wg_mosi_arr(8).wrdata(c_word_w-1 DOWNTO 0),
-
-      --ram_wg_9_clk_export                       => OPEN,
-      --ram_wg_9_reset_export                     => OPEN,
-      --ram_wg_9_address_export                   => ram_wg_mosi_arr(9).address(9 DOWNTO 0),
-      --ram_wg_9_read_export                      => ram_wg_mosi_arr(9).rd,
-      --ram_wg_9_readdata_export                  => ram_wg_miso_arr(9).rddata(c_word_w-1 DOWNTO 0),
-      --ram_wg_9_write_export                     => ram_wg_mosi_arr(9).wr,
-      --ram_wg_9_writedata_export                 => ram_wg_mosi_arr(9).wrdata(c_word_w-1 DOWNTO 0),
-
-      --ram_wg_10_clk_export                       => OPEN,
-      --ram_wg_10_reset_export                     => OPEN,
-      --ram_wg_10_address_export                   => ram_wg_mosi_arr(10).address(9 DOWNTO 0),
-      --ram_wg_10_read_export                      => ram_wg_mosi_arr(10).rd,
-      --ram_wg_10_readdata_export                  => ram_wg_miso_arr(10).rddata(c_word_w-1 DOWNTO 0),
-      --ram_wg_10_write_export                     => ram_wg_mosi_arr(10).wr,
-      --ram_wg_10_writedata_export                 => ram_wg_mosi_arr(10).wrdata(c_word_w-1 DOWNTO 0),
-
-      --ram_wg_11_clk_export                       => OPEN,
-      --ram_wg_11_reset_export                     => OPEN,
-      --ram_wg_11_address_export                   => ram_wg_mosi_arr(11).address(9 DOWNTO 0),
-      --ram_wg_11_read_export                      => ram_wg_mosi_arr(11).rd,
-      --ram_wg_11_readdata_export                  => ram_wg_miso_arr(11).rddata(c_word_w-1 DOWNTO 0),
-      --ram_wg_11_write_export                     => ram_wg_mosi_arr(11).wr,
-      --ram_wg_11_writedata_export                 => ram_wg_mosi_arr(11).wrdata(c_word_w-1 DOWNTO 0),
+      -- waveform generators (multiplexed)
+      reg_wg_clk_export                         => OPEN,
+      reg_wg_reset_export                       => OPEN,
+      reg_wg_address_export                     => reg_wg_mosi.address(5 DOWNTO 0),
+      reg_wg_read_export                        => reg_wg_mosi.rd,
+      reg_wg_readdata_export                    => reg_wg_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_wg_write_export                       => reg_wg_mosi.wr,
+      reg_wg_writedata_export                   => reg_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      ram_wg_clk_export                         => OPEN,
+      ram_wg_reset_export                       => OPEN,
+      ram_wg_address_export                     => ram_wg_mosi.address(13 DOWNTO 0),
+      ram_wg_read_export                        => ram_wg_mosi.rd,
+      ram_wg_readdata_export                    => ram_wg_miso.rddata(c_word_w-1 DOWNTO 0),
+      ram_wg_write_export                       => ram_wg_mosi.wr,
+      ram_wg_writedata_export                   => ram_wg_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_dp_shiftram_clk_export                => OPEN,
+      reg_dp_shiftram_reset_export              => OPEN,
+      reg_dp_shiftram_address_export            => reg_dp_shiftram_mosi.address(2 DOWNTO 0),
+      reg_dp_shiftram_read_export               => reg_dp_shiftram_mosi.rd,
+      reg_dp_shiftram_readdata_export           => reg_dp_shiftram_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_dp_shiftram_write_export              => reg_dp_shiftram_mosi.wr,
+      reg_dp_shiftram_writedata_export          => reg_dp_shiftram_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_bsn_source_clk_export                 => OPEN,
+      reg_bsn_source_reset_export               => OPEN,
+      reg_bsn_source_address_export             => reg_bsn_source_mosi.address(1 DOWNTO 0),
+      reg_bsn_source_read_export                => reg_bsn_source_mosi.rd,
+      reg_bsn_source_readdata_export            => reg_bsn_source_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_bsn_source_write_export               => reg_bsn_source_mosi.wr,
+      reg_bsn_source_writedata_export           => reg_bsn_source_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+      reg_bsn_scheduler_clk_export              => OPEN,
+      reg_bsn_scheduler_reset_export            => OPEN,
+      reg_bsn_scheduler_address_export          => reg_bsn_scheduler_mosi.address(0 DOWNTO 0),
+      reg_bsn_scheduler_read_export             => reg_bsn_scheduler_mosi.rd,
+      reg_bsn_scheduler_readdata_export         => reg_bsn_scheduler_miso.rddata(c_word_w-1 DOWNTO 0),
+      reg_bsn_scheduler_write_export            => reg_bsn_scheduler_mosi.wr,
+      reg_bsn_scheduler_writedata_export        => reg_bsn_scheduler_mosi.wrdata(c_word_w-1 DOWNTO 0),
 
       reg_epcs_reset_export                     => OPEN,
       reg_epcs_clk_export                       => OPEN,
@@ -527,9 +399,25 @@ BEGIN
       reg_mmdp_ctrl_writedata_export            => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
 
 
+      ram_diag_data_buf_bsn_clk_export          => OPEN,
+      ram_diag_data_buf_bsn_reset_export        => OPEN,
+      ram_diag_data_buf_bsn_address_export      => ram_diag_data_buf_bsn_mosi.address(16-1 DOWNTO 0),
+      ram_diag_data_buf_bsn_write_export        => ram_diag_data_buf_bsn_mosi.wr,
+      ram_diag_data_buf_bsn_writedata_export    => ram_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      ram_diag_data_buf_bsn_read_export         => ram_diag_data_buf_bsn_mosi.rd,
+      ram_diag_data_buf_bsn_readdata_export     => ram_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_diag_data_buf_bsn_reset_export        => OPEN,
+      reg_diag_data_buf_bsn_clk_export          => OPEN,
+      reg_diag_data_buf_bsn_address_export      => reg_diag_data_buf_bsn_mosi.address(12-1 DOWNTO 0),
+      reg_diag_data_buf_bsn_write_export        => reg_diag_data_buf_bsn_mosi.wr,
+      reg_diag_data_buf_bsn_writedata_export    => reg_diag_data_buf_bsn_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_diag_data_buf_bsn_read_export         => reg_diag_data_buf_bsn_mosi.rd,
+      reg_diag_data_buf_bsn_readdata_export     => reg_diag_data_buf_bsn_miso.rddata(c_word_w-1 DOWNTO 0),
+
       ram_diag_data_buf_jesd_clk_export         => OPEN,
       ram_diag_data_buf_jesd_reset_export       => OPEN,
-      ram_diag_data_buf_jesd_address_export     => ram_diag_data_buf_jesd_mosi.address(17-1 DOWNTO 0),
+      ram_diag_data_buf_jesd_address_export     => ram_diag_data_buf_jesd_mosi.address(16-1 DOWNTO 0),
       ram_diag_data_buf_jesd_write_export       => ram_diag_data_buf_jesd_mosi.wr,
       ram_diag_data_buf_jesd_writedata_export   => ram_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
       ram_diag_data_buf_jesd_read_export        => ram_diag_data_buf_jesd_mosi.rd,
@@ -541,7 +429,23 @@ BEGIN
       reg_diag_data_buf_jesd_write_export       => reg_diag_data_buf_jesd_mosi.wr,
       reg_diag_data_buf_jesd_writedata_export   => reg_diag_data_buf_jesd_mosi.wrdata(c_word_w-1 DOWNTO 0),
       reg_diag_data_buf_jesd_read_export        => reg_diag_data_buf_jesd_mosi.rd,
-      reg_diag_data_buf_jesd_readdata_export    => reg_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0)
+      reg_diag_data_buf_jesd_readdata_export    => reg_diag_data_buf_jesd_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      ram_aduh_monitor_clk_export               => OPEN,
+      ram_aduh_monitor_reset_export             => OPEN,
+      ram_aduh_monitor_address_export           => ram_aduh_monitor_mosi.address(12-1 DOWNTO 0),
+      ram_aduh_monitor_write_export             => ram_aduh_monitor_mosi.wr,
+      ram_aduh_monitor_writedata_export         => ram_aduh_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      ram_aduh_monitor_read_export              => ram_aduh_monitor_mosi.rd,
+      ram_aduh_monitor_readdata_export          => ram_aduh_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
+
+      reg_aduh_monitor_reset_export             => OPEN,
+      reg_aduh_monitor_clk_export               => OPEN,
+      reg_aduh_monitor_address_export           => reg_aduh_monitor_mosi.address(6-1 DOWNTO 0),
+      reg_aduh_monitor_write_export             => reg_aduh_monitor_mosi.wr,
+      reg_aduh_monitor_writedata_export         => reg_aduh_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
+      reg_aduh_monitor_read_export              => reg_aduh_monitor_mosi.rd,
+      reg_aduh_monitor_readdata_export          => reg_aduh_monitor_miso.rddata(c_word_w-1 DOWNTO 0)
 
     );
   END GENERATE;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..507992a5f4c29227bd311adadf09341f11a30089
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -0,0 +1,513 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author : J Hargreaves
+-- Purpose:  
+--   AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
+-- Description:
+--   Unb2b version for lab testing
+--   Contains all the signal processing blocks to receive and time the ADC input data
+--   See https://support.astron.nl/confluence/display/STAT/L5+SDPFW+DD%3A+ADC+data+input+and+timestamp
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, diag_lib, aduh_lib, dp_lib, tech_jesd204b_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_peripherals_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.lofar2_unb2b_adc_pkg.ALL;
+
+ENTITY node_adc_input_and_timing IS
+  GENERIC (
+    g_technology              : NATURAL := c_tech_arria10_e1sg;
+    g_buf_nof_data            : NATURAL := 1024;
+    g_nof_streams             : NATURAL := 12;
+    g_nof_sync_n              : NATURAL := 4;          -- Three ADCs per RCU share a sync
+    g_aduh_buffer_nof_symbols : NATURAL := 512;        -- Default 512
+    g_bsn_sync_timeout        : NATURAL := 200000000;  -- Default 200M, overide for short simulation 
+    g_sim                     : BOOLEAN := FALSE  
+  );
+  PORT (
+    -- clocks and resets
+    mm_clk                         : IN STD_LOGIC;
+    mm_rst                         : IN STD_LOGIC;
+    dp_clk                         : IN STD_LOGIC;
+    dp_rst                         : IN STD_LOGIC;
+
+    -- mm control buses
+    -- JESD 
+    jesd204b_mosi                  : IN  t_mem_mosi := c_mem_mosi_rst;
+    jesd204b_miso                  : OUT t_mem_miso := c_mem_miso_rst; 
+ 
+    -- Shiftram (applies per-antenna delay)
+    reg_dp_shiftram_mosi           : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_dp_shiftram_miso           : OUT t_mem_miso := c_mem_miso_rst;
+
+    -- bsn source
+    reg_bsn_source_mosi            : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_bsn_source_miso            : OUT t_mem_miso := c_mem_miso_rst;
+
+    -- bsn scheduler
+    reg_bsn_scheduler_wg_mosi      : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_bsn_scheduler_wg_miso      : OUT t_mem_miso := c_mem_miso_rst;
+
+    -- WG
+    reg_wg_mosi                    : IN  t_mem_mosi := c_mem_mosi_rst;
+    reg_wg_miso                    : OUT t_mem_miso := c_mem_miso_rst;
+    ram_wg_mosi                    : IN  t_mem_mosi := c_mem_mosi_rst;
+    ram_wg_miso                    : OUT t_mem_miso := c_mem_miso_rst;
+
+    -- BSN MONITOR
+    reg_bsn_monitor_input_mosi     : IN  t_mem_mosi;
+    reg_bsn_monitor_input_miso     : OUT t_mem_miso;
+
+    -- Data buffer for raw samples
+    ram_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
+    ram_diag_data_buf_jesd_miso    : OUT t_mem_miso;
+    reg_diag_data_buf_jesd_mosi    : IN  t_mem_mosi;
+    reg_diag_data_buf_jesd_miso    : OUT t_mem_miso;
+
+    -- Data buffer for framed samples (variable depth)
+    ram_diag_data_buf_bsn_mosi     : IN  t_mem_mosi;
+    ram_diag_data_buf_bsn_miso     : OUT t_mem_miso;
+    reg_diag_data_buf_bsn_mosi     : IN  t_mem_mosi;
+    reg_diag_data_buf_bsn_miso     : OUT t_mem_miso;
+
+    -- Aduh (statistics) monitor
+    ram_aduh_monitor_mosi          : IN  t_mem_mosi;
+    ram_aduh_monitor_miso          : OUT t_mem_miso;
+    reg_aduh_monitor_mosi          : IN  t_mem_mosi;
+    reg_aduh_monitor_miso          : OUT t_mem_miso;
+
+    -- JESD io signals
+    jesd204b_serial_data           : IN    STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0); 
+    jesd204b_refclk                : IN    STD_LOGIC; 
+    jesd204b_sysref                : IN    STD_LOGIC;
+    jesd204b_sync_n                : OUT   STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w*c_unb2b_board_tr_jesd204b.nof_bus)-1 DOWNTO 0);
+
+    -- Streaming data output
+    out_sosi_arr                   : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)        
+
+  );
+END node_adc_input_and_timing;
+
+
+ARCHITECTURE str OF node_adc_input_and_timing IS
+
+  -- Firmware version x.y
+  CONSTANT c_fw_version             : t_unb2b_board_fw_version := (1, 1);
+  CONSTANT c_mm_clk_freq            : NATURAL := c_unb2b_board_mm_clk_freq_100M;
+  CONSTANT c_lofar2_sample_clk_freq : NATURAL := 200 * 10**6;  -- alternate 160MHz. TODO: Use to check PPS
+
+  CONSTANT c_nof_streams_jesd204b   : NATURAL := 12;     -- IP is set up for 12 streams
+  CONSTANT c_nof_streams_db         : NATURAL := 2;      -- Streams of raw samples to record in db 
+
+  -- Waveform Generator
+  CONSTANT c_wg_buf_directory       : STRING := "data/";
+  CONSTANT c_wg_buf_dat_w           : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_dat_w;
+  CONSTANT c_wg_buf_addr_w          : NATURAL := c_unb2b_board_peripherals_mm_reg_default.ram_diag_wg_adr_w;
+  SIGNAL wg_out_ovr                 : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL wg_out_val                 : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL wg_out_data                : STD_LOGIC_VECTOR(g_nof_streams*c_wg_buf_dat_w-1 DOWNTO 0);    
+  SIGNAL wg_out_sync                : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL trigger_wg                 : STD_LOGIC;
+
+  -- Frame parameters TBC
+  CONSTANT c_bs_bsn_w               : NATURAL := 64; --51;
+  CONSTANT c_bs_block_size          : NATURAL := 1024;
+  CONSTANT c_bs_nof_block_per_sync  : NATURAL := 390625;  -- generate a sync every 2s for testing
+  CONSTANT c_dp_shiftram_nof_samples: NATURAL := 4096;
+  CONSTANT c_data_w                 : NATURAL := 16;
+  CONSTANT c_dp_fifo_dc_size        : NATURAL := 64;
+ 
+ 
+  -- QSFP leds
+  SIGNAL qsfp_green_led_arr         : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+  SIGNAL qsfp_red_led_arr           : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+
+  -- JESD signals
+  SIGNAL rx_clk                     : STD_LOGIC; -- formerly jesd204b_frame_clk
+  SIGNAL rx_rst                     : STD_LOGIC; 
+  SIGNAL rx_sysref                  : STD_LOGIC; 
+
+  -- Sosis and sosi arrays
+  SIGNAL rx_sosi_arr                : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);         
+  SIGNAL dp_shiftram_snk_in_arr     : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);         
+  SIGNAL ant_sosi_arr               : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL diag_data_buf_snk_in_arr   : t_dp_sosi_arr(c_nof_streams_db-1 DOWNTO 0);
+  SIGNAL bs_sosi                    : t_dp_sosi;    
+  SIGNAL wg_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
+  SIGNAL mux_sosi_arr               : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);         
+  SIGNAL nxt_mux_sosi_arr           : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL st_sosi_arr                : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    
+
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- JESD204B IP (ADC Handler)
+  -----------------------------------------------------------------------------
+  
+  u_jesd204b: ENTITY tech_jesd204b_lib.tech_jesd204b 
+  GENERIC MAP(
+    g_sim                => g_sim,                
+    g_nof_streams        => c_nof_streams_jesd204b,
+    g_nof_sync_n         => g_nof_sync_n        
+  )
+  PORT MAP(
+    jesd204b_refclk      => JESD204B_REFCLK,   
+    jesd204b_sysref      => JESD204B_SYSREF,   
+    jesd204b_sync_n_arr  => jesd204b_sync_n,   
+  
+    rx_sosi_arr          => rx_sosi_arr,          
+    rx_clk               => rx_clk,          
+    rx_rst               => rx_rst,          
+    rx_sysref            => rx_sysref,          
+  
+    -- MM
+    mm_clk               => mm_clk,           
+    mm_rst               => mm_rst,           
+  
+    jesd204b_mosi        => jesd204b_mosi,         
+    jesd204b_miso        => jesd204b_miso,         
+  
+     -- Serial
+    serial_tx_arr        => open,
+    serial_rx_arr        => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b-1 downto 0)
+  );
+
+
+  gen_jesd_mon_in : FOR i IN 0 TO c_nof_streams_db-1 GENERATE
+    diag_data_buf_snk_in_arr(i).data(c_data_w-1 downto 0) <= rx_sosi_arr(i).data(c_data_w-1 downto 0);
+    diag_data_buf_snk_in_arr(i).valid <= rx_sosi_arr(i).valid;
+    diag_data_buf_snk_in_arr(i).sop   <= '0';
+    diag_data_buf_snk_in_arr(i).eop   <= '0';
+    diag_data_buf_snk_in_arr(i).err   <= (OTHERS=>'0');
+  END GENERATE;
+
+
+  -----------------------------------------------------------------------------
+  -- Diagnostic Data Buffer (Records 8192 raw ADC samples after the PPS)
+  --   ToDo: Remove this JESD DB when the second (BSN) data buffer is working correctly
+  -----------------------------------------------------------------------------
+
+  u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
+  GENERIC MAP (
+    g_technology   => g_technology,
+    g_nof_streams  => c_nof_streams_db,
+    g_data_w       => c_data_w,
+    g_buf_nof_data => 8192,
+    g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+  )
+  PORT MAP (
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    dp_rst            => rx_rst,
+    dp_clk            => rx_clk,
+
+    ram_data_buf_mosi => ram_diag_data_buf_jesd_mosi,
+    ram_data_buf_miso => ram_diag_data_buf_jesd_miso,
+    reg_data_buf_mosi => reg_diag_data_buf_jesd_mosi,
+    reg_data_buf_miso => reg_diag_data_buf_jesd_miso,
+
+    in_sosi_arr       => diag_data_buf_snk_in_arr,
+    in_sync           => rx_sysref
+  );
+
+  -----------------------------------------------------------------------------
+  -- Time delay: dp_shiftram
+  -- . copied from unb1_bn_capture_input (apertif)
+  --   Array range reversal is not done because everything is DOWNTO
+  -- . the input valid is always '1', even when there is no data 
+  -----------------------------------------------------------------------------
+  
+  gen_force_valid : FOR I IN 0 TO c_nof_streams_jesd204b-1 GENERATE
+    p_sosi : PROCESS(rx_sosi_arr)
+    BEGIN
+      dp_shiftram_snk_in_arr(I)       <= rx_sosi_arr(I);
+      dp_shiftram_snk_in_arr(I).valid <= '1';
+    END PROCESS;
+  END GENERATE;
+
+
+  u_dp_shiftram : ENTITY dp_lib.dp_shiftram
+  GENERIC MAP (
+    g_nof_streams => c_nof_streams_jesd204b, 
+    g_nof_words   => c_dp_shiftram_nof_samples,
+    g_data_w      => c_data_w, 
+    g_use_sync_in => TRUE
+  )
+  PORT MAP (
+    dp_rst   => rx_rst,
+    dp_clk   => rx_clk,
+
+    mm_rst   => mm_rst,
+    mm_clk   => mm_clk,
+
+    sync_in  => bs_sosi.sync,
+
+    reg_mosi => reg_dp_shiftram_mosi,
+    reg_miso => reg_dp_shiftram_miso,
+
+    snk_in_arr => dp_shiftram_snk_in_arr,
+
+    src_out_arr => ant_sosi_arr
+  );
+
+  -----------------------------------------------------------------------------
+  -- Timestamp
+  -----------------------------------------------------------------------------  
+  u_bsn_source : ENTITY dp_lib.mms_dp_bsn_source
+  GENERIC MAP (
+    g_cross_clock_domain     => TRUE,
+    g_block_size             => c_bs_block_size,
+    g_nof_block_per_sync     => c_bs_nof_block_per_sync,
+    g_bsn_w                  => c_bs_bsn_w
+  )
+  PORT MAP (
+    -- Clocks and reset
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    dp_rst            => rx_rst,
+    dp_clk            => rx_clk,
+    dp_pps            => rx_sysref,
+    
+    -- Memory-mapped clock domain
+    reg_mosi          => reg_bsn_source_mosi,
+    reg_miso          => reg_bsn_source_miso,
+    
+    -- Streaming clock domain
+    bs_sosi           => bs_sosi
+  );
+
+  u_bsn_trigger_wg : ENTITY dp_lib.mms_dp_bsn_scheduler
+  GENERIC MAP (
+    g_cross_clock_domain => TRUE,
+    g_bsn_w              => c_bs_bsn_w
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst      => mm_rst,
+    mm_clk      => mm_clk,
+
+    reg_mosi    => reg_bsn_scheduler_wg_mosi,
+    reg_miso    => reg_bsn_scheduler_wg_miso,
+
+    -- Streaming clock domain
+    dp_rst      => rx_rst,
+    dp_clk      => rx_clk,
+
+    snk_in      => bs_sosi,  -- only uses eop (= block sync), bsn[]
+    trigger_out => trigger_wg
+  );
+
+
+  -----------------------------------------------------------------------------
+  -- WG (Test Signal Generator)
+  -----------------------------------------------------------------------------
+
+  u_wg_arr : ENTITY diag_lib.mms_diag_wg_wideband_arr
+  GENERIC MAP (
+    g_nof_streams        => g_nof_streams, 
+    g_cross_clock_domain => TRUE,
+    g_buf_dir            => c_wg_buf_directory,
+
+    -- Wideband parameters
+    g_wideband_factor    => 1, 
+
+    -- Basic WG parameters, see diag_wg.vhd for their meaning
+    g_buf_dat_w          => c_wg_buf_dat_w,
+    g_buf_addr_w         => c_wg_buf_addr_w,
+    g_calc_support       => TRUE,
+    g_calc_gain_w        => 1,
+    g_calc_dat_w         => c_wg_buf_dat_w
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst              => mm_rst,
+    mm_clk              => mm_clk,
+
+    reg_mosi            => reg_wg_mosi,
+    reg_miso            => reg_wg_miso,
+
+    buf_mosi            => ram_wg_mosi,
+    buf_miso            => ram_wg_miso,
+
+    -- Streaming clock domain
+    st_rst              => rx_rst,
+    st_clk              => rx_clk,
+    st_restart          => trigger_wg,
+
+    out_sosi_arr        => wg_sosi_arr
+  );
+
+
+  -----------------------------------------------------------------------------
+  -- ADC/WG Mux (Input Select)
+  -----------------------------------------------------------------------------
+  
+  gen_mux : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    p_sosi : PROCESS(ant_sosi_arr(I), wg_sosi_arr(I))
+    BEGIN
+      -- Default use the ADC data
+      nxt_mux_sosi_arr(I).data  <= ant_sosi_arr(I).data;
+      IF wg_sosi_arr(I).valid='1' THEN
+        -- Valid WG data overrules ADC data
+        nxt_mux_sosi_arr(I).data <= wg_sosi_arr(I).data;
+      END IF;
+    END PROCESS;
+  END GENERATE;
+
+  mux_sosi_arr  <= nxt_mux_sosi_arr WHEN rising_edge(rx_clk);
+
+  -----------------------------------------------------------------------------
+  -- Concatenate muxed data streams with bsn framing
+  -----------------------------------------------------------------------------
+  
+  gen_concat : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    p_sosi : PROCESS(mux_sosi_arr(I), bs_sosi)
+    BEGIN
+      st_sosi_arr(I)       <= bs_sosi;
+      st_sosi_arr(I).data  <= mux_sosi_arr(I).data;
+    END PROCESS;
+  END GENERATE;
+
+
+  ---------------------------------------------------------------------------------------
+  -- Diagnostics on the bsn-framed data
+  --   . BSN Monitor (ToDo: can be removed as not part of the spec)
+  --   . Aduh monitor
+  --   . Data Buffer (variable depth from 1k-128k)
+  ---------------------------------------------------------------------------------------
+  
+
+  ---------------------------------------------------------------------------------------
+  -- BSN monitor (Block Checker)
+  ---------------------------------------------------------------------------------------
+  u_bsn_monitor : ENTITY dp_lib.mms_dp_bsn_monitor
+  GENERIC MAP (
+    g_nof_streams        => 1,  -- They're all the same
+    g_sync_timeout       => g_bsn_sync_timeout,
+    g_bsn_w              => c_bs_bsn_w,
+    g_log_first_bsn      => FALSE
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst      => mm_rst,
+    mm_clk      => mm_clk,
+    reg_mosi    => reg_bsn_monitor_input_mosi,
+    reg_miso    => reg_bsn_monitor_input_miso,
+
+    -- Streaming clock domain
+    dp_rst      => rx_rst,
+    dp_clk      => rx_clk,
+    in_sosi_arr => st_sosi_arr(0 downto 0)
+  );
+
+
+  -----------------------------------------------------------------------------
+  -- Monitor ADU/WG output
+  -----------------------------------------------------------------------------
+  u_aduh_monitor : ENTITY aduh_lib.mms_aduh_monitor_arr
+  GENERIC MAP (
+    g_cross_clock_domain   => TRUE,
+    g_nof_streams          => g_nof_streams,
+    g_symbol_w             => c_data_w,   --TBD 16?
+    g_nof_symbols_per_data => 1,          -- Wideband factor is 1          
+    g_nof_accumulations    => 200000512,  -- = 195313 blocks * 1024 samples
+    g_buffer_nof_symbols   => g_aduh_buffer_nof_symbols,  -- default 512, larger for full design
+    g_buffer_use_sync      => TRUE        -- True to capture all streams synchronously
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst         => mm_rst,
+    mm_clk         => mm_clk,
+
+    reg_mosi       => reg_aduh_monitor_mosi, -- read only access to the signal path data mean sum and power sum registers
+    reg_miso       => reg_aduh_monitor_miso,
+    buf_mosi       => ram_aduh_monitor_mosi, -- read and overwrite access to the signal path data buffers
+    buf_miso       => ram_aduh_monitor_miso,
+
+    -- Streaming clock domain
+    st_rst         => rx_rst,
+    st_clk         => rx_clk,
+
+    in_sosi_arr    => st_sosi_arr
+  );
+
+
+ -----------------------------------------------------------------------------
+-- Diagnostic Data Buffer
+  -----------------------------------------------------------------------------
+
+  u_diag_data_buffer_bsn : ENTITY diag_lib.mms_diag_data_buffer
+  GENERIC MAP (
+    g_technology   => g_technology,
+    g_nof_streams  => g_nof_streams,
+    g_data_w       => c_data_w,
+    g_buf_nof_data => g_buf_nof_data,
+    g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
+  )
+  PORT MAP (
+    mm_rst            => mm_rst,
+    mm_clk            => mm_clk,
+    dp_rst            => rx_rst,
+    dp_clk            => rx_clk,
+
+    ram_data_buf_mosi => ram_diag_data_buf_bsn_mosi,
+    ram_data_buf_miso => ram_diag_data_buf_bsn_miso,
+    reg_data_buf_mosi => reg_diag_data_buf_bsn_mosi,
+    reg_data_buf_miso => reg_diag_data_buf_bsn_miso,
+
+    in_sosi_arr       => st_sosi_arr,
+    in_sync           => st_sosi_arr(0).sync
+  );
+
+
+  -----------------------------------------------------------------------------
+  -- Output Stage
+  --   . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
+  -----------------------------------------------------------------------------
+ 
+  gen_dp_fifo_dc : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
+      GENERIC MAP (
+        g_data_w         => c_data_w,
+        g_use_empty      => FALSE, --TRUE,
+        g_use_ctrl       => TRUE,
+        g_use_sync       => TRUE,
+        g_use_bsn        => TRUE,
+        g_fifo_size      => c_dp_fifo_dc_size
+      )
+      PORT MAP (
+        wr_rst           => rx_rst,
+        wr_clk           => rx_clk,
+        rd_rst           => dp_rst,
+        rd_clk           => dp_clk,
+        snk_in           => st_sosi_arr(I),
+        src_out          => out_sosi_arr(I)
+      );
+  END GENERATE;
+
+END str;
\ No newline at end of file
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index 76d7e11b927096a8be0c75a5be7cb5845a51b216..be030d7be84c9b58540aa735df6ea56de91cb8a0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -65,174 +65,41 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
             reg_bsn_monitor_input_write_export                           : out std_logic;
             reg_bsn_monitor_input_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => '0');
             reg_bsn_monitor_input_read_export                            : out std_logic;
-            reg_wg_0_address_export                                      : out std_logic_vector(1 downto 0);
-            reg_wg_0_writedata_export                                    : out std_logic_vector(31 downto 0);
-            reg_wg_0_reset_export                                        : out std_logic;
-            reg_wg_0_clk_export                                          : out std_logic;
-            reg_wg_0_write_export                                        : out std_logic;
-            reg_wg_0_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            reg_wg_0_read_export                                         : out std_logic;
-            reg_wg_1_address_export                                      : out std_logic_vector(1 downto 0);
-            reg_wg_1_writedata_export                                    : out std_logic_vector(31 downto 0);
-            reg_wg_1_reset_export                                        : out std_logic;
-            reg_wg_1_clk_export                                          : out std_logic;
-            reg_wg_1_write_export                                        : out std_logic;
-            reg_wg_1_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            reg_wg_1_read_export                                         : out std_logic;
-            reg_wg_2_address_export                                      : out std_logic_vector(1 downto 0);
-            reg_wg_2_writedata_export                                    : out std_logic_vector(31 downto 0);
-            reg_wg_2_reset_export                                        : out std_logic;
-            reg_wg_2_clk_export                                          : out std_logic;
-            reg_wg_2_write_export                                        : out std_logic;
-            reg_wg_2_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            reg_wg_2_read_export                                         : out std_logic;
-            reg_wg_3_address_export                                      : out std_logic_vector(1 downto 0);
-            reg_wg_3_writedata_export                                    : out std_logic_vector(31 downto 0);
-            reg_wg_3_reset_export                                        : out std_logic;
-            reg_wg_3_clk_export                                          : out std_logic;
-            reg_wg_3_write_export                                        : out std_logic;
-            reg_wg_3_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            reg_wg_3_read_export                                         : out std_logic;
-            --reg_wg_4_address_export                                      : out std_logic_vector(1 downto 0);
-            --reg_wg_4_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --reg_wg_4_reset_export                                        : out std_logic;
-            --reg_wg_4_clk_export                                          : out std_logic;
-            --reg_wg_4_write_export                                        : out std_logic;
-            --reg_wg_4_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --reg_wg_4_read_export                                         : out std_logic;
-            --reg_wg_5_address_export                                      : out std_logic_vector(1 downto 0);
-            --reg_wg_5_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --reg_wg_5_reset_export                                        : out std_logic;
-            --reg_wg_5_clk_export                                          : out std_logic;
-            --reg_wg_5_write_export                                        : out std_logic;
-            --reg_wg_5_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --reg_wg_5_read_export                                         : out std_logic;
-            --reg_wg_6_address_export                                      : out std_logic_vector(1 downto 0);
-            --reg_wg_6_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --reg_wg_6_reset_export                                        : out std_logic;
-            --reg_wg_6_clk_export                                          : out std_logic;
-            --reg_wg_6_write_export                                        : out std_logic;
-            --reg_wg_6_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --reg_wg_6_read_export                                         : out std_logic;
-            --reg_wg_7_address_export                                      : out std_logic_vector(1 downto 0);
-            --reg_wg_7_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --reg_wg_7_reset_export                                        : out std_logic;
-            --reg_wg_7_clk_export                                          : out std_logic;
-            --reg_wg_7_write_export                                        : out std_logic;
-            --reg_wg_7_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --reg_wg_7_read_export                                         : out std_logic;
-            --reg_wg_8_address_export                                      : out std_logic_vector(1 downto 0);
-            --reg_wg_8_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --reg_wg_8_reset_export                                        : out std_logic;
-            --reg_wg_8_clk_export                                          : out std_logic;
-            --reg_wg_8_write_export                                        : out std_logic;
-            --reg_wg_8_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --reg_wg_8_read_export                                         : out std_logic;
-            --reg_wg_9_address_export                                      : out std_logic_vector(1 downto 0);
-            --reg_wg_9_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --reg_wg_9_reset_export                                        : out std_logic;
-            --reg_wg_9_clk_export                                          : out std_logic;
-            --reg_wg_9_write_export                                        : out std_logic;
-            --reg_wg_9_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --reg_wg_9_read_export                                         : out std_logic;
-            --reg_wg_10_address_export                                      : out std_logic_vector(1 downto 0);
-            --reg_wg_10_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --reg_wg_10_reset_export                                        : out std_logic;
-            --reg_wg_10_clk_export                                          : out std_logic;
-            --reg_wg_10_write_export                                        : out std_logic;
-            --reg_wg_10_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --reg_wg_10_read_export                                         : out std_logic;
-            --reg_wg_11_address_export                                      : out std_logic_vector(1 downto 0);
-            --reg_wg_11_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --reg_wg_11_reset_export                                        : out std_logic;
-            --reg_wg_11_clk_export                                          : out std_logic;
-            --reg_wg_11_write_export                                        : out std_logic;
-            --reg_wg_11_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --reg_wg_11_read_export                                         : out std_logic;
-            ram_wg_0_address_export                                      : out std_logic_vector(9 downto 0);
-            ram_wg_0_writedata_export                                    : out std_logic_vector(31 downto 0);
-            ram_wg_0_reset_export                                        : out std_logic;
-            ram_wg_0_clk_export                                          : out std_logic;
-            ram_wg_0_write_export                                        : out std_logic;
-            ram_wg_0_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            ram_wg_0_read_export                                         : out std_logic;
-            ram_wg_1_address_export                                      : out std_logic_vector(9 downto 0);
-            ram_wg_1_writedata_export                                    : out std_logic_vector(31 downto 0);
-            ram_wg_1_reset_export                                        : out std_logic;
-            ram_wg_1_clk_export                                          : out std_logic;
-            ram_wg_1_write_export                                        : out std_logic;
-            ram_wg_1_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            ram_wg_1_read_export                                         : out std_logic;
-            ram_wg_2_address_export                                      : out std_logic_vector(9 downto 0);
-            ram_wg_2_writedata_export                                    : out std_logic_vector(31 downto 0);
-            ram_wg_2_reset_export                                        : out std_logic;
-            ram_wg_2_clk_export                                          : out std_logic;
-            ram_wg_2_write_export                                        : out std_logic;
-            ram_wg_2_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            ram_wg_2_read_export                                         : out std_logic;
-            ram_wg_3_address_export                                      : out std_logic_vector(9 downto 0);
-            ram_wg_3_writedata_export                                    : out std_logic_vector(31 downto 0);
-            ram_wg_3_reset_export                                        : out std_logic;
-            ram_wg_3_clk_export                                          : out std_logic;
-            ram_wg_3_write_export                                        : out std_logic;
-            ram_wg_3_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            ram_wg_3_read_export                                         : out std_logic;
-            --ram_wg_4_address_export                                      : out std_logic_vector(9 downto 0);
-            --ram_wg_4_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --ram_wg_4_reset_export                                        : out std_logic;
-            --ram_wg_4_clk_export                                          : out std_logic;
-            --ram_wg_4_write_export                                        : out std_logic;
-            --ram_wg_4_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --ram_wg_4_read_export                                         : out std_logic;
-            --ram_wg_5_address_export                                      : out std_logic_vector(9 downto 0);
-            --ram_wg_5_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --ram_wg_5_reset_export                                        : out std_logic;
-            --ram_wg_5_clk_export                                          : out std_logic;
-            --ram_wg_5_write_export                                        : out std_logic;
-            --ram_wg_5_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --ram_wg_5_read_export                                         : out std_logic;
-            --ram_wg_6_address_export                                      : out std_logic_vector(9 downto 0);
-            --ram_wg_6_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --ram_wg_6_reset_export                                        : out std_logic;
-            --ram_wg_6_clk_export                                          : out std_logic;
-            --ram_wg_6_write_export                                        : out std_logic;
-            --ram_wg_6_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --ram_wg_6_read_export                                         : out std_logic;
-            --ram_wg_7_address_export                                      : out std_logic_vector(9 downto 0);
-            --ram_wg_7_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --ram_wg_7_reset_export                                        : out std_logic;
-            --ram_wg_7_clk_export                                          : out std_logic;
-            --ram_wg_7_write_export                                        : out std_logic;
-            --ram_wg_7_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --ram_wg_7_read_export                                         : out std_logic;
-            --ram_wg_8_address_export                                      : out std_logic_vector(9 downto 0);
-            --ram_wg_8_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --ram_wg_8_reset_export                                        : out std_logic;
-            --ram_wg_8_clk_export                                          : out std_logic;
-            --ram_wg_8_write_export                                        : out std_logic;
-            --ram_wg_8_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --ram_wg_8_read_export                                         : out std_logic;
-            --ram_wg_9_address_export                                      : out std_logic_vector(9 downto 0);
-            --ram_wg_9_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --ram_wg_9_reset_export                                        : out std_logic;
-            --ram_wg_9_clk_export                                          : out std_logic;
-            --ram_wg_9_write_export                                        : out std_logic;
-            --ram_wg_9_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --ram_wg_9_read_export                                         : out std_logic;
-            --ram_wg_10_address_export                                      : out std_logic_vector(9 downto 0);
-            --ram_wg_10_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --ram_wg_10_reset_export                                        : out std_logic;
-            --ram_wg_10_clk_export                                          : out std_logic;
-            --ram_wg_10_write_export                                        : out std_logic;
-            --ram_wg_10_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --ram_wg_10_read_export                                         : out std_logic;
-            --ram_wg_11_address_export                                      : out std_logic_vector(1 downto 0);
-            --ram_wg_11_writedata_export                                    : out std_logic_vector(31 downto 0);
-            --ram_wg_11_reset_export                                        : out std_logic;
-            --ram_wg_11_clk_export                                          : out std_logic;
-            --ram_wg_11_write_export                                        : out std_logic;
-            --ram_wg_11_readdata_export                                     : in  std_logic_vector(31 downto 0) := (others => '0');
-            --ram_wg_11_read_export                                         : out std_logic;
+            reg_wg_address_export                                        : out std_logic_vector(5 downto 0);
+            reg_wg_writedata_export                                      : out std_logic_vector(31 downto 0);
+            reg_wg_reset_export                                          : out std_logic;
+            reg_wg_clk_export                                            : out std_logic;
+            reg_wg_write_export                                          : out std_logic;
+            reg_wg_readdata_export                                       : in  std_logic_vector(31 downto 0) := (others => '0');
+            reg_wg_read_export                                           : out std_logic;
+            ram_wg_address_export                                        : out std_logic_vector(13 downto 0);
+            ram_wg_writedata_export                                      : out std_logic_vector(31 downto 0);
+            ram_wg_reset_export                                          : out std_logic;
+            ram_wg_clk_export                                            : out std_logic;
+            ram_wg_write_export                                          : out std_logic;
+            ram_wg_readdata_export                                       : in  std_logic_vector(31 downto 0) := (others => '0');
+            ram_wg_read_export                                           : out std_logic;
+            reg_dp_shiftram_address_export                               : out std_logic_vector(2 downto 0);
+            reg_dp_shiftram_writedata_export                             : out std_logic_vector(31 downto 0);
+            reg_dp_shiftram_reset_export                                 : out std_logic;
+            reg_dp_shiftram_clk_export                                   : out std_logic;
+            reg_dp_shiftram_write_export                                 : out std_logic;
+            reg_dp_shiftram_readdata_export                              : in  std_logic_vector(31 downto 0) := (others => '0');
+            reg_dp_shiftram_read_export                                  : out std_logic;
+            reg_bsn_source_address_export                                : out std_logic_vector(1 downto 0);
+            reg_bsn_source_writedata_export                              : out std_logic_vector(31 downto 0);
+            reg_bsn_source_reset_export                                  : out std_logic;
+            reg_bsn_source_clk_export                                    : out std_logic;
+            reg_bsn_source_write_export                                  : out std_logic;
+            reg_bsn_source_readdata_export                               : in  std_logic_vector(31 downto 0) := (others => '0');
+            reg_bsn_source_read_export                                   : out std_logic;
+            reg_bsn_scheduler_address_export                             : out std_logic_vector(0 downto 0);
+            reg_bsn_scheduler_writedata_export                           : out std_logic_vector(31 downto 0);
+            reg_bsn_scheduler_reset_export                               : out std_logic;
+            reg_bsn_scheduler_clk_export                                 : out std_logic;
+            reg_bsn_scheduler_write_export                               : out std_logic;
+            reg_bsn_scheduler_readdata_export                            : in  std_logic_vector(31 downto 0) := (others => '0');
+            reg_bsn_scheduler_read_export                                : out std_logic;
             pio_pps_address_export                                       : out std_logic_vector(0 downto 0);                     -- export
             pio_pps_clk_export                                           : out std_logic;                                        -- export
             pio_pps_read_export                                          : out std_logic;                                        -- export
@@ -333,7 +200,7 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
             rom_system_info_reset_export                                 : out std_logic;                                        -- export
             rom_system_info_write_export                                 : out std_logic;                                        -- export
             rom_system_info_writedata_export                             : out std_logic_vector(31 downto 0);                     -- export
-            ram_diag_data_buf_jesd_address_export                        : out std_logic_vector(16 downto 0);                    -- export
+            ram_diag_data_buf_jesd_address_export                        : out std_logic_vector(15 downto 0);                    -- export
             ram_diag_data_buf_jesd_clk_export                            : out std_logic;                                        -- export
             ram_diag_data_buf_jesd_read_export                           : out std_logic;                                        -- export
             ram_diag_data_buf_jesd_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
@@ -346,7 +213,35 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
             reg_diag_data_buf_jesd_readdata_export                       : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
             reg_diag_data_buf_jesd_reset_export                          : out std_logic;                                        -- export
             reg_diag_data_buf_jesd_write_export                          : out std_logic;                                        -- export
-            reg_diag_data_buf_jesd_writedata_export                      : out std_logic_vector(31 downto 0)                    -- export
+            reg_diag_data_buf_jesd_writedata_export                      : out std_logic_vector(31 downto 0);                    -- export
+            ram_aduh_monitor_address_export                              : out std_logic_vector(11 downto 0);                    -- export
+            ram_aduh_monitor_clk_export                                  : out std_logic;                                        -- export
+            ram_aduh_monitor_read_export                                 : out std_logic;                                        -- export
+            ram_aduh_monitor_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_aduh_monitor_reset_export                                : out std_logic;                                        -- export
+            ram_aduh_monitor_write_export                                : out std_logic;                                        -- export
+            ram_aduh_monitor_writedata_export                            : out std_logic_vector(31 downto 0);                    -- export
+            reg_aduh_monitor_address_export                              : out std_logic_vector(5 downto 0);                     -- export
+            reg_aduh_monitor_clk_export                                  : out std_logic;                                        -- export
+            reg_aduh_monitor_read_export                                 : out std_logic;                                        -- export
+            reg_aduh_monitor_readdata_export                             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_aduh_monitor_reset_export                                : out std_logic;                                        -- export
+            reg_aduh_monitor_write_export                                : out std_logic;                                        -- export
+            reg_aduh_monitor_writedata_export                            : out std_logic_vector(31 downto 0);                    -- export
+            ram_diag_data_buf_bsn_address_export                         : out std_logic_vector(15 downto 0);                    -- export
+            ram_diag_data_buf_bsn_clk_export                             : out std_logic;                                        -- export
+            ram_diag_data_buf_bsn_read_export                            : out std_logic;                                        -- export
+            ram_diag_data_buf_bsn_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            ram_diag_data_buf_bsn_reset_export                           : out std_logic;                                        -- export
+            ram_diag_data_buf_bsn_write_export                           : out std_logic;                                        -- export
+            ram_diag_data_buf_bsn_writedata_export                       : out std_logic_vector(31 downto 0);                    -- export
+            reg_diag_data_buf_bsn_address_export                         : out std_logic_vector(11 downto 0);                     -- export
+            reg_diag_data_buf_bsn_clk_export                             : out std_logic;                                        -- export
+            reg_diag_data_buf_bsn_read_export                            : out std_logic;                                        -- export
+            reg_diag_data_buf_bsn_readdata_export                        : in  std_logic_vector(31 downto 0) := (others => 'X'); -- export
+            reg_diag_data_buf_bsn_reset_export                           : out std_logic;                                        -- export
+            reg_diag_data_buf_bsn_write_export                           : out std_logic;                                        -- export
+            reg_diag_data_buf_bsn_writedata_export                       : out std_logic_vector(31 downto 0)                    -- export
         );
     end component qsys_lofar2_unb2b_adc;
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
index 1473990bcdc6999aa84659dd277c98ef50bcc8bb..13d16b18dedb8ae741667b8636f46ba29cfa48ee 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
@@ -82,7 +82,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc IS
 
   -- jesd204b syncronization signals
   SIGNAL jesd204b_sysref     : STD_LOGIC;
-  SIGNAL jesd204b_sync       : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
+  SIGNAL jesd204b_sync_n     : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w)-1 DOWNTO 0);
 
 
 BEGIN
@@ -155,7 +155,7 @@ BEGIN
   
     -- jesd204b syncronization signals
     JESD204B_SYSREF => jesd204b_sysref,
-    JESD204B_SYNC   => jesd204b_sync
+    JESD204B_SYNC_N => jesd204b_sync_n
   );
 
 
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
index 9e5882d78073aeb840fa9fef4f01aaf248e6aa38..69af78de2eb6f28f3442d8541a4feadb98093104 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -145,8 +145,8 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_adc_multichannel IS
   SIGNAL jesd204b_sysref_adc         : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL jesd204b_sysref_adc_1       : STD_LOGIC_VECTOR(11 DOWNTO 0);
   SIGNAL jesd204b_sysref_adc_2       : STD_LOGIC_VECTOR(11 DOWNTO 0);
-  SIGNAL jesd204b_sync_adc           : STD_LOGIC_VECTOR(11 DOWNTO 0);
-  SIGNAL jesd204b_sync_fpga          : STD_LOGIC_VECTOR(11 DOWNTO 0);
+  SIGNAL jesd204b_sync_n_adc         : STD_LOGIC_VECTOR(11 DOWNTO 0);
+  SIGNAL jesd204b_sync_n_fpga        : STD_LOGIC_VECTOR(11 DOWNTO 0);
     
   -- Test bench data    
   SIGNAL jesd204b_tx_link_data_arr   : t_slv_32_arr(11 DOWNTO 0);
@@ -229,7 +229,7 @@ BEGIN
   
     -- jesd204b syncronization signals
     JESD204B_SYSREF => jesd204b_sysref_fpga,
-    JESD204B_SYNC   => jesd204b_sync_fpga
+    JESD204B_SYNC_N   => jesd204b_sync_n_fpga
   );
 
 
@@ -242,7 +242,7 @@ BEGIN
     jesd204b_sysref_adc(i)  <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
 --    txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
     bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
-    jesd204b_sync_adc(i) <= transport jesd204b_sync_fpga(i) after c_delay_data_arr(i);
+    jesd204b_sync_n_adc(i) <= transport jesd204b_sync_n_fpga(i) after c_delay_data_arr(i);
   END GENERATE;
 
   jesd204b_sampclk_fpga <= transport jesd204b_sampclk after c_delay_sysreftofpga;
@@ -292,7 +292,7 @@ BEGIN
         jesd204_tx_link_ready      => jesd204b_tx_link_ready(i),             --out
         mdev_sync_n                => dev_sync_n(i), --in
         pll_locked                 => pll_locked, --in
-        sync_n                     => jesd204b_sync_adc(i), --in
+        sync_n                     => jesd204b_sync_n_adc(i), --in
         tx_analogreset             => tx_analogreset,
         tx_bonding_clocks          => tx_bonding_clocks,--: in  std_logic_vector(5 downto 0)  := (others => 'X'); -- clk
         tx_cal_busy                => open,
diff --git a/applications/lofar2/doc/prestudy/desp_firmware_dag_erko.txt b/applications/lofar2/doc/prestudy/desp_firmware_dag_erko.txt
new file mode 100755
index 0000000000000000000000000000000000000000..6eb5b398050983aac280c3f948c3eaa774eac772
--- /dev/null
+++ b/applications/lofar2/doc/prestudy/desp_firmware_dag_erko.txt
@@ -0,0 +1,309 @@
+Author: Eric Kooistra, jan 2018
+Title: Status of FPGA firmware devlopment at DESP
+
+Purpose:
+- Explain how we currently develop FPGA firmware at DESP
+
+1) Develop FPGA hardware boards
+  - Review board design document and schematic, so that the board will not contain major bugs and
+    so that firmware engineers can already learn about the board and get familiar with it
+  - Pinning design to verify schematic
+  - Vendor reference designs to verify the IO
+  - Heater design to verify the cooling and the power supplies
+
+  - Board architecture:
+    . RSP ring with 4 AP (with ADC) and 1 BP
+    . UniBoard1 mesh with 4 BN (with ADC) and 4 FN, 4 transceivers per 10GbE, DDR3
+    . UniBoard2 4 PN, 1 transceiver per 10GbE, DDR4
+    . Gemini 1 FPGA, 25 Gb  transceivers, DDR4, HBM
+    
+2) Technology independent FPGA:
+  - Wrap IP (IO, DSP, memory, PLL) --> needed for board_heater design, board_minimal, board_test
+  - Use to support:
+    * different vendors:
+      . Xilinx (LOFAR, SKA CSP Low)
+      . Altera (Aartfaac, Apertif, Arts)
+    * FPGA type and sample versions
+    * synthesis tool versions
+    
+3) Board firmware
+  - board_minimal design that provides control access to the FPGA board and the board control functions.
+    uses the monitoring and control protocol via the MM bus (UniBoard using Nios and UCP, Gemini using hard
+    coded Gemini protocol)
+  - board_test design that contain the minimal design plus interfaces to use the board IO (gigabit transceivers
+    , DDR)
+  - board library back, mesh models
+  - pinning files 
+   
+
+4) Oneclick
+  - OneClick is our umbrella name for new ideas and design methods ('ideeen vijver'), focus on firmware specifcation and design.
+    New tools that are created within OneClick may end up as part of the RadioHDL envirionment. This has happened for example
+    with ARGS. Oneclick is about 'what' we could do, RadioHDL is about 'how' we do it.
+  - The name OneClick relates to our 'goal at the horizon' to get in rone click from design to realisation.
+  - Automate design flow
+  - Array notation (can be used in document and in code --> aims for simulatable specification)
+  - Modelling in python of data move, DSP and control
+  - We now work with data move libraries, but could we not better program these adhoc in 1 process?
+
+ 
+5) RadioHDL
+  - Board toolset (unb1, unb2a, rsp, gmi, etc) to manage combinations of board version, FPGA version, tool version
+  - RadioHDL is our umbrella name for set of tool scripts that we use for firmware development, focus on implementation.
+  - The name RadioHDL covers HDL code for RadioAstronomy as a link to what we do at Astron. However by using only the word Radio we keep
+    the name a bit more general, because in fact the RadioHDL tool scripts can be used for any (FPGA) HDL development.
+  - Automate implementation flow (source --> config file --> tool script --> product, a product can be the source of a next product)
+  - Organize code in libraries using hdllib.cfg
+  - Manage tool versions using hdltool_<toolset name>.cfg
+  - Create project files for sim and synth
+  - ARGS (Automatic Register Generation System using MM bus and MM register config files in yaml)
+    . add more configuration levels:
+       peripheral configuration yaml
+       fpga configuration yaml
+       board yaml (board with 1 or more FPGA)
+       application (application image on one or more FPGA)
+       system (one or more application images that together form the entire FPGA system)
+    . add constants configuration yaml --> to define terminology and parameter section in specification document and to use
+      these also in firmware and software.
+  - Create FPGA info (used to be called system info) address map stored in FPGA to allow dynamic definition of address maps. The definition
+    of the MM register fields is kept in files because it typically remains fixed.
+  - Easily enroll the environment on a new PC and introduce a new employee (to be done)
+  
+
+6) VHDL design:
+  - Clean coding
+  - Reuse through HDL libraries
+  - Standard interfaces: MM & ST, support Avalon, AXI using VHDL records mosi/miso, sosi/siso
+  - Build FPGA appliciation design upon a board minimal design and the relevant IO from the board test design
+  - dp_sosi :
+    . data, re/im  : real or complex data
+    . valid        : strobe to indicate clock cycles that carries valid data samples, not needed for ADC input
+    . sop, eop     : strobes to indicate start of packet and end of packet for blocks of data
+    . sync and bsn : timing strobe, block sequence number is timestamp, alignment of parallel streams
+    . channel      : valid at sop to multiplex multiple channels in one stream
+    . empty        : valid at eop
+    . error        : valid at eop
+  - dp_siso:
+    . ready : backpressure flow control per data valid, only used for components that realy need it to avoid complexity and 
+              to ease timing closure. The ready can be pipelined with dp_pipeline_ready.vhd. The ready flow control is e.g.
+              used to insert a header in front of data blocks to create a packet.
+    . xon   : backpressure flow control per block of data. The xon flow control is used to stop the input source to avoid
+              overflow internal FIFOs. Together these FIFOs must at least be capable to store the current blocks. Our 
+              applications are data driven, so making xon low will cause data to be dropped. For an application that read 
+              data from a disk like in the all data storage systems, the xon can be used read the disk as fast as possible 
+              by applciation, so DSP driven !!!.
+    
+  - Synthesis tool ensures that the logic per clock cycle is reliable, we have to ensure at functional level that only
+    complete blocks of data are being passed on !!!:
+    . Incomplete blocks must be dropped at the input
+    . FIFOs should never overflow and should not be reset. Avoid overflow by using xon. Clear a FIFO by reading it empty
+   
+  - Streaming data versus store and forward !!!
+    . dp_bsn_aligner.vhd, aligns input streams using the BSN
+      - The resource usage of the dp_bsn_aligner in Apertif Correlator (14 dec 2018) is:
+               nof       ALM            FF
+               streams   align    MM    align    MM
+         input   3         502   213      657   319
+         mesh    8        1162   544     1346   784
+      - Fill level of dp_bsn_aligner input FIFOs in Apertif Correlator (18 dec 2018) measured with util_dp_fifo_fill.py is:
+                  fifo size                  max (min/max)        used (min/max)
+                                             1st time  2nd time 
+          input   (3+5)*176 (or 180) = 1408  178/762   178/504    139/428
+          mesh    (4+3)*88 (or 120)  =  618  159/516   150/262     64/255
+          
+    . dp_sync_checker.vhd, detect incomplete sync intervals, these are recoved using data from the next sync interval, so
+        the next sync interval will get lost. To avoid this would require to store and forward the data of a sync interval
+        because then it is possible to fill in missing blocks with dummy data. With store and forward it is also possible
+        to recover block order if necessary. The disadvantage of store and forward is latency and memory. Store and forward
+        is the general concept for how software operates (on CPU and GPU).
+        This scheme of sync interval recovery is only acceptable if dropped packets occur very rarely, because if one
+        stream has a dropped packet then the output of the BSN aligner and sync checker will drop a sync interval. E.g.
+        apertif X needs to aligne N_dish * N_pol = 12*2 = input streams and sync interval = 1.024 s. These input streams 
+        come from 10GbE links. A bit error rate of 1e-10 means 1 bit error per s per link. A bit error will cause CRC error
+        and assume that then the packet gets dropped, this then causes that the BSN aligner cannot align that block and
+        that will cause that one sync interval gets corrupted and the next will get lost. After that the BSN aligner will
+        have recovered. Suppose this should only occur once per 8 hour observation = 28800 s. So with 24 links the BER 
+        per link should then be less than 1e-10 / 28800 / 24 ~= 1e-16 or 1e-17, so only 1 per month.
+        
+     . dp_packet_rx.vhd, ensure that only complete packets enter the FPGA
+     . FIFO overflow is a bug, as serious as a FPGA logic error
+     
+  - Pass on sosi.info fields along a function that only needs data and valid
+    . dp_fifo_fill           --> use FIFOs to delay sop info and eop info with variable latency
+    . dp_paged_sop_eop_reg   --> use array pf of register pages to delay sop info and eop info by fixed latency. If
+                                 the latency is many sops or if only sync and BSN need to be passed on, then consider
+                                 using dp_block_gen_valid_arr
+    . dp_block_gen_valid_arr --> recreate sync, local BSN, sop, eop based on valid and pass on global BSN at sync or at
+                                 all sop. Usefull if the latency is >= 1 sync intervals or many sops.
+  
+  - Component improvements:
+    . Verify flow control in tb of dp_offload_rx and dp_offload_tx_dev (wrapper of dp_concat_field_blk.vhd)
+    . reorder_matrix.vhd with timestamp accurate page swap
+    . dp_fifo_fill_eop.vhd : fill FIFO with one block instead of some number of words to avoid that FIFO cannot be read empty
+    . dp_bsn_aligner.vhd:
+      - A dp_bsn_aligner without flow control would make it much simpler.
+      - A further simplification is to make a dp_sync_aligner that only can recover alignement at a sync, instead of at
+        every sop (via the BSN).
+      - Instead of xoff_timeout it is also possible to wait until the FIFO has been read empty for all inputs.
+    
+     
+  - Timing and sync intervals
+    . At the ADC input the BSN timestamps are attached to the block data. The block size for the BSN depends on the length of
+      the FFT. This BSN relates the data to UTC. MAC initializes the BSN relative to 1 jan 1970.
+    . With ADC clock of 800MHz and FFT size of 1024 this yields 800M/1024 = 781250 subbands per sec. We process the data at
+      200MHz so we have 4 streams in parallel, each with 781250/4 = 195312.5 blocks per sec. In LOFAR we has also such 
+      a situation and there we define odd and even second sync intervals. The even interval then has 195313 blocks and the
+      odd interval than has 195312 intervals. This was awkward for control. In Apertif a similar fractional block issue
+      occured in the correlator with 781250 / 64 = 12207.03125 channels per second. Therefore for Apertif we increased the sync
+      to 1.024 s, such that we have 800000 / 64 = 12500 channels per sync interval. Now we do not have 
+      even and odd seconds anymore but still this 1.024 s sync interval is also akward because it does not align with the
+      1 s grid that human use and that also other parts of the telescope use. 
+      Possible solutions for future systems would be to use a sampling frequency that is a multiple of the FFT size, so
+      e.g. 809.6MHz with FFT size = 1024, or 800MHz with FFT size = 800. These schemes have the additional advantage that
+      then the subband bandwidth is 1 MHz which fits the typical band width grid in VLBI and it also fits the fact that the
+      Apertif LO can be tuned in steps of 10MHz. With subband bandwidth of 781250 Hz only once every 50 MHz the subbands
+      align with the 10MHz grid, because 64*781250 = 50M.
+    . Using an oversampled filterbank introduces yet another block grid. For example with 32/27 and an FFT block size
+      of 1024 the oversampled block size becomes 1024 * 27/32 = 864. This oversampled 864 block grid only aligns with
+      the 1024 block grid once every 27 blocks of size 1024. For Apertif the 781250 blocks of 1024 align with the 1
+      sec grid, but the 32/27 oversampled blocks will only align every 27 sec. Hence with oversampling it is necessary to
+      accept that it becomes impossible to main block alignment within a 1 second grid.
+    . In APERTIF the misalignment between the channel period and the one second grid was avoided by defining a sync
+      interval of 1.024 s and use that sync interval as integration period. A sync interval of 1.024 s for LOFAR would mean
+      that a sync interval contains 160000 blocks at f_adc = 160M and 200000 blocks at f_adc = 200 MHz. However if other
+      parts of the system rely on a one second or e.g. ten second grid, then using a 1.024 second grid does not fit well
+      with those parts. Using an oversampled filterbank introduces yet another block grid. For example with r_os = 32/27
+      and an FFT block size N_fft = 1024 the oversampled block size becomes M_blk = 1024 * 27/32 = 864. This oversampled
+      M_blk = 864 block grid only integer aligns with the one second grid once every 27 seconds, because 200M / 864 * 27
+      = 6250000 and 160M / 864 * 27 = 5000000 yield an integer. The alternative would be to define a sync interval that is
+      an integer multiple of M_blk and close to 1 s. Preferably T_int is the same for f_adc = 200M and 160MHz. The ratio
+      160M / 200M = 4 / 5, so choose the sync interval to be a multiple of 4 * 5 * 864 = 17280 blocks. This then yields
+      e.g. ceil(200M / 17280) * 17280 = 200016000 and ceil(160M / 17280) * 17280 = 160012800, which both correspond to
+      T_int = 1.00008 s exact. However LOFAR 2.0 needs to be compatible with LOFAR 1.0, so the fact that 1.00008 != 1
+      will cause misalignment regarding the statistics like SST, BST, XST from a LOFAR 1.0 station and a LOFAR 2.0
+      station. Furthermore to read the statistics and update the BF weights the LCU needs to keep track of the 1.00008 s
+      grid. Therefore it is best to keep the one second grid and accept that some sync intervals contain 1 block more than
+      the other sync intervals. For the critically sampled filterbank as in LOFAR 1.0 with r_os = 1 this yields
+      200M / 1024 = 195312.5 blocks per second on average, so the number of blocks per sync interval then repeats with
+      period 2 s as: 195312 + 0,1. For the oversampled filterbank with e.g. r_os = 32/27 and M_blk = 864 this would yield
+      200M / 864 = 231481.481 blocks per second on average, so the number of blocks per sync interval then repeats with
+      period 27 s as: 231481 + 0,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1 because 13 / 27 = 0.481. The
+      variation in number of blocks per sync interval is sufficiently small, 1/231481 = 4.3e-6, such that it does not
+      significantly affect the accuracy of the statistics values per sync interval.
+
+        
+  - Flow control
+    
+    . dp_siso : ready and xon  
+   
+  - Useful libraries and packages:
+    . base: common, dp, mm, diag, reorder, uth
+    . dsp: wpfb, bf, correlator, st
+    . io: eth, io_ddr, i2c
+
+7) Applications:
+  - Build upon reused libraries. 
+  - New functions are first added as libraries and then used in the application
+  - Qsys only used for the MM bus generation
+
+
+8) VHDL testing:
+  - detailed unit tests per HDL library using entity IO
+    . verify corner cases
+    . often use stimuli --> DUT --> inverse DUT --> expected results
+      e.g.
+         rx - tx
+         encode - decode
+         mux - demux
+    . sometimes the same component can suppot both directions:
+         dp_repack
+         dp_deinterleave
+    
+  - integration top level or multi FPGA tests using MM file IO
+    . MM file IO for testbenches at design level, 'breaking the hierarchy' in VHDL or providing access to Modelsim simulation with Python
+    . do not test the details those must be covered in the unit tests
+  - regard the firmware as a data computer, so independent of its functional (astronomical) use we need to verify and validate that for a 
+    known stream of input data it outputs the expected output data.
+  - detailed unit tests per HDL library using entity IO
+  - integration top level or multi FPGA tests using MM file IO
+    . MM file IO for testbenches at design level, 'breaking the hierarchy' in VHDL or providing access to Modelsim simulation with Python
+  - regard the firmware as a data computer, so independent of its functional (astronomical) use we need to verify and validate that for a 
+    known stream of input data it outputs the expected output data.
+  - Verification via simulation:
+    . use of g_sim, g_sim_record to differentiate between simulation and hardware
+    . use g_design_name to differentiate between revisions, e.g. to speed up simulation or synthesis
+    . behavoral models of external IO (DDR, Transceivers, ADC, I2C)
+    . break up data path using WG, BG, DB, data force
+    . optional use of transparant DSP models to pass on indices.
+    . verify data move by transporting meta data (indices) via the sosi data fields
+    . profiler to know time consuming parts
+  - VHDL regression test (if not there, then it is not used)
+  - Validation on hardware
+    . using Python peripherals for MM control using --cmd options per peripheral
+    . construct more complicated control scripts using sequence of peripheral scripts and --cmd
+    . we need proper data capture machines, to validata 10G, 40 GbE data output (e.g. using wireshark and some Python code)
+
+    
+9) Documentation
+  - Documentation is needed to specify what we have to make
+    . Detailed design document uses array notation to cleary describe all internal and external interfaces
+    . Detailed design document also identifies test logic that is needed for the integration top level tests
+  - No need to document what we have made, except for readme file and manuals
+  - The code is self explanatory (with comment in docstring style using purpose and description)
+  - The project scripts identify what is relevant for a product
+  - The regression tests identify what is relevant code (if it is not tested it is not important and should not have been made)
+  - It would be nice to have YouTube movies that show our workflow and boards
+
+
+10) Project planning
+  - Wild ass guess based on time logs of previous projects
+  - System engineering design approach for total product life cycle
+  - Agile style with scrum and sprints
+    . If it is not an allocated epic/story/task in Redmine then it will not be done
+  - Roles within the team
+    . System architects remain actively involved during entire project to ensure that design ideas are preserved or 
+      correctly adjusted
+  - Whiteboard meetings to steer detailed design
+    . with wide team to get common understanding and focus
+  - Definition of done 
+  - What maintenance support do we provide after a project has finished
+    . firmware tends to become hardware in time, ' het verstaft'
+    . using virtual machines (dockers) to bundle a complete set of operating system, tools and code for the future or to
+      export as a starting point to an external party (e.g. for outsourcing)
+    
+11) Ethernet networks
+  - 1GbE, 10GbE, 40GbE, 100GbE IP
+  - Knowledege of switches
+  - Knowledege of UDP, IP, VLAN
+  - Monitoring and Control protocol (UniBoard, Gemini)
+  - Streaming data offload
+  
+12) Outreach, papers, collaborations, recruiting
+  - Oliscience opencores
+  - NWO digital special interest group
+  - student assignments
+  - Write paper on ARGS (done by Mia @ CSIRO)
+  - Write paper on RadioHDL (= also intro paper / user guide for RadioHDL on OpenCores)
+  - Write paper on RL = 0 coding style with state reg and pipeline reg clearly separated. The design should also work
+    without pipeline. Possibly the pipelining should be added automatically and only where needed.
+  
+13) DESP pillars
+  - All data storage
+  
+  
+14) Externe info
+  * Technolotion in B&C 2019/2
+    - own IP libraries
+    - self-checking testbenches made by developer
+    - own HDL implementation of opensource Risc-V-Processor (instruction set architecture) can run Linux
+    - generic build server for simulation and synthesis (with all tool versions)
+    - regression test using nightly build
+    - version control using GIT (merge request --> review by collegue --> discussion via GIT server)
+    - HW regression test using a stimuli generator (e.g. video)
+  * High Tech Institute: System Configuration Management
+    - start with a model of the company processes
+    - first organize then automate
+    - baselinen is create timestamp versions numbers of components (HW, SW)
+  * Dutch system architecting conference 20 june 2019 Den Bosch
+    
+  
diff --git a/applications/lofar2/doc/prestudy/desp_firmware_overview.txt b/applications/lofar2/doc/prestudy/desp_firmware_overview.txt
new file mode 100755
index 0000000000000000000000000000000000000000..a730491ee975526ea90ed9c0c8eefe89287dc8c3
--- /dev/null
+++ b/applications/lofar2/doc/prestudy/desp_firmware_overview.txt
@@ -0,0 +1,177 @@
+Author: Eric Kooistra, jan 2018
+Title: Key aspects of FPGA firmware devlopment at DESP
+
+Purpose:
+- Provide a list of key aspects of FPGA firmware devlopment at DESP
+- Identify libraries or toolscript that we could isolate and make public via e.g. OpenCores or GitHub
+- Identify topics that we need to focus on in the future
+
+
+1) Develop FPGA hardware boards
+  - Review board design document and schematic and layout, so that the board will not contain major bugs and
+    so that firmware engineers can already learn about the board and get familiar with it
+  - Pinning design to verify schematic
+  - Vendor reference designs to verify the IO
+  - Heater design to verify the cooling and the power supplies
+  
+2) Technology independent FPGA:
+  - Wrap IP (IO, DSP, memory, PLL)
+  - Xilinx (LOFAR, SKA CSP Low)
+  - Altera (Aartfaac, Apertif, Arts)
+  
+3) VHDL design:
+  - Clean coding
+  - Reuse through HDL libraries
+  - Standard interfaces: MM & ST, support Avalon, AXI using VHDL records mosi/miso, sosi/siso
+  - Use records not only for signals but also for generics, because adding a record field does not change the 
+    component interface.
+  - Distinguish beteen state registers and pipeline registers.
+    . For example: dp_block_resize.vhd, dp_counter.vhd.
+  - Board minimal design that provides control access to the FPGA board and the board control functions
+  - Board test design that contain the minimal design plus interfaces to use the board IO (transceivers, DDR)
+  - Build FPGA application design upon a board minimal design and the relevant IO from the board test design
+  - Useful libraries and packages:
+    . base: common, dp, mm, diag, reorder, uth
+    . dsp: wpfb, bf, correlator, st
+    . io: eth, io_ddr, i2c
+  - Design for scaleability with generics that can be scaled over the logical range, e.g. >= 0, even if the
+    application only requires a certain fixed value. The reasons are:
+    . During development the application typically starts small (e.g. a BF with 4 inputs) while the final
+      application is much larger (e.g. a BF with 64 input). With generics both can be supported through a
+      parameter change.
+    . For simulation it is often necessary to reduce the size of the design to be able to simulate it in a
+      reasonable time. By scaling it down via generics the design preserves its structure but becomes much
+      smaller. 
+
+3) VHDL testing:
+  * Levels of application verification
+    - use refrence designs to verify the vendor phy IO IP, in the application these are replaced by models.
+      For example: tranceiver, DDR3, MM interface via MM file IO, ...
+    - detailed unit tests per HDL library using entity IO to proved that the unit is correct in all relevant
+      use cases and corner cases, usch that application tests can focus on integration tests.
+    - integration top level or multi FPGA tests using MM file IO
+      . MM file IO for testbenches at design level, 'breaking the hierarchy' in VHDL or providing access to Modelsim simulation with Python
+      . preferrably use MM file IO and revisions of the top level design to verify parts in the top level design, rather then making
+        a testbench for only that part using the IO of that part. The control interface should be enough to test the part, therefore 
+        using MM file IO is enough and avoids testbenches that make use of other entity IO signals. Typically the revision can contain BG
+        and DB (with MM interface) to also have direct streaming access to the part in the top level.
+  * regard the firmware as a data computer, so independent of its functional (astronomical) use we need to verify and validate that for a 
+    known stream of input data it outputs the expected output data.
+  * Verification via simulation:
+    . use of g_sim, g_sim_record to differentiate between simulation and hardware
+      speed up MM clk, I2C clk, skip PHY startup time, reduce size while keeping the structure,
+      skip or bypass functions
+    . use g_design_name to differentiate between revisions, e.g. to speed up simulation or synthesis
+    . behavoral models of external IO (DDR, Transceivers, ADC, I2C)
+    . break up data path using WG, BG, DB, data force
+    . optional use of transparant DSP models to pass on indices.
+    . verify data move by transporting meta data (indices) via the sosi data fields
+    . profiler to know time consuming parts
+  * VHDL regression test (if not there, then it is not used)
+  * Validation on hardware
+    . using Python peripherals for MM control using --cmd options per peripheral
+    . construct more complicated control scripts using sequence of peripheral scripts and --cmd
+    . we need proper data capture machines, to validata 10G, 40 GbE data output (e.g. using wireshark and some Python code)
+
+4) RadioHDL
+  - RadioHDL is our umbrella name for set of tool scripts that we use for firmware development, focus on implementation. RadioHDL makes
+    it easier for developers to organize different versions and combinations of their firmware, tools and boards. RadioHDL is a platform?
+  - The name RadioHDL covers HDL code for RadioAstronomy as a link to what we do at Astron. However by using only the word Radio we keep
+    the name a bit more general, because in fact the RadioHDL tool scripts can be used for any (FPGA) HDL development. Outside Astron
+    the word RadioHDL can be advertised as an HDL radio station that one likes to listen to, ie. to use, so a feel good name with a
+    strong link to HDL but otherwise not explicitely telling what it is. The word RadioHDL also has no hits in Google search, so no
+    conflict or confusion with others.
+  - Automate implementation flow (source --> config file --> tool script --> product, a product can be the source of a next product)
+  - Organize code in libraries using hdllib.cfg
+  - Manage tool versions using hdltool_<toolset name>.cfg
+  - Create project files for sim and synth
+  - ARGS (Automatic Register Generation System using MM bus and MM register config files in yaml)
+  - Create FPGA info (used to be called system info) address map stored in FPGA to allow dynamic definition of address maps. The definition
+    of the MM register fields is kept in files because it typically remains fixed.
+  - Easily enroll the environment on a new PC and introduce a new employee (to be done --> OpenCores, Ruud Overeem)
+  
+5) Oneclick
+  - OneClick is our umbrella name for new ideas and design methods, focus on firmware specifcation and design. New tools that are
+    created within OneClick may end up as part of the RadioHDL envirionment. This has happened for example with ARGS.
+  - The name OneClick relates to our 'goal at the horizon' to get in one click from design to realisation.
+  - Automate design flow
+  - Array notation (can be used in document and in code --> aims for simulatable specification)
+  - Modelling in python of data move, DSP and control
+
+6) New hardware, tools and languages
+  - FPGA, GPU, DSP, ASIC
+  - OpenCL
+  - HLS
+  - Compaan, Clash, Wavecore
+    
+7) Documentation
+  - Documentation is needed to specify what we have to make
+    . Detailed design document uses array notation to cleary describe all internal and external interfaces
+    . Detailed design document also identifies test logic that is needed for the integration top level tests
+  - No need to document what we have made, except for readme file and manuals
+  - The code is self explanatory (with comment in docstring style using purpose and description)
+  - The project scripts identify what is relevant for a product
+  - The regression tests identify what is relevant code (if it is not tested it is not important and should not have been made)
+  - It would be nice to have YouTube movies that show our workflow and boards
+
+8) Project planning
+  - Wild ass guess based on time logs of previous projects
+  - Agile style with backlog, scrum and 3 week sprints (If it is not an allocated epic/story/task in Redmine then it will not be done).
+  - Review process:
+    . purpose is to ensure value and quality and to spread knowledge and awareness
+    . coder works based on a ticket in Rdemine, all production code must be reviewed by another team member
+    . coder delivers code according to coding style, with purpose-description/docstring and with regression test
+    . reviewer reviews code and function, reports via redmine ticket
+    . reviewer only reports
+    . coder does corrections and merges branch to trunk
+  - Roles within the team
+  - Definition of done 
+  - Outsourcing
+  - Hiring temporary consultants
+  - What maintenance support do we provide after a project has finished
+    . firmware tends to become hardware in time, ' het verstaft'
+    . using virtual machines (dockers) to bundle a complete set of operating system, tools and code for the future or to
+      export as a starting point to an external party (e.g. for outsourcing)
+  - What if we would be with 10 - 15 digital/firmware engineers instead of about 5 as now (Gijs, Leon, Pieter, Jonathan, Eric, Daniel)
+    
+9) Ethernet networks
+  - 1GbE, 10GbE, 40GbE, 100GbE IP
+  - Knowledege of switches
+  - Knowledege of UDP, IP, VLAN
+  - Monitoring and Control protocol (UniBoard, Gemini)
+  - Streaming data offload
+  
+10) Outreach, collaborations. recruiting
+  - Oliscience opencores
+  - NWO digital special interest group
+  - student assignments
+  
+11) DESP pillars
+  - All data storage
+  
+  
+12) Version control
+  - We use SVN and work on the trunk. This is feasible because we are a small team and has the advantage that issues are noted
+    in an early stage
+  - Common practice in larger software development teams is that code is developed on branches and merged to the trunk after 
+    it has been verified
+  - In future use GIT?
+  
+  
+13) FPGA - GPU
+  - ASTRON_MEM_193_Comparison_FPGA_GPU_switch
+  - FPGA are good at:
+    . can interface to ADC (not possible with GPU, so always need for a glue logic FPGA, but such an FPGA with gigabit
+      transceivers is also capable of quite some processing)
+    . can support many external IO ports via upto ~100 transceivers (GPU only a few fast external IO ports)
+    . reorder blocks of data, e.g. in a packet payload
+    . low latency applications (e.g. low latency trading), fixed latency (e.g. fast control loops, absolute timing)
+    . embedded, standalone applications
+    . have life time/ support time of > 10 years (GPU < 5 years)
+  - GPU are good at:
+    . more general to program
+    . fast compile times (< minutes, versus > hours for FPGA)
+    . uses floating point arithmetic by default (versus fixed point by default for FPGA)
+    . matrix operations
+    
+    
\ No newline at end of file
diff --git a/applications/lofar2/doc/prestudy/desp_howtools_erko.txt b/applications/lofar2/doc/prestudy/desp_howtools_erko.txt
index b23f9fef1919bb23d60e1129c0a5a739e4aa2118..333a8408d089a47e39190a4c3fad92f446fb5e13 100755
--- a/applications/lofar2/doc/prestudy/desp_howtools_erko.txt
+++ b/applications/lofar2/doc/prestudy/desp_howtools_erko.txt
@@ -1,5 +1,6 @@
 * RadioHDL with GIT (LOFAR2.0)
 * RadioHDL with SVN (APERTIF/ARTS)
+* RadioHDL issues
 * GIT workflow
 * Confluence
 * Polarion
@@ -8,6 +9,7 @@
 * Vi
 * Screen to run a terminal session without ssh connection
 * Quartus Qsys IP files in GIT
+* Quartus version
 
 
 *******************************************************************************
@@ -89,6 +91,16 @@ export SVN=${HOME}/svnroot/UniBoard_FP7
 . ${SVN}/RadioHDL/trunk/tools/setup_unb.sh
 
 
+*******************************************************************************
+* RadioHDL issues
+*******************************************************************************
+
+1) may 2020 PD quartus_config.py unb2b failed
+Error : Unavailable library ip_arria10_e1sg_altera_jesd204_180 at 'hdl_lib_uses_sim' key is not disclosed at 'hdl_lib_disclose_library_clause_names' key in library ['ip_arria10_fractional_pll_clk200', 'ip_arria10_fractional_pll_clk125', 'ip_arria10_e3sge3_fractional_pll_clk200', 'ip_arria10_e3sge3_fractional_pll_clk125', 'ip_arria10_e1sg_fractional_pll_clk200', 'ip_arria10_e1sg_fractional_pll_clk125', 'ip_arria10_e2sg_fractional_pll_clk200', 'ip_arria10_e2sg_fractional_pll_clk125']
+
+Temporary fix commented line 4,5 in:
+https://git.astron.nl/desp/hdl/-/blob/L2SDP-36/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+
 
 *******************************************************************************
 * GIT references
@@ -457,6 +469,10 @@ hardstatus alwayslastline
 hardstatus string '%{= kG}[ %{G}%H %{g}][%= %{= kw}%?%-Lw%?%{r}(%{W}%n*%f%t%?(%u)%?%{r})%{w}%?%+Lw%?%?%= %{g}][%{B} %m-%d %{W}%c %{g}]'
 Copy
 
+* uex in screen lijkt eerst niet op te starten,
+  matlab wel dus het ligt niet aan GUI, daarna lukts uex wel.
+* :kooistra@dop386:~/git/hdl>  --> in gewone terminal
+* ::kooistra@dop386:~/git/hdl> --> in screen terminal
 
 *******************************************************************************
 * Quartus Qsys IP files in GIT
@@ -525,3 +541,20 @@ total 2492
 -rw-r--r-- 1 kooistra users  62209 Sep 23 13:01 qsys_unb2b_minimal_rom_system_info.ip
 -rw-r--r-- 1 kooistra users  63384 Sep 23 13:01 qsys_unb2b_minimal_timer_0.ip
 
+
+*******************************************************************************
+* Quartus version
+*******************************************************************************
+
+Quartus version meeting minutes 13 may 2020 (RW, LH JH, EK):
+
+1) UniBoard2b IP is created using Quartus 18.0, same as used for ARTS SC3.
+
+2) UniBoard2b synthesis is done with Q18.0 or newer. In case of a newer Quartus version we rely on Quartus to upgrade the Q18.0 IP for synthesis which works fine sofar. We also rely on that the Q18.0 models are still sufficiently correct.
+
+2a) Jonathan uses Q19.4, because Q18.0 does not work remotely via ssh.
+2b) Reinier uses Q19.2, because that is the latest version that support OpenCL without microprocesor.
+
+3) UniBoard2c IP was created using Q19.4 by Jonathan, but we need to reconsider going to the latest Quartus version and recreate the IP, when we continue with the pinning and test designs for UniBoard2c
+
+
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_deliverables.txt b/applications/lofar2/doc/prestudy/station2_sdp_deliverables.txt
old mode 100644
new mode 100755
index 0f084180c7f642469f0c412f22a300976b6b827a..ca85b6f5912606001bc5c41916cec10bf80efac5
--- a/applications/lofar2/doc/prestudy/station2_sdp_deliverables.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_deliverables.txt
@@ -1,7 +1,7 @@
 D1  UniBoard2 Detailed Design document
 D2  Gemini LRU board for initial SW M&C tests
 D3  unb2c_test_pinning (using 10GbE)
-D4  unb2c_test_pinning_jesd (using JESD204b)
+D4  unb2c_test_pinning_jesd (using JESD204b) ~= lofar2_unb2b_adc_one_node
 D5  unb2c_heater (verify speed grade)
 D6  unb2c_test_ddr4 (both slots)
 D7  unb2c_test_10GbE (QSFP + ring, back)
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_dsp.txt b/applications/lofar2/doc/prestudy/station2_sdp_dsp.txt
old mode 100644
new mode 100755
index 8b659737013ef01fa996825d1c900f584ab3a097..4e34ba565af2cee3c3076768dc3815582d24c1b0
--- a/applications/lofar2/doc/prestudy/station2_sdp_dsp.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_dsp.txt
@@ -1,3 +1,25 @@
+*******************************************************************************
+* ADC input and timing
+*******************************************************************************
+
+- BSN source uses sysref or extpps
+- BSN source v2
+- sysref dig voor of na sysref ana, moet kunnen denk ik binnen multi frame period of
+  als tegelijk dan komt data van ADC zeker na sysref dig binnen op FPGA tgv latency van ADC en transceiver.
+- < 12 vd 12 inputs moet ook werken, want nodig tijdens development en ook in de praktijk als 1 RCU2 defect of uit is.
+
+*******************************************************************************
+* Subband filterbank
+*******************************************************************************
+
+The prototype FIR filter defines the transfer function of each subband sampled at fs. The FFT creates bins that effectively down convert each subband from n*f_sub to 0 Hz and downsample each subband by the factor N_fft. The PFB structure is such that for each subband only the samples that remain after downsampling are calculated. The PFB output sample rate per subband for the critically sampled PFB is f_sub = fs / N_fft. The subband sample rate is equal to the subband bandwidth, which does meat the Nyquist criterium, because the Nyquist factor 2 is hidden in the fact that the subband samples are complex, so they consist of 2 parts (real and imaginary).
+
+The prototype FIR filter can be regarded as a window function. For a static FFT operation the window function is typically equal or shorter than the FFT size. In a critially sampled PFB the FFT is calculated for every N_fft input samples. The response of the prototype filter is N_tap times longer than the FFT size. Hence for the dynamic operation of the FFT in an PFB the prototype filter provides a long window function and can thus achieve much sharper bandpass transition for the subbands, than a regular FFT window function. 
+
+For the oversampling PFB the FFT is calculated every M input samples, where the oversampling factor R_os = N_fft / M. Note that the oversampling PFB increases the subband sample rate f_sub_os = f_sub * R_os, but not the subband frequency grid. The subband frequency grid is n * f_sub, for any R_os, because the downsampling factor N_fft is the same for any R_os.
+
+
+
 *******************************************************************************
 * Beamformer
 *******************************************************************************
@@ -65,6 +87,15 @@ M&C:
 * Transient buffer
 *******************************************************************************
 
+TBB
+. seqnr 32b intern TBB only
+. time 32b (in seconds) + samplenr 32b (in this 1 s interval) form timestamp of first sample in frame
+. nof samples per frame <= 
+. payload 1948 bytes = 487 complex subbands (2*16b)
+. if we skip seqnr, then 488 subbands can fit in frame
+. the gap is needed due to the interface between RSP and TBB, not needed for LOFAR2.0 SDP
+. 22 hdr + 487 payload + 1 crc = 510 words
+. 1024 * 12/8 = 1536 bytes, 1024 * 14/8 = 1792 bytes
 
 
 *******************************************************************************
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt b/applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt
old mode 100644
new mode 100755
index 600f497c64b3281c8f29e8e4604c5992cb6ae94f..e68d68a84e514832446c8fdc78a80ea967f3228b
--- a/applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_firmware_design.txt
@@ -2,6 +2,55 @@
 * Detailed Design Document of the LOFAR 2.0 Station SDP firmware
 *******************************************************************************
 
+The System Engineering breaks up the product into sub products until the sub product is small enough. The product and the break down into sub products are defined in the product ADD. Where necessary additional design decision documents provide the rationale for the ADD. This SE approach repeats for every sub product.
+
+* = Product ADD
+<-- Design decisions for product ADD
++ = Decision document for product ADD
+--> Sub products in ADD
+
+* L2 Station ADD
+  <-- L2 STAT Design decisions
+    + L2 STAT Decision: Location of SC-SDP Translator function
+	+ L2 STAT Decision: Selection of Interface Protocol
+	+ L2 STAT Decision: Timing in Station
+	+ L2 STAT Decision: Synchronisation between STF, RCU2S and SDP
+	+ L2 STAT Decision: Impact of oversampled subband filterbank
+	+ L2 STAT Decision: Independent Receiver
+	+ L2 STAT Decision: Decomposition into L3 products
+  --> L3 STAT Products
+    * L3 RECV Design Document
+    * L3 STCA Design Document
+    * L3 SC Design Document
+    * L3 STF Design Document
+    * L3 SDP Design Document
+      <-- L3 SDP Design decisions
+		+ L3 SDP Decision: FPGA Monitor and Control Protocol
+		+ L3 SDP Decision: Timing in SDP				   
+      --> L4 SDP Products
+        * L4 SDP Firmware Design Document
+          <-- L4 SDPFW Design decisions
+          --> L5 SDPFW Products
+            * L5 SDPFW Design Document: ADC input and timestamp
+            * L5 SDPFW Design Document: Subband filterbank (+ calibration weigths)
+            * L5 SDPFW Design Document: Digital beamformer (+ CEP output)
+            * L5 SDPFW Design Document: Subband correlator
+            * L5 SDPFW Design Document: Ring
+            * L5 SDPFW Design Document: Transient buffer (+ CEP readout)
+            * L5 SDPFW Design Document: Transient detection
+			* L5 SDPFW Design Document: Library components
+              --> L6 SDPFWLIB Products
+			    * L6 SDPFWLIB Design Document: Pulse interval monitor (= mms_common_interval_stable_monitor.vhd)
+			    * L6 SDPFWLIB Design Document: Pulse alignment monitor(= mms_common_alignment_stable_monitor.vhd)
+				* L6 SDPFWLIB Design Document: BSN source with BSN offset 
+				* L6 SDPFWLIB Design Document: BSN aligner using filler data
+				* L6 SDPFWLIB Design Document: PPS handler with time since last PPS
+			  
+         * L4 SDP Translator ADD
+    
+         * L4 SDP Hardware ADD (= UniBoard2 modifications document)
+
+Busy with SDP Firmware design documents (L2SDP-39, 90)
 
 ? Link with functions in ADD
 ? Link with L4 requirements on SDP
@@ -31,16 +80,22 @@ Station overview
   . ADD fig 4.5.1.2-1 UniBoard2 with 4 PN
   . ADD fig 4.5.2-1 Firmware toplevel with ICDs
   . ADD fig 4.5.2-2 External FPGA interfaces for M&C and data offload
-               
-Hardware architecture (SDP, STCA)
-  . Two UniBoard2 per subrack, one PCC, 32 RCU each with 3 signal inputs (ADCs)
-  . 12 ADC per FPGA, 48 ADC per UniBoard, 96 ADC per subrack
-  . LBA ring : two subracks
-  . HBA ring : one subrack for core (two sub-arrays, but one ring to have subband correlations for all)
-               one subrack for remote
-               two subracks for international
-               
-Firmware infrastructure
+
+SDP toplevel
+  - SDP Translator (controller, OPC-UA)
+  - SDP Hardware (UniBoard2)
+    * Array architecture (SDP, STCA)
+      . Two UniBoard2 per subrack, one PCC, 32 RCU each with 3 signal inputs (ADCs)
+      . 12 ADC per FPGA, 48 ADC per UniBoard, 96 ADC per subrack
+      . LBA ring : two subracks
+      . HBA ring : one subrack for core (two sub-arrays, but one ring to have subband correlations for all)
+                   one subrack for remote
+                   two subracks for international
+  - SDP Firmware
+  
+              
+SDP Firmware
+* Firmware infrastructure
   . BSP (unb2_minimal_gmi)
     - Clock, reset, PPS, flash, fpga regmap info from YAML
     - MM bus and ARGS
@@ -65,8 +120,7 @@ Firmware infrastructure
     - M&C software
     - Coding style (constants package derived from parameters in doc)
     
-
-Firmware architecture
+* Firmware architecture
   . Application overview  (array notation of interfaces and packets, ...)
     - ADC ingress and time stamp
     - Subband filterbank (critically sampled)
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt b/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
index fa252fc30377578b6b3e2fa29f33858f3d85d967..12e9287ab6be6d4a8541dbadc8732a36daeb3c2e 100755
--- a/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
@@ -621,6 +621,13 @@ all    12-2021  CDR       M Complete SDP document package for Station CDR
 * Q1 = Increment 1 Lab Test Station (LTS)
 *******************************************************************************
 
+LTS = RCU2_ANA (Italian, hack RCU1?)
+      RCU2_DIG + midplane + unb2b + power + clock + control OPC-UA
+	  GS: march 2020: 6wk devel, 3 wk order, 3w make
+	  BH: Test case --> requirements
+DTS = PCC
+	  BH: requirements --> Test case
+
 Main deliverables
 - EK: D19/20 SDP design documents for LTS
 - EK: D41 ICD SC-SDP for unb2b_minimal_gp
@@ -716,21 +723,8 @@ BSP - PD
 2) D42 SDP OPC-UA server prototype
 
 l2SDP-43: L2 STAT DD Location of SC-SDP translator function
-         Update downselect of location of OPC-UA translator (combined task of
-         SDP and station Control)
-         - different types of M&C (volume, high rate, low rate, time critical)
-           . only the low rate M&C will go via OPC-UA, so BF weights and statistics via
-             a separate UDP path between LCU2 and SDP
-           . what abpout high volume write flash (readback)
-         - BF weights with timestamp to apply in future, or immediately if in
-           the past.
-         - Statistics read or stream at PPS or shorter intervals. Also stream
-           low rate BST, because streaming is for any time critical monitoring
-           not only for high rate time critical.
 l2SDP-32: L3 SDP DD Monitoring and Control
          Finish downselect of Gemini Protocol and Uniboard COntrol Protocol
-         (mainly task within SDP)
-         - GP-UCP, QSYS-RTL, NiosII-RTL
          - risk of delay due to:
            . complexity of porting to VHDL (64b-32b, Axi-Avalon, IP data mover)
            . low TRL of GP
@@ -772,6 +766,14 @@ Jira EK : L5 SDP DD ADC input and timing
              - new BSN source with BSN offset
           
 
+*******************************************************************************
+* New sprint
+*******************************************************************************
+- how are you
+- retrospective last sprints
+- tasks for next sprint + availability
+- sprint goal (e.g. achieve some test case)
+
 
 *******************************************************************************
 * Q2 = Increment 2
@@ -784,3 +786,16 @@ Jira EK : L5 SDP DD ADC input and timing
 - subband correlator on one node
 - beamformer output to CEP
 - ring (Cédric Dumez-Viou ?)
+
+*******************************************************************************
+* Q3,4 2020
+*******************************************************************************
+BF one input --> BF output
+TB DDR4 access R/W via M&C
+
+*******************************************************************************
+* 2021
+*******************************************************************************
+BF full (ring)
+TB one node --> output via 10GbE --> full (ring)
+
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_icd.txt b/applications/lofar2/doc/prestudy/station2_sdp_icd.txt
old mode 100644
new mode 100755
index eae9e9eb74ef969be3faabcfe5dfbd24c6cd3f63..fc4df59b74238af5989fe4e094339c9cc29f9726
--- a/applications/lofar2/doc/prestudy/station2_sdp_icd.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_icd.txt
@@ -20,6 +20,16 @@ ICD interface types:
     d - Data exchange specifications (protocol stack)
     h - Human-Machine Interface (special combination of some of the above) 
 
+ICD template:
+An interface is an agreement between the two interfacing products.
+The interface agreement leads to requirements in the SRS of the interfacing products. The ICD is organised per interface type.
+An definition is a block of facts that can be referred to from one or more interfaces.
+Each L# level has a section header in the ICD.
+Within the level there are interfaces that describe the interface only at that level.
+The lowest level is reach when the interface description is sufficient to implement it.
+From top L# level to implementation L# level the ICD should read like a document. Per level the interface agreements provide more detail and follow the PBS.
+Eye opener: Hence the ICD is like a normal written document, the difference is that all sections are captured by numbered interfaces and definitions in Polarion, so that they can be traced and referred to.
+The template should only contain the structure and hidden information for the editor. The read only text should only contain a link to the ICD general explanations, to ensure that nearly all text is manually written tekst.
 
 
 ###################################################################################################
@@ -187,7 +197,7 @@ b) actuators, sensors
 
 2) Firmware
 a) 1GbE per 4 FPGA / 10GbE at SCU
-b) FPGA register access via Gemini Protocol/UDP/IPv4
+b) FPGA register access via UniBoard Protocol/UDP/IPv4
 c) FPGA register map:
   - BSP : info, PPS, flash
   - ring 
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_m_and_c.txt b/applications/lofar2/doc/prestudy/station2_sdp_m_and_c.txt
old mode 100644
new mode 100755
index eaf504b262098fe26e103f193416d3251b4bb7f3..65b134f8b4b61b6fea6866d814b58da3bf2f4f14
--- a/applications/lofar2/doc/prestudy/station2_sdp_m_and_c.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_m_and_c.txt
@@ -17,6 +17,11 @@ may provide a monitoring point that allows the master to monitor the progress. O
 events that originate in the device it may be necessary to use the publish-subscribe pattern, whereby
 the slave self-generates an event message.
 
+The Station Control (SC) distinguishes between Control and Monitoring and Control (M&C). The Control in SC determines the behaviour of the Station in time. Via M&C the SC can control the Station Digital Processor (SDP) and monitor whether SDP behaves as expected. The SC uses OPC-UA over TCP/IP as standard Station M&C access interface. From SDP point of view all data access points are considered part of SDP M&C, however from SC point of view only a subset of these SDP M&C data points are part of Station M&C, and these are defined in the ICD SC-SDP.
+The SC M&C of SDP concerns two seperate parts:
+
+* The SDP Hardware is controlled via OPC-UA in the Control subrack in the STCA (STCACO).
+* The SDP Firmware is controlled via OPC-UA in the SDP Translator (SDPT). The complete memory map of all data access points in the SDP Firmware is defined by a configuration file that can be read from the SDP Firmware.
 
 *******************************************************************************
 * M&C of SDP firmware
@@ -27,6 +32,33 @@ SDP converter/bridge that translates between the FPGA memory map and OPC-UA [4.1
 it may be possible to generate the device specific parts of the bridge software, because the number
 of FPGAs and all register fields in the FPGA memory map are known [4.1.2.5.1].
 
+Relevant L2 requirements for SDP monitoring points (BH):
+- station self-test (LOFAR2-8113)
+- station health-test (LOFAR2-8119 )
+- operationele aspecten (LOFAR2-8193 )
+
+*******************************************************************************
+* Update scheme for the beamlet weigths
+*******************************************************************************
+
+For the beamformer weights an update period of about once every 4.5 s is fast enough for all astronomical observations [AD-2f] --> BH partioniong rationale for LOFAR2-4392. In LOFAR1 the beamlet weights were applied at every pulse per second (PPS), so every 1 s [RD-8]. The required update rate of the beamlet weigths depends on the beamlet pointing, however all beamlet weigths are controlled as a set, and the beamlets may point in any direction, so therefore the update rate needs to be at least once every 4.5 s. Using a faster update rate makes the beamformer more robust to occasionally loosing an update, because then the previous weigths will still apply well. Table 3.1 lists beamlet weight update schemes that are all suitable for a LOFAR2.0 Station.
+
+Table  Possible beamlet weigths update scheme options for the SC-SDP ICD
+
+Option Beamlet weights update scheme                       SDP weigths memory   Timing
+ A     SDP applies weights immediately when received       Single buffer        Asynchronous
+ B     SDP applies weights at the next PPS                 Dual buffer          Synchronous with fixed timing grid as in LOFAR1
+ C     SDP applies weights at a timestamp specified by SC  Dual buffer          Synchronous with flexible timing grid
+
+Comparison of the beamlet weigths update schemes in Table:
+
+* The advantage of scheme A and C compared to scheme B of LOFAR is that they are less time critica, because they are not tight to thefixed 1 s grid of the PPS.
+* The advantage of scheme A compared to scheme B and C is that it takes less weights memory in SDP, but the weights memory is not a critical resource for SDP
+* The advantage of scheme C compared to scheme A is that the weights can be send in advance, which relaxes the real time constraints on the SC to about 4.5 s.
+
+All schemes in Table can be applied via the SDP Translator as well as via the bypass control path. Scheme C is the most relaxed regarding the real time constrains on the SC and scheme C is quite feasible to realize in the SDP Firmware. Therefore assume that the SC-SDP ICD will specify using scheme C to update the beamlet weights (note that in [AD-2f] a mix of scheme A and scheme B was proposed, so SC sends control every 1 s and SDP applies immediately when received).
+
+Design decision: Use option C.
   
   
 *******************************************************************************
@@ -168,12 +200,62 @@ Behaviour of the data points:
   . SYnc, dual page control, periodic event page swap at sync when last value was written (so only then swap)
     - DP_FRINGE_STOP_OFFSET
                           
-                               
+*******************************************************************************
+* TCP and UDP OSI TRansport layer protocols
+*******************************************************************************
+
+[1] https://en.wikibooks.org/wiki/Communication_Networks/TCP_and_UDP_Protocols
+[2] TCP = Transmission Control Protocol (RFC 793)
+[3] UDP = User Datagram Protocol (RFC 768)
+
+TCP is a connection oriented protocol and is used when the data transfer needs to be intact and complete (e.g. files).
+
+ - retransmit corrupt or lost datagrams
+ - remove duplicate datagrams
+ - reassemble datagrams in the proper order
+ - rate adaption dependent on the throughput capacity of the network and the receiver
+ - fragmentation of application data into datagrams [1]
+ 
+UDP is a transaction oriented and connectionless protocol and is used when the data transfer needs low latency and lost data may remain lost (e.g. video). The data interface to the application is discrete packets.
+
+
+IP takes care of:
+- addressing
+- fragmentation of datagrams, to support transport across different networks
+- time to live to self destruct datagrams that take too many hops to reach their destination
+
+Ethernet
+- identifying and encapsulating network layer protocols into an Ethernet frame
+- error checking
+- flow control
+- medium access control
+
+
+A socket pair identifies both ends of a connection, i.e. the virtual circuit [3]. For UDP the end-to-end connection identified by the source MAC, IP and UDP port tuple and destination MAC, IP and UDP port is sufficient, because UDP operates per datagram [3]. For TCP in addition a connection needs to be setup, because TCP needs to maintain the state of multiple datagrams that are communicated [2].
+
+To make a reliable transport protocol involves:
+
+- Connection handling (keep track of a connection)
+- Sequencing (to rely on order of frames)
+- Acknowledgement (to make sure all frames are received)
+- Flow control (throttle the flow of data)
+
+Client server + MM transaction
+Reliable communciation
+
+MM transaction
+- REG, RAM, FIFO
+
+Verify flash
+- using readback is necessary with UCP due to that it uses a MM-DP fifo.
+- the transaction from FPGA to flash on UniBoard should preferrably have been readback already for each write request.
+
+*******************************************************************************
+* Conclusion:
+*******************************************************************************
 
-                                 
-Conclusion:
 - Identify casue of error preferrably via a single monitoring point
 - With proper monitoring no test time is needed
-- Support writing status fields in a test mpd for SW - FW interface testing 
+- Support writing status fields in a test mode for SW - FW interface testing 
 - Use 1 s sync interval of PPS to time period M&C events for all. Optionally support a local BSN scheduler
   for the XST.
diff --git a/applications/lofar2/doc/prestudy/station2_sdp_srs.txt b/applications/lofar2/doc/prestudy/station2_sdp_srs.txt
index 773445b4e0a8069cfa1b9effeb458aacc4fad527..d746394cc07a9d48053b47fa9cad3127747bdeaf 100755
--- a/applications/lofar2/doc/prestudy/station2_sdp_srs.txt
+++ b/applications/lofar2/doc/prestudy/station2_sdp_srs.txt
@@ -23,6 +23,7 @@ LOFAR2-3187 Simultaneous existance of production modes
 LOFAR2-3269 Justification of single-points of failure
 LOFAR2-4000 Robustness: No single point of failure
 LOFAR2-4001 Graceful degradation
+
 . Monitor HW, FW and interfaces --> Ring, 1GbE, 10GbE, DDR4, PPS, JESD
 LOFAR2-3227 x--> 3248
 LOFAR2-3209 Monitoring in Hybernate State
diff --git a/libraries/base/diag/hdllib.cfg b/libraries/base/diag/hdllib.cfg
index 8b5452b5c4b6ee04dcd8f2ae78e6805d2ef09a40..71f326b22ef7b7736cc1ae0947466d33ca72b006 100644
--- a/libraries/base/diag/hdllib.cfg
+++ b/libraries/base/diag/hdllib.cfg
@@ -18,6 +18,7 @@ synth_files =
     src/vhdl/diag_wg_wideband.vhd
     src/vhdl/diag_wg_wideband_reg.vhd
     src/vhdl/mms_diag_wg_wideband.vhd
+    src/vhdl/mms_diag_wg_wideband_arr.vhd
     src/vhdl/diag_data_buffer.vhd
     src/vhdl/diag_data_buffer_dev.vhd
     src/vhdl/mms_diag_data_buffer.vhd
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d5cdd64377eeacac7e6c8cad33ae7f234e0977df
--- /dev/null
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
@@ -0,0 +1,170 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Provides a wideband WG by using multiple diag_wg
+-- Description:
+-- Remarks:
+-- Remarks:
+-- . For g_wideband_factor=1 this diag_wg_wideband defaults to diag_wg. Hence
+--   no need to make a mms_diag_wg.vhd.
+
+LIBRARY IEEE, common_lib, technology_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE work.diag_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+
+ENTITY mms_diag_wg_wideband_arr IS
+  GENERIC (
+    g_technology         : NATURAL := c_tech_select_default;
+    -- Use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+    g_nof_streams        : POSITIVE := 1;
+    g_cross_clock_domain : BOOLEAN := TRUE;
+    
+    -- Use g_buf_dir to be able to have different path to waveform file for sim and for synth
+    g_buf_dir            : STRING := "data/";
+    
+    -- Wideband parameters
+    g_wideband_factor    : NATURAL := 4;      -- Wideband rate factor >= 1 for unit frequency of g_wideband_factor * Fs
+    
+    -- Basic WG parameters, see diag_wg.vhd for their meaning
+    g_buf_dat_w          : NATURAL := 18;
+    g_buf_addr_w         : NATURAL := 11;
+    g_calc_support       : BOOLEAN := TRUE;
+    g_calc_gain_w        : NATURAL := 1;
+    g_calc_dat_w         : NATURAL := 12
+  );
+  PORT (
+    -- Memory-mapped clock domain
+    mm_rst               : IN  STD_LOGIC;
+    mm_clk               : IN  STD_LOGIC;
+
+    reg_mosi             : IN  t_mem_mosi;
+    reg_miso             : OUT t_mem_miso;
+    
+    buf_mosi             : IN  t_mem_mosi;
+    buf_miso             : OUT t_mem_miso;
+    
+    -- Streaming clock domain
+    st_rst               : IN  STD_LOGIC;
+    st_clk               : IN  STD_LOGIC;
+    st_restart           : IN  STD_LOGIC := '0';
+
+    out_sosi_arr         : OUT  t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
+  );
+END mms_diag_wg_wideband_arr;
+
+
+ARCHITECTURE str OF mms_diag_wg_wideband_arr IS
+
+  CONSTANT c_reg_adr_w    : NATURAL := ceil_log2(2);
+  CONSTANT c_buf_adr_w    : NATURAL := ceil_log2(10);
+    
+  SIGNAL reg_mosi_arr     : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL reg_miso_arr     : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 
+  SIGNAL buf_mosi_arr     : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL buf_miso_arr     : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 
+
+  SIGNAL wg_ovr           : STD_LOGIC_VECTOR(g_nof_streams*g_wideband_factor            -1 DOWNTO 0);  -- big endian, so first output sample in MSBit, MSData
+  SIGNAL wg_dat           : STD_LOGIC_VECTOR(g_nof_streams*g_wideband_factor*g_buf_dat_w-1 DOWNTO 0);
+  SIGNAL wg_val           : STD_LOGIC_VECTOR(g_nof_streams*g_wideband_factor            -1 DOWNTO 0);
+  SIGNAL wg_sync          : STD_LOGIC_VECTOR(g_nof_streams*g_wideband_factor            -1 DOWNTO 0);
+
+BEGIN
+
+  u_common_mem_mux_reg : ENTITY common_lib.common_mem_mux
+  GENERIC MAP (    
+    g_nof_mosi    => g_nof_streams,
+    g_mult_addr_w => c_reg_adr_w
+  )
+  PORT MAP (
+    mosi     => reg_mosi,
+    miso     => reg_miso,
+    mosi_arr => reg_mosi_arr,
+    miso_arr => reg_miso_arr
+  );
+
+  u_common_mem_mux_buf : ENTITY common_lib.common_mem_mux
+  GENERIC MAP (    
+    g_nof_mosi    => g_nof_streams,
+    g_mult_addr_w => c_buf_adr_w
+  )
+  PORT MAP (
+    mosi     => buf_mosi,
+    miso     => buf_miso,
+    mosi_arr => buf_mosi_arr,
+    miso_arr => buf_miso_arr
+  );
+
+  gen_wg : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    u_mms_diag_wg_wideband : ENTITY work.mms_diag_wg_wideband
+    GENERIC MAP (
+      g_technology         => g_technology,
+      g_cross_clock_domain => g_cross_clock_domain,
+      g_buf_dir            => g_buf_dir,
+      g_wideband_factor    => g_wideband_factor,   
+      g_buf_dat_w          => g_buf_dat_w,
+      g_buf_addr_w         => g_buf_addr_w,
+      g_calc_support       => g_calc_support,
+      g_calc_gain_w        => g_calc_gain_w,
+      g_calc_dat_w         => g_calc_dat_w
+    )
+    PORT MAP (
+   -- Memory-mapped clock domain
+      mm_rst               => mm_rst,
+      mm_clk               => mm_clk,
+
+      reg_mosi             => reg_mosi_arr(I),
+      reg_miso             => reg_miso_arr(I),
+    
+      buf_mosi             => buf_mosi_arr(I),
+      buf_miso             => buf_miso_arr(I),
+    
+      -- Streaming clock domain
+      st_rst               => st_rst,
+      st_clk               => st_clk,
+      st_restart           => st_restart,
+
+      out_ovr              => wg_ovr( (I+1)*g_wideband_factor            -1 DOWNTO I*g_wideband_factor            ),
+      out_dat              => wg_dat( (I+1)*g_wideband_factor*g_buf_dat_w-1 DOWNTO I*g_wideband_factor*g_buf_dat_w),
+      out_val              => wg_val( (I+1)*g_wideband_factor            -1 DOWNTO I*g_wideband_factor            ),
+      out_sync             => wg_sync((I+1)*g_wideband_factor            -1 DOWNTO I*g_wideband_factor            )
+  );
+
+
+    -- wire the wg signals to sosi outputs
+    -- This is done as per the method used in unb1_bn_capture_input (Apertif)
+    -- . all wideband samples will be valid in parallel, so using vector_or() or vector_and() is fine
+    -- . if one of the wideband sample has overflow, then set the overflow error, so use vector_or()
+    out_sosi_arr(I).data  <= RESIZE_DP_SDATA(wg_dat( (I+1)*g_wideband_factor*g_buf_dat_w-1 DOWNTO I*g_wideband_factor*g_buf_dat_w));
+    out_sosi_arr(I).valid <=       vector_or(wg_val( (I+1)*g_wideband_factor            -1 DOWNTO I*g_wideband_factor            ));
+    out_sosi_arr(I).sync  <=       vector_or(wg_sync((I+1)*g_wideband_factor            -1 DOWNTO I*g_wideband_factor            ));
+    out_sosi_arr(I).err   <= TO_DP_ERROR(0) WHEN
+                                  vector_or(wg_ovr( (I+1)*g_wideband_factor             -1 DOWNTO I*g_wideband_factor            ))='0' ELSE
+                            TO_DP_ERROR(2**7);  -- pass ADC or WG overflow info on as an error signal
+
+ 
+  END GENERATE;
+ 
+END str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index c421daa4c7752c4da19427d7dc638c3a35b23422..d36166ae617efaf3d60c7c5214d84eb47d8120e5 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -62,7 +62,7 @@ ENTITY dp_fifo_dc IS
     snk_out     : OUT t_dp_siso;
     snk_in      : IN  t_dp_sosi;
     -- ST source
-    src_in      : IN  t_dp_siso;
+    src_in      : IN  t_dp_siso := c_dp_siso_rdy;
     src_out     : OUT t_dp_sosi
   );
 END dp_fifo_dc;
diff --git a/libraries/io/aduh/hdllib.cfg b/libraries/io/aduh/hdllib.cfg
index 281df2877a498bc15e2dc7bda73db19a9f3e62e6..0813bc7a7ef6de0f00f2f32883306c14e22d6847 100644
--- a/libraries/io/aduh/hdllib.cfg
+++ b/libraries/io/aduh/hdllib.cfg
@@ -21,6 +21,7 @@ synth_files =
     src/vhdl/aduh_quad_reg.vhd      
     src/vhdl/aduh_quad_scope.vhd    
     src/vhdl/mms_aduh_monitor.vhd   
+    src/vhdl/mms_aduh_monitor_arr.vhd   
     src/vhdl/mms_aduh_quad.vhd      
     
 test_bench_files = 
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b70f97da90909fbddf627f5578ec433cd00faf40
--- /dev/null
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
@@ -0,0 +1,127 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib, diag_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+-- Purpose : Monitor signal path statistics (array version)
+-- Description :
+--   Array wrapper to allow insatntiation of g_nof_streams channel ADUH
+-- Remarks:
+
+ENTITY mms_aduh_monitor_arr IS
+  GENERIC (
+    g_cross_clock_domain   : BOOLEAN := TRUE;       -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+    g_nof_streams          : POSITIVE := 1;
+    g_symbol_w             : NATURAL := 8;
+    g_nof_symbols_per_data : NATURAL := 4;          -- big endian in_data, t0 in MSSymbol, so [h:0] = [t0]&[t1]&[t2]&[t3]
+    g_nof_accumulations    : NATURAL := 800*10**6;  -- integration time in symbols, defines internal accumulator widths
+    g_buffer_nof_symbols   : NATURAL := 1024;
+    g_buffer_use_sync      : BOOLEAN := FALSE       -- when TRUE start filling the buffer after the in_sync, else after the last word was read
+  );
+  PORT (
+    -- Memory-mapped clock domain
+    mm_rst     : IN  STD_LOGIC;
+    mm_clk     : IN  STD_LOGIC;
+    
+    reg_mosi   : IN  t_mem_mosi;  -- read only access to the mean_sum and power_sum
+    reg_miso   : OUT t_mem_miso;
+    buf_mosi   : IN  t_mem_mosi;  -- read and overwrite access to the data buffer
+    buf_miso   : OUT t_mem_miso;
+    
+    -- Streaming clock domain
+    st_rst     : IN  STD_LOGIC;
+    st_clk     : IN  STD_LOGIC;
+    
+    in_sosi_arr: IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)    
+  );
+END mms_aduh_monitor_arr;
+
+
+ARCHITECTURE str OF mms_aduh_monitor_arr IS
+
+  CONSTANT c_reg_adr_w    : NATURAL := ceil_log2(2);
+  CONSTANT c_buf_adr_w    : NATURAL := ceil_log2(8);
+
+  SIGNAL reg_mosi_arr     : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL reg_miso_arr     : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 
+  SIGNAL buf_mosi_arr     : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL buf_miso_arr     : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 
+
+  
+BEGIN
+
+  u_common_mem_mux_reg : ENTITY common_lib.common_mem_mux
+  GENERIC MAP (    
+    g_nof_mosi    => g_nof_streams,
+    g_mult_addr_w => c_reg_adr_w
+  )
+  PORT MAP (
+    mosi     => reg_mosi,
+    miso     => reg_miso,
+    mosi_arr => reg_mosi_arr,
+    miso_arr => reg_miso_arr
+  );
+
+  u_common_mem_mux_buf : ENTITY common_lib.common_mem_mux
+  GENERIC MAP (    
+    g_nof_mosi    => g_nof_streams,
+    g_mult_addr_w => c_buf_adr_w
+  )
+  PORT MAP (
+    mosi     => buf_mosi,
+    miso     => buf_miso,
+    mosi_arr => buf_mosi_arr,
+    miso_arr => buf_miso_arr
+  );
+
+  gen_aduh_monitor : FOR I IN 0 TO g_nof_streams-1 GENERATE
+    u_mms_aduh_monitor : ENTITY work.mms_aduh_monitor
+    GENERIC MAP (
+      g_cross_clock_domain   => g_cross_clock_domain,
+      g_symbol_w             => g_symbol_w,
+      g_nof_symbols_per_data => g_nof_symbols_per_data,
+      g_nof_accumulations    => g_nof_accumulations,
+      g_buffer_nof_symbols   => g_buffer_nof_symbols,
+      g_buffer_use_sync      => g_buffer_use_sync
+   )
+    PORT MAP (
+      -- Clocks and reset
+      mm_rst                 => mm_rst,
+      mm_clk                 => mm_clk,
+      st_rst                 => st_rst,
+      st_clk                 => st_clk,
+    
+      -- Memory Mapped Slave in mm_clk domain
+      reg_mosi               => reg_mosi_arr(I),
+      reg_miso               => reg_miso_arr(I),
+      buf_mosi               => buf_mosi_arr(I),
+      buf_miso               => buf_miso_arr(I),
+    
+      -- Streaming inputs
+      in_sosi                => in_sosi_arr(I)
+    );
+  END GENERATE;
+  
+END str;
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
index 3de92111d3a77ab97db8a7b966c2a42b09119285..0299c5007222a2bcd0684eb28b4a37b6f572135f 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
@@ -2,8 +2,8 @@
 hdl_lib_name = ip_arria10_e1sg_jesd204b
 hdl_library_clause_name = ip_arria10_e1sg_jesd204b_lib
 hdl_lib_uses_synth = technology tech_pll common dp
-# hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180
-hdl_lib_uses_sim =
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180
+# hdl_lib_uses_sim =
 hdl_lib_technology = ip_arria10_e1sg 
 
 synth_files =
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 8f51551b8db170520bae645cc241cc9e32bbd99b..2d2db8edf768156d7d85d81ccb6fb2a4a96b6c82 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -24,7 +24,8 @@
 -- Purpose: Combine IP components needed to create a JESD204B interface
 --   Initially supports RX_ONLY for receiving data from an ADC
 -- Description 
---   
+--   Currently only 12 streams because of the 12 channel reset block
+--   The sync_n signals are gated together to form g_nof_sync_n outputs
 --  
 
 --LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_rx, ip_arria10_e1sg_jesd204b_rx_reset_seq, ip_arria10_e1sg_jesd204b_rx_core_pll, ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
@@ -39,18 +40,21 @@ USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
 ENTITY ip_arria10_e1sg_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_nof_channels        : NATURAL := 1;
+    g_nof_streams         : NATURAL := 1;
+    g_nof_sync_n          : NATURAL := 1;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
   PORT (
     -- JESD204B external signals
     jesd204b_refclk       : IN STD_LOGIC := '0';                             -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
     jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
-    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);  -- output to control ADC initialization/syncronization phase
     
     -- Data to fabric
-    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';                           -- Regenerated data clock to fabric
+    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    -- Parallel data out to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -60,8 +64,8 @@ ENTITY ip_arria10_e1sg_jesd204b IS
     jesd204b_miso         : OUT t_mem_miso; 
          
     -- Serial connections to transceiver pins
-    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);      -- Not used for ADC
-    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);      -- Not used for ADC
+    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
   );
 END ip_arria10_e1sg_jesd204b;
 
@@ -74,12 +78,13 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
   CONSTANT c_jesd204b_rx_framer_data_w     : NATURAL :=c_jesd204b_rx_data_w/2; -- IP outputs two samples in parallel
   CONSTANT c_jesd204b_rx_somf_w            : NATURAL :=c_jesd204b_rx_data_w/8; -- One somf bit per octet
   CONSTANT c_jesd204b_rx_framer_somf_w     : NATURAL :=c_jesd204b_rx_somf_w/2; -- IP outputs two samples in parallel
+  CONSTANT c_nof_sync_n_per_group          : NATURAL :=sel_a_b(g_nof_streams / g_nof_sync_n = 0, 1, g_nof_streams / g_nof_sync_n);
 
   -- JESD204 control status registers
-  SIGNAL jesd204b_mosi_arr          : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
-  SIGNAL jesd204b_miso_arr          : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0); 
-  SIGNAL reset_seq_mosi_arr         : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
-  SIGNAL reset_seq_miso_arr         : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst); 
+  SIGNAL jesd204b_mosi_arr          : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
+  SIGNAL jesd204b_miso_arr          : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0); 
+  SIGNAL reset_seq_mosi_arr         : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+  SIGNAL reset_seq_miso_arr         : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst); 
 
   -- Clocks
   SIGNAL rxframe_clk                : STD_LOGIC; 
@@ -87,33 +92,37 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
   SIGNAL jesd204b_avs_clk           : STD_LOGIC;
 
   -- Reset and control signals
-  SIGNAL dev_lane_aligned           : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);  -- 1 bit, each interface channel has 1 lane
-  SIGNAL rx_analogreset_arr         : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);                
-  SIGNAL rx_cal_busy_arr            : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_digitalreset_arr        : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_islockedtodata_arr      : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL dev_lane_aligned_arr       : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_csr_lane_powerdown_arr  : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_xcvr_ready_in_arr       : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL pll_reset_arr              : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL xcvr_rst_arr               : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS => '1');               
-  SIGNAL rx_avs_rst_arr             : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rxlink_rst_arr             : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rxframe_rst_arr            : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rx_avs_rst_n_arr           : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rxlink_rst_n_arr           : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL rxframe_rst_n_arr          : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL f2_div1_cnt_arr            : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
+  SIGNAL dev_lane_aligned           : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);  -- 1 bit, each interface channel has 1 lane
+  SIGNAL rx_analogreset_arr         : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);                
+  SIGNAL rx_cal_busy_arr            : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_digitalreset_arr        : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_islockedtodata_arr      : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL dev_lane_aligned_arr       : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_csr_lane_powerdown_arr  : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_xcvr_ready_in_arr       : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL pll_reset_arr              : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL xcvr_rst_arr               : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1');               
+  SIGNAL rx_avs_rst_arr             : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rxlink_rst_arr             : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rxframe_rst_arr            : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rx_avs_rst_n_arr           : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rxlink_rst_n_arr           : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL rxframe_rst_n_arr          : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL f2_div1_cnt_arr            : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
   SIGNAL core_pll_locked            : STD_LOGIC;               
   SIGNAL core_pll_locked_reg        : STD_LOGIC;               
   SIGNAL jesd204b_sysref_1          : STD_LOGIC;               
   SIGNAL jesd204b_sysref_2          : STD_LOGIC;               
+  SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;               
+  SIGNAL jesd204b_sysref_frameclk_2 : STD_LOGIC;               
 
   -- Data path
-  SIGNAL jesd204b_rx_link_data_arr  : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_channels-1 DOWNTO 0);               
-  SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);               
-  SIGNAL jesd204b_rx_somf_arr       : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w*g_nof_channels-1 DOWNTO 0);               
+  SIGNAL jesd204b_rx_link_data_arr  : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_streams-1 DOWNTO 0);               
+  SIGNAL jesd204b_rx_link_valid_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);               
+  SIGNAL jesd204b_rx_somf_arr       : STD_LOGIC_VECTOR(c_jesd204b_rx_somf_w*g_nof_streams-1 DOWNTO 0);               
+
+  SIGNAL jesd204b_sync_n_internal_arr   : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);  -- output to control ADC initialization/syncronization phase
 
 
   -- Component declarations for the IP blocks
@@ -221,7 +230,8 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
 
 BEGIN
 
-  jesd204b_frame_clk <= rxframe_clk;
+  rx_clk <= rxframe_clk;
+  rx_rst <= not core_pll_locked;
 
   -- The avs clock is driven by the rxlink_clk for simulation. This is a workaround for a bug 
   -- in the Q18.0 IP where the jesd receiver fails to recognize the SYSREF pulse
@@ -236,7 +246,7 @@ BEGIN
 
   
   gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
-    gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_channels-1 GENERATE
+    gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
   
       -----------------------------------------------------------------------------
       -- The JESD204 IP (rx only)
@@ -259,8 +269,8 @@ BEGIN
         csr_rx_testmode            => OPEN, 
         csr_s                      => OPEN, 
         dev_lane_aligned           => dev_lane_aligned_arr(i),           
-        dev_sync_n                 => jesd204b_sync_n_arr(i),
-        jesd204_rx_avs_chipselect         => '0', --jesd204b_mosi_arr(i).chipselect,
+        dev_sync_n                 => jesd204b_sync_n_internal_arr(i),
+        jesd204_rx_avs_chipselect         => '1', --jesd204b_mosi_arr(i).chipselect,
         jesd204_rx_avs_address            => jesd204b_mosi_arr(i).address(c_jesd204b_mm_addr_w-1 downto 0),
         jesd204_rx_avs_read               => jesd204b_mosi_arr(i).rd,
         jesd204_rx_avs_readdata           => jesd204b_miso_arr(i).rddata(31 downto 0),
@@ -377,6 +387,28 @@ BEGIN
       END IF;
     END PROCESS;
 
+    -----------------------------------------------------------------------------
+    -- Capture sysref on the frame clock for export
+    -----------------------------------------------------------------------------
+    p_rx_sysref : PROCESS (rxframe_clk, core_pll_locked)
+    BEGIN
+      IF core_pll_locked = '0' THEN
+        jesd204b_sysref_frameclk_1 <= '0';
+        jesd204b_sysref_frameclk_2 <= '0';
+        rx_sysref <= '0';
+      ELSE
+        IF rising_edge(rxframe_clk) THEN
+          jesd204b_sysref_frameclk_1 <= jesd204b_sysref;
+          jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
+          IF jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' THEN
+            rx_sysref <= '1';
+          ELSE
+            rx_sysref <= '0';
+          END IF;
+        END IF;
+      END IF;
+    END PROCESS;
+
   
     -- IOPLL in source synchronous or normal mode. (Intel JESD204B-UG p66)
     u_ip_arria10_e1sg_jesd204b_rx_corepll : ip_arria10_e1sg_jesd204b_rx_core_pll
@@ -400,7 +432,7 @@ BEGIN
     END PROCESS;
  
 
-    -- Transceiver reset controller. Use g_nof_channels out of 12 channels. Receive only
+    -- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
     -- Clock set to 100MHz (use mm_clk)
 
     u_ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
@@ -416,12 +448,20 @@ BEGIN
 
   END GENERATE;
 
+
+  -----------------------------------------------------------------------------
+  -- Group the SYNC_N outputs
+  -----------------------------------------------------------------------------
+  gen_group_sync_n : FOR i IN 0 TO g_nof_sync_n-1 GENERATE
+      jesd204b_sync_n_arr(i) <= vector_and(jesd204b_sync_n_internal_arr(c_nof_sync_n_per_group*i+c_nof_sync_n_per_group-1 downto c_nof_sync_n_per_group*i));
+  END GENERATE;
+
   -----------------------------------------------------------------------------
   -- MM bus mux
   -----------------------------------------------------------------------------
   u_common_mem_mux_mac : ENTITY common_lib.common_mem_mux
   GENERIC MAP (    
-    g_nof_mosi    => g_nof_channels,
+    g_nof_mosi    => g_nof_streams,
     g_mult_addr_w => c_jesd204b_mm_addr_w 
   )
   PORT MAP (
diff --git a/libraries/technology/jesd204b/hdllib.cfg b/libraries/technology/jesd204b/hdllib.cfg
index 622e2554b8ff8e95c0575a225af553ac3e376839..26c30b19cb5fbf3936010a78cb3a2aba00046c15 100644
--- a/libraries/technology/jesd204b/hdllib.cfg
+++ b/libraries/technology/jesd204b/hdllib.cfg
@@ -17,7 +17,7 @@ synth_files =
 
 test_bench_files =
 #    tb_tech_jesd204b_pkg.vhd
-#    tb_tech_jesd204b.vhd
+    tb_tech_jesd204b.vhd
 #    tb_tb_tech_jesd204b.vhd
 
 regression_test_vhdl = 
@@ -26,7 +26,7 @@ regression_test_vhdl =
 
 [modelsim_project_file]
 modelsim_copy_files =
-#    wave_tb_tech_jesd204b.do .
+    wave_tb_tech_jesd204b.do .
     
 
 [quartus_project_file]
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..500d94b4c885746cecaebe4c8ebaa976b52a1eea
--- /dev/null
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -0,0 +1,455 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2020
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author: J Hargreaves
+-- Purpose: Tb for tech_jesd204b IP
+-- Description:
+--   Includes 3 JESD transmit sources to test multichannel syncronization
+--   Relative delays between TX and RX channels can be varied by editing c_delay_*
+--   ToDo: Make a tb_tb to run several test cases automatically
+-- Usage:
+--   Load sim    # check that design can load in vsim
+--   > as 3      # check that the hierarchy for g_design_name is complete (or use do wave_tb_tech_jesd204b.do)
+--   > run 120us # enough time to reset and syncronize the JESD IP
+
+LIBRARY IEEE, common_lib, ip_arria10_e1sg_jesd204b_lib, dp_lib; --, tech_jesd204b_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
+
+ENTITY tb_tech_jesd204b IS
+END tb_tech_jesd204b;
+
+ARCHITECTURE tb OF tb_tech_jesd204b IS
+
+  CONSTANT c_sim                      : BOOLEAN := TRUE;
+
+  CONSTANT c_jesd204b_sampclk_period  : TIME := 5 ns;
+  CONSTANT c_bondingclk_period        : TIME := 10 ns;
+  CONSTANT c_sysref_period            : NATURAL := 10000; -- number of sample clocks between sysref pulses
+
+  CONSTANT c_nof_jesd204b_tx          : NATURAL := 3;  -- number of jesd204b input sources to instantiate
+  CONSTANT c_nof_streams_jesd204b     : NATURAL := 12; -- number of jesd204b receiver channels
+
+  -- Transport delays
+  TYPE t_time_arr            IS ARRAY (0 TO c_nof_streams_jesd204b-1) OF TIME;
+  CONSTANT c_delay_data_arr     : t_time_arr := (4000 ps, 
+                                                 5000 ps,
+                                                 6000 ps, 
+                                                 5000 ps, 
+                                                 5000 ps,
+                                                 5000 ps,
+                                                 5000 ps,
+                                                 5000 ps,
+                                                 5000 ps,
+                                                 5000 ps,
+                                                 5000 ps,
+                                                 5000 ps) ;  -- transport delays tx to rx data
+  CONSTANT c_delay_sysreftoadc_arr : t_time_arr := (4000 ps,
+                                                 5000 ps,
+                                                 6000 ps, 
+                                                 1000 ps, 
+                                                 1000 ps,
+                                                 1000 ps,
+                                                 1000 ps,
+                                                 1000 ps,
+                                                 1000 ps,
+                                                 1000 ps,
+                                                 1000 ps,
+                                                 1000 ps) ;  -- transport delays clock source to adc(tx)
+  CONSTANT c_delay_sysreftofpga : TIME := 10200 ps;
+
+
+
+  -- clocks and resets for the jesd204b tx
+  SIGNAL txlink_clk          : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+  SIGNAL dev_sync_n          : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+  SIGNAL txphy_clk           : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+  SIGNAL mm_rst              : STD_LOGIC;
+  SIGNAL avs_rst_n           : STD_LOGIC;
+  SIGNAL txlink_rst_n        : STD_LOGIC;
+  SIGNAL tx_analogreset      : STD_LOGIC_VECTOR(0 downto 0);
+  SIGNAL tx_digitalreset     : STD_LOGIC_VECTOR(0 downto 0);
+  SIGNAL tx_bonding_clocks   : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
+  SIGNAL bonding_clock_0     : STD_LOGIC := '0';
+  SIGNAL bonding_clock_1     : STD_LOGIC := '0';
+  SIGNAL bonding_clock_2     : STD_LOGIC := '0';
+  SIGNAL bonding_clock_3     : STD_LOGIC := '0';
+  SIGNAL bonding_clock_4     : STD_LOGIC := '0';
+  SIGNAL bonding_clock_5     : STD_LOGIC := '0';
+  SIGNAL pll_locked          : STD_LOGIC_VECTOR(0 downto 0);
+
+  CONSTANT c_mm_clk_period   : TIME := 20 ns;  
+  SIGNAL mm_clk              : STD_LOGIC := '0';
+
+  -- Tb
+  SIGNAL tb_end                      : STD_LOGIC := '0';
+  SIGNAL sim_done                    : STD_LOGIC := '0';
+
+  -- mm control buses
+  -- JESD 
+  SIGNAL jesd204b_mosi               : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL jesd204b_miso               : t_mem_miso := c_mem_miso_rst; 
+                
+  -- serial transceivers
+  SIGNAL serial_tx                   : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0); 
+  SIGNAL bck_rx                      : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 downto 0) := (others => '0');
+
+  -- jesd204b syncronization signals and delayed copies
+  SIGNAL jesd204b_sysref             : STD_LOGIC;
+  SIGNAL jesd204b_sampclk            : STD_LOGIC := '0';
+  SIGNAL rx_clk                      : STD_LOGIC := '0';
+  SIGNAL rx_rst                      : STD_LOGIC := '0';
+  SIGNAL rx_sysref                   : STD_LOGIC := '0';
+  SIGNAL rx_sosi_arr                 : t_dp_sosi_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+
+  SIGNAL jesd204b_sampclk_fpga       : STD_LOGIC := '1';
+  SIGNAL jesd204b_sampclk_adc        : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_sysref_fpga        : STD_LOGIC;
+  SIGNAL jesd204b_sysref_adc         : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_sysref_adc_1       : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_sysref_adc_2       : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_sync_n_adc         : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_sync_n_fpga        : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+    
+  -- Test bench data    
+  SIGNAL jesd204b_tx_link_data_arr   : t_slv_32_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_tx_link_valid      : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_tx_link_ready      : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL jesd204b_tx_frame_ready     : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+
+  -- Diagnostic signals
+  SIGNAL avs_chipselect              : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL avs_read                    : STD_LOGIC_VECTOR(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL avs_readdata                : t_slv_32_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+  SIGNAL avs_address                 : t_slv_8_arr(c_nof_streams_jesd204b-1 DOWNTO 0);
+
+BEGIN
+
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  jesd204b_sampclk <= NOT jesd204b_sampclk AFTER c_jesd204b_sampclk_period/2;  -- JESD sample clock (200MHz) 
+  mm_clk <= not mm_clk after c_mm_clk_period/2;  
+  mm_rst <= '1', '0' after 800 ns;
+
+
+ 
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_jesd204b: ENTITY work.tech_jesd204b 
+  GENERIC MAP(
+    g_sim                => c_sim,                
+    g_nof_streams        => c_nof_streams_jesd204b,
+    g_nof_sync_n         => c_nof_streams_jesd204b        -- Todo: Try three ADCs per RCU share a sync
+  )
+  PORT MAP(
+    jesd204b_refclk      => jesd204b_sampclk_fpga,   
+    jesd204b_sysref      => jesd204b_sysref_fpga,   
+    jesd204b_sync_n_arr  => jesd204b_sync_n_fpga,   
+  
+    rx_sosi_arr          => rx_sosi_arr,          
+    rx_clk               => rx_clk,          
+    rx_rst               => rx_rst,          
+    rx_sysref            => rx_sysref,          
+  
+    -- MM
+    mm_clk               => mm_clk,           
+    mm_rst               => mm_rst,           
+  
+    jesd204b_mosi        => jesd204b_mosi,         
+    jesd204b_miso        => jesd204b_miso,         
+  
+     -- Serial
+    serial_tx_arr        => open,
+    serial_rx_arr        => bck_rx(c_nof_streams_jesd204b-1 downto 0)
+  );
+
+
+
+  -----------------------------------------------------------------------------
+  -- Transport 
+  -----------------------------------------------------------------------------
+
+  gen_transport : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
+    jesd204b_sampclk_adc(i) <= transport jesd204b_sampclk after c_delay_sysreftoadc_arr(i);
+    jesd204b_sysref_adc(i)  <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
+--    txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
+    bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
+    jesd204b_sync_n_adc(i) <= transport jesd204b_sync_n_fpga(i) after c_delay_data_arr(i);
+  END GENERATE;
+
+  jesd204b_sampclk_fpga <= transport jesd204b_sampclk after c_delay_sysreftofpga;
+  jesd204b_sysref_fpga <= transport jesd204b_sysref after c_delay_sysreftofpga;
+
+  -----------------------------------------------------------------------------
+  -- Use a jesd204b instance in TX-ONLY modeTransmit Only. 
+  -----------------------------------------------------------------------------
+
+  gen_jesd204b_tx : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
+    u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx
+      PORT MAP 
+      (
+        csr_cf                     => OPEN,
+        csr_cs                     => OPEN,
+        csr_f                      => OPEN, 
+        csr_hd                     => OPEN,
+        csr_k                      => OPEN,
+        csr_l                      => OPEN, 
+        csr_lane_powerdown         => open, --out
+        csr_m                      => OPEN, 
+        csr_n                      => OPEN, 
+        csr_np                     => OPEN, 
+        csr_tx_testmode            => OPEN, 
+        csr_tx_testpattern_a       => OPEN,
+        csr_tx_testpattern_b       => OPEN,
+        csr_tx_testpattern_c       => OPEN,
+        csr_tx_testpattern_d       => OPEN,
+        csr_s                      => OPEN, 
+        dev_sync_n                 => dev_sync_n(i), --out
+        jesd204_tx_avs_chipselect  => avs_chipselect(i), --jesd204b_mosi_arr(i).chipselect,
+        jesd204_tx_avs_address     => avs_address(i),
+        jesd204_tx_avs_read        => avs_read(i),
+        jesd204_tx_avs_readdata    => avs_readdata(i),
+        jesd204_tx_avs_waitrequest => open,
+        jesd204_tx_avs_write       => '0',
+        jesd204_tx_avs_writedata   => (others => '0'),
+        jesd204_tx_avs_clk         => mm_clk,
+        jesd204_tx_avs_rst_n       => avs_rst_n,
+        jesd204_tx_dlb_data        => open, -- debug/loopback testing
+        jesd204_tx_dlb_kchar_data  => open, -- debug/loopback testing
+        jesd204_tx_frame_ready     => jesd204b_tx_frame_ready(i),
+        jesd204_tx_frame_error     => '0',
+        jesd204_tx_int             => OPEN,            -- Connected to status IO in example design 
+        jesd204_tx_link_data       => jesd204b_tx_link_data_arr(i),              --in
+        jesd204_tx_link_valid      => jesd204b_tx_link_valid(i),             --in  
+        jesd204_tx_link_ready      => jesd204b_tx_link_ready(i),             --out
+        mdev_sync_n                => dev_sync_n(i), --in
+        pll_locked                 => pll_locked, --in
+        sync_n                     => jesd204b_sync_n_adc(i), --in
+        tx_analogreset             => tx_analogreset,
+        tx_bonding_clocks          => tx_bonding_clocks,--: in  std_logic_vector(5 downto 0)  := (others => 'X'); -- clk
+        tx_cal_busy                => open,
+        tx_digitalreset            => tx_digitalreset,
+        tx_serial_data             => serial_tx(i downto i),
+        txlink_clk                 => txlink_clk(i),             
+        txlink_rst_n_reset_n       => txlink_rst_n,           
+        txphy_clk                  => txphy_clk(i downto i),                  
+        somf                       => OPEN,
+        sysref                     => jesd204b_sysref_adc(i)
+      );
+
+    -- Generate test pattern at each ADC
+
+    proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst)
+      VARIABLE data  : INTEGER := 0;
+      VARIABLE even_sample : BOOLEAN := TRUE;
+    BEGIN
+      IF mm_rst = '1' THEN
+         jesd204b_tx_link_data_arr(i) <= (others => '0');
+         jesd204b_tx_link_valid(i) <= '0';
+         txlink_clk(i) <= '0';
+         data := 0;
+         even_sample := TRUE;
+       ELSE
+         IF rising_edge(jesd204b_sampclk_adc(i)) THEN
+           txlink_clk(i) <= not txlink_clk(i);
+           jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
+           jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+           IF (jesd204b_sysref_adc(i) = '1' and jesd204b_sysref_adc_1(i) = '0') THEN
+             data := 1000;
+           ELSIF (jesd204b_sysref_adc_1(i) = '1' and jesd204b_sysref_adc_2(i) = '0') THEN
+             data := -1000;
+           ELSE
+             data := 0;
+           END IF;
+
+           -- Frame the data to 32 bits at half the rate
+           IF(jesd204b_tx_link_ready(i) = '0') THEN
+             even_sample := TRUE;
+           ELSE
+             even_sample := not even_sample;
+           END IF;
+           IF (even_sample = TRUE) THEN
+             jesd204b_tx_link_data_arr(i)(15 downto 0) <= TO_SVEC(data, 16);
+             jesd204b_tx_link_valid(i) <= '0';
+           ELSE
+             jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
+             jesd204b_tx_link_valid(i) <= '1';
+           END IF;
+
+         END IF;
+       END IF;
+    END PROCESS;
+
+
+
+  END GENERATE;
+
+
+  -----------------------------------------------------------------------------
+  -- Stimulii 
+  -----------------------------------------------------------------------------
+
+  -- Clocks and resets
+  avs_rst_n <= '0', '1'  after 23500 ns;
+  tx_analogreset(0) <= '1', '0' after 18500 ns;
+  tx_digitalreset(0) <= '1', '0' after 23000 ns;
+  txlink_rst_n <= '0', '1' after 25500 ns;
+  pll_locked(0) <= '0', '1' after 1000 ns;
+  
+  bonding_clock_5 <= not bonding_clock_5 after 250 ps;
+  bonding_clock_4 <= not bonding_clock_4 after 250 ps;
+  bonding_clock_3 <= not bonding_clock_3 after 500 ps;
+  bonding_clock_2 <= not bonding_clock_2 after 500 ps;
+  bonding_clock_0 <= not bonding_clock_0 after 2500 ps;
+
+  bonding_clock_1_process : process
+  begin
+    bonding_clock_1 <= '0';
+    wait for 4000 ps; 
+    bonding_clock_1 <= '1';
+    wait for 1000 ps; 
+  end process;
+
+  tx_bonding_clocks(5) <= transport bonding_clock_5 after 4890 ps; 		     
+  tx_bonding_clocks(4) <= transport bonding_clock_4 after 4640 ps; 		     
+  tx_bonding_clocks(3) <= transport bonding_clock_3 after 4920 ps; 		     
+  tx_bonding_clocks(2) <= transport bonding_clock_2 after 4930 ps; 		     
+  tx_bonding_clocks(1) <= transport bonding_clock_1 after 7490 ps; 		     
+  tx_bonding_clocks(0) <= transport bonding_clock_0 after 4000 ps; 		     
+		     
+  
+  -- clock source process
+
+  proc_sysref : PROCESS (jesd204b_sampclk, mm_rst)
+    VARIABLE count  : NATURAL := 0;
+  BEGIN
+    IF mm_rst = '1' THEN
+       jesd204b_sysref <= '0';
+       count := 0;
+     ELSE
+       IF rising_edge(jesd204b_sampclk) THEN
+        IF (count = c_sysref_period-1) THEN
+           count := 0;
+         ELSE
+           count := count + 1;
+         END IF;
+
+         IF count > c_sysref_period-8 THEN
+           jesd204b_sysref <= '1';
+         ELSE
+           jesd204b_sysref <= '0';
+         END IF;
+       END IF;
+     END IF;
+  END PROCESS;
+
+  ------------------------------------------------------------------------------
+  -- Diagnostics
+  ------------------------------------------------------------------------------
+  proc_read_avs_regs : PROCESS
+  BEGIN
+    wait for 100ns;
+    avs_address(0) <= (others => '0');
+    avs_chipselect(0) <= '0';
+    avs_read(0) <= '0';
+    wait until avs_rst_n = '1';
+    while true loop
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= X"14"; -- dll control
+      avs_chipselect(0) <= '1';
+      avs_read(0) <= '1';
+      wait for c_mm_clk_period * 1;
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= (others => '0');
+      avs_chipselect(0) <= '0';
+      avs_read(0) <= '0';
+      wait for c_mm_clk_period * 32;
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= X"15"; -- syncn_sysref control
+      avs_chipselect(0) <= '1';
+      avs_read(0) <= '1';
+      wait for c_mm_clk_period * 1;
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= (others => '0');
+      avs_chipselect(0) <= '0';
+      avs_read(0) <= '0';
+      wait for c_mm_clk_period * 32;
+      wait until rising_edge(mm_clk);
+
+      avs_address(0) <= X"18"; -- syncn_sysref control
+      avs_chipselect(0) <= '1';
+      avs_read(0) <= '1';
+      wait for c_mm_clk_period * 1;
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= (others => '0');
+      avs_chipselect(0) <= '0';
+      avs_read(0) <= '0';
+      wait for c_mm_clk_period * 32;
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= X"19"; -- syncn_sysref control
+      avs_chipselect(0) <= '1';
+      avs_read(0) <= '1';
+      wait for c_mm_clk_period * 1;
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= (others => '0');
+      avs_chipselect(0) <= '0';
+      avs_read(0) <= '0';
+      wait for c_mm_clk_period * 32;
+      wait until rising_edge(mm_clk);
+
+      avs_address(0) <= X"20"; -- tx control0
+      avs_chipselect(0) <= '1';
+      avs_read(0) <= '1';
+      wait for c_mm_clk_period * 1;
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= (others => '0');
+      avs_chipselect(0) <= '0';
+      avs_read(0) <= '0';
+      wait for c_mm_clk_period * 32;
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= X"26"; -- tx control0
+      avs_chipselect(0) <= '1';
+      avs_read(0) <= '1';
+      wait for c_mm_clk_period * 1;
+      wait until rising_edge(mm_clk);
+      avs_address(0) <= (others => '0');
+      avs_chipselect(0) <= '0';
+      avs_read(0) <= '0';
+      wait for c_mm_clk_period * 32;
+    END LOOP;
+  END PROCESS;
+ 
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  --sim_done <= '0', '1' AFTER 1 us;
+  sim_done <= '0';
+
+  proc_common_stop_simulation(TRUE, jesd204b_sampclk, sim_done, tb_end);
+
+END tb;
diff --git a/libraries/technology/jesd204b/tech_jesd204b.vhd b/libraries/technology/jesd204b/tech_jesd204b.vhd
index 23c308cfe0b5948a2236af47149271df9b649c39..ecf327e563b86d2f60d03bc027f321dde7deda78 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b.vhd
@@ -21,7 +21,8 @@
 --------------------------------------------------------------------------------
 
 
--- Purpose: Technology selecttion wrapper to instantiate 
+-- Author : J Hargreaves
+-- Purpose: Technology selection wrapper to instantiate 
 --   JESD204b interface for ADCs and DACs
 -- Description:
 --
@@ -43,6 +44,7 @@
 --                  mac_mm
 --
 --
+-- ToDo: Change g_nof_channels to g_nof_streams in IP
 
 LIBRARY IEEE, common_lib, dp_lib, technology_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -57,18 +59,21 @@ ENTITY tech_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
     g_technology          : NATURAL := c_tech_arria10_e1sg;
-    g_nof_channels        : NATURAL := 12;
+    g_nof_streams         : NATURAL := 12;
+    g_nof_sync_n          : NATURAL := 12;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
   PORT (
     -- JESD204B external signals
     jesd204b_refclk       : IN STD_LOGIC := '0';                             -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
     jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
-    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
     
     -- Data to fabric
-    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';                           -- Regenerated data clock to fabric
+    rx_sosi_arr           : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    -- Parallel data out to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -78,8 +83,8 @@ ENTITY tech_jesd204b IS
     jesd204b_miso         : OUT t_mem_miso; 
     
     -- Serial connections to transceiver pins
-    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);      -- Not used for ADC
-    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);      -- Not used for ADC
+    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
   );
 END tech_jesd204b;
 
@@ -91,7 +96,8 @@ BEGIN
     u0 : ENTITY work.tech_jesd204b_arria10_e1sg
     GENERIC MAP(
       g_sim                => g_sim,                
-      g_nof_channels       => g_nof_channels,      
+      g_nof_streams        => g_nof_streams,      
+      g_nof_sync_n         => g_nof_sync_n,        
       g_direction          => g_direction
     )
     PORT MAP(
@@ -99,8 +105,10 @@ BEGIN
       jesd204b_sysref      => jesd204b_sysref,   
       jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
   
-      rx_src_out_arr       => rx_src_out_arr,          
-      jesd204b_frame_clk   => jesd204b_frame_clk,          
+      rx_src_out_arr       => rx_sosi_arr,          
+      rx_clk               => rx_clk,          
+      rx_rst               => rx_rst,          
+      rx_sysref            => rx_sysref,          
   
       -- MM
       mm_clk               => mm_clk,           
@@ -119,7 +127,8 @@ BEGIN
     u0 : ENTITY work.tech_jesd204b_arria10_e2sg
     GENERIC MAP(
       g_sim                => g_sim,                
-      g_nof_channels       => g_nof_channels,      
+      g_nof_streams        => g_nof_streams,      
+      g_nof_sync_n         => g_nof_sync_n,       
       g_direction          => g_direction
     )
     PORT MAP(
@@ -127,8 +136,10 @@ BEGIN
       jesd204b_sysref      => jesd204b_sysref,   
       jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
   
-      rx_src_out_arr       => rx_src_out_arr,          
-      jesd204b_frame_clk   => jesd204b_frame_clk,          
+      rx_src_out_arr       => rx_sosi_arr,          
+      rx_clk               => rx_clk,          
+      rx_rst               => rx_rst,          
+      rx_sysref            => rx_sysref,          
   
       -- MM
       mm_clk               => mm_clk,           
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
index c61ec365e8a64d87da5482dd1585141211758bf0..1880c76a8f7255763173ecbd2f1e24b8a9859533 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
@@ -20,12 +20,11 @@
 --
 --------------------------------------------------------------------------------
 
-
+-- Author: J Hargreaves
 -- Purpose: Wrapper for the Intel Arria 10 e1sg (unb2b, unb2c) tecnology version of the
 --   JESD204b interface for ADCs and DACs
 -- Description 
---   
---  
+--   Current configuration supports 12 channels receive only
 
 LIBRARY IEEE, common_lib, dp_lib, technology_lib, ip_arria10_e1sg_jesd204b_lib;
 USE IEEE.STD_LOGIC_1164.ALL;
@@ -38,18 +37,21 @@ USE work.tech_jesd204b_component_pkg.ALL;
 ENTITY tech_jesd204b_arria10_e1sg IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_nof_channels        : NATURAL := 12;
+    g_nof_streams         : NATURAL := 12;
+    g_nof_sync_n          : NATURAL := 12;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
   PORT (
     -- JESD204B external signals
     jesd204b_refclk       : IN STD_LOGIC := '0';                             -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
     jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
-    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);  -- output to control ADC initialization/syncronization phase
     
     -- Data to fabric
-    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';                           -- Regenerated data clock to fabric
+    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    -- Parallel data out to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -59,8 +61,8 @@ ENTITY tech_jesd204b_arria10_e1sg IS
     jesd204b_miso         : OUT t_mem_miso; 
     
     -- Serial connections to transceiver pins
-    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);      -- Not used for ADC
-    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);      -- Not used for ADC
+    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
   );
 END tech_jesd204b_arria10_e1sg;
 
@@ -71,7 +73,8 @@ BEGIN
   u_ip_arria10_e1sg_jesd204b : ip_arria10_e1sg_jesd204b
   GENERIC MAP(
     g_sim                => g_sim,                
-    g_nof_channels       => g_nof_channels,      
+    g_nof_streams        => g_nof_streams,      
+    g_nof_sync_n         => g_nof_sync_n,        
     g_direction          => g_direction
   )
   PORT MAP(
@@ -80,7 +83,9 @@ BEGIN
     jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
 
     rx_src_out_arr       => rx_src_out_arr,          
-    jesd204b_frame_clk   => jesd204b_frame_clk,          
+    rx_clk               => rx_clk,          
+    rx_rst               => rx_rst,          
+    rx_sysref            => rx_sysref,          
 
     -- MM
     mm_clk               => mm_clk,           
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
index e92e465237ed17cc5c6c251a86c6b144772c969c..2ff054424354a47838c528b57443b32db290de37 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
@@ -38,18 +38,21 @@ USE work.tech_jesd204b_component_pkg.ALL;
 ENTITY tech_jesd204b_arria10_e2sg IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_nof_channels        : NATURAL := 12;
+    g_nof_streams         : NATURAL := 12;
+    g_nof_sync_n          : NATURAL := 12;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
   PORT (
     -- JESD204B external signals
     jesd204b_refclk       : IN STD_LOGIC := '0';                             -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
     jesd204b_sysref       : IN STD_LOGIC := '0';                             -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
-    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
     
     -- Data to fabric
-    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';                           -- Regenerated data clock to fabric
+    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    -- Parallel data out to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -59,8 +62,8 @@ ENTITY tech_jesd204b_arria10_e2sg IS
     jesd204b_miso         : OUT t_mem_miso; 
     
     -- Serial connections to transceiver pins
-    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);      -- Not used for ADC
-    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);      -- Not used for ADC
+    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
   );
 END tech_jesd204b_arria10_e2sg;
 
@@ -71,7 +74,7 @@ BEGIN
   u_ip_arria10_e2sg_jesd204b : ip_arria10_e2sg_jesd204b
   GENERIC MAP(
     g_sim                => g_sim,                
-    g_nof_channels       => g_nof_channels,      
+    g_nof_streams       => g_nof_streams,      
     g_direction          => g_direction
   )
   PORT MAP(
@@ -80,7 +83,9 @@ BEGIN
     jesd204b_sync_n_arr  => jesd204b_sync_n_arr,   
 
     rx_src_out_arr       => rx_src_out_arr,          
-    jesd204b_frame_clk   => jesd204b_frame_clk,          
+    rx_clk               => rx_clk,          
+    rx_rst               => rx_rst,          
+    rx_sysref            => rx_sysref,          
 
     -- MM
     mm_clk               => mm_clk,           
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index eb6077a69411a3ad8f3dfbb9d30f47cb68a9fc5b..3714caf7bd57edef58083f65160299fd1af8ce3a 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -38,18 +38,21 @@ PACKAGE tech_jesd204b_component_pkg IS
   COMPONENT ip_arria10_e1sg_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_nof_channels        : NATURAL := 1;
+    g_nof_streams         : NATURAL := 1;
+    g_nof_sync_n          : NATURAL := 1;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
  PORT (
     -- JESD204B external signals
     jesd204b_refclk       : IN STD_LOGIC := '0';                 -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
     jesd204b_sysref       : IN STD_LOGIC := '0';                 -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
-    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
     
     -- Data to fabric
-    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';               -- Regenerated data clock to fabric
+    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    -- Parallel data out to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -59,8 +62,8 @@ PACKAGE tech_jesd204b_component_pkg IS
     jesd204b_miso         : OUT t_mem_miso; 
          
     -- Serial connections to transceiver pins
-    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
-    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- Not used for ADC
+    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
   );
   END COMPONENT;
 
@@ -71,18 +74,21 @@ PACKAGE tech_jesd204b_component_pkg IS
   COMPONENT ip_arria10_e2sg_jesd204b IS
   GENERIC (
     g_sim                 : BOOLEAN := FALSE;
-    g_nof_channels        : NATURAL := 1;
+    g_nof_streams         : NATURAL := 1;
+    g_nof_sync_n          : NATURAL := 1;
     g_direction           : STRING := "RX_ONLY"  -- "TX_RX", "TX_ONLY", "RX_ONLY"
   );
  PORT (
     -- JESD204B external signals
     jesd204b_refclk       : IN STD_LOGIC := '0';                 -- Reference clock. For AD9683 use 200MHz direct from clock reference pin
     jesd204b_sysref       : IN STD_LOGIC := '0';                 -- SYSREF should drive ADC and FPGA with correct phase wrt jesd204b_device_clk 
-    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
+    jesd204b_sync_n_arr   : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- output to control ADC initialization/syncronization phase
     
     -- Data to fabric
-    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0);    -- Parallel data out to fabric
-    jesd204b_frame_clk    : OUT  STD_LOGIC := '0';               -- Regenerated data clock to fabric
+    rx_src_out_arr        : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);    -- Parallel data out to fabric
+    rx_clk                : OUT  STD_LOGIC := '0';                           -- Exported data clock (frame clock) to fabric
+    rx_rst                : OUT  STD_LOGIC := '0';                           -- Exported reset on rx_clk domain
+    rx_sysref             : OUT  STD_LOGIC := '0';                           -- Exported copy of sysref
 
     -- MM Control
     mm_clk                : IN  STD_LOGIC;
@@ -92,8 +98,8 @@ PACKAGE tech_jesd204b_component_pkg IS
     jesd204b_miso         : OUT t_mem_miso; 
          
     -- Serial connections to transceiver pins
-    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- Not used for ADC
-    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
+    serial_tx_arr         : OUT STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0); -- Not used for ADC
+    serial_rx_arr         : IN  STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0)
   );
   END COMPONENT;