diff --git a/libraries/dsp/fft/hdllib.cfg b/libraries/dsp/fft/hdllib.cfg
index a75778467bbdea6b49354de1f431115a5b5dd9d8..aee1489da150feebf22084542d8ebd71b86484e8 100644
--- a/libraries/dsp/fft/hdllib.cfg
+++ b/libraries/dsp/fft/hdllib.cfg
@@ -21,7 +21,8 @@ synth_files =
     
 test_bench_files = 
     tb/vhdl/tb_fft_pkg.vhd 
-    tb/vhdl/tb_fft_functions.vhd 
+    tb/vhdl/tb_fft_functions.vhd
+    tb/vhdl/tb_fft_lfsr.vhd
     tb/vhdl/tb_fft_switch.vhd
     tb/vhdl/tb_fft_sepa.vhd
     tb/vhdl/tb_fft_reorder_sepa_pipe.vhd 
@@ -32,11 +33,12 @@ test_bench_files =
     tb/vhdl/tb_fft_wide_unit.vhd 
     tb/vhdl/tb_mmf_fft_r2.vhd 
     tb/vhdl/tb_mmf_fft_wide_unit.vhd 
-    tb/vhdl/tb_tb_fft_r2_pipe.vhd 
+    tb/vhdl/tb_tb_fft_r2_pipe.vhd
     tb/vhdl/tb_tb_fft_r2_par.vhd
     tb/vhdl/tb_tb_fft_r2_wide.vhd
 
 regression_test_vhdl = 
+    tb/vhdl/tb_fft_lfsr.vhd
     tb/vhdl/tb_fft_switch.vhd
     tb/vhdl/tb_tb_fft_r2_pipe.vhd
     tb/vhdl/tb_tb_fft_r2_par.vhd
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..23791ba61bcdf56d68adae81c6b3d1672fb22166
--- /dev/null
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
@@ -0,0 +1,92 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2021
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+--
+-- Author: E. Kooistra
+-- Purpose: Verify fft_lsfr for different seeds
+-- Description:
+--   Check that after c_fft_lfsr_len = 41 blocks the LFSR1 and LFSR2 bits of
+--   the two instances u0 and u1 indeed start to differ.
+--
+-- Usage:
+--   > as 4
+--   > run -all
+--   # Not self checking, manually compare that u0_lfsr_bit1 and u1_lfsr_bit1
+--     start to differ after about c_fft_lfsr_len blocks. Similar for
+--     u0_lfsr_bit1 and u1_lfsr_bit1.
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.fft_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_fft_lfsr IS
+END tb_fft_lfsr;
+
+ARCHITECTURE tb OF tb_fft_lfsr IS
+
+  CONSTANT clk_period      : TIME := 10 ns;
+
+  CONSTANT c_block_period  : NATURAL := 10;
+  CONSTANT c_nof_block     : NATURAL := 1000;
+
+  SIGNAL tb_end            : STD_LOGIC := '0';
+  SIGNAL rst               : STD_LOGIC := '1';
+  SIGNAL clk               : STD_LOGIC := '0';
+
+  SIGNAL in_en             : STD_LOGIC := '0';
+  SIGNAL u0_lfsr_bit1      : STD_LOGIC;
+  SIGNAL u1_lfsr_bit1      : STD_LOGIC;
+  SIGNAL u0_lfsr_bit2      : STD_LOGIC;
+  SIGNAL u1_lfsr_bit2      : STD_LOGIC;
+
+BEGIN
+
+  clk <= NOT clk OR tb_end AFTER clk_period/2;
+  rst <= '1', '0' AFTER 10 * clk_period;
+  tb_end <= '0', '1' AFTER c_nof_block * c_block_period * clk_period;
+
+  proc_common_gen_pulse(1, c_block_period, '1', rst, clk, in_en);
+
+  u0 : ENTITY work.fft_lfsr
+  GENERIC MAP (
+    g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 0),
+    g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 0)
+  )
+  PORT MAP (
+    in_en          => in_en,
+    out_bit1       => u0_lfsr_bit1,
+    out_bit2       => u0_lfsr_bit2,
+    clk            => clk,
+    rst            => rst
+  );
+
+  u1 : ENTITY work.fft_lfsr
+  GENERIC MAP (
+    g_seed1 => fft_switch_new_seed(c_fft_switch_seed1, 1),
+    g_seed2 => fft_switch_new_seed(c_fft_switch_seed2, 1)
+  )
+  PORT MAP (
+    in_en          => in_en,
+    out_bit1       => u1_lfsr_bit1,
+    out_bit2       => u1_lfsr_bit2,
+    clk            => clk,
+    rst            => rst
+  );
+
+END tb;