From c05b8dad2cad40f03507cbebacc3bdeb9e91733a Mon Sep 17 00:00:00 2001 From: Reinier van der Walle <walle@astron.nl> Date: Wed, 21 Mar 2018 15:51:39 +0000 Subject: [PATCH] Changed to use the verilog files instead of the vhdl files --- .../technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl index afd11ccfcc..d583f8dd2f 100644 --- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl +++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl @@ -30,8 +30,8 @@ set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/complex_mult/generated/sim" -vmap altmult_complex_170 ./work/ + vmap altmult_complex_170 ./work/ + vlog "$IP_DIR/../altmult_complex_170/sim/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.v" -work altmult_complex_170 - vcom "$IP_DIR/../altmult_complex_170/sim/ip_arria10_e1sg_complex_mult_altmult_complex_170_myrk3hi.vhd" -work altmult_complex_170 - vcom "$IP_DIR/ip_arria10_e1sg_complex_mult.vhd" +vlog "$IP_DIR/ip_arria10_e1sg_complex_mult.v" -- GitLab