diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/README.txt b/libraries/technology/ip_agi027_xxxx/reset_release/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..c64f758a8aef4ea2cb8128d6b0e50c242a4fd7d5
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/reset_release/README.txt
@@ -0,0 +1,198 @@
+###############################################################################
+#
+# Copyright 2024
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+###############################################################################
+
+
+README.txt for $HDL_WORK/libraries/technology/ip_agi027_xxxx/reset_release
+VERSION 01 - 20240105
+
+Contents:
+
+1) IP component
+2) Compilation, simulation and verification
+3) Synthesis
+4) Remarks
+5) References
+
+
+1) IP component
+
+ The reset_release IP component was created with Quartus 23.2 for agi027_1e1v.
+ That was the result of a critical warning [1] during synthesis of
+ iwave_synthesis_wpfb_lofar2.vhd, that is the top-level entity for
+ wpfb_unit_dev.vhd, when Agilex 7 is used. For more see 4) Remarks.
+ A familar name that can be used is user_rst_clkgate due to the IP catalog name
+ altera_s10_user_rst_clkgate in Quartus. s10 is because it must also be used for
+ Stratix10.
+
+ Description:
+ This IP outputs nINIT_DONE after finishing device initalization.
+ User mode initialization can begin as soon as the nINIT_DONE signal asserts.
+
+ The generated IPs are not kept in git repository, only the ip source files:
+
+ ip_agi027_xxxx_reset_release_ci.ip
+ ip_agi027_xxxx_reset_release_ri.ip
+
+ Therefore first the IP needs to be generated using:
+
+ generate_ip_libs iwave
+
+
+2) Compilation, simulation and verification
+
+ compile_ip.tcl is manually created (by using the msim_setup.tcl file, which is
+ part of the generated IPs) and this compile_ip.tcl is added in the hdllib.cfg
+ to 'modelsim_compile_ip_files =' and gets compiled before the other code.
+ However, a separate testbench has not been created for the FPGA reset release
+ IP in ModelSim Simulation and no other verification have to be done for creating
+ the IP.
+
+
+3) Synthesis
+
+ No synthesis trials were done by ASTRON, because this will implicitely be done
+ when the IP is used in a design. For the iwave example_design also this IP (ci)
+ is used, no issues are reported by the QUI during compilation.
+
+ The QIP file:
+
+ ip_agi027_xxxx_reset_release_ci.qip
+ ip_agi027_xxxx_reset_release_ri.qip
+
+ is included in the hdllib.cfg and contains what is needed to synthesize the IP.
+
+
+4) Remarks
+
+a) Necessary use for Agilex devices
+
+ . Related to the critical warning [1]
+
+ . According to the user guide [2] and a YouTube video from Intel [3], this IP is
+ necessary to use in all Intel Stratix 10 and Intel Agilex devices to hold your
+ design in reset until the FPGAs have finished with the configuration process.
+ This means that this IP must be used, and some additions need to be made in the
+ BSP (Board Support Package) and application design.
+
+ . See [4] for documentation about this critcial warning on Confluence.
+
+b) Reset output port can be a Reset Interface (ri) or Conduit Interface (ci):
+
+ . ci = conduit interface, is the selected type of reset output port
+ Desc. : legacy reset output
+ . ri = reset interface, is the selected type of reset output port
+ Desc. : allow reset connection in Platform Designer
+
+ . The ci IP is used in the vendor FPGA Design Example.
+
+c) Choose between using or not using a separate library in altera_libraries:
+
+ When multiple IPs are generated, each utilizing the same IP function but with
+ different settings, it results in the generation of the same library name:
+
+ . When containing the same source files, no separate library has to be
+ created (only when it is preferable for a reason).
+ . When containing a different source file, as opposed to the previously
+ used unique library names. This leads to issues. To address this, shared
+ libraries are combined within a single library with the IP-specific library
+ name in the build directory when 'generate_ip_libs' is used. Therefore, a
+ directory is manually created in 'altera_libraries' with the IP-specific
+ library name, containing two files: 'compile_ip.tcl' and 'hdllib.cfg'.
+
+ I) No separate library (currently used)
+
+ So when the same source files are used by the IPs (no hashes) use:
+
+ hdl_lib_name = ip_agi027_xxxx_<lib_name>
+ hdl_library_clause_name = ip_agi027_xxxx_<lib_name>_lib
+
+ Therefore the compile_ip.tcl has to vmap IP specific libraries, compile all
+ IP source files into these libraries and to compile the sim source files:
+
+ #repeat for all ip specific libraries
+ vmap <lib_name>_<ip_specific>
+
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>"
+ #repeat for all IP source files. When multiple same files? Only one IP source file is
+ #needed for compilation into those libraries
+ vlog -sv <ip_specific>.sv -work <ip_specific>
+
+ #Repeat for all IPs
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>/sim"
+ vcom "$IP_DIR/<ip_name>.vhd"
+
+ II) Separate library
+
+ So when different source files are used by the IPs (hashes) or when it is
+ preferable to move the library to the altera_libraries, use generated IP
+ specific library clause name and IP specific lib uses sim.
+
+ The generated ip_agi027_xxxx_<lib_name>.vhd uses an IP specific library name.
+ Therefore the hdllib.cfg uses the IP specific part as library clause name and,
+ in addition, uses lib uses sim to make it known:
+
+ hdl_lib_name = ip_agi027_xxxx_<lib_name>
+ hdl_library_clause_name = ip_agi027_xxxx_<lib_name>_<ip_specific>
+ hdl_lib_uses_sim = ip_agi027_xxxx_<ip_specific>
+
+ Therefore the compile_ip.tcl has only to compile the sim source files:
+
+ #Repeat for all IPs
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>/sim"
+ vcom "$IP_DIR/<ip_name>.vhd"
+
+ #This means:
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ci/sim"
+ vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ci.vhd"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ri/sim"
+ vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ri.vhd"
+
+ Therefore the altera_libraries hdllib.cfg uses ip specific part as library clause
+ name and assign the altera_libraries compile_ip.tcl to 'modelsim_compile_ip_files =':
+
+ hdl_lib_name = ip_agi027_xxxx_<ip_specific>
+ hdl_library_clause_name = <ip_specific>
+
+ modelsim_compile_ip_files =
+ $HDL_WORK/libraries/technology/ip_agi027_xxxx/altera_libraries/<ip_specific>/compile_ip.tcl
+
+ Therefore the altera_libraries compile.tcl has to vmap IP specific libraries, compile all
+ IP source files into these 'shared' libraries:
+
+ #repeat for all ip specific libraries
+ vmap <lib_name>_<ip_specific>
+
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_<ip_name>"
+ #repeat for all IP source files. When multiple same files? Only one IP source file is
+ #needed for compilation into those libraries
+ vlog -sv <ip_specific>.sv -work <ip_specific>
+
+
+5) References:
+
+ [1] Critical Warning(20759): Use the Reset Release IP in Intel Agilex 7 FPGA designs to ensure a successful configuration.
+ For more information about the Reset Release IP, refer to the Intel Agilex Configuration User Guide.
+ [2] "File: ug-ag-config-683673-777132-1.pdf; AN 891: Using the Reset Release Intel FPGA IP - User Guide", Sept 30, 2019
+ https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/pdfs/literature/an/archives/an891-19-3.pdf
+ See Reset Release Chapter 4.3. Gating the PLL Reset Signal
+ [3] "An Essential Reset for Intel® Stratix® 10 & Intel Agilex™ Devices", Jun 28, 2021
+ https://www.youtube.com/watch?v=qhGfZwX9jKw
+ [4] "Key porting highlights: Reset Release IP - needed for BSP", Jan 05, 2024,
+ https://support.astron.nl/confluence/display/SBe/Reset+Release+IP+-+needed+for+BSP
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/compile_ip.tcl b/libraries/technology/ip_agi027_xxxx/reset_release/compile_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..cd8d75dbb23042ad54850a45d657c73795a5b02a
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/reset_release/compile_ip.tcl
@@ -0,0 +1,50 @@
+# ------------------------------------------------------------------------------
+#
+# Copyright 2024
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# ------------------------------------------------------------------------------
+#
+# Author: D.F. Brouwer
+# Description:
+# This file is based on generated file mentor/msim_setup.tcl.
+# - the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
+# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
+# - replace QSYS_SIMDIR by IP_DIR
+# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
+# Remark:
+# Both uses the same library source file, so only one source file initialization (compilation) into the IP library for simulation is needed
+
+# Create the work library
+vlib ./work/ ;# Assume library work already exist
+
+# Map the following libraries to the work library:
+# . Map the altera_s10_user_rst_clkgate_1945 library to the work library
+vmap altera_s10_user_rst_clkgate_1945 ./work/
+
+# Compile SystemVerilog file for altera_s10_user_rst_clkgate_1945. Read remark.
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ci"
+ vlog -sv "$IP_DIR/altera_s10_user_rst_clkgate_1945/sim/altera_s10_user_rst_clkgate.sv" -work altera_s10_user_rst_clkgate_1945
+#set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ri"
+# vlog -sv "$IP_DIR/altera_s10_user_rst_clkgate_1945/sim/altera_s10_user_rst_clkgate.sv" -work altera_s10_user_rst_clkgate_1945
+
+# Compile VHDL file for ip_agi027_xxxx_reset_release_ci
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ci/sim"
+ vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ci.vhd"
+
+# Compile VHDL file for ip_agi027_xxxx_reset_release_ri
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_agi027_xxxx_reset_release_ri/sim"
+ vcom "$IP_DIR/ip_agi027_xxxx_reset_release_ri.vhd"
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/reset_release/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c16b7e1e92bf4205b712575b8138cde34a10d6bc
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/reset_release/hdllib.cfg
@@ -0,0 +1,25 @@
+hdl_lib_name = ip_agi027_xxxx_reset_release
+hdl_library_clause_name = ip_agi027_xxxx_reset_release_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+ ip_agi027_xxxx_reset_release_component_pkg.vhd
+
+test_bench_files =
+
+modelsim_compile_ip_files =
+ $HDL_WORK/libraries/technology/ip_agi027_xxxx/reset_release/compile_ip.tcl
+
+[modelsim_project_file]
+
+[quartus_project_file]
+quartus_qip_files =
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_reset_release/ip_agi027_xxxx_reset_release_ci.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_agi027_xxxx_reset_release/ip_agi027_xxxx_reset_release_ri.qip
+
+[generate_ip_libs]
+qsys-generate_ip_files =
+ ip_agi027_xxxx_reset_release_ci.ip
+ ip_agi027_xxxx_reset_release_ri.ip
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ci.ip b/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ci.ip
new file mode 100644
index 0000000000000000000000000000000000000000..8c047759742c1fa09b148c4e8ae3518eb8dd8eed
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ci.ip
@@ -0,0 +1,182 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_reset_release_ci</ipxact:library>
+ <ipxact:name>s10_user_rst_clkgate_0</ipxact:name>
+ <ipxact:version>19.4.5</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>ninit_done</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="conduit" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>ninit_done</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>ninit_done</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:slave></ipxact:slave>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>associatedClock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedReset" type="string">
+ <ipxact:name>associatedReset</ipxact:name>
+ <ipxact:displayName>associatedReset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="prSafe" type="bit">
+ <ipxact:name>prSafe</ipxact:name>
+ <ipxact:displayName>Partial Reconfiguration Safe</ipxact:displayName>
+ <ipxact:value>false</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>altera_s10_user_rst_clkgate</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>ninit_done</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_reset_release_ci</ipxact:library>
+ <ipxact:name>altera_s10_user_rst_clkgate</ipxact:name>
+ <ipxact:version>19.4.5</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="outputType" type="string">
+ <ipxact:name>outputType</ipxact:name>
+ <ipxact:displayName>Type of reset output port</ipxact:displayName>
+ <ipxact:value>Conduit Interface</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31B1E1V</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element s10_user_rst_clkgate_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="ninit_done" altera:internal="s10_user_rst_clkgate_0.ninit_done" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="ninit_done" altera:internal="ninit_done"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_component_pkg.vhd b/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_component_pkg.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..90ba11325703d11480a3ed6a945289bb99658a2c
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_component_pkg.vhd
@@ -0,0 +1,58 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright 2024
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+-- http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--
+-- Author:
+-- . D.F. Brouwer
+-- Purpose:
+-- . Component declarations for reset release IP blocks
+-- Description:
+-- . Wrapper for reset release IPs, specific for technology c_tech_agi027_1e1v
+-- that is used by the iwave FPGA platform.
+-- . The Reset Release IP is necessary to use for Agilex7 devices.
+-- See README.txt for more information about this.
+--
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package ip_agi027_xxxx_reset_release_component_pkg is
+ -----------------------------------------------------------------------------
+ -- Agilex 7 components
+ -----------------------------------------------------------------------------
+
+ component ip_agi027_xxxx_reset_release_ci is
+ port (
+ ninit_done : out std_logic -- ninit_done
+ );
+ end component;
+
+ component ip_agi027_xxxx_reset_release_ri is
+ port (
+ ninit_done : out std_logic -- reset
+ );
+ end component ip_agi027_xxxx_reset_release_ri;
+
+end ip_agi027_xxxx_reset_release_component_pkg;
+
+package body ip_agi027_xxxx_reset_release_component_pkg is
+end ip_agi027_xxxx_reset_release_component_pkg;
diff --git a/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ri.ip b/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ri.ip
new file mode 100644
index 0000000000000000000000000000000000000000..6914cd70b60e4b2fc6d9255ffa3188ca36bb3d45
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/reset_release/ip_agi027_xxxx_reset_release_ri.ip
@@ -0,0 +1,187 @@
+<?xml version="1.0" ?>
+<!--Your use of Intel Corporation's design tools, logic functions
+and other software and tools, and any partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Intel Program License
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors. Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.-->
+<ipxact:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact2014/extensions" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014">
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_reset_release_ri</ipxact:library>
+ <ipxact:name>s10_user_rst_clkgate_0</ipxact:name>
+ <ipxact:version>19.4.5</ipxact:version>
+ <ipxact:busInterfaces>
+ <ipxact:busInterface>
+ <ipxact:name>ninit_done</ipxact:name>
+ <ipxact:busType vendor="intel" library="intel" name="reset" version="23.2"></ipxact:busType>
+ <ipxact:abstractionTypes>
+ <ipxact:abstractionType>
+ <ipxact:abstractionRef vendor="intel" library="intel" name="reset" version="23.2"></ipxact:abstractionRef>
+ <ipxact:portMaps>
+ <ipxact:portMap>
+ <ipxact:logicalPort>
+ <ipxact:name>reset</ipxact:name>
+ </ipxact:logicalPort>
+ <ipxact:physicalPort>
+ <ipxact:name>ninit_done</ipxact:name>
+ </ipxact:physicalPort>
+ </ipxact:portMap>
+ </ipxact:portMaps>
+ </ipxact:abstractionType>
+ </ipxact:abstractionTypes>
+ <ipxact:master></ipxact:master>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="associatedClock" type="string">
+ <ipxact:name>associatedClock</ipxact:name>
+ <ipxact:displayName>Associated clock</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedDirectReset" type="string">
+ <ipxact:name>associatedDirectReset</ipxact:name>
+ <ipxact:displayName>Associated direct reset</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="associatedResetSinks" type="string">
+ <ipxact:name>associatedResetSinks</ipxact:name>
+ <ipxact:displayName>Associated reset sinks</ipxact:displayName>
+ <ipxact:value>none</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="synchronousEdges" type="string">
+ <ipxact:name>synchronousEdges</ipxact:name>
+ <ipxact:displayName>Synchronous edges</ipxact:displayName>
+ <ipxact:value>NONE</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </ipxact:busInterface>
+ </ipxact:busInterfaces>
+ <ipxact:model>
+ <ipxact:views>
+ <ipxact:view>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:envIdentifier>:quartus.altera.com:</ipxact:envIdentifier>
+ <ipxact:componentInstantiationRef>QUARTUS_SYNTH</ipxact:componentInstantiationRef>
+ </ipxact:view>
+ </ipxact:views>
+ <ipxact:instantiations>
+ <ipxact:componentInstantiation>
+ <ipxact:name>QUARTUS_SYNTH</ipxact:name>
+ <ipxact:moduleName>altera_s10_user_rst_clkgate</ipxact:moduleName>
+ <ipxact:fileSetRef>
+ <ipxact:localName>QUARTUS_SYNTH</ipxact:localName>
+ </ipxact:fileSetRef>
+ </ipxact:componentInstantiation>
+ </ipxact:instantiations>
+ <ipxact:ports>
+ <ipxact:port>
+ <ipxact:name>ninit_done</ipxact:name>
+ <ipxact:wire>
+ <ipxact:direction>out</ipxact:direction>
+ <ipxact:wireTypeDefs>
+ <ipxact:wireTypeDef>
+ <ipxact:typeName>STD_LOGIC</ipxact:typeName>
+ <ipxact:viewRef>QUARTUS_SYNTH</ipxact:viewRef>
+ </ipxact:wireTypeDef>
+ </ipxact:wireTypeDefs>
+ </ipxact:wire>
+ </ipxact:port>
+ </ipxact:ports>
+ </ipxact:model>
+ <ipxact:vendorExtensions>
+ <altera:entity_info>
+ <ipxact:vendor>Intel Corporation</ipxact:vendor>
+ <ipxact:library>ip_agi027_xxxx_reset_release_ri</ipxact:library>
+ <ipxact:name>altera_s10_user_rst_clkgate</ipxact:name>
+ <ipxact:version>19.4.5</ipxact:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="outputType" type="string">
+ <ipxact:name>outputType</ipxact:name>
+ <ipxact:displayName>Type of reset output port</ipxact:displayName>
+ <ipxact:value>Reset Interface</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="DEVICE_FAMILY" type="string">
+ <ipxact:name>DEVICE_FAMILY</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <ipxact:parameters>
+ <ipxact:parameter parameterId="board" type="string">
+ <ipxact:name>board</ipxact:name>
+ <ipxact:displayName>Board</ipxact:displayName>
+ <ipxact:value>default</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="device" type="string">
+ <ipxact:name>device</ipxact:name>
+ <ipxact:displayName>Device</ipxact:displayName>
+ <ipxact:value>AGIB027R31B1E1V</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceFamily" type="string">
+ <ipxact:name>deviceFamily</ipxact:name>
+ <ipxact:displayName>Device family</ipxact:displayName>
+ <ipxact:value>Agilex 7</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="deviceSpeedGrade" type="string">
+ <ipxact:name>deviceSpeedGrade</ipxact:name>
+ <ipxact:displayName>Device Speed Grade</ipxact:displayName>
+ <ipxact:value>1</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="generationId" type="int">
+ <ipxact:name>generationId</ipxact:name>
+ <ipxact:displayName>Generation Id</ipxact:displayName>
+ <ipxact:value>0</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="bonusData" type="string">
+ <ipxact:name>bonusData</ipxact:name>
+ <ipxact:displayName>bonusData</ipxact:displayName>
+ <ipxact:value>bonusData
+{
+ element s10_user_rst_clkgate_0
+ {
+ datum _sortIndex
+ {
+ value = "0";
+ type = "int";
+ }
+ }
+}
+</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="hideFromIPCatalog" type="bit">
+ <ipxact:name>hideFromIPCatalog</ipxact:name>
+ <ipxact:displayName>Hide from IP Catalog</ipxact:displayName>
+ <ipxact:value>true</ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="lockedInterfaceDefinition" type="string">
+ <ipxact:name>lockedInterfaceDefinition</ipxact:name>
+ <ipxact:displayName>lockedInterfaceDefinition</ipxact:displayName>
+ <ipxact:value></ipxact:value>
+ </ipxact:parameter>
+ <ipxact:parameter parameterId="systemInfos" type="string">
+ <ipxact:name>systemInfos</ipxact:name>
+ <ipxact:displayName>systemInfos</ipxact:displayName>
+ <ipxact:value><systemInfosDefinition>
+ <connPtSystemInfos/>
+</systemInfosDefinition></ipxact:value>
+ </ipxact:parameter>
+ </ipxact:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="ninit_done" altera:internal="s10_user_rst_clkgate_0.ninit_done" altera:type="reset" altera:dir="start">
+ <altera:port_mapping altera:name="ninit_done" altera:internal="ninit_done"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </ipxact:vendorExtensions>
+</ipxact:component>
\ No newline at end of file