From c0225bceb27c5acd0f388a3f376631887b10c964 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Wed, 20 Mar 2024 10:28:23 +0100
Subject: [PATCH] Added note.
---
libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml b/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml
index 215c802fa4..9f02f033ae 100644
--- a/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml
+++ b/libraries/io/tr_10GbE/tr_10GbE.peripheral.yaml
@@ -16,6 +16,8 @@ peripherals:
they are stored with their 4 most significant bits first and their 32 least significant bits last, so
with word 0 = [3:0] = [35:32] and word 1 = [31:0].
Here the address map and 36 bit word order from [2] are used.
+ - From [2]: When you read the statistic counters, read the LSB before reading the MSB. For example, when
+ you read tx_stats_framesOK, read the register offset 0x1C02 before reading the register offset 0x1C03.
[1] LL 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_32b_10g_ethernet_mac.pdf
[2] Legacy 10GbE MAC, https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/10gbps_mac.pdf
--
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