From bfe1e61b0c8ab965e162954404b8cf997d12e0f7 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Mon, 31 Oct 2022 17:31:58 +0100
Subject: [PATCH] Use dp_offload_rx to remove CRC word and pass on Rx status
via sosi.err.
---
libraries/io/eth/src/vhdl/eth_tester.vhd | 7 ++++--
libraries/io/eth/src/vhdl/eth_tester_rx.vhd | 27 ++++++++++++++++++---
2 files changed, 28 insertions(+), 6 deletions(-)
diff --git a/libraries/io/eth/src/vhdl/eth_tester.vhd b/libraries/io/eth/src/vhdl/eth_tester.vhd
index ccc63fb866..b187a16d27 100644
--- a/libraries/io/eth/src/vhdl/eth_tester.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester.vhd
@@ -38,7 +38,9 @@ USE work.eth_tester_pkg.ALL;
ENTITY eth_tester IS
GENERIC (
g_nof_streams : NATURAL := 1;
- g_bg_sync_timeout : NATURAL := 220*10**6 -- 10% margin for nominal 1 s with st_clk at 200MHz
+ g_bg_sync_timeout : NATURAL := 220*10**6; -- 10% margin for nominal 1 s with st_clk at 200MHz
+ g_remove_crc : BOOLEAN := TRUE -- use TRUE when using sim_tse and tech_tse link interface,
+ -- use FALSE when streaming link interface
);
PORT (
-- Clocks and reset
@@ -142,7 +144,8 @@ BEGIN
u_rx : ENTITY work.eth_tester_rx
GENERIC MAP (
- g_bg_sync_timeout => g_bg_sync_timeout
+ g_bg_sync_timeout => g_bg_sync_timeout,
+ g_remove_crc => g_remove_crc
)
PORT MAP (
-- Clocks and reset
diff --git a/libraries/io/eth/src/vhdl/eth_tester_rx.vhd b/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
index e4012c32f3..a7a65bdfbc 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
@@ -24,7 +24,7 @@
-- References:
-- [1] https://support.astron.nl/confluence/display/L2M/L6+FWLIB+Design+Document%3A+ETH+tester+unit+for+1GbE
-LIBRARY IEEE, common_lib, dp_lib, diag_lib;
+LIBRARY IEEE, common_lib, dp_lib, diag_lib, tech_tse_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -32,11 +32,14 @@ USE common_lib.common_mem_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
USE work.eth_tester_pkg.ALL;
ENTITY eth_tester_rx IS
GENERIC (
- g_bg_sync_timeout : NATURAL := 220*10**6 -- 10% margin for nominal 1 s with st_clk at 200MHz
+ g_bg_sync_timeout : NATURAL := 220*10**6; -- 10% margin for nominal 1 s with st_clk at 200MHz
+ g_remove_crc : BOOLEAN := TRUE -- use TRUE when using sim_tse and tech_tse link interface,
+ -- use FALSE when streaming link interface
);
PORT (
-- Clocks and reset
@@ -65,6 +68,7 @@ ARCHITECTURE str OF eth_tester_rx IS
CONSTANT c_nof_total_counts : NATURAL := 3; -- 0 = nof_sop, 1 = nof_valid, 2 = nof_crc_corrupt
CONSTANT c_empty_w : NATURAL := 2; -- for 0, 1, 2, 3 empty octets per word
+ CONSTANT c_error_w : NATURAL := 1;
-- Rx FIFO size can be much less than rx_block_sz_max, because st_clk >
-- eth_clk rate, but with st level tx-rx loopback the Rx FIFO does need
@@ -113,7 +117,7 @@ BEGIN
g_data_w => c_word_w,
g_symbol_w => c_octet_w,
g_hdr_field_arr => c_eth_tester_hdr_field_arr,
- g_remove_crc => FALSE,
+ g_remove_crc => g_remove_crc,
g_crc_nof_words => 1
)
PORT MAP (
@@ -140,6 +144,11 @@ BEGIN
decoded_length <= TO_UINT(hdr_fields_raw_slv(field_hi(c_eth_tester_hdr_field_arr, "dp_length") DOWNTO field_lo(c_eth_tester_hdr_field_arr, "dp_length")));
decoded_sosi.sync <= sl(hdr_fields_out_slv(field_hi(c_eth_tester_hdr_field_arr, "dp_sync") DOWNTO field_lo(c_eth_tester_hdr_field_arr, "dp_sync")));
decoded_sosi.bsn <= RESIZE_DP_BSN(hdr_fields_raw_slv(field_hi(c_eth_tester_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_eth_tester_hdr_field_arr, "dp_bsn")));
+ -- Map rx_offload_sosi.err c_tech_tse_error_w = 6 bit value on to c_error_w = 1 bit decoded_sosi.err value
+ decoded_sosi.err <= TO_DP_ERROR(0);
+ IF UNSIGNED(rx_offload_sosi.err(c_tech_tse_error_w-1 DOWNTO 0)) /= 0 THEN
+ decoded_sosi.err <= TO_DP_ERROR(1);
+ END IF;
END PROCESS;
-- synthesis translate_off
@@ -158,9 +167,11 @@ BEGIN
g_data_w => c_word_w,
g_bsn_w => c_diag_bg_bsn_init_w, -- = 64 bit
g_empty_w => c_empty_w,
+ g_error_w => c_error_w,
g_use_bsn => TRUE,
g_use_empty => TRUE,
g_use_sync => TRUE,
+ g_use_error => TRUE,
g_fifo_size => c_fifo_size
)
PORT MAP (
@@ -218,7 +229,15 @@ BEGIN
);
-- Rx CRC result is available at last octet
- crc_corrupt <= '1' WHEN rising_edge(st_clk) AND unpacked_sosi.eop = '1' AND UNSIGNED(unpacked_data) /= 0 ELSE '0';
+ p_crc_corrupt : PROCESS(st_clk)
+ BEGIN
+ IF rising_edge(st_clk) THEN
+ crc_corrupt <= '0';
+ IF unpacked_sosi.eop = '1' AND unpacked_sosi.err(0) = '1' THEN
+ crc_corrupt <= '1';
+ END IF;
+ END IF;
+ END PROCESS;
in_strobe_arr(0) <= unpacked_sosi.sop; -- count total nof Rx packets
in_strobe_arr(1) <= unpacked_sosi.valid; -- count total nof Rx valid octets
--
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