diff --git a/applications/arts/designs/arts_unb1_sc1_bg_1GbE/hdllib.cfg b/applications/arts/designs/arts_unb1_sc1_bg_1GbE/hdllib.cfg
index 26a2236291bbaf76f6505a56fda88e8458cba95d..b49c1748581554b65a9e9fd6850fc758dca2fceb 100644
--- a/applications/arts/designs/arts_unb1_sc1_bg_1GbE/hdllib.cfg
+++ b/applications/arts/designs/arts_unb1_sc1_bg_1GbE/hdllib.cfg
@@ -11,6 +11,8 @@ synth_files =
 test_bench_files =
     tb/vhdl/tb_arts_unb1_sc1_bg_1GbE.vhd
 
+regression_test_vhdl = 
+    tb/vhdl/tb_arts_unb1_sc1_bg_1GbE.vhd
 
 [modelsim_project_file]
 modelsim_copy_files = 
@@ -35,3 +37,5 @@ quartus_qip_files =
     
 quartus_tcl_files =
     $RADIOHDL/applications/arts/designs/arts_unb1_sc1_bg_1GbE/quartus/pinning/arts_unb1_sc1_bg_1GbE_pins.tcl
+
+
diff --git a/libraries/io/eth/src/vhdl/eth_statistics.vhd b/libraries/io/eth/src/vhdl/eth_statistics.vhd
index 1e350b7cd3507eb9ecb302ed785b941f5e4bb964..be3d0796321065df6eb95c87a7d11f5a24e404f8 100644
--- a/libraries/io/eth/src/vhdl/eth_statistics.vhd
+++ b/libraries/io/eth/src/vhdl/eth_statistics.vhd
@@ -149,7 +149,7 @@ BEGIN
   ------------------------------------------------------------------------------
   -- On tb_end; do the checks defined in the generics
   ------------------------------------------------------------------------------
-  p_tb_end_check: PROCESS(nxt_tb_end, timeout)
+  p_tb_end_check: PROCESS(eth_clk)
   BEGIN
     IF timeout='1' AND nxt_tb_end='0' THEN
       REPORT "[eth_statistics] Timeout occured!" SEVERITY FAILURE;