diff --git a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
index 6b507231b2dc1ee37e5e5f5d516b299168c93e7f..6937ac0de018e235f75f84c5e57b0306acc034e2 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
@@ -174,15 +174,20 @@ begin
     -- Determine and keep last expected sosi field values after end of stimuli
     -- . e_qual
     v_last.bsn     := std_logic_vector( unsigned(g_bsn_init) + g_nof_repeat - 1);
-    v_last.channel := TO_DP_CHANNEL(g_channel_init           + (g_nof_repeat - 1) * g_channel_incr);
-    v_last.err     := TO_DP_ERROR(g_err_init                 + (g_nof_repeat - 1) * g_err_incr);
+    v_last.channel := TO_DP_CHANNEL(g_channel_init + (g_nof_repeat - 1) * g_channel_incr);
+    v_last.err     := TO_DP_ERROR(g_err_init + (g_nof_repeat - 1) * g_err_incr);
     -- . account for g_pkt_len
     v_last.data    := INCR_UVEC(v_sosi.data, g_pkt_len - 1);
     v_last.data    := RESIZE_DP_DATA(v_last.data(g_in_dat_w - 1 downto 0));  -- wrap when >= 2**g_in_dat_w
+    v_last.re      := INCR_UVEC(v_sosi.re, g_pkt_len - 1);
+    v_last.re      := RESIZE_DP_DSP_DATA(v_last.re(g_in_dat_w - 1 downto 0));  -- wrap when >= 2**g_in_dat_w
+    v_last.im      := INCR_UVEC(v_sosi.im, g_pkt_len - 1);
+    v_last.im      := RESIZE_DP_DSP_DATA(v_last.im(g_in_dat_w - 1 downto 0));  -- wrap when >= 2**g_in_dat_w
     last_snk_in <= v_last;
 
     -- Signal end of stimuli
-    proc_common_wait_some_cycles(clk, g_wait_last_evt);  -- latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+    -- . latency from stimuli to verify depends on the flow control, so wait sufficiently long for last packet to have passed through
+    proc_common_wait_some_cycles(clk, g_wait_last_evt);
     proc_common_gen_pulse(clk, last_snk_in_evt);
     proc_common_wait_some_cycles(clk, 50);
     tb_end <= '1';