From bd6c05b2965bcbe54e8016e5c75a31d45fc12be1 Mon Sep 17 00:00:00 2001
From: Eric Kooistra <kooistra@astron.nl>
Date: Thu, 22 Jul 2021 10:20:57 +0200
Subject: [PATCH] Corrected number of mm_ports = 12 and mm_port_span = 256 for
JESD204B.
---
.../lofar2_unb2b_sdp_station.fpga.yaml | 2 ++
libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml | 6 ++++++
2 files changed, 8 insertions(+)
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index ef26e22f8b..259d0c1739 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -101,6 +101,8 @@ peripherals:
- PIO_JESD_CTRL
- peripheral_name: tech_jesd204b/jesd204b_arria10
+ parameter_overrides:
+ - { name: g_nof_streams, value: c_S_pn }
mm_port_names:
- JESD204B
diff --git a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
index 7fe5b2d604..26c020232c 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
+++ b/libraries/technology/jesd204b/tech_jesd204b.peripheral.yaml
@@ -12,6 +12,7 @@ peripherals:
# MM port for node_adc_input_and_timing.vhd
- mm_port_name: PIO_JESD_CTRL
mm_port_type: REG
+ mm_port_span: 2 * MM_BUS_SIZE
mm_port_description: ""
fields:
- - field_name: reset
@@ -30,11 +31,16 @@ peripherals:
- peripheral_name: jesd204b_arria10 # pi_jesd204b_unb2.py
peripheral_description: |
"M&C of Intel Arria10 JESD204B ADC interface IP, see https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf"
+ parameters:
+ # Parameters of tech_jesd204b.vhd
+ - { name: g_nof_streams, value: 1 }
mm_ports:
# MM port for tech_jesd204b.vhd
- mm_port_name: REG_JESD204B
mm_port_type: REG
+ mm_port_span: 256 * MM_BUS_SIZE # c_jesd204b_mm_addr_w = 8 bit, see ip_arria10_e1sg_jesd204b.vhd
mm_port_description: ""
+ number_of_mm_ports: g_nof_streams
fields:
- - {field_name: rx_dll_ctrl, mm_width: 17, bit_offset: 0, access_mode: RW, address_offset: 0x50}
- - {field_name: rx_syncn_sysref_ctrl, mm_width: 25, bit_offset: 0, access_mode: RW, address_offset: 0x54}
--
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