diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index 0d5b21ea615ec19a28357937cc811b4c43b23ddc..22099bf168a065ce4064308f9e30c4a84b12f1e0 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -111,29 +111,31 @@ USE work.dp_stream_pkg.ALL;
ENTITY dp_bsn_sync_scheduler IS
GENERIC (
- g_bsn_w : NATURAL := c_dp_stream_bsn_w;
- g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
- g_pipeline : NATURAL := 1 -- use '1' on HW, use '0' for easier debugging in Wave window
+ g_bsn_w : NATURAL := c_dp_stream_bsn_w;
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_ctrl_interval_size_min : NATURAL := 1; -- Minimum interval size to use if MM write interval size is set too small.
+ g_pipeline : NATURAL := 1 -- use '1' on HW, use '0' for easier debugging in Wave window
);
PORT (
- rst : IN STD_LOGIC;
- clk : IN STD_LOGIC;
+ rst : IN STD_LOGIC;
+ clk : IN STD_LOGIC;
-- M&C
- ctrl_enable : IN STD_LOGIC;
- ctrl_enable_evt : IN STD_LOGIC;
- ctrl_interval_size : IN NATURAL;
- ctrl_start_bsn : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
- mon_current_input_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- mon_input_bsn_at_sync : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- mon_output_enable : OUT STD_LOGIC;
- mon_output_sync_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ ctrl_enable : IN STD_LOGIC;
+ ctrl_enable_evt : IN STD_LOGIC;
+ ctrl_interval_size : IN NATURAL;
+ ctrl_start_bsn : IN STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ mon_current_input_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ mon_input_bsn_at_sync : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ mon_output_enable : OUT STD_LOGIC;
+ mon_output_interval_size : OUT NATURAL;
+ mon_output_sync_bsn : OUT STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
-- Streaming
- in_sosi : IN t_dp_sosi;
- out_sosi : OUT t_dp_sosi;
- out_start : OUT STD_LOGIC; -- pulse at out_sosi.sync at ctrl_start_bsn
- out_enable : OUT STD_LOGIC -- for tb verification purposes
+ in_sosi : IN t_dp_sosi;
+ out_sosi : OUT t_dp_sosi;
+ out_start : OUT STD_LOGIC; -- pulse at out_sosi.sync at ctrl_start_bsn
+ out_enable : OUT STD_LOGIC -- for tb verification purposes
);
END dp_bsn_sync_scheduler;
@@ -158,7 +160,7 @@ ARCHITECTURE rtl OF dp_bsn_sync_scheduler IS
output_sync_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
END RECORD;
- CONSTANT c_reg_rst : t_reg := ('0', '0', 0, 0, (OTHERS=>'0'), (OTHERS=>'0'), 0, 0, 0, 0, 0, '1', '0', '0', (OTHERS=>'0'));
+ CONSTANT c_reg_rst : t_reg := ('0', '0', 0, g_ctrl_interval_size_min, (OTHERS=>'0'), (OTHERS=>'0'), 0, 0, 0, 0, 0, '1', '0', '0', (OTHERS=>'0'));
-- Local registers
SIGNAL r : t_reg;
@@ -173,10 +175,11 @@ BEGIN
ASSERT g_block_size >= 2 REPORT "g_block_size must be >= 2." SEVERITY FAILURE;
-- Capture monitoring info
- mon_current_input_bsn <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sop = '1';
- mon_input_bsn_at_sync <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sync = '1';
- mon_output_enable <= r.output_enable;
- mon_output_sync_bsn <= r.output_sync_bsn;
+ mon_current_input_bsn <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sop = '1';
+ mon_input_bsn_at_sync <= in_sosi.bsn(g_bsn_w-1 DOWNTO 0) WHEN rising_edge(clk) AND in_sosi.sync = '1';
+ mon_output_enable <= r.output_enable;
+ mon_output_interval_size <= g_ctrl_interval_size_min WHEN rst='1' ELSE r.interval_size WHEN rising_edge(clk) AND output_start = '1';
+ mon_output_sync_bsn <= r.output_sync_bsn;
p_clk : PROCESS(rst, clk)
BEGIN
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 75b42316d077b32591da03f6a12aff7ee6da26d9..9cfe48f8dba79806999f160015e2e625b4753190 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -22,7 +22,8 @@
--
-- wi Bits Access Type Name
-- 0 [0] RW boolean ctrl_enable, '1' is on, '0' is FALSE is off
--- 1 [31:0] RW uint32 ctrl_interval_size
+-- 1 [31:0] RW uint32 W: ctrl_interval_size
+-- R: mon_output_interval_size
-- 2 [31:0] RW uint64 ctrl_start_bsn[31:0]
-- 3 [31:0] RW ctrl_start_bsn[63:32]
-- 4 [31:0] RO uint64 mon_current_input_bsn[31:0]
@@ -63,7 +64,7 @@ USE work.dp_stream_pkg.ALL;
ENTITY mmp_dp_bsn_sync_scheduler IS
GENERIC (
g_bsn_w : NATURAL := c_dp_stream_bsn_w;
- g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
+ g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
g_ctrl_interval_size_min : NATURAL := 1 -- Minimum interval size to use if MM write interval size is set too small.
);
PORT (
@@ -95,20 +96,21 @@ ARCHITECTURE str OF mmp_dp_bsn_sync_scheduler IS
-- init_sl : STD_LOGIC; -- optional, init all dat words to std_logic '0', '1' or 'X'
CONSTANT c_mm_reg : t_c_mem := (1, 4, c_word_w, 12, '0');
- SIGNAL reg_wr_arr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat -1 DOWNTO 0);
- SIGNAL reg_wr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
- SIGNAL reg_rd : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
-
- SIGNAL wr_ctrl_enable : STD_LOGIC;
- SIGNAL wr_ctrl_enable_evt : STD_LOGIC;
- SIGNAL ctrl_enable : STD_LOGIC := '0';
- SIGNAL ctrl_enable_evt : STD_LOGIC := '0';
- SIGNAL ctrl_interval_size : NATURAL;
- SIGNAL ctrl_start_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL mon_current_input_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- SIGNAL mon_input_bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
- SIGNAL mon_output_enable : STD_LOGIC;
- SIGNAL mon_output_sync_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL reg_wr_arr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat -1 DOWNTO 0);
+ SIGNAL reg_wr : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0);
+ SIGNAL reg_rd : STD_LOGIC_VECTOR(c_mm_reg.nof_dat*c_mm_reg.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
+
+ SIGNAL wr_ctrl_enable : STD_LOGIC;
+ SIGNAL wr_ctrl_enable_evt : STD_LOGIC;
+ SIGNAL ctrl_enable : STD_LOGIC := '0';
+ SIGNAL ctrl_enable_evt : STD_LOGIC := '0';
+ SIGNAL ctrl_interval_size : NATURAL;
+ SIGNAL ctrl_start_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0) := (OTHERS=>'0');
+ SIGNAL mon_current_input_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL mon_input_bsn_at_sync : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
+ SIGNAL mon_output_enable : STD_LOGIC;
+ SIGNAL mon_output_interval_size : NATURAL;
+ SIGNAL mon_output_sync_bsn : STD_LOGIC_VECTOR(g_bsn_w-1 DOWNTO 0);
-- Resize BSN values to 64 bit
SIGNAL wr_start_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
@@ -151,7 +153,7 @@ BEGIN
-- . Read
reg_rd( 0) <= ctrl_enable; -- read back internal ctrl_enable
- reg_rd( 2*c_word_w-1 DOWNTO 1*c_word_w) <= TO_UVEC(ctrl_interval_size, c_word_w);
+ reg_rd( 2*c_word_w-1 DOWNTO 1*c_word_w) <= TO_UVEC(mon_output_interval_size, c_word_w);
reg_rd( 3*c_word_w-1 DOWNTO 2*c_word_w) <= wr_start_bsn_64( c_word_w-1 DOWNTO 0); -- low word
reg_rd( 4*c_word_w-1 DOWNTO 3*c_word_w) <= wr_start_bsn_64( 2*c_word_w-1 DOWNTO c_word_w); -- high word
reg_rd( 5*c_word_w-1 DOWNTO 4*c_word_w) <= rd_current_input_bsn_64( c_word_w-1 DOWNTO 0); -- low word
@@ -189,29 +191,31 @@ BEGIN
u_dp_bsn_sync_scheduler : ENTITY work.dp_bsn_sync_scheduler
GENERIC MAP (
- g_bsn_w => g_bsn_w,
- g_block_size => g_block_size,
- g_pipeline => 1
+ g_bsn_w => g_bsn_w,
+ g_block_size => g_block_size,
+ g_ctrl_interval_size_min => g_ctrl_interval_size_min,
+ g_pipeline => 1
)
PORT MAP (
- rst => dp_rst,
- clk => dp_clk,
+ rst => dp_rst,
+ clk => dp_clk,
-- M&C
- ctrl_enable => ctrl_enable,
- ctrl_enable_evt => ctrl_enable_evt,
- ctrl_interval_size => ctrl_interval_size,
- ctrl_start_bsn => ctrl_start_bsn,
- mon_current_input_bsn => mon_current_input_bsn,
- mon_input_bsn_at_sync => mon_input_bsn_at_sync,
- mon_output_enable => mon_output_enable,
- mon_output_sync_bsn => mon_output_sync_bsn,
+ ctrl_enable => ctrl_enable,
+ ctrl_enable_evt => ctrl_enable_evt,
+ ctrl_interval_size => ctrl_interval_size,
+ ctrl_start_bsn => ctrl_start_bsn,
+ mon_current_input_bsn => mon_current_input_bsn,
+ mon_input_bsn_at_sync => mon_input_bsn_at_sync,
+ mon_output_enable => mon_output_enable,
+ mon_output_interval_size => mon_output_interval_size,
+ mon_output_sync_bsn => mon_output_sync_bsn,
-- Streaming
- in_sosi => in_sosi,
- out_sosi => out_sosi,
- out_start => out_start,
- out_enable => out_enable
+ in_sosi => in_sosi,
+ out_sosi => out_sosi,
+ out_start => out_start,
+ out_enable => out_enable
);
END str;
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
index ce4e5f605e7efbba13cb3ec7a972a5d9b9548805..43162d9c6df7dd1b3e4b768e0353f9f65d51e791 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -52,6 +52,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_sync_scheduler IS
CONSTANT c_nof_block_per_input_sync : NATURAL := 17;
CONSTANT c_nof_block_per_output_sync : NATURAL := 5;
CONSTANT c_block_size : NATURAL := 10;
+ CONSTANT c_ctrl_interval_size_min : NATURAL := 19; -- Minimum interval size to use if MM write interval size is set too small.
CONSTANT c_input_gap_size : NATURAL := 3;
CONSTANT c_sim_nof_blocks : NATURAL := c_nof_block_per_input_sync * c_nof_input_sync;
@@ -75,6 +76,7 @@ ARCHITECTURE tb OF tb_mmp_dp_bsn_sync_scheduler IS
SIGNAL ctrl_start_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_output_enable : STD_LOGIC;
+ SIGNAL mon_output_interval_size : NATURAL;
SIGNAL mon_current_input_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_input_bsn_at_sync_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
SIGNAL mon_output_sync_bsn_64 : STD_LOGIC_VECTOR(2*c_word_w-1 DOWNTO 0);
@@ -118,6 +120,13 @@ BEGIN
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_block_size = c_block_size REPORT "Wrong block_size." SEVERITY ERROR;
+ -- . Read mon_output_interval_size
+ proc_mem_mm_bus_rd(1, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ mon_output_interval_size <= TO_UINT(reg_miso.rddata(c_word_w-1 DOWNTO 0));
+ proc_common_wait_some_cycles(mm_clk, 1);
+ ASSERT mon_output_interval_size = c_ctrl_interval_size_min REPORT "Wrong minimum output interval_size." SEVERITY ERROR;
+
-- . Read mon_output_enable
proc_mem_mm_bus_rd(8, mm_clk, reg_miso, reg_mosi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
@@ -214,10 +223,16 @@ BEGIN
proc_mem_mm_bus_rd_latency(1, mm_clk);
mon_output_enable <= reg_miso.rddata(0);
+ -- . Read mon_output_interval_size
+ proc_mem_mm_bus_rd(1, mm_clk, reg_miso, reg_mosi);
+ proc_mem_mm_bus_rd_latency(1, mm_clk);
+ mon_output_interval_size <= TO_UINT(reg_miso.rddata(c_word_w-1 DOWNTO 0));
+
-- Verify output is on and running
proc_common_wait_some_cycles(mm_clk, 1);
ASSERT mon_output_enable = '1' REPORT "mon_output_enable is not enabled." SEVERITY ERROR;
ASSERT out_enable = '1' REPORT "output_enable is not enabled." SEVERITY ERROR;
+ ASSERT mon_output_interval_size = c_ctrl_interval_size REPORT "mon_output_interval_size is not ctrl_interval_size." SEVERITY ERROR;
---------------------------------------------------------------------------
-- Check that monitor BSN are incrementing
@@ -381,8 +396,9 @@ BEGIN
u_mmp_dp_bsn_sync_scheduler : ENTITY work.mmp_dp_bsn_sync_scheduler
GENERIC MAP (
- g_bsn_w => c_bsn_w,
- g_block_size => c_block_size
+ g_bsn_w => c_bsn_w,
+ g_block_size => c_block_size,
+ g_ctrl_interval_size_min => c_ctrl_interval_size_min
)
PORT MAP (
-- Clocks and reset