diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 72263827c36312d13ea97ddcd2c0b11cc28e2d4f..44d48af186c2691e98c150bd1cef97d9b7dda1d0 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -101,11 +101,14 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
SIGNAL dev_lane_aligned_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL rx_csr_lane_powerdown_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
- SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL pll_reset_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0) := (OTHERS => '1');
- SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
- SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rxlink_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
+ SIGNAL rxframe_rst_async_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL rxframe_rst_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL rx_avs_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
SIGNAL rxlink_rst_n_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
@@ -117,8 +120,6 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
SIGNAL jesd204b_sysref_2 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_1 : STD_LOGIC;
SIGNAL jesd204b_sysref_frameclk_2 : STD_LOGIC;
- SIGNAL jesd204b_sysref_linkclk_1 : STD_LOGIC;
- SIGNAL jesd204b_sysref_linkclk_2 : STD_LOGIC;
-- Data path
SIGNAL jesd204b_rx_link_data_arr : STD_LOGIC_VECTOR(c_jesd204b_rx_data_w*g_nof_streams-1 DOWNTO 0);
@@ -176,7 +177,7 @@ ARCHITECTURE str OF ip_arria10_e2sg_jesd204b IS
rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
rxphy_clk : out std_logic_vector(0 downto 0); -- export
sof : out std_logic_vector(3 downto 0); -- export
somf : out std_logic_vector(c_jesd204b_rx_somf_w-1 downto 0); -- export
@@ -328,16 +329,43 @@ BEGIN
reset2_dsrt_qual => '1', -- Tied to '1' in example design. Tx xcvr is not used.
reset5_dsrt_qual => rx_xcvr_ready_in_arr(i),
reset_in0 => mm_rst,
- reset_out0 => pll_reset_arr(i), -- Use channel 0 to reset the core pll
+ reset_out0 => pll_reset_async_arr(i), -- Use channel 0 to reset the core pll
reset_out1 => xcvr_rst_arr(i), -- Use channel 1 to reset the transceiver reset controller
reset_out2 => open,
reset_out3 => open,
reset_out4 => open,
- reset_out5 => rx_avs_rst_arr(i),
- reset_out6 => rxlink_rst_arr(i),
- reset_out7 => rxframe_rst_arr(i)
+ reset_out5 => rx_avs_rst_arr(i), -- mm_clk domain
+ reset_out6 => rxlink_rst_async_arr(i),
+ reset_out7 => rxframe_rst_async_arr(i)
);
+ -- synchronize pll_reset
+ u_common_areset_pll : ENTITY common_lib.common_areset
+ PORT MAP (
+ in_rst => pll_reset_async_arr(i),
+ clk => jesd204b_refclk,
+ out_rst => pll_reset_arr(i)
+ );
+
+ -- No need to synchronize xcvr_rst as it is synchronized in ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12
+
+ -- synchronize rxlink reset
+ u_common_areset_rxlink : ENTITY common_lib.common_areset
+ PORT MAP (
+ in_rst => rxlink_rst_async_arr(i),
+ clk => rxlink_clk,
+ out_rst => rxlink_rst_arr(i)
+ );
+
+ -- synchronize rxframe reset
+ u_common_areset_rxframe : ENTITY common_lib.common_areset
+ PORT MAP (
+ in_rst => rxframe_rst_async_arr(i),
+ clk => rxframe_clk,
+ out_rst => rxframe_rst_arr(i)
+ );
+
+
rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
-- Invert thr active-low resets
@@ -399,7 +427,6 @@ BEGIN
END IF;
END PROCESS;
-
-----------------------------------------------------------------------------
-- Move sysref from rxlink_clk to rxframe_clk
-----------------------------------------------------------------------------
@@ -412,7 +439,7 @@ BEGIN
ELSE
IF rising_edge(rxframe_clk) THEN
jesd204b_sysref_frameclk_1 <= jesd204b_sysref_2; -- sysref from rxlink_clk domain
- jesd204b_sysref_frameclk_2 <= jesd204b_sysref_linkclk_1;
+ jesd204b_sysref_frameclk_2 <= jesd204b_sysref_frameclk_1;
IF jesd204b_sysref_frameclk_1 = '1' and jesd204b_sysref_frameclk_2 = '0' THEN
rx_sysref <= '1';
ELSE
@@ -435,25 +462,24 @@ BEGIN
);
END GENERATE;
- p_pll_locked_reg : PROCESS (mm_rst, mm_clk)
- BEGIN
- IF mm_rst = '1' THEN
- core_pll_locked_reg <= '0';
- ELSE
- IF rising_edge(mm_clk) THEN
- core_pll_locked_reg <= core_pll_locked;
- END IF;
- END IF;
- END PROCESS;
+ u_common_areset_pll_locked : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '0' -- synchronises the rising edge input.
+ )
+ PORT MAP (
+ in_rst => core_pll_locked,
+ clk => mm_clk,
+ out_rst => core_pll_locked_reg
+ );
-- Transceiver reset controller. Use g_nof_streams out of 12 channels. Receive only
- -- Clock set to 100MHz (use mm_clk)
+ -- Clock set to 100MHz (use rxlink_clk)
u_ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control : ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12
PORT MAP (
- clock => mm_clk,
- reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design
+ clock => rxlink_clk,
+ reset => xcvr_rst_arr(0), -- From Reset Sequencer output1 as per example design, the reset input is synchronised internally.
rx_analogreset => rx_analogreset_arr, -- output to reset RX PMA. Release before deasserting link and avs resets (Intel JESD204B-UG p70)
rx_cal_busy => rx_cal_busy_arr, -- input from PHY
rx_digitalreset => rx_digitalreset_arr, -- output to reset RX PCS. Release before deasserting link and avs resets (Intel JESD204B-UG p70)