diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0.ip
index 3191ec23f4cfc8c3ddc57373b06ac794aab8a3ae..ae7093a5e2dc859102e19403b588cf4388ac82e4 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0.ip
@@ -2,7 +2,7 @@
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_arts_unb2b_sc3_avs_eth_0</spirit:library>
- <spirit:name>qsys_arts_unb2b_sc3_avs_eth_0</spirit:name>
+ <spirit:name>avs_eth_0</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -3646,36 +3646,36 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="avs_eth_0.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="interrupt" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.interrupt" altera:type="interrupt" altera:dir="end">
+ <altera:interface_mapping altera:name="interrupt" altera:internal="avs_eth_0.interrupt" altera:type="interrupt" altera:dir="end">
<altera:port_mapping altera:name="ins_interrupt_irq" altera:internal="ins_interrupt_irq"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="irq" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.irq" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="irq" altera:internal="avs_eth_0.irq" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_irq_export" altera:internal="coe_irq_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mm" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.mm" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="mm" altera:internal="avs_eth_0.mm" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_mm_clk" altera:internal="csi_mm_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mm_reset" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.mm_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="mm_reset" altera:internal="avs_eth_0.mm_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_mm_reset" altera:internal="csi_mm_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mms_ram" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.mms_ram" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mms_ram" altera:internal="avs_eth_0.mms_ram" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="mms_ram_address" altera:internal="mms_ram_address"></altera:port_mapping>
<altera:port_mapping altera:name="mms_ram_read" altera:internal="mms_ram_read"></altera:port_mapping>
<altera:port_mapping altera:name="mms_ram_readdata" altera:internal="mms_ram_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="mms_ram_write" altera:internal="mms_ram_write"></altera:port_mapping>
<altera:port_mapping altera:name="mms_ram_writedata" altera:internal="mms_ram_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mms_reg" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.mms_reg" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mms_reg" altera:internal="avs_eth_0.mms_reg" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="mms_reg_address" altera:internal="mms_reg_address"></altera:port_mapping>
<altera:port_mapping altera:name="mms_reg_read" altera:internal="mms_reg_read"></altera:port_mapping>
<altera:port_mapping altera:name="mms_reg_readdata" altera:internal="mms_reg_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="mms_reg_write" altera:internal="mms_reg_write"></altera:port_mapping>
<altera:port_mapping altera:name="mms_reg_writedata" altera:internal="mms_reg_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mms_tse" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.mms_tse" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mms_tse" altera:internal="avs_eth_0.mms_tse" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="mms_tse_address" altera:internal="mms_tse_address"></altera:port_mapping>
<altera:port_mapping altera:name="mms_tse_read" altera:internal="mms_tse_read"></altera:port_mapping>
<altera:port_mapping altera:name="mms_tse_readdata" altera:internal="mms_tse_readdata"></altera:port_mapping>
@@ -3683,55 +3683,55 @@
<altera:port_mapping altera:name="mms_tse_write" altera:internal="mms_tse_write"></altera:port_mapping>
<altera:port_mapping altera:name="mms_tse_writedata" altera:internal="mms_tse_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_address" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.ram_address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_address" altera:internal="avs_eth_0.ram_address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_address_export" altera:internal="coe_ram_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_read" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.ram_read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_read" altera:internal="avs_eth_0.ram_read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_read_export" altera:internal="coe_ram_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_readdata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.ram_readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_readdata" altera:internal="avs_eth_0.ram_readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_readdata_export" altera:internal="coe_ram_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_write" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.ram_write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_write" altera:internal="avs_eth_0.ram_write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_write_export" altera:internal="coe_ram_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_writedata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.ram_writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_writedata" altera:internal="avs_eth_0.ram_writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_writedata_export" altera:internal="coe_ram_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_address" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.reg_address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_address" altera:internal="avs_eth_0.reg_address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_address_export" altera:internal="coe_reg_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_read" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.reg_read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_read" altera:internal="avs_eth_0.reg_read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_read_export" altera:internal="coe_reg_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_readdata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.reg_readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_readdata" altera:internal="avs_eth_0.reg_readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_readdata_export" altera:internal="coe_reg_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_write" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.reg_write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_write" altera:internal="avs_eth_0.reg_write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_write_export" altera:internal="coe_reg_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_writedata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.reg_writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_writedata" altera:internal="avs_eth_0.reg_writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_writedata_export" altera:internal="coe_reg_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="avs_eth_0.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_address" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.tse_address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_address" altera:internal="avs_eth_0.tse_address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_address_export" altera:internal="coe_tse_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_read" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.tse_read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_read" altera:internal="avs_eth_0.tse_read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_read_export" altera:internal="coe_tse_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_readdata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.tse_readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_readdata" altera:internal="avs_eth_0.tse_readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_readdata_export" altera:internal="coe_tse_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_waitrequest" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.tse_waitrequest" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_waitrequest" altera:internal="avs_eth_0.tse_waitrequest" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_waitrequest_export" altera:internal="coe_tse_waitrequest_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_write" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.tse_write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_write" altera:internal="avs_eth_0.tse_write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_write_export" altera:internal="coe_tse_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_writedata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_0.tse_writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_writedata" altera:internal="avs_eth_0.tse_writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_writedata_export" altera:internal="coe_tse_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0/qsys_arts_unb2b_sc3_avs_eth_0_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0/qsys_arts_unb2b_sc3_avs_eth_0_generation.rpt
deleted file mode 100644
index c964dca5e0831b352a235a3b4d48d2a57dd589dd..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0/qsys_arts_unb2b_sc3_avs_eth_0_generation.rpt
+++ /dev/null
@@ -1,67 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Warning: qsys_arts_unb2b_sc3_avs_eth_0: Component type avs2_eth_coe is not in the library
-Error: qsys_arts_unb2b_sc3_avs_eth_0.qsys_arts_unb2b_sc3_avs_eth_0: Component avs2_eth_coe 1.0 not found or could not be instantiated
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "clk". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "interrupt". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "irq". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mm". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mm_reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_ram". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_reg". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_tse". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_waitrequest". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Error: qsys-generate failed with exit code 1: 1 Error, 26 Warnings
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Warning: qsys_arts_unb2b_sc3_avs_eth_0: Component type avs2_eth_coe is not in the library
-Error: qsys_arts_unb2b_sc3_avs_eth_0.qsys_arts_unb2b_sc3_avs_eth_0: Component avs2_eth_coe 1.0 not found or could not be instantiated
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "clk". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "interrupt". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "irq". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mm". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mm_reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_ram". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_reg". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "mms_tse". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "ram_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reg_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_waitrequest". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_0.interface_requirements: Your system is missing the required interface "tse_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Error: qsys-generate failed with exit code 1: 1 Error, 26 Warnings
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_avs_eth_0. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1.ip
index 3cc6759a0588f521e9046a0eafb605eeb1c15099..a59d3cd60449bc32cb18a5281d447d516a9dc1bc 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1.ip
@@ -2,7 +2,7 @@
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_arts_unb2b_sc3_avs_eth_1</spirit:library>
- <spirit:name>qsys_arts_unb2b_sc3_avs_eth_1</spirit:name>
+ <spirit:name>avs_eth_1</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
@@ -3646,36 +3646,36 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.clk" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="clk" altera:internal="avs_eth_1.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="interrupt" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.interrupt" altera:type="interrupt" altera:dir="end">
+ <altera:interface_mapping altera:name="interrupt" altera:internal="avs_eth_1.interrupt" altera:type="interrupt" altera:dir="end">
<altera:port_mapping altera:name="ins_interrupt_irq" altera:internal="ins_interrupt_irq"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="irq" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.irq" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="irq" altera:internal="avs_eth_1.irq" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_irq_export" altera:internal="coe_irq_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mm" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.mm" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="mm" altera:internal="avs_eth_1.mm" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_mm_clk" altera:internal="csi_mm_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mm_reset" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.mm_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="mm_reset" altera:internal="avs_eth_1.mm_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_mm_reset" altera:internal="csi_mm_reset"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mms_ram" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.mms_ram" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mms_ram" altera:internal="avs_eth_1.mms_ram" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="mms_ram_address" altera:internal="mms_ram_address"></altera:port_mapping>
<altera:port_mapping altera:name="mms_ram_read" altera:internal="mms_ram_read"></altera:port_mapping>
<altera:port_mapping altera:name="mms_ram_readdata" altera:internal="mms_ram_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="mms_ram_write" altera:internal="mms_ram_write"></altera:port_mapping>
<altera:port_mapping altera:name="mms_ram_writedata" altera:internal="mms_ram_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mms_reg" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.mms_reg" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mms_reg" altera:internal="avs_eth_1.mms_reg" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="mms_reg_address" altera:internal="mms_reg_address"></altera:port_mapping>
<altera:port_mapping altera:name="mms_reg_read" altera:internal="mms_reg_read"></altera:port_mapping>
<altera:port_mapping altera:name="mms_reg_readdata" altera:internal="mms_reg_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="mms_reg_write" altera:internal="mms_reg_write"></altera:port_mapping>
<altera:port_mapping altera:name="mms_reg_writedata" altera:internal="mms_reg_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="mms_tse" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.mms_tse" altera:type="avalon" altera:dir="end">
+ <altera:interface_mapping altera:name="mms_tse" altera:internal="avs_eth_1.mms_tse" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="mms_tse_address" altera:internal="mms_tse_address"></altera:port_mapping>
<altera:port_mapping altera:name="mms_tse_read" altera:internal="mms_tse_read"></altera:port_mapping>
<altera:port_mapping altera:name="mms_tse_readdata" altera:internal="mms_tse_readdata"></altera:port_mapping>
@@ -3683,55 +3683,55 @@
<altera:port_mapping altera:name="mms_tse_write" altera:internal="mms_tse_write"></altera:port_mapping>
<altera:port_mapping altera:name="mms_tse_writedata" altera:internal="mms_tse_writedata"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_address" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.ram_address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_address" altera:internal="avs_eth_1.ram_address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_address_export" altera:internal="coe_ram_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_read" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.ram_read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_read" altera:internal="avs_eth_1.ram_read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_read_export" altera:internal="coe_ram_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_readdata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.ram_readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_readdata" altera:internal="avs_eth_1.ram_readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_readdata_export" altera:internal="coe_ram_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_write" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.ram_write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_write" altera:internal="avs_eth_1.ram_write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_write_export" altera:internal="coe_ram_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="ram_writedata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.ram_writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="ram_writedata" altera:internal="avs_eth_1.ram_writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_ram_writedata_export" altera:internal="coe_ram_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_address" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.reg_address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_address" altera:internal="avs_eth_1.reg_address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_address_export" altera:internal="coe_reg_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_read" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.reg_read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_read" altera:internal="avs_eth_1.reg_read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_read_export" altera:internal="coe_reg_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_readdata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.reg_readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_readdata" altera:internal="avs_eth_1.reg_readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_readdata_export" altera:internal="coe_reg_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_write" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.reg_write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_write" altera:internal="avs_eth_1.reg_write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_write_export" altera:internal="coe_reg_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reg_writedata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.reg_writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reg_writedata" altera:internal="avs_eth_1.reg_writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reg_writedata_export" altera:internal="coe_reg_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="reset" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.reset" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="reset" altera:internal="avs_eth_1.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_address" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.tse_address" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_address" altera:internal="avs_eth_1.tse_address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_address_export" altera:internal="coe_tse_address_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_read" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.tse_read" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_read" altera:internal="avs_eth_1.tse_read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_read_export" altera:internal="coe_tse_read_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_readdata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.tse_readdata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_readdata" altera:internal="avs_eth_1.tse_readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_readdata_export" altera:internal="coe_tse_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_waitrequest" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.tse_waitrequest" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_waitrequest" altera:internal="avs_eth_1.tse_waitrequest" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_waitrequest_export" altera:internal="coe_tse_waitrequest_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_write" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.tse_write" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_write" altera:internal="avs_eth_1.tse_write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_write_export" altera:internal="coe_tse_write_export"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="tse_writedata" altera:internal="qsys_arts_unb2b_sc3_avs_eth_1.tse_writedata" altera:type="conduit" altera:dir="end">
+ <altera:interface_mapping altera:name="tse_writedata" altera:internal="avs_eth_1.tse_writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_tse_writedata_export" altera:internal="coe_tse_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1/qsys_arts_unb2b_sc3_avs_eth_1_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1/qsys_arts_unb2b_sc3_avs_eth_1_generation.rpt
deleted file mode 100644
index bf49d73f04d88039efb2d5a905603ac51aeb63c8..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1/qsys_arts_unb2b_sc3_avs_eth_1_generation.rpt
+++ /dev/null
@@ -1,67 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1 --family="Arria 10" --part=10AX115U2F45E1SG
-Warning: qsys_arts_unb2b_sc3_avs_eth_1: Component type avs2_eth_coe is not in the library
-Error: qsys_arts_unb2b_sc3_avs_eth_1.qsys_arts_unb2b_sc3_avs_eth_1: Component avs2_eth_coe 1.0 not found or could not be instantiated
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "clk". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "interrupt". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "irq". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mm". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mm_reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_ram". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_reg". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_tse". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_waitrequest". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Error: qsys-generate failed with exit code 1: 1 Error, 26 Warnings
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1 --family="Arria 10" --part=10AX115U2F45E1SG
-Warning: qsys_arts_unb2b_sc3_avs_eth_1: Component type avs2_eth_coe is not in the library
-Error: qsys_arts_unb2b_sc3_avs_eth_1.qsys_arts_unb2b_sc3_avs_eth_1: Component avs2_eth_coe 1.0 not found or could not be instantiated
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "clk". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "interrupt". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "irq". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mm". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mm_reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_ram". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_reg". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "mms_tse". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "ram_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reg_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "reset". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_address". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_read". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_readdata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_waitrequest". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_write". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Warning: qsys_arts_unb2b_sc3_avs_eth_1.interface_requirements: Your system is missing the required interface "tse_writedata". Either export the interface, or edit your definitions in the Interface Requirements tab."
-Error: qsys-generate failed with exit code 1: 1 Error, 26 Warnings
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_avs_eth_1. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_0.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_0.ip
index 3a8451ded022ed6e8932eb8341b827678863a769..2bf648aeb4e28a95492d361c259646d015dc4722 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_0.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_0.ip
@@ -2,8 +2,8 @@
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>Altera Corporation</spirit:vendor>
<spirit:library>qsys_arts_unb2b_sc3_clk_0</spirit:library>
- <spirit:name>qsys_arts_unb2b_sc3_clk_0</spirit:name>
- <spirit:version>0</spirit:version>
+ <spirit:name>clk_0</spirit:name>
+ <spirit:version>17.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
@@ -47,48 +47,6 @@
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk1</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="17.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>clk</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>clk_clk</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>qsys.ui.export_name</spirit:name>
- <spirit:value spirit:format="string" spirit:id="qsys.ui.export_name">qsys_arts_unb2b_sc3_clk_0_clk</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk_in</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="17.0"></spirit:busType>
@@ -168,48 +126,6 @@
</altera:altera_assignments>
</spirit:vendorExtensions>
</spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk_in_reset1</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="17.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset_n</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>clk_in_reset_reset_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>qsys.ui.export_name</spirit:name>
- <spirit:value spirit:format="string" spirit:id="qsys.ui.export_name">qsys_arts_unb2b_sc3_clk_0_clk_in_reset</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk_reset</spirit:name>
<spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="17.0"></spirit:busType>
@@ -247,73 +163,19 @@
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
- <spirit:busInterface>
- <spirit:name>clk_reset1</spirit:name>
- <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="17.0"></spirit:busType>
- <spirit:slave></spirit:slave>
- <spirit:portMaps>
- <spirit:portMap>
- <spirit:logicalPort>
- <spirit:name>reset_n</spirit:name>
- </spirit:logicalPort>
- <spirit:physicalPort>
- <spirit:name>clk_reset_reset_n</spirit:name>
- </spirit:physicalPort>
- </spirit:portMap>
- </spirit:portMaps>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>associatedClock</spirit:name>
- <spirit:displayName>associatedClock</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>associatedReset</spirit:name>
- <spirit:displayName>associatedReset</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>prSafe</spirit:name>
- <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- <spirit:vendorExtensions>
- <altera:altera_assignments>
- <spirit:parameters>
- <spirit:parameter>
- <spirit:name>qsys.ui.export_name</spirit:name>
- <spirit:value spirit:format="string" spirit:id="qsys.ui.export_name">qsys_arts_unb2b_sc3_clk_0_clk_reset</spirit:value>
- </spirit:parameter>
- </spirit:parameters>
- </altera:altera_assignments>
- </spirit:vendorExtensions>
- </spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>QUARTUS_SYNTH</spirit:name>
<spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
- <spirit:modelName>clk_0_hw</spirit:modelName>
+ <spirit:modelName>clock_source</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>QUARTUS_SYNTH</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
- <spirit:port>
- <spirit:name>clk_out</spirit:name>
- <spirit:wire>
- <spirit:direction>out</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
<spirit:port>
<spirit:name>in_clk</spirit:name>
<spirit:wire>
@@ -339,7 +201,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>reset_n_out</spirit:name>
+ <spirit:name>clk_out</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -351,19 +213,7 @@
</spirit:wire>
</spirit:port>
<spirit:port>
- <spirit:name>clk_clk</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
- <spirit:port>
- <spirit:name>clk_in_reset_reset_n</spirit:name>
+ <spirit:name>reset_n_out</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
@@ -374,34 +224,37 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
- <spirit:port>
- <spirit:name>clk_reset_reset_n</spirit:name>
- <spirit:wire>
- <spirit:direction>in</spirit:direction>
- <spirit:wireTypeDefs>
- <spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC</spirit:typeName>
- <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
- </spirit:wireTypeDef>
- </spirit:wireTypeDefs>
- </spirit:wire>
- </spirit:port>
</spirit:ports>
</spirit:model>
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>Altera Corporation</spirit:vendor>
<spirit:library>qsys_arts_unb2b_sc3_clk_0</spirit:library>
- <spirit:name>clk_0_hw</spirit:name>
- <spirit:version>0</spirit:version>
+ <spirit:name>clock_source</spirit:name>
+ <spirit:version>17.0</spirit:version>
</altera:entity_info>
<altera:altera_module_parameters>
<spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockFrequency</spirit:name>
+ <spirit:displayName>Clock frequency</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockFrequency">125000000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>clockFrequencyKnown</spirit:name>
+ <spirit:displayName>Clock frequency is known</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="clockFrequencyKnown">true</spirit:value>
+ </spirit:parameter>
<spirit:parameter>
<spirit:name>inputClockFrequency</spirit:name>
<spirit:displayName>inputClockFrequency</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="inputClockFrequency">0</spirit:value>
</spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>resetSynchronousEdges</spirit:name>
+ <spirit:displayName>Reset synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="resetSynchronousEdges">NONE</spirit:value>
+ </spirit:parameter>
</spirit:parameters>
</altera:altera_module_parameters>
<altera:altera_system_parameters>
@@ -480,43 +333,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>clk1</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_clk</name>
- <role>clk</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>qsys_arts_unb2b_sc3_clk_0_clk</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>clk_in</name>
<type>clock</type>
@@ -589,43 +405,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>clk_in_reset1</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_in_reset_reset_n</name>
- <role>reset_n</role>
- <direction>Output</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>qsys_arts_unb2b_sc3_clk_0_clk_in_reset</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
<interface>
<name>clk_reset</name>
<type>reset</type>
@@ -663,43 +442,6 @@
</parameterValueMap>
</parameters>
</interface>
- <interface>
- <name>clk_reset1</name>
- <type>conduit</type>
- <isStart>false</isStart>
- <ports>
- <port>
- <name>clk_reset_reset_n</name>
- <role>reset_n</role>
- <direction>Input</direction>
- <width>1</width>
- <lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC</vhdlType>
- </port>
- </ports>
- <assignments>
- <assignmentValueMap>
- <entry>
- <key>qsys.ui.export_name</key>
- <value>qsys_arts_unb2b_sc3_clk_0_clk_reset</value>
- </entry>
- </assignmentValueMap>
- </assignments>
- <parameters>
- <parameterValueMap>
- <entry>
- <key>associatedClock</key>
- </entry>
- <entry>
- <key>associatedReset</key>
- </entry>
- <entry>
- <key>prSafe</key>
- <value>false</value>
- </entry>
- </parameterValueMap>
- </parameters>
- </interface>
</interfaces>
</boundaryDefinition>]]></spirit:value>
</spirit:parameter>
@@ -740,27 +482,18 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
- <altera:interface_mapping altera:name="clk" altera:internal="qsys_arts_unb2b_sc3_clk_0.clk" altera:type="clock" altera:dir="start">
+ <altera:interface_mapping altera:name="clk" altera:internal="clk_0.clk" altera:type="clock" altera:dir="start">
<altera:port_mapping altera:name="clk_out" altera:internal="clk_out"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk1" altera:internal="qsys_arts_unb2b_sc3_clk_0.clk1" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="clk_clk" altera:internal="clk_clk"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk_in" altera:internal="qsys_arts_unb2b_sc3_clk_0.clk_in" altera:type="clock" altera:dir="end">
+ <altera:interface_mapping altera:name="clk_in" altera:internal="clk_0.clk_in" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="in_clk" altera:internal="in_clk"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk_in_reset" altera:internal="qsys_arts_unb2b_sc3_clk_0.clk_in_reset" altera:type="reset" altera:dir="end">
+ <altera:interface_mapping altera:name="clk_in_reset" altera:internal="clk_0.clk_in_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="reset_n" altera:internal="reset_n"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk_in_reset1" altera:internal="qsys_arts_unb2b_sc3_clk_0.clk_in_reset1" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="clk_in_reset_reset_n" altera:internal="clk_in_reset_reset_n"></altera:port_mapping>
- </altera:interface_mapping>
- <altera:interface_mapping altera:name="clk_reset" altera:internal="qsys_arts_unb2b_sc3_clk_0.clk_reset" altera:type="reset" altera:dir="start">
+ <altera:interface_mapping altera:name="clk_reset" altera:internal="clk_0.clk_reset" altera:type="reset" altera:dir="start">
<altera:port_mapping altera:name="reset_n_out" altera:internal="reset_n_out"></altera:port_mapping>
</altera:interface_mapping>
- <altera:interface_mapping altera:name="clk_reset1" altera:internal="qsys_arts_unb2b_sc3_clk_0.clk_reset1" altera:type="conduit" altera:dir="end">
- <altera:port_mapping altera:name="clk_reset_reset_n" altera:internal="clk_reset_reset_n"></altera:port_mapping>
- </altera:interface_mapping>
</altera:altera_interface_boundary>
<altera:altera_has_warnings>false</altera:altera_has_warnings>
<altera:altera_has_errors>false</altera:altera_has_errors>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.bsf
deleted file mode 100644
index 4e12093ad42ea323918a7e38aadb273d31aef59a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.bsf
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 256 144)
- (text "qsys_arts_unb2b_sc3_clk_1" (rect 44 -1 160 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 128 20 140)(font "Arial" ))
- (port
- (pt 0 72)
- (input)
- (text "in_clk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
- (text "in_clk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 80 72)(line_width 1))
- )
- (port
- (pt 0 112)
- (input)
- (text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8)))
- (text "reset_n" (rect 4 101 46 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 80 112)(line_width 1))
- )
- (port
- (pt 256 72)
- (output)
- (text "clk_out" (rect 0 0 28 12)(font "Arial" (font_size 8)))
- (text "clk_out" (rect 219 61 261 72)(font "Arial" (font_size 8)))
- (line (pt 256 72)(pt 176 72)(line_width 1))
- )
- (port
- (pt 256 112)
- (output)
- (text "reset_n_out" (rect 0 0 48 12)(font "Arial" (font_size 8)))
- (text "reset_n_out" (rect 194 101 260 112)(font "Arial" (font_size 8)))
- (line (pt 256 112)(pt 176 112)(line_width 1))
- )
- (drawing
- (text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 161 67 340 144)(font "Arial" (color 0 0 0)))
- (text "clk_in" (rect 47 43 130 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 85 67 188 144)(font "Arial" (color 0 0 0)))
- (text "clk_in_reset" (rect 9 83 90 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset_n" (rect 85 107 212 224)(font "Arial" (color 0 0 0)))
- (text "clk_reset" (rect 177 83 408 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset_n" (rect 140 107 322 224)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_clk_1 " (rect 129 128 420 266)(font "Arial" ))
- (line (pt 80 32)(pt 176 32)(line_width 1))
- (line (pt 176 32)(pt 176 128)(line_width 1))
- (line (pt 80 128)(pt 176 128)(line_width 1))
- (line (pt 80 32)(pt 80 128)(line_width 1))
- (line (pt 175 52)(pt 175 76)(line_width 1))
- (line (pt 174 52)(pt 174 76)(line_width 1))
- (line (pt 81 52)(pt 81 76)(line_width 1))
- (line (pt 82 52)(pt 82 76)(line_width 1))
- (line (pt 81 92)(pt 81 116)(line_width 1))
- (line (pt 82 92)(pt 82 116)(line_width 1))
- (line (pt 175 92)(pt 175 116)(line_width 1))
- (line (pt 174 92)(pt 174 116)(line_width 1))
- (line (pt 0 0)(pt 256 0)(line_width 1))
- (line (pt 256 0)(pt 256 144)(line_width 1))
- (line (pt 0 144)(pt 256 144)(line_width 1))
- (line (pt 0 0)(pt 0 144)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.cmp
deleted file mode 100644
index 5deb745cd416176695df566b4f89a2aab5dce47d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.cmp
+++ /dev/null
@@ -1,9 +0,0 @@
- component qsys_arts_unb2b_sc3_clk_1 is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component qsys_arts_unb2b_sc3_clk_1;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.html
deleted file mode 100644
index 4001bea3135043f730ececbbb115fefa84e91943..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.html
+++ /dev/null
@@ -1,153 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_clk_1</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_clk_1</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:37:26</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr>
- <td class="lefthandwire">  clk_0 </td>
- <td class="main" rowspan="2">qsys_arts_unb2b_sc3_clk_1</td>
- </tr>
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/></span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- </table>
- <a name="module_clk_0"> </a>
- <div>
- <hr/>
- <h2>clk_0</h2>clock_source v17.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">clockFrequency</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">clockFrequencyKnown</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">inputClockFrequency</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">resetSynchronousEdges</td>
- <td class="parametervalue">NONE</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.01 seconds</td>
- <td class="r">rendering took 0.02 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.qgsynthc
deleted file mode 100644
index d1bb00cd5da80e89183b73a80248026788010ade..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.qgsynthc
+++ /dev/null
@@ -1,57 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_clk_1</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_clk_1</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_clk_1</name>
- <uniqueName>qsys_arts_unb2b_sc3_clk_1</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">clk_0</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>clockFrequency</name>
- <value>125000000</value>
- </parameter>
- <parameter>
- <name>clockFrequencyKnown</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>inputClockFrequency</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>resetSynchronousEdges</name>
- <value>NONE</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>clock_source</className>
- <version>17.0</version>
- <name>clk_0</name>
- <uniqueName>qsys_arts_unb2b_sc3_clk_1_clock_source_170_yubjnyi</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_clk_1.clk_0</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.qip
deleted file mode 100644
index dd7c455060a766f76ae8e39fa05b4b8f26b01b26..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.qip
+++ /dev/null
@@ -1,25 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_clk_1" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_clk_1.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_clk_1 HAS_SOPCINFO 1 GENERATION_ID 1527683845"
-set_global_assignment -library "qsys_arts_unb2b_sc3_clk_1" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_clk_1.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_clk_1" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_clk_1.ip"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19jbGtfMQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4Mzg0NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfSU5fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfSU5fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_clk_1" -library "qsys_arts_unb2b_sc3_clk_1" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfSU5fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "qsys_arts_unb2b_sc3_clk_1" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_clk_1.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.sopcinfo
deleted file mode 100644
index 4c3be49da4b0faefb7a3b349190b417c135e940c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.sopcinfo
+++ /dev/null
@@ -1,442 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_clk_1"
- kind="qsys_arts_unb2b_sc3_clk_1"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:37:26 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527683845</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_CLK_IN_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk_in</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_IN_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk_in</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_IN_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk_in</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module name="clk_0" kind="clock_source" version="17.0" path="clk_0">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="clockFrequency">
- <type>long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockFrequencyKnown">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="inputClockFrequency">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk_in</sysinfo_arg>
- </parameter>
- <parameter name="resetSynchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>NONE</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="clk_in" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>qsys.ui.export_name</name>
- <value>clk</value>
- </assignment>
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>in_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="clk_in_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>qsys.ui.export_name</name>
- <value>reset</value>
- </assignment>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>NONE</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>reset_n</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset_n</role>
- </port>
- </interface>
- <interface name="clk" kind="clock_source" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedDirectClock">
- <type>java.lang.String</type>
- <value>clk_in</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>true</isStart>
- <port>
- <name>clk_out</name>
- <direction>Output</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="clk_reset" kind="reset_source" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedDirectReset">
- <type>java.lang.String</type>
- <value>clk_in_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedResetSinks">
- <type>[Ljava.lang.String;</type>
- <value>clk_in_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>NONE</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>true</isStart>
- <port>
- <name>reset_n_out</name>
- <direction>Output</direction>
- <width>1</width>
- <role>reset_n</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_source</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>Clock Source</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_source</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Output</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_source</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Output</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.xml
deleted file mode 100644
index 2788bcb0771b7c651de23c71db8fb6eaa6746025..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1.xml
+++ /dev/null
@@ -1,112 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:37:28"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_IN_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_IN_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_IN_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="clk" kind="clock" start="1">
- <property name="associatedDirectClock" value="clk_in" />
- <property name="clockRate" value="125000000" />
- <property name="clockRateKnown" value="true" />
- <property name="externallyDriven" value="true" />
- <property name="ptfSchematicName" value="" />
- <port name="clk_out" direction="output" role="clk" width="1" />
- </interface>
- <interface name="clk_in" kind="clock" start="0">
- <property name="clockRate" value="125000000" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="in_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="clk_in_reset" kind="reset" start="0">
- <property name="associatedClock" value="" />
- <property name="synchronousEdges" value="NONE" />
- <port name="reset_n" direction="input" role="reset_n" width="1" />
- </interface>
- <interface name="clk_reset" kind="reset" start="1">
- <property name="associatedClock" value="" />
- <property name="associatedDirectReset" value="clk_in_reset" />
- <property name="associatedResetSinks" value="clk_in_reset" />
- <property name="synchronousEdges" value="NONE" />
- <port name="reset_n_out" direction="output" role="reset_n" width="1" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_clk_1"
- version="1.0"
- name="qsys_arts_unb2b_sc3_clk_1">
- <parameter name="AUTO_CLK_IN_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527683845" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_CLK_IN_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_CLK_IN_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/synth/qsys_arts_unb2b_sc3_clk_1.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/synth/qsys_arts_unb2b_sc3_clk_1.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1.ip" />
- </sourceFiles>
- <childSourceFiles/>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_clk_1">"Generating: qsys_arts_unb2b_sc3_clk_1"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_bb.v
deleted file mode 100644
index 1985e393bcaaf3fd1310952be4d613c205d54bab..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_bb.v
+++ /dev/null
@@ -1,12 +0,0 @@
-
-module qsys_arts_unb2b_sc3_clk_1 (
- clk_out,
- in_clk,
- reset_n,
- reset_n_out);
-
- output clk_out;
- input in_clk;
- input reset_n;
- output reset_n_out;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_generation.rpt
deleted file mode 100644
index fe04b472e75bdb9704bba72ac741c5f7a8997a3c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_generation.rpt
+++ /dev/null
@@ -1,22 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_clk_1: "Transforming system: qsys_arts_unb2b_sc3_clk_1"
-Info: qsys_arts_unb2b_sc3_clk_1: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_clk_1: Running transform generation_view_transform took 0.001s
-Info: qsys_arts_unb2b_sc3_clk_1: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_clk_1: Running transform interconnect_transform_chooser took 2.118s
-Info: qsys_arts_unb2b_sc3_clk_1: "Naming system components in system: qsys_arts_unb2b_sc3_clk_1"
-Info: qsys_arts_unb2b_sc3_clk_1: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_clk_1: "Generating: qsys_arts_unb2b_sc3_clk_1"
-Info: qsys_arts_unb2b_sc3_clk_1: Done "qsys_arts_unb2b_sc3_clk_1" with 1 modules, 1 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_clk_1. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_inst.v
deleted file mode 100644
index 17e77fb3dad522cc3b165841d67d6ee84ac0451e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_inst.v
+++ /dev/null
@@ -1,7 +0,0 @@
- qsys_arts_unb2b_sc3_clk_1 u0 (
- .clk_out (_connected_to_clk_out_), // clk.clk
- .in_clk (_connected_to_in_clk_), // clk_in.clk
- .reset_n (_connected_to_reset_n_), // clk_in_reset.reset_n
- .reset_n_out (_connected_to_reset_n_out_) // clk_reset.reset_n
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_inst.vhd
deleted file mode 100644
index afa97a0b98de0faae4ba5bf830747ff550716579..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/qsys_arts_unb2b_sc3_clk_1_inst.vhd
+++ /dev/null
@@ -1,17 +0,0 @@
- component qsys_arts_unb2b_sc3_clk_1 is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component qsys_arts_unb2b_sc3_clk_1;
-
- u0 : component qsys_arts_unb2b_sc3_clk_1
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/synth/qsys_arts_unb2b_sc3_clk_1.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/synth/qsys_arts_unb2b_sc3_clk_1.vhd
deleted file mode 100644
index 3501e8590341fec4ca4859c1fe8fb9972b208cad..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1/synth/qsys_arts_unb2b_sc3_clk_1.vhd
+++ /dev/null
@@ -1,25 +0,0 @@
--- qsys_arts_unb2b_sc3_clk_1.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_clk_1 is
- port (
- clk_out : out std_logic; -- clk.clk
- in_clk : in std_logic := '0'; -- clk_in.clk
- reset_n : in std_logic := '0'; -- clk_in_reset.reset_n
- reset_n_out : out std_logic -- clk_reset.reset_n
- );
-end entity qsys_arts_unb2b_sc3_clk_1;
-
-architecture rtl of qsys_arts_unb2b_sc3_clk_1 is
-begin
-
- clk_out <= in_clk;
-
- reset_n_out <= reset_n;
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_clk_1
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0.ip
index 3f9b01e70b25e310ebab8b2f92fa07a85ff2d7ab..3e820bbf7bbe0790f5368461aed5d591b92e389a 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0.ip
@@ -1018,7 +1018,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>17</spirit:right>
+ <spirit:right>21</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -2073,7 +2073,7 @@
<spirit:parameter>
<spirit:name>breakAbsoluteAddr</spirit:name>
<spirit:displayName>Break vector</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="breakAbsoluteAddr">6176</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="breakAbsoluteAddr">14368</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>mmu_TLBMissExcAbsAddr</spirit:name>
@@ -2153,7 +2153,7 @@
<spirit:parameter>
<spirit:name>dataAddrWidth</spirit:name>
<spirit:displayName>dataAddrWidth</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="dataAddrWidth">18</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="dataAddrWidth">22</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0AddrWidth</spirit:name>
@@ -2208,7 +2208,7 @@
<spirit:parameter>
<spirit:name>instSlaveMapParam</spirit:name>
<spirit:displayName>instSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='null.null' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>faSlaveMapParam</spirit:name>
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' type='null.null' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x80' end='0x100' type='null.null' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x100' end='0x180' type='null.null' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x180' end='0x200' type='null.null' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x200' end='0x280' type='null.null' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x280' end='0x300' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x300' end='0x380' type='null.null' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x380' end='0x400' type='null.null' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x400' end='0x480' type='null.null' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x480' end='0x500' type='null.null' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x500' end='0x580' type='null.null' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x600' type='null.null' datawidth='32' /><slave name='reg_remu.mem' start='0x600' end='0x680' type='null.null' datawidth='32' /><slave name='pio_pps.mem' start='0x680' end='0x700' type='null.null' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x780' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' type='null.null' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x1080' type='null.null' datawidth='32' /><slave name='timer_0.s1' start='0x1080' end='0x10A0' type='null.null' datawidth='16' /><slave name='pio_wdi.s1' start='0x10A0' end='0x10B0' type='null.null' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10B0' end='0x10B8' type='null.null' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' type='null.null' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3080' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x80' end='0xC0' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' type='null.null' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' type='null.null' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' type='null.null' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x400' end='0x500' type='null.null' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x500' end='0x540' type='null.null' datawidth='32' /><slave name='timer_0.s1' start='0x540' end='0x560' type='null.null' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x560' end='0x580' type='null.null' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x5A0' type='null.null' datawidth='32' /><slave name='reg_remu.mem' start='0x5A0' end='0x5C0' type='null.null' datawidth='32' /><slave name='pio_wdi.s1' start='0x5C0' end='0x5D0' type='null.null' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x5D0' end='0x5D8' type='null.null' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x5D8' end='0x5E0' type='null.null' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x5E0' end='0x5E8' type='null.null' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x5E8' end='0x5F0' type='null.null' datawidth='32' /><slave name='pio_pps.mem' start='0x5F0' end='0x5F8' type='null.null' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x5F8' end='0x600' type='null.null' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' type='null.null' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' type='null.null' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' type='null.null' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x40000' end='0x60000' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' type='null.null' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -2344,7 +2344,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.BREAK_ADDR</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BREAK_ADDR">0x00001820</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BREAK_ADDR">0x00003820</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</spirit:name>
@@ -2368,7 +2368,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.DATA_ADDR_WIDTH</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_ADDR_WIDTH">18</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_ADDR_WIDTH">22</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.DCACHE_LINE_SIZE</spirit:name>
@@ -2663,7 +2663,7 @@
<name>d_address</name>
<role>address</role>
<direction>Output</direction>
- <width>18</width>
+ <width>22</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -3484,11 +3484,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x100' end='0x180' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x180' end='0x200' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x200' end='0x280' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x280' end='0x300' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x300' end='0x380' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x380' end='0x400' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x400' end='0x480' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x480' end='0x500' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x500' end='0x580' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x600' datawidth='32' /><slave name='reg_remu.mem' start='0x600' end='0x680' datawidth='32' /><slave name='pio_pps.mem' start='0x680' end='0x700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x780' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x1080' datawidth='32' /><slave name='timer_0.s1' start='0x1080' end='0x10A0' datawidth='16' /><slave name='pio_wdi.s1' start='0x10A0' end='0x10B0' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10B0' end='0x10B8' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3080' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x400' end='0x500' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x500' end='0x540' datawidth='32' /><slave name='timer_0.s1' start='0x540' end='0x560' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x560' end='0x580' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x5A0' datawidth='32' /><slave name='reg_remu.mem' start='0x5A0' end='0x5C0' datawidth='32' /><slave name='pio_wdi.s1' start='0x5C0' end='0x5D0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x5D0' end='0x5D8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x5D8' end='0x5E0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x5E0' end='0x5E8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x5E8' end='0x5F0' datawidth='32' /><slave name='pio_pps.mem' start='0x5F0' end='0x5F8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x5F8' end='0x600' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x200000' end='0x400000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>18</value>
+ <value>22</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
@@ -3522,7 +3522,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey.v
deleted file mode 100644
index d152fec577632f5c4e547a14f62e04c1b59de7dd..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey.v
+++ /dev/null
@@ -1,67 +0,0 @@
-// qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey.v
-
-// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
-// will probably be lost.
-//
-// Generated using ACDS version 17.0.2 297
-
-`timescale 1 ps / 1 ps
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey (
- input wire clk, // clk.clk
- output wire dummy_ci_port, // custom_instruction_master.readra
- output wire [17:0] d_address, // data_master.address
- output wire [3:0] d_byteenable, // .byteenable
- output wire d_read, // .read
- input wire [31:0] d_readdata, // .readdata
- input wire d_waitrequest, // .waitrequest
- output wire d_write, // .write
- output wire [31:0] d_writedata, // .writedata
- output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
- input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
- input wire [3:0] debug_mem_slave_byteenable, // .byteenable
- input wire debug_mem_slave_debugaccess, // .debugaccess
- input wire debug_mem_slave_read, // .read
- output wire [31:0] debug_mem_slave_readdata, // .readdata
- output wire debug_mem_slave_waitrequest, // .waitrequest
- input wire debug_mem_slave_write, // .write
- input wire [31:0] debug_mem_slave_writedata, // .writedata
- output wire debug_reset_request, // debug_reset_request.reset
- output wire [17:0] i_address, // instruction_master.address
- output wire i_read, // .read
- input wire [31:0] i_readdata, // .readdata
- input wire i_waitrequest, // .waitrequest
- input wire [31:0] irq, // irq.irq
- input wire reset_n, // reset.reset_n
- input wire reset_req // .reset_req
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq cpu (
- .clk (clk), // clk.clk
- .reset_n (reset_n), // reset.reset_n
- .reset_req (reset_req), // .reset_req
- .d_address (d_address), // data_master.address
- .d_byteenable (d_byteenable), // .byteenable
- .d_read (d_read), // .read
- .d_readdata (d_readdata), // .readdata
- .d_waitrequest (d_waitrequest), // .waitrequest
- .d_write (d_write), // .write
- .d_writedata (d_writedata), // .writedata
- .debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
- .i_address (i_address), // instruction_master.address
- .i_read (i_read), // .read
- .i_readdata (i_readdata), // .readdata
- .i_waitrequest (i_waitrequest), // .waitrequest
- .irq (irq), // irq.irq
- .debug_reset_request (debug_reset_request), // debug_reset_request.reset
- .debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
- .debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
- .debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
- .debug_mem_slave_read (debug_mem_slave_read), // .read
- .debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
- .debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
- .debug_mem_slave_write (debug_mem_slave_write), // .write
- .debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
- .dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
- );
-
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.sdc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.sdc
deleted file mode 100644
index c3fa5e0f1f9ad640e32f4277f55dc8a1eb1f806d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.sdc
+++ /dev/null
@@ -1,53 +0,0 @@
-# Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-# use of Altera Corporation's design tools, logic functions and other
-# software and tools, and its AMPP partner logic functions, and any
-# output files any of the foregoing (including device programming or
-# simulation files), and any associated documentation or information are
-# expressly subject to the terms and conditions of the Altera Program
-# License Subscription Agreement or other applicable license agreement,
-# including, without limitation, that your use is for the sole purpose
-# of programming logic devices manufactured by Altera and sold by Altera
-# or its authorized distributors. Please refer to the applicable
-# agreement for further details.
-
-#**************************************************************
-# Timequest JTAG clock definition
-# Uncommenting the following lines will define the JTAG
-# clock in TimeQuest Timing Analyzer
-#**************************************************************
-
-#create_clock -period 10MHz {altera_reserved_tck}
-#set_clock_groups -asynchronous -group {altera_reserved_tck}
-
-#**************************************************************
-# Set TCL Path Variables
-#**************************************************************
-
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq:*
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci:the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_break qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_break:the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_break
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ocimem qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_ocimem:the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_ocimem
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_debug qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_debug:the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_debug
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_wrapper qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper:the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_tck qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck:the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sysclk qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk:the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_path [format "%s|%s" $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci]
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_break_path [format "%s|%s" $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_path $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_break]
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ocimem_path [format "%s|%s" $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_path $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ocimem]
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_debug_path [format "%s|%s" $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_path $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_debug]
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_tck_path [format "%s|%s|%s" $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_path $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_wrapper $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_tck]
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sysclk_path [format "%s|%s|%s" $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_path $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_wrapper $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sysclk]
-set qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sr [format "%s|*sr" $qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_tck_path]
-
-#**************************************************************
-# Set False Paths
-#**************************************************************
-
-set_false_path -from [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_break_path|break_readreg*] -to [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sr*]
-set_false_path -from [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_debug_path|*resetlatch] -to [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sr[33]]
-set_false_path -from [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_debug_path|monitor_ready] -to [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sr[0]]
-set_false_path -from [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_debug_path|monitor_error] -to [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sr[34]]
-set_false_path -from [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ocimem_path|*MonDReg*] -to [get_keepers *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sr*]
-set_false_path -from *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sr* -to *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sysclk_path|*jdo*
-set_false_path -from *sld_jtag_hub:*|irf_reg* -to *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_jtag_sysclk_path|ir*
-set_false_path -from *sld_jtag_hub:*|sld_shadow_jsm:shadow_jsm|state[1] -to *$qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_oci_debug_path|monitor_go
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.v
deleted file mode 100644
index 47980d042fa1af58592d0d8a8f53daa38f3e7b91..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.v
+++ /dev/null
@@ -1,5658 +0,0 @@
-//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_a_module (
- // inputs:
- clock,
- data,
- rdaddress,
- wraddress,
- wren,
-
- // outputs:
- q
- )
-;
-
- parameter lpm_file = "UNUSED";
-
-
- output [ 31: 0] q;
- input clock;
- input [ 31: 0] data;
- input [ 4: 0] rdaddress;
- input [ 4: 0] wraddress;
- input wren;
-
-
-wire [ 31: 0] q;
-wire [ 31: 0] ram_data;
-wire [ 31: 0] ram_q;
- assign q = ram_q;
- assign ram_data = data;
- altsyncram the_altsyncram
- (
- .address_a (wraddress),
- .address_b (rdaddress),
- .clock0 (clock),
- .data_a (ram_data),
- .q_b (ram_q),
- .wren_a (wren)
- );
-
- defparam the_altsyncram.address_reg_b = "CLOCK0",
- the_altsyncram.init_file = lpm_file,
- the_altsyncram.maximum_depth = 0,
- the_altsyncram.numwords_a = 32,
- the_altsyncram.numwords_b = 32,
- the_altsyncram.operation_mode = "DUAL_PORT",
- the_altsyncram.outdata_reg_b = "UNREGISTERED",
- the_altsyncram.ram_block_type = "AUTO",
- the_altsyncram.rdcontrol_reg_b = "CLOCK0",
- the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
- the_altsyncram.width_a = 32,
- the_altsyncram.width_b = 32,
- the_altsyncram.widthad_a = 5,
- the_altsyncram.widthad_b = 5;
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_b_module (
- // inputs:
- clock,
- data,
- rdaddress,
- wraddress,
- wren,
-
- // outputs:
- q
- )
-;
-
- parameter lpm_file = "UNUSED";
-
-
- output [ 31: 0] q;
- input clock;
- input [ 31: 0] data;
- input [ 4: 0] rdaddress;
- input [ 4: 0] wraddress;
- input wren;
-
-
-wire [ 31: 0] q;
-wire [ 31: 0] ram_data;
-wire [ 31: 0] ram_q;
- assign q = ram_q;
- assign ram_data = data;
- altsyncram the_altsyncram
- (
- .address_a (wraddress),
- .address_b (rdaddress),
- .clock0 (clock),
- .data_a (ram_data),
- .q_b (ram_q),
- .wren_a (wren)
- );
-
- defparam the_altsyncram.address_reg_b = "CLOCK0",
- the_altsyncram.init_file = lpm_file,
- the_altsyncram.maximum_depth = 0,
- the_altsyncram.numwords_a = 32,
- the_altsyncram.numwords_b = 32,
- the_altsyncram.operation_mode = "DUAL_PORT",
- the_altsyncram.outdata_reg_b = "UNREGISTERED",
- the_altsyncram.ram_block_type = "AUTO",
- the_altsyncram.rdcontrol_reg_b = "CLOCK0",
- the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
- the_altsyncram.width_a = 32,
- the_altsyncram.width_b = 32,
- the_altsyncram.widthad_a = 5,
- the_altsyncram.widthad_b = 5;
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_debug (
- // inputs:
- clk,
- dbrk_break,
- debugreq,
- hbreak_enabled,
- jdo,
- jrst_n,
- ocireg_ers,
- ocireg_mrs,
- reset,
- st_ready_test_idle,
- take_action_ocimem_a,
- take_action_ocireg,
- xbrk_break,
-
- // outputs:
- debugack,
- monitor_error,
- monitor_go,
- monitor_ready,
- oci_hbreak_req,
- resetlatch,
- resetrequest
- )
-;
-
- output debugack;
- output monitor_error;
- output monitor_go;
- output monitor_ready;
- output oci_hbreak_req;
- output resetlatch;
- output resetrequest;
- input clk;
- input dbrk_break;
- input debugreq;
- input hbreak_enabled;
- input [ 37: 0] jdo;
- input jrst_n;
- input ocireg_ers;
- input ocireg_mrs;
- input reset;
- input st_ready_test_idle;
- input take_action_ocimem_a;
- input take_action_ocireg;
- input xbrk_break;
-
-
-reg break_on_reset /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-wire debugack;
-reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
-reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
-reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
-wire oci_hbreak_req;
-wire reset_sync;
-reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-wire unxcomplemented_resetxx0;
- assign unxcomplemented_resetxx0 = jrst_n;
- altera_std_synchronizer the_altera_std_synchronizer
- (
- .clk (clk),
- .din (reset),
- .dout (reset_sync),
- .reset_n (unxcomplemented_resetxx0)
- );
-
- defparam the_altera_std_synchronizer.depth = 2;
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- begin
- resetrequest <= 1'b0;
- break_on_reset <= 1'b0;
- jtag_break <= 1'b0;
- end
- else if (take_action_ocimem_a)
- begin
- resetrequest <= jdo[22];
- jtag_break <= jdo[21] ? 1
- : jdo[20] ? 0
- : jtag_break;
-
- break_on_reset <= jdo[19] ? 1
- : jdo[18] ? 0
- : break_on_reset;
-
- resetlatch <= jdo[24] ? 0 : resetlatch;
- end
- else if (reset_sync)
- begin
- jtag_break <= break_on_reset;
- resetlatch <= 1;
- end
- else if (debugreq & ~debugack & break_on_reset)
- jtag_break <= 1'b1;
- end
-
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- begin
- monitor_ready <= 1'b0;
- monitor_error <= 1'b0;
- monitor_go <= 1'b0;
- end
- else
- begin
- if (take_action_ocimem_a && jdo[25])
- monitor_ready <= 1'b0;
- else if (take_action_ocireg && ocireg_mrs)
- monitor_ready <= 1'b1;
- if (take_action_ocimem_a && jdo[25])
- monitor_error <= 1'b0;
- else if (take_action_ocireg && ocireg_ers)
- monitor_error <= 1'b1;
- if (take_action_ocimem_a && jdo[23])
- monitor_go <= 1'b1;
- else if (st_ready_test_idle)
- monitor_go <= 1'b0;
- end
- end
-
-
- assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
- assign debugack = ~hbreak_enabled;
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_break (
- // inputs:
- clk,
- dbrk_break,
- dbrk_goto0,
- dbrk_goto1,
- jdo,
- jrst_n,
- take_action_break_a,
- take_action_break_b,
- take_action_break_c,
- take_no_action_break_a,
- take_no_action_break_b,
- take_no_action_break_c,
- xbrk_goto0,
- xbrk_goto1,
-
- // outputs:
- break_readreg,
- dbrk_hit0_latch,
- dbrk_hit1_latch,
- dbrk_hit2_latch,
- dbrk_hit3_latch,
- trigbrktype,
- trigger_state_0,
- trigger_state_1,
- xbrk_ctrl0,
- xbrk_ctrl1,
- xbrk_ctrl2,
- xbrk_ctrl3
- )
-;
-
- output [ 31: 0] break_readreg;
- output dbrk_hit0_latch;
- output dbrk_hit1_latch;
- output dbrk_hit2_latch;
- output dbrk_hit3_latch;
- output trigbrktype;
- output trigger_state_0;
- output trigger_state_1;
- output [ 7: 0] xbrk_ctrl0;
- output [ 7: 0] xbrk_ctrl1;
- output [ 7: 0] xbrk_ctrl2;
- output [ 7: 0] xbrk_ctrl3;
- input clk;
- input dbrk_break;
- input dbrk_goto0;
- input dbrk_goto1;
- input [ 37: 0] jdo;
- input jrst_n;
- input take_action_break_a;
- input take_action_break_b;
- input take_action_break_c;
- input take_no_action_break_a;
- input take_no_action_break_b;
- input take_no_action_break_c;
- input xbrk_goto0;
- input xbrk_goto1;
-
-
-wire [ 3: 0] break_a_wpr;
-wire [ 1: 0] break_a_wpr_high_bits;
-wire [ 1: 0] break_a_wpr_low_bits;
-wire [ 1: 0] break_b_rr;
-wire [ 1: 0] break_c_rr;
-reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-wire dbrk0_high_value;
-wire dbrk0_low_value;
-wire dbrk1_high_value;
-wire dbrk1_low_value;
-wire dbrk2_high_value;
-wire dbrk2_low_value;
-wire dbrk3_high_value;
-wire dbrk3_low_value;
-wire dbrk_hit0_latch;
-wire dbrk_hit1_latch;
-wire dbrk_hit2_latch;
-wire dbrk_hit3_latch;
-wire take_action_any_break;
-reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-reg trigger_state;
-wire trigger_state_0;
-wire trigger_state_1;
-wire [ 31: 0] xbrk0_value;
-wire [ 31: 0] xbrk1_value;
-wire [ 31: 0] xbrk2_value;
-wire [ 31: 0] xbrk3_value;
-reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
- assign break_a_wpr = jdo[35 : 32];
- assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
- assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
- assign break_b_rr = jdo[33 : 32];
- assign break_c_rr = jdo[33 : 32];
- assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- begin
- xbrk_ctrl0 <= 0;
- xbrk_ctrl1 <= 0;
- xbrk_ctrl2 <= 0;
- xbrk_ctrl3 <= 0;
- trigbrktype <= 0;
- end
- else
- begin
- if (take_action_any_break)
- trigbrktype <= 0;
- else if (dbrk_break)
- trigbrktype <= 1;
- if (take_action_break_b)
- begin
- if ((break_b_rr == 2'b00) && (0 >= 1))
- begin
- xbrk_ctrl0[0] <= jdo[27];
- xbrk_ctrl0[1] <= jdo[28];
- xbrk_ctrl0[2] <= jdo[29];
- xbrk_ctrl0[3] <= jdo[30];
- xbrk_ctrl0[4] <= jdo[21];
- xbrk_ctrl0[5] <= jdo[20];
- xbrk_ctrl0[6] <= jdo[19];
- xbrk_ctrl0[7] <= jdo[18];
- end
- if ((break_b_rr == 2'b01) && (0 >= 2))
- begin
- xbrk_ctrl1[0] <= jdo[27];
- xbrk_ctrl1[1] <= jdo[28];
- xbrk_ctrl1[2] <= jdo[29];
- xbrk_ctrl1[3] <= jdo[30];
- xbrk_ctrl1[4] <= jdo[21];
- xbrk_ctrl1[5] <= jdo[20];
- xbrk_ctrl1[6] <= jdo[19];
- xbrk_ctrl1[7] <= jdo[18];
- end
- if ((break_b_rr == 2'b10) && (0 >= 3))
- begin
- xbrk_ctrl2[0] <= jdo[27];
- xbrk_ctrl2[1] <= jdo[28];
- xbrk_ctrl2[2] <= jdo[29];
- xbrk_ctrl2[3] <= jdo[30];
- xbrk_ctrl2[4] <= jdo[21];
- xbrk_ctrl2[5] <= jdo[20];
- xbrk_ctrl2[6] <= jdo[19];
- xbrk_ctrl2[7] <= jdo[18];
- end
- if ((break_b_rr == 2'b11) && (0 >= 4))
- begin
- xbrk_ctrl3[0] <= jdo[27];
- xbrk_ctrl3[1] <= jdo[28];
- xbrk_ctrl3[2] <= jdo[29];
- xbrk_ctrl3[3] <= jdo[30];
- xbrk_ctrl3[4] <= jdo[21];
- xbrk_ctrl3[5] <= jdo[20];
- xbrk_ctrl3[6] <= jdo[19];
- xbrk_ctrl3[7] <= jdo[18];
- end
- end
- end
- end
-
-
- assign dbrk_hit0_latch = 1'b0;
- assign dbrk0_low_value = 0;
- assign dbrk0_high_value = 0;
- assign dbrk_hit1_latch = 1'b0;
- assign dbrk1_low_value = 0;
- assign dbrk1_high_value = 0;
- assign dbrk_hit2_latch = 1'b0;
- assign dbrk2_low_value = 0;
- assign dbrk2_high_value = 0;
- assign dbrk_hit3_latch = 1'b0;
- assign dbrk3_low_value = 0;
- assign dbrk3_high_value = 0;
- assign xbrk0_value = 32'b0;
- assign xbrk1_value = 32'b0;
- assign xbrk2_value = 32'b0;
- assign xbrk3_value = 32'b0;
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- break_readreg <= 32'b0;
- else if (take_action_any_break)
- break_readreg <= jdo[31 : 0];
- else if (take_no_action_break_a)
- case (break_a_wpr_high_bits)
-
- 2'd0: begin
- case (break_a_wpr_low_bits) // synthesis full_case
-
- 2'd0: begin
- break_readreg <= xbrk0_value;
- end // 2'd0
-
- 2'd1: begin
- break_readreg <= xbrk1_value;
- end // 2'd1
-
- 2'd2: begin
- break_readreg <= xbrk2_value;
- end // 2'd2
-
- 2'd3: begin
- break_readreg <= xbrk3_value;
- end // 2'd3
-
- endcase // break_a_wpr_low_bits
- end // 2'd0
-
- 2'd1: begin
- break_readreg <= 32'b0;
- end // 2'd1
-
- 2'd2: begin
- case (break_a_wpr_low_bits) // synthesis full_case
-
- 2'd0: begin
- break_readreg <= dbrk0_low_value;
- end // 2'd0
-
- 2'd1: begin
- break_readreg <= dbrk1_low_value;
- end // 2'd1
-
- 2'd2: begin
- break_readreg <= dbrk2_low_value;
- end // 2'd2
-
- 2'd3: begin
- break_readreg <= dbrk3_low_value;
- end // 2'd3
-
- endcase // break_a_wpr_low_bits
- end // 2'd2
-
- 2'd3: begin
- case (break_a_wpr_low_bits) // synthesis full_case
-
- 2'd0: begin
- break_readreg <= dbrk0_high_value;
- end // 2'd0
-
- 2'd1: begin
- break_readreg <= dbrk1_high_value;
- end // 2'd1
-
- 2'd2: begin
- break_readreg <= dbrk2_high_value;
- end // 2'd2
-
- 2'd3: begin
- break_readreg <= dbrk3_high_value;
- end // 2'd3
-
- endcase // break_a_wpr_low_bits
- end // 2'd3
-
- endcase // break_a_wpr_high_bits
- else if (take_no_action_break_b)
- break_readreg <= jdo[31 : 0];
- else if (take_no_action_break_c)
- break_readreg <= jdo[31 : 0];
- end
-
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- trigger_state <= 0;
- else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
- trigger_state <= 0;
- else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
- trigger_state <= -1;
- end
-
-
- assign trigger_state_0 = ~trigger_state;
- assign trigger_state_1 = trigger_state;
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_xbrk (
- // inputs:
- D_valid,
- E_valid,
- F_pc,
- clk,
- reset_n,
- trigger_state_0,
- trigger_state_1,
- xbrk_ctrl0,
- xbrk_ctrl1,
- xbrk_ctrl2,
- xbrk_ctrl3,
-
- // outputs:
- xbrk_break,
- xbrk_goto0,
- xbrk_goto1,
- xbrk_traceoff,
- xbrk_traceon,
- xbrk_trigout
- )
-;
-
- output xbrk_break;
- output xbrk_goto0;
- output xbrk_goto1;
- output xbrk_traceoff;
- output xbrk_traceon;
- output xbrk_trigout;
- input D_valid;
- input E_valid;
- input [ 15: 0] F_pc;
- input clk;
- input reset_n;
- input trigger_state_0;
- input trigger_state_1;
- input [ 7: 0] xbrk_ctrl0;
- input [ 7: 0] xbrk_ctrl1;
- input [ 7: 0] xbrk_ctrl2;
- input [ 7: 0] xbrk_ctrl3;
-
-
-wire D_cpu_addr_en;
-wire E_cpu_addr_en;
-reg E_xbrk_goto0;
-reg E_xbrk_goto1;
-reg E_xbrk_traceoff;
-reg E_xbrk_traceon;
-reg E_xbrk_trigout;
-wire [ 17: 0] cpu_i_address;
-wire xbrk0_armed;
-wire xbrk0_break_hit;
-wire xbrk0_goto0_hit;
-wire xbrk0_goto1_hit;
-wire xbrk0_toff_hit;
-wire xbrk0_ton_hit;
-wire xbrk0_tout_hit;
-wire xbrk1_armed;
-wire xbrk1_break_hit;
-wire xbrk1_goto0_hit;
-wire xbrk1_goto1_hit;
-wire xbrk1_toff_hit;
-wire xbrk1_ton_hit;
-wire xbrk1_tout_hit;
-wire xbrk2_armed;
-wire xbrk2_break_hit;
-wire xbrk2_goto0_hit;
-wire xbrk2_goto1_hit;
-wire xbrk2_toff_hit;
-wire xbrk2_ton_hit;
-wire xbrk2_tout_hit;
-wire xbrk3_armed;
-wire xbrk3_break_hit;
-wire xbrk3_goto0_hit;
-wire xbrk3_goto1_hit;
-wire xbrk3_toff_hit;
-wire xbrk3_ton_hit;
-wire xbrk3_tout_hit;
-reg xbrk_break;
-wire xbrk_break_hit;
-wire xbrk_goto0;
-wire xbrk_goto0_hit;
-wire xbrk_goto1;
-wire xbrk_goto1_hit;
-wire xbrk_toff_hit;
-wire xbrk_ton_hit;
-wire xbrk_tout_hit;
-wire xbrk_traceoff;
-wire xbrk_traceon;
-wire xbrk_trigout;
- assign cpu_i_address = {F_pc, 2'b00};
- assign D_cpu_addr_en = D_valid;
- assign E_cpu_addr_en = E_valid;
- assign xbrk0_break_hit = 0;
- assign xbrk0_ton_hit = 0;
- assign xbrk0_toff_hit = 0;
- assign xbrk0_tout_hit = 0;
- assign xbrk0_goto0_hit = 0;
- assign xbrk0_goto1_hit = 0;
- assign xbrk1_break_hit = 0;
- assign xbrk1_ton_hit = 0;
- assign xbrk1_toff_hit = 0;
- assign xbrk1_tout_hit = 0;
- assign xbrk1_goto0_hit = 0;
- assign xbrk1_goto1_hit = 0;
- assign xbrk2_break_hit = 0;
- assign xbrk2_ton_hit = 0;
- assign xbrk2_toff_hit = 0;
- assign xbrk2_tout_hit = 0;
- assign xbrk2_goto0_hit = 0;
- assign xbrk2_goto1_hit = 0;
- assign xbrk3_break_hit = 0;
- assign xbrk3_ton_hit = 0;
- assign xbrk3_toff_hit = 0;
- assign xbrk3_tout_hit = 0;
- assign xbrk3_goto0_hit = 0;
- assign xbrk3_goto1_hit = 0;
- assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
- assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
- assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
- assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
- assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
- assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- xbrk_break <= 0;
- else if (E_cpu_addr_en)
- xbrk_break <= xbrk_break_hit;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_xbrk_traceon <= 0;
- else if (E_cpu_addr_en)
- E_xbrk_traceon <= xbrk_ton_hit;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_xbrk_traceoff <= 0;
- else if (E_cpu_addr_en)
- E_xbrk_traceoff <= xbrk_toff_hit;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_xbrk_trigout <= 0;
- else if (E_cpu_addr_en)
- E_xbrk_trigout <= xbrk_tout_hit;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_xbrk_goto0 <= 0;
- else if (E_cpu_addr_en)
- E_xbrk_goto0 <= xbrk_goto0_hit;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_xbrk_goto1 <= 0;
- else if (E_cpu_addr_en)
- E_xbrk_goto1 <= xbrk_goto1_hit;
- end
-
-
- assign xbrk_traceon = 1'b0;
- assign xbrk_traceoff = 1'b0;
- assign xbrk_trigout = 1'b0;
- assign xbrk_goto0 = 1'b0;
- assign xbrk_goto1 = 1'b0;
- assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
- (xbrk_ctrl0[5] & trigger_state_1);
-
- assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
- (xbrk_ctrl1[5] & trigger_state_1);
-
- assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
- (xbrk_ctrl2[5] & trigger_state_1);
-
- assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
- (xbrk_ctrl3[5] & trigger_state_1);
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_dbrk (
- // inputs:
- E_st_data,
- av_ld_data_aligned_filtered,
- clk,
- d_address,
- d_read,
- d_waitrequest,
- d_write,
- debugack,
- reset_n,
-
- // outputs:
- cpu_d_address,
- cpu_d_read,
- cpu_d_readdata,
- cpu_d_wait,
- cpu_d_write,
- cpu_d_writedata,
- dbrk_break,
- dbrk_goto0,
- dbrk_goto1,
- dbrk_traceme,
- dbrk_traceoff,
- dbrk_traceon,
- dbrk_trigout
- )
-;
-
- output [ 17: 0] cpu_d_address;
- output cpu_d_read;
- output [ 31: 0] cpu_d_readdata;
- output cpu_d_wait;
- output cpu_d_write;
- output [ 31: 0] cpu_d_writedata;
- output dbrk_break;
- output dbrk_goto0;
- output dbrk_goto1;
- output dbrk_traceme;
- output dbrk_traceoff;
- output dbrk_traceon;
- output dbrk_trigout;
- input [ 31: 0] E_st_data;
- input [ 31: 0] av_ld_data_aligned_filtered;
- input clk;
- input [ 17: 0] d_address;
- input d_read;
- input d_waitrequest;
- input d_write;
- input debugack;
- input reset_n;
-
-
-wire [ 17: 0] cpu_d_address;
-wire cpu_d_read;
-wire [ 31: 0] cpu_d_readdata;
-wire cpu_d_wait;
-wire cpu_d_write;
-wire [ 31: 0] cpu_d_writedata;
-wire dbrk0_armed;
-wire dbrk0_break_pulse;
-wire dbrk0_goto0;
-wire dbrk0_goto1;
-wire dbrk0_traceme;
-wire dbrk0_traceoff;
-wire dbrk0_traceon;
-wire dbrk0_trigout;
-wire dbrk1_armed;
-wire dbrk1_break_pulse;
-wire dbrk1_goto0;
-wire dbrk1_goto1;
-wire dbrk1_traceme;
-wire dbrk1_traceoff;
-wire dbrk1_traceon;
-wire dbrk1_trigout;
-wire dbrk2_armed;
-wire dbrk2_break_pulse;
-wire dbrk2_goto0;
-wire dbrk2_goto1;
-wire dbrk2_traceme;
-wire dbrk2_traceoff;
-wire dbrk2_traceon;
-wire dbrk2_trigout;
-wire dbrk3_armed;
-wire dbrk3_break_pulse;
-wire dbrk3_goto0;
-wire dbrk3_goto1;
-wire dbrk3_traceme;
-wire dbrk3_traceoff;
-wire dbrk3_traceon;
-wire dbrk3_trigout;
-reg dbrk_break;
-reg dbrk_break_pulse;
-wire [ 31: 0] dbrk_data;
-reg dbrk_goto0;
-reg dbrk_goto1;
-reg dbrk_traceme;
-reg dbrk_traceoff;
-reg dbrk_traceon;
-reg dbrk_trigout;
- assign cpu_d_address = d_address;
- assign cpu_d_readdata = av_ld_data_aligned_filtered;
- assign cpu_d_read = d_read;
- assign cpu_d_writedata = E_st_data;
- assign cpu_d_write = d_write;
- assign cpu_d_wait = d_waitrequest;
- assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- dbrk_break <= 0;
- else
- dbrk_break <= dbrk_break ? ~debugack
- : dbrk_break_pulse;
-
- end
-
-
- assign dbrk0_armed = 1'b0;
- assign dbrk0_trigout = 1'b0;
- assign dbrk0_break_pulse = 1'b0;
- assign dbrk0_traceoff = 1'b0;
- assign dbrk0_traceon = 1'b0;
- assign dbrk0_traceme = 1'b0;
- assign dbrk0_goto0 = 1'b0;
- assign dbrk0_goto1 = 1'b0;
- assign dbrk1_armed = 1'b0;
- assign dbrk1_trigout = 1'b0;
- assign dbrk1_break_pulse = 1'b0;
- assign dbrk1_traceoff = 1'b0;
- assign dbrk1_traceon = 1'b0;
- assign dbrk1_traceme = 1'b0;
- assign dbrk1_goto0 = 1'b0;
- assign dbrk1_goto1 = 1'b0;
- assign dbrk2_armed = 1'b0;
- assign dbrk2_trigout = 1'b0;
- assign dbrk2_break_pulse = 1'b0;
- assign dbrk2_traceoff = 1'b0;
- assign dbrk2_traceon = 1'b0;
- assign dbrk2_traceme = 1'b0;
- assign dbrk2_goto0 = 1'b0;
- assign dbrk2_goto1 = 1'b0;
- assign dbrk3_armed = 1'b0;
- assign dbrk3_trigout = 1'b0;
- assign dbrk3_break_pulse = 1'b0;
- assign dbrk3_traceoff = 1'b0;
- assign dbrk3_traceon = 1'b0;
- assign dbrk3_traceme = 1'b0;
- assign dbrk3_goto0 = 1'b0;
- assign dbrk3_goto1 = 1'b0;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- dbrk_trigout <= 0;
- dbrk_break_pulse <= 0;
- dbrk_traceoff <= 0;
- dbrk_traceon <= 0;
- dbrk_traceme <= 0;
- dbrk_goto0 <= 0;
- dbrk_goto1 <= 0;
- end
- else
- begin
- dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
- dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
- dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
- dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
- dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
- dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
- dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
- end
- end
-
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_itrace (
- // inputs:
- clk,
- dbrk_traceoff,
- dbrk_traceon,
- jdo,
- jrst_n,
- take_action_tracectrl,
- xbrk_traceoff,
- xbrk_traceon,
- xbrk_wrap_traceoff,
-
- // outputs:
- itm,
- trc_ctrl,
- trc_on
- )
-;
-
- output [ 35: 0] itm;
- output [ 15: 0] trc_ctrl;
- output trc_on;
- input clk;
- input dbrk_traceoff;
- input dbrk_traceon;
- input [ 15: 0] jdo;
- input jrst_n;
- input take_action_tracectrl;
- input xbrk_traceoff;
- input xbrk_traceon;
- input xbrk_wrap_traceoff;
-
-
-wire advanced_exc_occured;
-wire curr_pid;
-wire [ 1: 0] dct_code;
-wire dct_is_taken;
-wire [ 31: 0] eic_addr;
-wire [ 31: 0] exc_addr;
-wire instr_retired;
-wire is_cond_dct;
-wire is_dct;
-wire is_exception_no_break;
-wire is_external_interrupt;
-wire is_fast_tlb_miss_exception;
-wire is_idct;
-wire [ 35: 0] itm;
-wire not_in_debug_mode;
-wire record_dct_outcome_in_sync;
-wire record_itrace;
-wire [ 31: 0] retired_pcb;
-wire [ 1: 0] sync_code;
-wire [ 6: 0] sync_interval;
-wire [ 6: 0] sync_timer;
-wire [ 6: 0] sync_timer_next;
-wire sync_timer_reached_zero;
-wire [ 15: 0] trc_ctrl;
-reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-wire trc_on;
- assign is_cond_dct = 1'b0;
- assign is_dct = 1'b0;
- assign dct_is_taken = 1'b0;
- assign is_idct = 1'b0;
- assign retired_pcb = 32'b0;
- assign not_in_debug_mode = 1'b0;
- assign instr_retired = 1'b0;
- assign advanced_exc_occured = 1'b0;
- assign is_exception_no_break = 1'b0;
- assign is_external_interrupt = 1'b0;
- assign is_fast_tlb_miss_exception = 1'b0;
- assign curr_pid = 1'b0;
- assign exc_addr = 32'b0;
- assign eic_addr = 32'b0;
- assign sync_code = trc_ctrl[3 : 2];
- assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
- assign sync_timer_reached_zero = sync_timer == 0;
- assign record_dct_outcome_in_sync = dct_is_taken & sync_timer_reached_zero;
- assign sync_timer_next = sync_timer_reached_zero ? sync_timer : (sync_timer - 1);
- assign record_itrace = trc_on & trc_ctrl[4];
- assign dct_code = {is_cond_dct, dct_is_taken};
- assign itm = 36'd0;
- assign sync_timer = 7'd1;
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- begin
- trc_ctrl_reg[0] <= 1'b0;
- trc_ctrl_reg[1] <= 1'b0;
- trc_ctrl_reg[3 : 2] <= 2'b00;
- trc_ctrl_reg[4] <= 1'b0;
- trc_ctrl_reg[7 : 5] <= 3'b000;
- trc_ctrl_reg[8] <= 0;
- trc_ctrl_reg[9] <= 1'b0;
- trc_ctrl_reg[10] <= 1'b0;
- end
- else if (take_action_tracectrl)
- begin
- trc_ctrl_reg[0] <= jdo[5];
- trc_ctrl_reg[1] <= jdo[6];
- trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
- trc_ctrl_reg[4] <= jdo[9];
- trc_ctrl_reg[9] <= jdo[14];
- trc_ctrl_reg[10] <= jdo[2];
- trc_ctrl_reg[7 : 5] <= 3'b000;
- trc_ctrl_reg[8] <= 1'b0;
- end
- else if (xbrk_wrap_traceoff)
- begin
- trc_ctrl_reg[1] <= 0;
- trc_ctrl_reg[0] <= 0;
- end
- else if (dbrk_traceoff | xbrk_traceoff)
- trc_ctrl_reg[1] <= 0;
- else if (trc_ctrl_reg[0] &
- (dbrk_traceon | xbrk_traceon))
- trc_ctrl_reg[1] <= 1;
- end
-
-
- assign trc_ctrl = 0;
- assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_td_mode (
- // inputs:
- ctrl,
-
- // outputs:
- td_mode
- )
-;
-
- output [ 3: 0] td_mode;
- input [ 8: 0] ctrl;
-
-
-wire [ 2: 0] ctrl_bits_for_mux;
-reg [ 3: 0] td_mode;
- assign ctrl_bits_for_mux = ctrl[7 : 5];
- always @(ctrl_bits_for_mux)
- begin
- case (ctrl_bits_for_mux)
-
- 3'b000: begin
- td_mode = 4'b0000;
- end // 3'b000
-
- 3'b001: begin
- td_mode = 4'b1000;
- end // 3'b001
-
- 3'b010: begin
- td_mode = 4'b0100;
- end // 3'b010
-
- 3'b011: begin
- td_mode = 4'b1100;
- end // 3'b011
-
- 3'b100: begin
- td_mode = 4'b0010;
- end // 3'b100
-
- 3'b101: begin
- td_mode = 4'b1010;
- end // 3'b101
-
- 3'b110: begin
- td_mode = 4'b0101;
- end // 3'b110
-
- 3'b111: begin
- td_mode = 4'b1111;
- end // 3'b111
-
- endcase // ctrl_bits_for_mux
- end
-
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_dtrace (
- // inputs:
- clk,
- cpu_d_address,
- cpu_d_read,
- cpu_d_readdata,
- cpu_d_wait,
- cpu_d_write,
- cpu_d_writedata,
- jrst_n,
- trc_ctrl,
-
- // outputs:
- atm,
- dtm
- )
-;
-
- output [ 35: 0] atm;
- output [ 35: 0] dtm;
- input clk;
- input [ 17: 0] cpu_d_address;
- input cpu_d_read;
- input [ 31: 0] cpu_d_readdata;
- input cpu_d_wait;
- input cpu_d_write;
- input [ 31: 0] cpu_d_writedata;
- input jrst_n;
- input [ 15: 0] trc_ctrl;
-
-
-reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
-wire [ 31: 0] cpu_d_address_0_padded;
-wire [ 31: 0] cpu_d_readdata_0_padded;
-wire [ 31: 0] cpu_d_writedata_0_padded;
-reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
-wire dummy_tie_off;
-wire record_load_addr;
-wire record_load_data;
-wire record_store_addr;
-wire record_store_data;
-wire [ 3: 0] td_mode_trc_ctrl;
- assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
- assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
- assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
- //qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_trc_ctrl_td_mode, which is an e_instance
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_td_mode qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_trc_ctrl_td_mode
- (
- .ctrl (trc_ctrl[8 : 0]),
- .td_mode (td_mode_trc_ctrl)
- );
-
- assign {record_load_addr, record_store_addr,
- record_load_data, record_store_data} = td_mode_trc_ctrl;
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- begin
- atm <= 0;
- dtm <= 0;
- end
- else
- begin
- atm <= 0;
- dtm <= 0;
- end
- end
-
-
- assign dummy_tie_off = cpu_d_wait|cpu_d_read|cpu_d_write;
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_compute_input_tm_cnt (
- // inputs:
- atm_valid,
- dtm_valid,
- itm_valid,
-
- // outputs:
- compute_input_tm_cnt
- )
-;
-
- output [ 1: 0] compute_input_tm_cnt;
- input atm_valid;
- input dtm_valid;
- input itm_valid;
-
-
-reg [ 1: 0] compute_input_tm_cnt;
-wire [ 2: 0] switch_for_mux;
- assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
- always @(switch_for_mux)
- begin
- case (switch_for_mux)
-
- 3'b000: begin
- compute_input_tm_cnt = 0;
- end // 3'b000
-
- 3'b001: begin
- compute_input_tm_cnt = 1;
- end // 3'b001
-
- 3'b010: begin
- compute_input_tm_cnt = 1;
- end // 3'b010
-
- 3'b011: begin
- compute_input_tm_cnt = 2;
- end // 3'b011
-
- 3'b100: begin
- compute_input_tm_cnt = 1;
- end // 3'b100
-
- 3'b101: begin
- compute_input_tm_cnt = 2;
- end // 3'b101
-
- 3'b110: begin
- compute_input_tm_cnt = 2;
- end // 3'b110
-
- 3'b111: begin
- compute_input_tm_cnt = 3;
- end // 3'b111
-
- endcase // switch_for_mux
- end
-
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_fifo_wrptr_inc (
- // inputs:
- ge2_free,
- ge3_free,
- input_tm_cnt,
-
- // outputs:
- fifo_wrptr_inc
- )
-;
-
- output [ 3: 0] fifo_wrptr_inc;
- input ge2_free;
- input ge3_free;
- input [ 1: 0] input_tm_cnt;
-
-
-reg [ 3: 0] fifo_wrptr_inc;
- always @(ge2_free or ge3_free or input_tm_cnt)
- begin
- if (ge3_free & (input_tm_cnt == 3))
- fifo_wrptr_inc = 3;
- else if (ge2_free & (input_tm_cnt >= 2))
- fifo_wrptr_inc = 2;
- else if (input_tm_cnt >= 1)
- fifo_wrptr_inc = 1;
- else
- fifo_wrptr_inc = 0;
- end
-
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_fifo_cnt_inc (
- // inputs:
- empty,
- ge2_free,
- ge3_free,
- input_tm_cnt,
-
- // outputs:
- fifo_cnt_inc
- )
-;
-
- output [ 4: 0] fifo_cnt_inc;
- input empty;
- input ge2_free;
- input ge3_free;
- input [ 1: 0] input_tm_cnt;
-
-
-reg [ 4: 0] fifo_cnt_inc;
- always @(empty or ge2_free or ge3_free or input_tm_cnt)
- begin
- if (empty)
- fifo_cnt_inc = input_tm_cnt[1 : 0];
- else if (ge3_free & (input_tm_cnt == 3))
- fifo_cnt_inc = 2;
- else if (ge2_free & (input_tm_cnt >= 2))
- fifo_cnt_inc = 1;
- else if (input_tm_cnt >= 1)
- fifo_cnt_inc = 0;
- else
- fifo_cnt_inc = {5{1'b1}};
- end
-
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_fifo (
- // inputs:
- atm,
- clk,
- dbrk_traceme,
- dbrk_traceoff,
- dbrk_traceon,
- dtm,
- itm,
- jrst_n,
- reset_n,
- trc_on,
-
- // outputs:
- tw
- )
-;
-
- output [ 35: 0] tw;
- input [ 35: 0] atm;
- input clk;
- input dbrk_traceme;
- input dbrk_traceoff;
- input dbrk_traceon;
- input [ 35: 0] dtm;
- input [ 35: 0] itm;
- input jrst_n;
- input reset_n;
- input trc_on;
-
-
-wire atm_valid;
-wire [ 1: 0] compute_input_tm_cnt;
-wire dtm_valid;
-wire empty;
-reg [ 35: 0] fifo_0;
-wire fifo_0_enable;
-wire [ 35: 0] fifo_0_mux;
-reg [ 35: 0] fifo_1;
-reg [ 35: 0] fifo_10;
-wire fifo_10_enable;
-wire [ 35: 0] fifo_10_mux;
-reg [ 35: 0] fifo_11;
-wire fifo_11_enable;
-wire [ 35: 0] fifo_11_mux;
-reg [ 35: 0] fifo_12;
-wire fifo_12_enable;
-wire [ 35: 0] fifo_12_mux;
-reg [ 35: 0] fifo_13;
-wire fifo_13_enable;
-wire [ 35: 0] fifo_13_mux;
-reg [ 35: 0] fifo_14;
-wire fifo_14_enable;
-wire [ 35: 0] fifo_14_mux;
-reg [ 35: 0] fifo_15;
-wire fifo_15_enable;
-wire [ 35: 0] fifo_15_mux;
-wire fifo_1_enable;
-wire [ 35: 0] fifo_1_mux;
-reg [ 35: 0] fifo_2;
-wire fifo_2_enable;
-wire [ 35: 0] fifo_2_mux;
-reg [ 35: 0] fifo_3;
-wire fifo_3_enable;
-wire [ 35: 0] fifo_3_mux;
-reg [ 35: 0] fifo_4;
-wire fifo_4_enable;
-wire [ 35: 0] fifo_4_mux;
-reg [ 35: 0] fifo_5;
-wire fifo_5_enable;
-wire [ 35: 0] fifo_5_mux;
-reg [ 35: 0] fifo_6;
-wire fifo_6_enable;
-wire [ 35: 0] fifo_6_mux;
-reg [ 35: 0] fifo_7;
-wire fifo_7_enable;
-wire [ 35: 0] fifo_7_mux;
-reg [ 35: 0] fifo_8;
-wire fifo_8_enable;
-wire [ 35: 0] fifo_8_mux;
-reg [ 35: 0] fifo_9;
-wire fifo_9_enable;
-wire [ 35: 0] fifo_9_mux;
-reg [ 4: 0] fifo_cnt /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
-wire [ 4: 0] fifo_cnt_inc;
-wire [ 35: 0] fifo_head;
-reg [ 3: 0] fifo_rdptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
-wire [ 35: 0] fifo_read_mux;
-reg [ 3: 0] fifo_wrptr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
-wire [ 3: 0] fifo_wrptr_inc;
-wire [ 3: 0] fifo_wrptr_plus1;
-wire [ 3: 0] fifo_wrptr_plus2;
-wire ge2_free;
-wire ge3_free;
-wire input_ge1;
-wire input_ge2;
-wire input_ge3;
-wire [ 1: 0] input_tm_cnt;
-wire itm_valid;
-reg overflow_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
-wire [ 35: 0] overflow_pending_atm;
-wire [ 35: 0] overflow_pending_dtm;
-wire trc_this;
-wire [ 35: 0] tw;
- assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
- assign itm_valid = |itm[35 : 32];
- assign atm_valid = |atm[35 : 32] & trc_this;
- assign dtm_valid = |dtm[35 : 32] & trc_this;
- assign ge2_free = ~fifo_cnt[4];
- assign ge3_free = ge2_free & ~&fifo_cnt[3 : 0];
- assign empty = ~|fifo_cnt;
- assign fifo_wrptr_plus1 = fifo_wrptr + 1;
- assign fifo_wrptr_plus2 = fifo_wrptr + 2;
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_compute_input_tm_cnt the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_compute_input_tm_cnt
- (
- .atm_valid (atm_valid),
- .compute_input_tm_cnt (compute_input_tm_cnt),
- .dtm_valid (dtm_valid),
- .itm_valid (itm_valid)
- );
-
- assign input_tm_cnt = compute_input_tm_cnt;
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_fifo_wrptr_inc the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_fifo_wrptr_inc
- (
- .fifo_wrptr_inc (fifo_wrptr_inc),
- .ge2_free (ge2_free),
- .ge3_free (ge3_free),
- .input_tm_cnt (input_tm_cnt)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_fifo_cnt_inc the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_fifo_cnt_inc
- (
- .empty (empty),
- .fifo_cnt_inc (fifo_cnt_inc),
- .ge2_free (ge2_free),
- .ge3_free (ge3_free),
- .input_tm_cnt (input_tm_cnt)
- );
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- begin
- fifo_rdptr <= 0;
- fifo_wrptr <= 0;
- fifo_cnt <= 0;
- overflow_pending <= 1;
- end
- else
- begin
- fifo_wrptr <= fifo_wrptr + fifo_wrptr_inc;
- fifo_cnt <= fifo_cnt + fifo_cnt_inc;
- if (~empty)
- fifo_rdptr <= fifo_rdptr + 1;
- if (~trc_this || (~ge2_free & input_ge2) || (~ge3_free & input_ge3))
- overflow_pending <= 1;
- else if (atm_valid | dtm_valid)
- overflow_pending <= 0;
- end
- end
-
-
- assign fifo_head = fifo_read_mux;
- assign tw = itm;
- assign fifo_0_enable = ((fifo_wrptr == 4'd0) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd0) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd0) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_0 <= 0;
- else if (fifo_0_enable)
- fifo_0 <= fifo_0_mux;
- end
-
-
- assign fifo_0_mux = (((fifo_wrptr == 4'd0) && itm_valid))? itm :
- (((fifo_wrptr == 4'd0) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd0) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd0) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd0) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_1_enable = ((fifo_wrptr == 4'd1) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd1) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd1) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_1 <= 0;
- else if (fifo_1_enable)
- fifo_1 <= fifo_1_mux;
- end
-
-
- assign fifo_1_mux = (((fifo_wrptr == 4'd1) && itm_valid))? itm :
- (((fifo_wrptr == 4'd1) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd1) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd1) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd1) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_2_enable = ((fifo_wrptr == 4'd2) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd2) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd2) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_2 <= 0;
- else if (fifo_2_enable)
- fifo_2 <= fifo_2_mux;
- end
-
-
- assign fifo_2_mux = (((fifo_wrptr == 4'd2) && itm_valid))? itm :
- (((fifo_wrptr == 4'd2) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd2) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd2) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd2) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_3_enable = ((fifo_wrptr == 4'd3) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd3) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd3) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_3 <= 0;
- else if (fifo_3_enable)
- fifo_3 <= fifo_3_mux;
- end
-
-
- assign fifo_3_mux = (((fifo_wrptr == 4'd3) && itm_valid))? itm :
- (((fifo_wrptr == 4'd3) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd3) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd3) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd3) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_4_enable = ((fifo_wrptr == 4'd4) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd4) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd4) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_4 <= 0;
- else if (fifo_4_enable)
- fifo_4 <= fifo_4_mux;
- end
-
-
- assign fifo_4_mux = (((fifo_wrptr == 4'd4) && itm_valid))? itm :
- (((fifo_wrptr == 4'd4) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd4) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd4) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd4) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_5_enable = ((fifo_wrptr == 4'd5) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd5) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd5) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_5 <= 0;
- else if (fifo_5_enable)
- fifo_5 <= fifo_5_mux;
- end
-
-
- assign fifo_5_mux = (((fifo_wrptr == 4'd5) && itm_valid))? itm :
- (((fifo_wrptr == 4'd5) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd5) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd5) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd5) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_6_enable = ((fifo_wrptr == 4'd6) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd6) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd6) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_6 <= 0;
- else if (fifo_6_enable)
- fifo_6 <= fifo_6_mux;
- end
-
-
- assign fifo_6_mux = (((fifo_wrptr == 4'd6) && itm_valid))? itm :
- (((fifo_wrptr == 4'd6) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd6) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd6) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd6) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_7_enable = ((fifo_wrptr == 4'd7) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd7) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd7) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_7 <= 0;
- else if (fifo_7_enable)
- fifo_7 <= fifo_7_mux;
- end
-
-
- assign fifo_7_mux = (((fifo_wrptr == 4'd7) && itm_valid))? itm :
- (((fifo_wrptr == 4'd7) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd7) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd7) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd7) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_8_enable = ((fifo_wrptr == 4'd8) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd8) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd8) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_8 <= 0;
- else if (fifo_8_enable)
- fifo_8 <= fifo_8_mux;
- end
-
-
- assign fifo_8_mux = (((fifo_wrptr == 4'd8) && itm_valid))? itm :
- (((fifo_wrptr == 4'd8) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd8) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd8) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd8) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_9_enable = ((fifo_wrptr == 4'd9) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd9) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd9) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_9 <= 0;
- else if (fifo_9_enable)
- fifo_9 <= fifo_9_mux;
- end
-
-
- assign fifo_9_mux = (((fifo_wrptr == 4'd9) && itm_valid))? itm :
- (((fifo_wrptr == 4'd9) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd9) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd9) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd9) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_10_enable = ((fifo_wrptr == 4'd10) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd10) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd10) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_10 <= 0;
- else if (fifo_10_enable)
- fifo_10 <= fifo_10_mux;
- end
-
-
- assign fifo_10_mux = (((fifo_wrptr == 4'd10) && itm_valid))? itm :
- (((fifo_wrptr == 4'd10) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd10) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd10) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd10) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_11_enable = ((fifo_wrptr == 4'd11) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd11) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd11) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_11 <= 0;
- else if (fifo_11_enable)
- fifo_11 <= fifo_11_mux;
- end
-
-
- assign fifo_11_mux = (((fifo_wrptr == 4'd11) && itm_valid))? itm :
- (((fifo_wrptr == 4'd11) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd11) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd11) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd11) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_12_enable = ((fifo_wrptr == 4'd12) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd12) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd12) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_12 <= 0;
- else if (fifo_12_enable)
- fifo_12 <= fifo_12_mux;
- end
-
-
- assign fifo_12_mux = (((fifo_wrptr == 4'd12) && itm_valid))? itm :
- (((fifo_wrptr == 4'd12) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd12) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd12) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd12) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_13_enable = ((fifo_wrptr == 4'd13) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd13) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd13) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_13 <= 0;
- else if (fifo_13_enable)
- fifo_13 <= fifo_13_mux;
- end
-
-
- assign fifo_13_mux = (((fifo_wrptr == 4'd13) && itm_valid))? itm :
- (((fifo_wrptr == 4'd13) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd13) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd13) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd13) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_14_enable = ((fifo_wrptr == 4'd14) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd14) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd14) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_14 <= 0;
- else if (fifo_14_enable)
- fifo_14 <= fifo_14_mux;
- end
-
-
- assign fifo_14_mux = (((fifo_wrptr == 4'd14) && itm_valid))? itm :
- (((fifo_wrptr == 4'd14) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd14) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd14) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd14) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign fifo_15_enable = ((fifo_wrptr == 4'd15) && input_ge1) || (ge2_free && (fifo_wrptr_plus1== 4'd15) && input_ge2) ||(ge3_free && (fifo_wrptr_plus2== 4'd15) && input_ge3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- fifo_15 <= 0;
- else if (fifo_15_enable)
- fifo_15 <= fifo_15_mux;
- end
-
-
- assign fifo_15_mux = (((fifo_wrptr == 4'd15) && itm_valid))? itm :
- (((fifo_wrptr == 4'd15) && atm_valid))? overflow_pending_atm :
- (((fifo_wrptr == 4'd15) && dtm_valid))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & atm_valid)))? overflow_pending_atm :
- (((fifo_wrptr_plus1 == 4'd15) && (ge2_free & itm_valid & dtm_valid)))? overflow_pending_dtm :
- (((fifo_wrptr_plus1 == 4'd15) && (ge2_free & atm_valid & dtm_valid)))? overflow_pending_dtm :
- overflow_pending_dtm;
-
- assign input_ge1 = |input_tm_cnt;
- assign input_ge2 = input_tm_cnt[1];
- assign input_ge3 = &input_tm_cnt;
- assign overflow_pending_atm = {overflow_pending, atm[34 : 0]};
- assign overflow_pending_dtm = {overflow_pending, dtm[34 : 0]};
- assign fifo_read_mux = (fifo_rdptr == 4'd0)? fifo_0 :
- (fifo_rdptr == 4'd1)? fifo_1 :
- (fifo_rdptr == 4'd2)? fifo_2 :
- (fifo_rdptr == 4'd3)? fifo_3 :
- (fifo_rdptr == 4'd4)? fifo_4 :
- (fifo_rdptr == 4'd5)? fifo_5 :
- (fifo_rdptr == 4'd6)? fifo_6 :
- (fifo_rdptr == 4'd7)? fifo_7 :
- (fifo_rdptr == 4'd8)? fifo_8 :
- (fifo_rdptr == 4'd9)? fifo_9 :
- (fifo_rdptr == 4'd10)? fifo_10 :
- (fifo_rdptr == 4'd11)? fifo_11 :
- (fifo_rdptr == 4'd12)? fifo_12 :
- (fifo_rdptr == 4'd13)? fifo_13 :
- (fifo_rdptr == 4'd14)? fifo_14 :
- fifo_15;
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_pib (
- // outputs:
- tr_data
- )
-;
-
- output [ 35: 0] tr_data;
-
-
-wire [ 35: 0] tr_data;
- assign tr_data = 0;
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_im (
- // inputs:
- clk,
- jrst_n,
- trc_ctrl,
- tw,
-
- // outputs:
- tracemem_on,
- tracemem_trcdata,
- tracemem_tw,
- trc_im_addr,
- trc_wrap,
- xbrk_wrap_traceoff
- )
-;
-
- output tracemem_on;
- output [ 35: 0] tracemem_trcdata;
- output tracemem_tw;
- output [ 6: 0] trc_im_addr;
- output trc_wrap;
- output xbrk_wrap_traceoff;
- input clk;
- input jrst_n;
- input [ 15: 0] trc_ctrl;
- input [ 35: 0] tw;
-
-
-wire tracemem_on;
-wire [ 35: 0] tracemem_trcdata;
-wire tracemem_tw;
-reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-wire [ 35: 0] trc_im_data;
-wire trc_on_chip;
-reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-wire tw_valid;
-wire xbrk_wrap_traceoff;
- assign trc_im_data = tw;
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- begin
- trc_im_addr <= 0;
- trc_wrap <= 0;
- end
- else
- begin
- trc_im_addr <= 0;
- trc_wrap <= 0;
- end
- end
-
-
- assign trc_on_chip = ~trc_ctrl[8];
- assign tw_valid = |trc_im_data[35 : 32];
- assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
- assign tracemem_trcdata = 0;
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_performance_monitors
-;
-
-
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_avalon_reg (
- // inputs:
- address,
- clk,
- debugaccess,
- monitor_error,
- monitor_go,
- monitor_ready,
- reset_n,
- write,
- writedata,
-
- // outputs:
- oci_ienable,
- oci_reg_readdata,
- oci_single_step_mode,
- ocireg_ers,
- ocireg_mrs,
- take_action_ocireg
- )
-;
-
- output [ 31: 0] oci_ienable;
- output [ 31: 0] oci_reg_readdata;
- output oci_single_step_mode;
- output ocireg_ers;
- output ocireg_mrs;
- output take_action_ocireg;
- input [ 8: 0] address;
- input clk;
- input debugaccess;
- input monitor_error;
- input monitor_go;
- input monitor_ready;
- input reset_n;
- input write;
- input [ 31: 0] writedata;
-
-
-reg [ 31: 0] oci_ienable;
-wire oci_reg_00_addressed;
-wire oci_reg_01_addressed;
-wire [ 31: 0] oci_reg_readdata;
-reg oci_single_step_mode;
-wire ocireg_ers;
-wire ocireg_mrs;
-wire ocireg_sstep;
-wire take_action_oci_intr_mask_reg;
-wire take_action_ocireg;
-wire write_strobe;
- assign oci_reg_00_addressed = address == 9'h100;
- assign oci_reg_01_addressed = address == 9'h101;
- assign write_strobe = write & debugaccess;
- assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
- assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
- assign ocireg_ers = writedata[1];
- assign ocireg_mrs = writedata[0];
- assign ocireg_sstep = writedata[3];
- assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
- monitor_ready, monitor_error} :
- oci_reg_01_addressed ? oci_ienable :
- 32'b0;
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- oci_single_step_mode <= 1'b0;
- else if (take_action_ocireg)
- oci_single_step_mode <= ocireg_sstep;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- oci_ienable <= 32'b00000000000000000000000000001111;
- else if (take_action_oci_intr_mask_reg)
- oci_ienable <= writedata | ~(32'b00000000000000000000000000001111);
- end
-
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_sp_ram_module (
- // inputs:
- address,
- byteenable,
- clock,
- data,
- reset_req,
- wren,
-
- // outputs:
- q
- )
-;
-
- parameter lpm_file = "UNUSED";
-
-
- output [ 31: 0] q;
- input [ 7: 0] address;
- input [ 3: 0] byteenable;
- input clock;
- input [ 31: 0] data;
- input reset_req;
- input wren;
-
-
-wire clocken;
-wire [ 31: 0] q;
-wire [ 31: 0] ram_q;
- assign q = ram_q;
- assign clocken = ~reset_req;
- altsyncram the_altsyncram
- (
- .address_a (address),
- .byteena_a (byteenable),
- .clock0 (clock),
- .clocken0 (clocken),
- .data_a (data),
- .q_a (ram_q),
- .wren_a (wren)
- );
-
- defparam the_altsyncram.init_file = lpm_file,
- the_altsyncram.maximum_depth = 0,
- the_altsyncram.numwords_a = 256,
- the_altsyncram.operation_mode = "SINGLE_PORT",
- the_altsyncram.outdata_reg_a = "UNREGISTERED",
- the_altsyncram.ram_block_type = "AUTO",
- the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
- the_altsyncram.width_a = 32,
- the_altsyncram.width_byteena_a = 4,
- the_altsyncram.widthad_a = 8;
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_ocimem (
- // inputs:
- address,
- byteenable,
- clk,
- debugaccess,
- jdo,
- jrst_n,
- read,
- reset_req,
- take_action_ocimem_a,
- take_action_ocimem_b,
- take_no_action_ocimem_a,
- write,
- writedata,
-
- // outputs:
- MonDReg,
- ociram_readdata,
- waitrequest
- )
-;
-
- output [ 31: 0] MonDReg;
- output [ 31: 0] ociram_readdata;
- output waitrequest;
- input [ 8: 0] address;
- input [ 3: 0] byteenable;
- input clk;
- input debugaccess;
- input [ 37: 0] jdo;
- input jrst_n;
- input read;
- input reset_req;
- input take_action_ocimem_a;
- input take_action_ocimem_b;
- input take_no_action_ocimem_a;
- input write;
- input [ 31: 0] writedata;
-
-
-reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-wire [ 8: 0] MonARegAddrInc;
-wire MonARegAddrIncAccessingRAM;
-reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-reg avalon_ociram_readdata_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-wire avalon_ram_wr;
-wire [ 31: 0] cfgrom_readdata;
-reg jtag_ram_access /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-reg jtag_ram_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-reg jtag_ram_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-reg jtag_ram_wr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-reg jtag_rd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-reg jtag_rd_d1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-wire [ 7: 0] ociram_addr;
-wire [ 3: 0] ociram_byteenable;
-wire [ 31: 0] ociram_readdata;
-wire ociram_reset_req;
-wire [ 31: 0] ociram_wr_data;
-wire ociram_wr_en;
-reg waitrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- begin
- jtag_rd <= 1'b0;
- jtag_rd_d1 <= 1'b0;
- jtag_ram_wr <= 1'b0;
- jtag_ram_rd <= 1'b0;
- jtag_ram_rd_d1 <= 1'b0;
- jtag_ram_access <= 1'b0;
- MonAReg <= 0;
- MonDReg <= 0;
- waitrequest <= 1'b1;
- avalon_ociram_readdata_ready <= 1'b0;
- end
- else
- begin
- if (take_no_action_ocimem_a)
- begin
- MonAReg[10 : 2] <= MonARegAddrInc;
- jtag_rd <= 1'b1;
- jtag_ram_rd <= MonARegAddrIncAccessingRAM;
- jtag_ram_access <= MonARegAddrIncAccessingRAM;
- end
- else if (take_action_ocimem_a)
- begin
- MonAReg[10 : 2] <= { jdo[17],
- jdo[33 : 26] };
-
- jtag_rd <= 1'b1;
- jtag_ram_rd <= ~jdo[17];
- jtag_ram_access <= ~jdo[17];
- end
- else if (take_action_ocimem_b)
- begin
- MonAReg[10 : 2] <= MonARegAddrInc;
- MonDReg <= jdo[34 : 3];
- jtag_ram_wr <= MonARegAddrIncAccessingRAM;
- jtag_ram_access <= MonARegAddrIncAccessingRAM;
- end
- else
- begin
- jtag_rd <= 0;
- jtag_ram_wr <= 0;
- jtag_ram_rd <= 0;
- jtag_ram_access <= 0;
- if (jtag_rd_d1)
- MonDReg <= jtag_ram_rd_d1 ? ociram_readdata : cfgrom_readdata;
- end
- jtag_rd_d1 <= jtag_rd;
- jtag_ram_rd_d1 <= jtag_ram_rd;
- if (~waitrequest)
- begin
- waitrequest <= 1'b1;
- avalon_ociram_readdata_ready <= 1'b0;
- end
- else if (write)
- waitrequest <= ~address[8] & jtag_ram_access;
- else if (read)
- begin
- avalon_ociram_readdata_ready <= ~(~address[8] & jtag_ram_access);
- waitrequest <= ~avalon_ociram_readdata_ready;
- end
- else
- begin
- waitrequest <= 1'b1;
- avalon_ociram_readdata_ready <= 1'b0;
- end
- end
- end
-
-
- assign MonARegAddrInc = MonAReg[10 : 2]+1;
- assign MonARegAddrIncAccessingRAM = ~MonARegAddrInc[8];
- assign avalon_ram_wr = write & ~address[8] & debugaccess;
- assign ociram_addr = jtag_ram_access ? MonAReg[9 : 2] : address[7 : 0];
- assign ociram_wr_data = jtag_ram_access ? MonDReg[31 : 0] : writedata;
- assign ociram_byteenable = jtag_ram_access ? 4'b1111 : byteenable;
- assign ociram_wr_en = jtag_ram_access ? jtag_ram_wr : avalon_ram_wr;
- assign ociram_reset_req = reset_req & ~jtag_ram_access;
-//qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_sp_ram, which is an nios_sp_ram
-qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_sp_ram_module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_sp_ram
- (
- .address (ociram_addr),
- .byteenable (ociram_byteenable),
- .clock (clk),
- .data (ociram_wr_data),
- .q (ociram_readdata),
- .reset_req (ociram_reset_req),
- .wren (ociram_wr_en)
- );
-
-//synthesis translate_off
-`ifdef NO_PLI
-defparam qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_sp_ram.lpm_file = "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_default_contents.dat";
-`else
-defparam qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_sp_ram.lpm_file = "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_default_contents.hex";
-`endif
-//synthesis translate_on
- assign cfgrom_readdata = (MonAReg[4 : 2] == 3'd0)? 32'h00020020 :
- (MonAReg[4 : 2] == 3'd1)? 32'h00001212 :
- (MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
- (MonAReg[4 : 2] == 3'd3)? 32'h00000100 :
- (MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
- (MonAReg[4 : 2] == 3'd5)? 32'h00020000 :
- (MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
- 32'h00000000;
-
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci (
- // inputs:
- D_valid,
- E_st_data,
- E_valid,
- F_pc,
- address_nxt,
- av_ld_data_aligned_filtered,
- byteenable_nxt,
- clk,
- d_address,
- d_read,
- d_waitrequest,
- d_write,
- debugaccess_nxt,
- hbreak_enabled,
- read_nxt,
- reset,
- reset_n,
- reset_req,
- write_nxt,
- writedata_nxt,
-
- // outputs:
- debug_mem_slave_debugaccess_to_roms,
- oci_hbreak_req,
- oci_ienable,
- oci_single_step_mode,
- readdata,
- resetrequest,
- waitrequest
- )
-;
-
- output debug_mem_slave_debugaccess_to_roms;
- output oci_hbreak_req;
- output [ 31: 0] oci_ienable;
- output oci_single_step_mode;
- output [ 31: 0] readdata;
- output resetrequest;
- output waitrequest;
- input D_valid;
- input [ 31: 0] E_st_data;
- input E_valid;
- input [ 15: 0] F_pc;
- input [ 8: 0] address_nxt;
- input [ 31: 0] av_ld_data_aligned_filtered;
- input [ 3: 0] byteenable_nxt;
- input clk;
- input [ 17: 0] d_address;
- input d_read;
- input d_waitrequest;
- input d_write;
- input debugaccess_nxt;
- input hbreak_enabled;
- input read_nxt;
- input reset;
- input reset_n;
- input reset_req;
- input write_nxt;
- input [ 31: 0] writedata_nxt;
-
-
-wire [ 31: 0] MonDReg;
-reg [ 8: 0] address;
-wire [ 35: 0] atm;
-wire [ 31: 0] break_readreg;
-reg [ 3: 0] byteenable;
-wire [ 17: 0] cpu_d_address;
-wire cpu_d_read;
-wire [ 31: 0] cpu_d_readdata;
-wire cpu_d_wait;
-wire cpu_d_write;
-wire [ 31: 0] cpu_d_writedata;
-wire dbrk_break;
-wire dbrk_goto0;
-wire dbrk_goto1;
-wire dbrk_hit0_latch;
-wire dbrk_hit1_latch;
-wire dbrk_hit2_latch;
-wire dbrk_hit3_latch;
-wire dbrk_traceme;
-wire dbrk_traceoff;
-wire dbrk_traceon;
-wire dbrk_trigout;
-wire debug_mem_slave_debugaccess_to_roms;
-reg debugaccess;
-wire debugack;
-wire debugreq;
-wire [ 35: 0] dtm;
-wire dummy_sink;
-wire [ 35: 0] itm;
-wire [ 37: 0] jdo;
-wire jrst_n;
-wire monitor_error;
-wire monitor_go;
-wire monitor_ready;
-wire oci_hbreak_req;
-wire [ 31: 0] oci_ienable;
-wire [ 31: 0] oci_reg_readdata;
-wire oci_single_step_mode;
-wire [ 31: 0] ociram_readdata;
-wire ocireg_ers;
-wire ocireg_mrs;
-reg read;
-reg [ 31: 0] readdata;
-wire resetlatch;
-wire resetrequest;
-wire st_ready_test_idle;
-wire take_action_break_a;
-wire take_action_break_b;
-wire take_action_break_c;
-wire take_action_ocimem_a;
-wire take_action_ocimem_b;
-wire take_action_ocireg;
-wire take_action_tracectrl;
-wire take_no_action_break_a;
-wire take_no_action_break_b;
-wire take_no_action_break_c;
-wire take_no_action_ocimem_a;
-wire [ 35: 0] tr_data;
-wire tracemem_on;
-wire [ 35: 0] tracemem_trcdata;
-wire tracemem_tw;
-wire [ 15: 0] trc_ctrl;
-wire [ 6: 0] trc_im_addr;
-wire trc_on;
-wire trc_wrap;
-wire trigbrktype;
-wire trigger_state_0;
-wire trigger_state_1;
-wire trigout;
-wire [ 35: 0] tw;
-wire waitrequest;
-reg write;
-reg [ 31: 0] writedata;
-wire xbrk_break;
-wire [ 7: 0] xbrk_ctrl0;
-wire [ 7: 0] xbrk_ctrl1;
-wire [ 7: 0] xbrk_ctrl2;
-wire [ 7: 0] xbrk_ctrl3;
-wire xbrk_goto0;
-wire xbrk_goto1;
-wire xbrk_traceoff;
-wire xbrk_traceon;
-wire xbrk_trigout;
-wire xbrk_wrap_traceoff;
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_debug the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_debug
- (
- .clk (clk),
- .dbrk_break (dbrk_break),
- .debugack (debugack),
- .debugreq (debugreq),
- .hbreak_enabled (hbreak_enabled),
- .jdo (jdo),
- .jrst_n (jrst_n),
- .monitor_error (monitor_error),
- .monitor_go (monitor_go),
- .monitor_ready (monitor_ready),
- .oci_hbreak_req (oci_hbreak_req),
- .ocireg_ers (ocireg_ers),
- .ocireg_mrs (ocireg_mrs),
- .reset (reset),
- .resetlatch (resetlatch),
- .resetrequest (resetrequest),
- .st_ready_test_idle (st_ready_test_idle),
- .take_action_ocimem_a (take_action_ocimem_a),
- .take_action_ocireg (take_action_ocireg),
- .xbrk_break (xbrk_break)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_break the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_break
- (
- .break_readreg (break_readreg),
- .clk (clk),
- .dbrk_break (dbrk_break),
- .dbrk_goto0 (dbrk_goto0),
- .dbrk_goto1 (dbrk_goto1),
- .dbrk_hit0_latch (dbrk_hit0_latch),
- .dbrk_hit1_latch (dbrk_hit1_latch),
- .dbrk_hit2_latch (dbrk_hit2_latch),
- .dbrk_hit3_latch (dbrk_hit3_latch),
- .jdo (jdo),
- .jrst_n (jrst_n),
- .take_action_break_a (take_action_break_a),
- .take_action_break_b (take_action_break_b),
- .take_action_break_c (take_action_break_c),
- .take_no_action_break_a (take_no_action_break_a),
- .take_no_action_break_b (take_no_action_break_b),
- .take_no_action_break_c (take_no_action_break_c),
- .trigbrktype (trigbrktype),
- .trigger_state_0 (trigger_state_0),
- .trigger_state_1 (trigger_state_1),
- .xbrk_ctrl0 (xbrk_ctrl0),
- .xbrk_ctrl1 (xbrk_ctrl1),
- .xbrk_ctrl2 (xbrk_ctrl2),
- .xbrk_ctrl3 (xbrk_ctrl3),
- .xbrk_goto0 (xbrk_goto0),
- .xbrk_goto1 (xbrk_goto1)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_xbrk the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_xbrk
- (
- .D_valid (D_valid),
- .E_valid (E_valid),
- .F_pc (F_pc),
- .clk (clk),
- .reset_n (reset_n),
- .trigger_state_0 (trigger_state_0),
- .trigger_state_1 (trigger_state_1),
- .xbrk_break (xbrk_break),
- .xbrk_ctrl0 (xbrk_ctrl0),
- .xbrk_ctrl1 (xbrk_ctrl1),
- .xbrk_ctrl2 (xbrk_ctrl2),
- .xbrk_ctrl3 (xbrk_ctrl3),
- .xbrk_goto0 (xbrk_goto0),
- .xbrk_goto1 (xbrk_goto1),
- .xbrk_traceoff (xbrk_traceoff),
- .xbrk_traceon (xbrk_traceon),
- .xbrk_trigout (xbrk_trigout)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_dbrk the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_dbrk
- (
- .E_st_data (E_st_data),
- .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
- .clk (clk),
- .cpu_d_address (cpu_d_address),
- .cpu_d_read (cpu_d_read),
- .cpu_d_readdata (cpu_d_readdata),
- .cpu_d_wait (cpu_d_wait),
- .cpu_d_write (cpu_d_write),
- .cpu_d_writedata (cpu_d_writedata),
- .d_address (d_address),
- .d_read (d_read),
- .d_waitrequest (d_waitrequest),
- .d_write (d_write),
- .dbrk_break (dbrk_break),
- .dbrk_goto0 (dbrk_goto0),
- .dbrk_goto1 (dbrk_goto1),
- .dbrk_traceme (dbrk_traceme),
- .dbrk_traceoff (dbrk_traceoff),
- .dbrk_traceon (dbrk_traceon),
- .dbrk_trigout (dbrk_trigout),
- .debugack (debugack),
- .reset_n (reset_n)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_itrace the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_itrace
- (
- .clk (clk),
- .dbrk_traceoff (dbrk_traceoff),
- .dbrk_traceon (dbrk_traceon),
- .itm (itm),
- .jdo (jdo),
- .jrst_n (jrst_n),
- .take_action_tracectrl (take_action_tracectrl),
- .trc_ctrl (trc_ctrl),
- .trc_on (trc_on),
- .xbrk_traceoff (xbrk_traceoff),
- .xbrk_traceon (xbrk_traceon),
- .xbrk_wrap_traceoff (xbrk_wrap_traceoff)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_dtrace the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_dtrace
- (
- .atm (atm),
- .clk (clk),
- .cpu_d_address (cpu_d_address),
- .cpu_d_read (cpu_d_read),
- .cpu_d_readdata (cpu_d_readdata),
- .cpu_d_wait (cpu_d_wait),
- .cpu_d_write (cpu_d_write),
- .cpu_d_writedata (cpu_d_writedata),
- .dtm (dtm),
- .jrst_n (jrst_n),
- .trc_ctrl (trc_ctrl)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_fifo the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_fifo
- (
- .atm (atm),
- .clk (clk),
- .dbrk_traceme (dbrk_traceme),
- .dbrk_traceoff (dbrk_traceoff),
- .dbrk_traceon (dbrk_traceon),
- .dtm (dtm),
- .itm (itm),
- .jrst_n (jrst_n),
- .reset_n (reset_n),
- .trc_on (trc_on),
- .tw (tw)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_pib the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_pib
- (
- .tr_data (tr_data)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_im the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci_im
- (
- .clk (clk),
- .jrst_n (jrst_n),
- .tracemem_on (tracemem_on),
- .tracemem_trcdata (tracemem_trcdata),
- .tracemem_tw (tracemem_tw),
- .trc_ctrl (trc_ctrl),
- .trc_im_addr (trc_im_addr),
- .trc_wrap (trc_wrap),
- .tw (tw),
- .xbrk_wrap_traceoff (xbrk_wrap_traceoff)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_avalon_reg the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_avalon_reg
- (
- .address (address),
- .clk (clk),
- .debugaccess (debugaccess),
- .monitor_error (monitor_error),
- .monitor_go (monitor_go),
- .monitor_ready (monitor_ready),
- .oci_ienable (oci_ienable),
- .oci_reg_readdata (oci_reg_readdata),
- .oci_single_step_mode (oci_single_step_mode),
- .ocireg_ers (ocireg_ers),
- .ocireg_mrs (ocireg_mrs),
- .reset_n (reset_n),
- .take_action_ocireg (take_action_ocireg),
- .write (write),
- .writedata (writedata)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_ocimem the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_ocimem
- (
- .MonDReg (MonDReg),
- .address (address),
- .byteenable (byteenable),
- .clk (clk),
- .debugaccess (debugaccess),
- .jdo (jdo),
- .jrst_n (jrst_n),
- .ociram_readdata (ociram_readdata),
- .read (read),
- .reset_req (reset_req),
- .take_action_ocimem_a (take_action_ocimem_a),
- .take_action_ocimem_b (take_action_ocimem_b),
- .take_no_action_ocimem_a (take_no_action_ocimem_a),
- .waitrequest (waitrequest),
- .write (write),
- .writedata (writedata)
- );
-
- assign trigout = dbrk_trigout | xbrk_trigout;
- assign debug_mem_slave_debugaccess_to_roms = debugack;
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- address <= 0;
- else
- address <= address_nxt;
- end
-
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- byteenable <= 0;
- else
- byteenable <= byteenable_nxt;
- end
-
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- writedata <= 0;
- else
- writedata <= writedata_nxt;
- end
-
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- debugaccess <= 0;
- else
- debugaccess <= debugaccess_nxt;
- end
-
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- read <= 0;
- else
- read <= read ? waitrequest : read_nxt;
- end
-
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- write <= 0;
- else
- write <= write ? waitrequest : write_nxt;
- end
-
-
- always @(posedge clk or negedge jrst_n)
- begin
- if (jrst_n == 0)
- readdata <= 0;
- else
- readdata <= address[8] ? oci_reg_readdata : ociram_readdata;
- end
-
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper
- (
- .MonDReg (MonDReg),
- .break_readreg (break_readreg),
- .clk (clk),
- .dbrk_hit0_latch (dbrk_hit0_latch),
- .dbrk_hit1_latch (dbrk_hit1_latch),
- .dbrk_hit2_latch (dbrk_hit2_latch),
- .dbrk_hit3_latch (dbrk_hit3_latch),
- .debugack (debugack),
- .jdo (jdo),
- .jrst_n (jrst_n),
- .monitor_error (monitor_error),
- .monitor_ready (monitor_ready),
- .reset_n (reset_n),
- .resetlatch (resetlatch),
- .st_ready_test_idle (st_ready_test_idle),
- .take_action_break_a (take_action_break_a),
- .take_action_break_b (take_action_break_b),
- .take_action_break_c (take_action_break_c),
- .take_action_ocimem_a (take_action_ocimem_a),
- .take_action_ocimem_b (take_action_ocimem_b),
- .take_action_tracectrl (take_action_tracectrl),
- .take_no_action_break_a (take_no_action_break_a),
- .take_no_action_break_b (take_no_action_break_b),
- .take_no_action_break_c (take_no_action_break_c),
- .take_no_action_ocimem_a (take_no_action_ocimem_a),
- .tracemem_on (tracemem_on),
- .tracemem_trcdata (tracemem_trcdata),
- .tracemem_tw (tracemem_tw),
- .trc_im_addr (trc_im_addr),
- .trc_on (trc_on),
- .trc_wrap (trc_wrap),
- .trigbrktype (trigbrktype),
- .trigger_state_1 (trigger_state_1)
- );
-
- //dummy sink, which is an e_mux
- assign dummy_sink = tr_data |
- trigout |
- debugack;
-
- assign debugreq = 0;
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq (
- // inputs:
- clk,
- d_readdata,
- d_waitrequest,
- debug_mem_slave_address,
- debug_mem_slave_byteenable,
- debug_mem_slave_debugaccess,
- debug_mem_slave_read,
- debug_mem_slave_write,
- debug_mem_slave_writedata,
- i_readdata,
- i_waitrequest,
- irq,
- reset_n,
- reset_req,
-
- // outputs:
- d_address,
- d_byteenable,
- d_read,
- d_write,
- d_writedata,
- debug_mem_slave_debugaccess_to_roms,
- debug_mem_slave_readdata,
- debug_mem_slave_waitrequest,
- debug_reset_request,
- dummy_ci_port,
- i_address,
- i_read
- )
-;
-
- output [ 17: 0] d_address;
- output [ 3: 0] d_byteenable;
- output d_read;
- output d_write;
- output [ 31: 0] d_writedata;
- output debug_mem_slave_debugaccess_to_roms;
- output [ 31: 0] debug_mem_slave_readdata;
- output debug_mem_slave_waitrequest;
- output debug_reset_request;
- output dummy_ci_port;
- output [ 17: 0] i_address;
- output i_read;
- input clk;
- input [ 31: 0] d_readdata;
- input d_waitrequest;
- input [ 8: 0] debug_mem_slave_address;
- input [ 3: 0] debug_mem_slave_byteenable;
- input debug_mem_slave_debugaccess;
- input debug_mem_slave_read;
- input debug_mem_slave_write;
- input [ 31: 0] debug_mem_slave_writedata;
- input [ 31: 0] i_readdata;
- input i_waitrequest;
- input [ 31: 0] irq;
- input reset_n;
- input reset_req;
-
-
-reg A_valid_from_M /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
-wire [ 1: 0] D_compare_op;
-wire D_ctrl_alu_force_and;
-wire D_ctrl_alu_force_xor;
-wire D_ctrl_alu_signed_comparison;
-wire D_ctrl_alu_subtract;
-wire D_ctrl_b_is_dst;
-wire D_ctrl_br;
-wire D_ctrl_br_cmp;
-wire D_ctrl_br_uncond;
-wire D_ctrl_break;
-wire D_ctrl_crst;
-wire D_ctrl_custom;
-wire D_ctrl_custom_multi;
-wire D_ctrl_exception;
-wire D_ctrl_force_src2_zero;
-wire D_ctrl_hi_imm16;
-wire D_ctrl_ignore_dst;
-wire D_ctrl_implicit_dst_eretaddr;
-wire D_ctrl_implicit_dst_retaddr;
-wire D_ctrl_intr_inst;
-wire D_ctrl_jmp_direct;
-wire D_ctrl_jmp_indirect;
-wire D_ctrl_ld;
-wire D_ctrl_ld_ex;
-wire D_ctrl_ld_io;
-wire D_ctrl_ld_non_io;
-wire D_ctrl_ld_signed;
-wire D_ctrl_ld_st_ex;
-wire D_ctrl_logic;
-wire D_ctrl_mem16;
-wire D_ctrl_mem32;
-wire D_ctrl_mem8;
-wire D_ctrl_rd_ctl_reg;
-wire D_ctrl_retaddr;
-wire D_ctrl_rot_right;
-wire D_ctrl_set_src2_rem_imm;
-wire D_ctrl_shift_logical;
-wire D_ctrl_shift_right_arith;
-wire D_ctrl_shift_rot;
-wire D_ctrl_shift_rot_right;
-wire D_ctrl_signed_imm12;
-wire D_ctrl_src2_choose_imm;
-wire D_ctrl_src_imm5_shift_rot;
-wire D_ctrl_st;
-wire D_ctrl_st_ex;
-wire D_ctrl_uncond_cti_non_br;
-wire D_ctrl_unsigned_lo_imm16;
-wire D_ctrl_wrctl_inst;
-wire [ 4: 0] D_dst_regnum;
-wire [ 55: 0] D_inst;
-wire D_is_opx_inst;
-reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
-wire [ 4: 0] D_iw_a;
-wire [ 4: 0] D_iw_b;
-wire [ 4: 0] D_iw_c;
-wire [ 4: 0] D_iw_control_regnum;
-wire [ 7: 0] D_iw_custom_n;
-wire D_iw_custom_readra;
-wire D_iw_custom_readrb;
-wire D_iw_custom_writerc;
-wire [ 15: 0] D_iw_imm16;
-wire [ 25: 0] D_iw_imm26;
-wire [ 4: 0] D_iw_imm5;
-wire [ 1: 0] D_iw_memsz;
-wire [ 5: 0] D_iw_op;
-wire [ 5: 0] D_iw_opx;
-wire [ 15: 0] D_jmp_direct_target_waddr;
-wire [ 1: 0] D_logic_op;
-wire [ 1: 0] D_logic_op_raw;
-wire D_mem16;
-wire D_mem32;
-wire D_mem8;
-wire D_op_add;
-wire D_op_addi;
-wire D_op_and;
-wire D_op_andhi;
-wire D_op_andi;
-wire D_op_beq;
-wire D_op_bge;
-wire D_op_bgeu;
-wire D_op_blt;
-wire D_op_bltu;
-wire D_op_bne;
-wire D_op_br;
-wire D_op_break;
-wire D_op_bret;
-wire D_op_call;
-wire D_op_callr;
-wire D_op_cmpeq;
-wire D_op_cmpeqi;
-wire D_op_cmpge;
-wire D_op_cmpgei;
-wire D_op_cmpgeu;
-wire D_op_cmpgeui;
-wire D_op_cmplt;
-wire D_op_cmplti;
-wire D_op_cmpltu;
-wire D_op_cmpltui;
-wire D_op_cmpne;
-wire D_op_cmpnei;
-wire D_op_crst;
-wire D_op_custom;
-wire D_op_div;
-wire D_op_divu;
-wire D_op_eret;
-wire D_op_flushd;
-wire D_op_flushda;
-wire D_op_flushi;
-wire D_op_flushp;
-wire D_op_hbreak;
-wire D_op_initd;
-wire D_op_initda;
-wire D_op_initi;
-wire D_op_intr;
-wire D_op_jmp;
-wire D_op_jmpi;
-wire D_op_ldb;
-wire D_op_ldbio;
-wire D_op_ldbu;
-wire D_op_ldbuio;
-wire D_op_ldh;
-wire D_op_ldhio;
-wire D_op_ldhu;
-wire D_op_ldhuio;
-wire D_op_ldl;
-wire D_op_ldw;
-wire D_op_ldwio;
-wire D_op_mul;
-wire D_op_muli;
-wire D_op_mulxss;
-wire D_op_mulxsu;
-wire D_op_mulxuu;
-wire D_op_nextpc;
-wire D_op_nor;
-wire D_op_op_rsv02;
-wire D_op_op_rsv09;
-wire D_op_op_rsv10;
-wire D_op_op_rsv17;
-wire D_op_op_rsv18;
-wire D_op_op_rsv25;
-wire D_op_op_rsv26;
-wire D_op_op_rsv33;
-wire D_op_op_rsv34;
-wire D_op_op_rsv41;
-wire D_op_op_rsv42;
-wire D_op_op_rsv49;
-wire D_op_op_rsv57;
-wire D_op_op_rsv61;
-wire D_op_op_rsv62;
-wire D_op_op_rsv63;
-wire D_op_opx_rsv00;
-wire D_op_opx_rsv10;
-wire D_op_opx_rsv15;
-wire D_op_opx_rsv17;
-wire D_op_opx_rsv21;
-wire D_op_opx_rsv25;
-wire D_op_opx_rsv33;
-wire D_op_opx_rsv34;
-wire D_op_opx_rsv35;
-wire D_op_opx_rsv42;
-wire D_op_opx_rsv43;
-wire D_op_opx_rsv44;
-wire D_op_opx_rsv47;
-wire D_op_opx_rsv50;
-wire D_op_opx_rsv51;
-wire D_op_opx_rsv55;
-wire D_op_opx_rsv56;
-wire D_op_opx_rsv60;
-wire D_op_opx_rsv63;
-wire D_op_or;
-wire D_op_orhi;
-wire D_op_ori;
-wire D_op_rdctl;
-wire D_op_rdprs;
-wire D_op_ret;
-wire D_op_rol;
-wire D_op_roli;
-wire D_op_ror;
-wire D_op_sll;
-wire D_op_slli;
-wire D_op_sra;
-wire D_op_srai;
-wire D_op_srl;
-wire D_op_srli;
-wire D_op_stb;
-wire D_op_stbio;
-wire D_op_stc;
-wire D_op_sth;
-wire D_op_sthio;
-wire D_op_stw;
-wire D_op_stwio;
-wire D_op_sub;
-wire D_op_sync;
-wire D_op_trap;
-wire D_op_wrctl;
-wire D_op_wrprs;
-wire D_op_xor;
-wire D_op_xorhi;
-wire D_op_xori;
-reg D_valid;
-wire [ 71: 0] D_vinst;
-wire D_wr_dst_reg;
-wire [ 31: 0] E_alu_result;
-reg E_alu_sub;
-wire [ 32: 0] E_arith_result;
-wire [ 31: 0] E_arith_src1;
-wire [ 31: 0] E_arith_src2;
-wire E_ci_multi_stall;
-wire [ 31: 0] E_ci_result;
-wire E_cmp_result;
-wire [ 31: 0] E_control_rd_data;
-wire E_eq;
-reg E_invert_arith_src_msb;
-wire E_ld_stall;
-wire [ 31: 0] E_logic_result;
-wire E_logic_result_is_0;
-wire E_lt;
-wire [ 17: 0] E_mem_baddr;
-wire [ 3: 0] E_mem_byte_en;
-reg E_new_inst;
-wire E_rf_ecc_recoverable_valid;
-wire E_rf_ecc_unrecoverable_valid;
-wire E_rf_ecc_valid_any;
-reg [ 4: 0] E_shift_rot_cnt;
-wire [ 4: 0] E_shift_rot_cnt_nxt;
-wire E_shift_rot_done;
-wire E_shift_rot_fill_bit;
-reg [ 31: 0] E_shift_rot_result;
-wire [ 31: 0] E_shift_rot_result_nxt;
-wire [ 4: 0] E_shift_rot_shfcnt;
-wire E_shift_rot_stall;
-reg [ 31: 0] E_src1;
-reg [ 31: 0] E_src2;
-wire [ 31: 0] E_st_data;
-wire E_st_stall;
-wire E_stall;
-wire E_valid;
-reg E_valid_from_R;
-wire [ 71: 0] E_vinst;
-wire E_wrctl_bstatus;
-wire E_wrctl_estatus;
-wire E_wrctl_ienable;
-wire E_wrctl_status;
-wire [ 31: 0] F_av_iw;
-wire [ 4: 0] F_av_iw_a;
-wire [ 4: 0] F_av_iw_b;
-wire [ 4: 0] F_av_iw_c;
-wire [ 4: 0] F_av_iw_control_regnum;
-wire [ 7: 0] F_av_iw_custom_n;
-wire F_av_iw_custom_readra;
-wire F_av_iw_custom_readrb;
-wire F_av_iw_custom_writerc;
-wire [ 15: 0] F_av_iw_imm16;
-wire [ 25: 0] F_av_iw_imm26;
-wire [ 4: 0] F_av_iw_imm5;
-wire [ 1: 0] F_av_iw_memsz;
-wire [ 5: 0] F_av_iw_op;
-wire [ 5: 0] F_av_iw_opx;
-wire F_av_mem16;
-wire F_av_mem32;
-wire F_av_mem8;
-wire [ 55: 0] F_inst;
-wire F_is_opx_inst;
-wire [ 31: 0] F_iw;
-wire [ 4: 0] F_iw_a;
-wire [ 4: 0] F_iw_b;
-wire [ 4: 0] F_iw_c;
-wire [ 4: 0] F_iw_control_regnum;
-wire [ 7: 0] F_iw_custom_n;
-wire F_iw_custom_readra;
-wire F_iw_custom_readrb;
-wire F_iw_custom_writerc;
-wire [ 15: 0] F_iw_imm16;
-wire [ 25: 0] F_iw_imm26;
-wire [ 4: 0] F_iw_imm5;
-wire [ 1: 0] F_iw_memsz;
-wire [ 5: 0] F_iw_op;
-wire [ 5: 0] F_iw_opx;
-wire F_mem16;
-wire F_mem32;
-wire F_mem8;
-wire F_op_add;
-wire F_op_addi;
-wire F_op_and;
-wire F_op_andhi;
-wire F_op_andi;
-wire F_op_beq;
-wire F_op_bge;
-wire F_op_bgeu;
-wire F_op_blt;
-wire F_op_bltu;
-wire F_op_bne;
-wire F_op_br;
-wire F_op_break;
-wire F_op_bret;
-wire F_op_call;
-wire F_op_callr;
-wire F_op_cmpeq;
-wire F_op_cmpeqi;
-wire F_op_cmpge;
-wire F_op_cmpgei;
-wire F_op_cmpgeu;
-wire F_op_cmpgeui;
-wire F_op_cmplt;
-wire F_op_cmplti;
-wire F_op_cmpltu;
-wire F_op_cmpltui;
-wire F_op_cmpne;
-wire F_op_cmpnei;
-wire F_op_crst;
-wire F_op_custom;
-wire F_op_div;
-wire F_op_divu;
-wire F_op_eret;
-wire F_op_flushd;
-wire F_op_flushda;
-wire F_op_flushi;
-wire F_op_flushp;
-wire F_op_hbreak;
-wire F_op_initd;
-wire F_op_initda;
-wire F_op_initi;
-wire F_op_intr;
-wire F_op_jmp;
-wire F_op_jmpi;
-wire F_op_ldb;
-wire F_op_ldbio;
-wire F_op_ldbu;
-wire F_op_ldbuio;
-wire F_op_ldh;
-wire F_op_ldhio;
-wire F_op_ldhu;
-wire F_op_ldhuio;
-wire F_op_ldl;
-wire F_op_ldw;
-wire F_op_ldwio;
-wire F_op_mul;
-wire F_op_muli;
-wire F_op_mulxss;
-wire F_op_mulxsu;
-wire F_op_mulxuu;
-wire F_op_nextpc;
-wire F_op_nor;
-wire F_op_op_rsv02;
-wire F_op_op_rsv09;
-wire F_op_op_rsv10;
-wire F_op_op_rsv17;
-wire F_op_op_rsv18;
-wire F_op_op_rsv25;
-wire F_op_op_rsv26;
-wire F_op_op_rsv33;
-wire F_op_op_rsv34;
-wire F_op_op_rsv41;
-wire F_op_op_rsv42;
-wire F_op_op_rsv49;
-wire F_op_op_rsv57;
-wire F_op_op_rsv61;
-wire F_op_op_rsv62;
-wire F_op_op_rsv63;
-wire F_op_opx_rsv00;
-wire F_op_opx_rsv10;
-wire F_op_opx_rsv15;
-wire F_op_opx_rsv17;
-wire F_op_opx_rsv21;
-wire F_op_opx_rsv25;
-wire F_op_opx_rsv33;
-wire F_op_opx_rsv34;
-wire F_op_opx_rsv35;
-wire F_op_opx_rsv42;
-wire F_op_opx_rsv43;
-wire F_op_opx_rsv44;
-wire F_op_opx_rsv47;
-wire F_op_opx_rsv50;
-wire F_op_opx_rsv51;
-wire F_op_opx_rsv55;
-wire F_op_opx_rsv56;
-wire F_op_opx_rsv60;
-wire F_op_opx_rsv63;
-wire F_op_or;
-wire F_op_orhi;
-wire F_op_ori;
-wire F_op_rdctl;
-wire F_op_rdprs;
-wire F_op_ret;
-wire F_op_rol;
-wire F_op_roli;
-wire F_op_ror;
-wire F_op_sll;
-wire F_op_slli;
-wire F_op_sra;
-wire F_op_srai;
-wire F_op_srl;
-wire F_op_srli;
-wire F_op_stb;
-wire F_op_stbio;
-wire F_op_stc;
-wire F_op_sth;
-wire F_op_sthio;
-wire F_op_stw;
-wire F_op_stwio;
-wire F_op_sub;
-wire F_op_sync;
-wire F_op_trap;
-wire F_op_wrctl;
-wire F_op_wrprs;
-wire F_op_xor;
-wire F_op_xorhi;
-wire F_op_xori;
-reg [ 15: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
-wire F_pc_en;
-wire [ 15: 0] F_pc_no_crst_nxt;
-wire [ 15: 0] F_pc_nxt;
-wire [ 15: 0] F_pc_plus_one;
-wire [ 1: 0] F_pc_sel_nxt;
-wire [ 17: 0] F_pcb;
-wire [ 17: 0] F_pcb_nxt;
-wire [ 17: 0] F_pcb_plus_four;
-wire F_valid;
-wire [ 71: 0] F_vinst;
-reg [ 1: 0] R_compare_op;
-reg R_ctrl_alu_force_and;
-wire R_ctrl_alu_force_and_nxt;
-reg R_ctrl_alu_force_xor;
-wire R_ctrl_alu_force_xor_nxt;
-reg R_ctrl_alu_signed_comparison;
-wire R_ctrl_alu_signed_comparison_nxt;
-reg R_ctrl_alu_subtract;
-wire R_ctrl_alu_subtract_nxt;
-reg R_ctrl_b_is_dst;
-wire R_ctrl_b_is_dst_nxt;
-reg R_ctrl_br;
-reg R_ctrl_br_cmp;
-wire R_ctrl_br_cmp_nxt;
-wire R_ctrl_br_nxt;
-reg R_ctrl_br_uncond;
-wire R_ctrl_br_uncond_nxt;
-reg R_ctrl_break;
-wire R_ctrl_break_nxt;
-reg R_ctrl_crst;
-wire R_ctrl_crst_nxt;
-reg R_ctrl_custom;
-reg R_ctrl_custom_multi;
-wire R_ctrl_custom_multi_nxt;
-wire R_ctrl_custom_nxt;
-reg R_ctrl_exception;
-wire R_ctrl_exception_nxt;
-reg R_ctrl_force_src2_zero;
-wire R_ctrl_force_src2_zero_nxt;
-reg R_ctrl_hi_imm16;
-wire R_ctrl_hi_imm16_nxt;
-reg R_ctrl_ignore_dst;
-wire R_ctrl_ignore_dst_nxt;
-reg R_ctrl_implicit_dst_eretaddr;
-wire R_ctrl_implicit_dst_eretaddr_nxt;
-reg R_ctrl_implicit_dst_retaddr;
-wire R_ctrl_implicit_dst_retaddr_nxt;
-reg R_ctrl_intr_inst;
-wire R_ctrl_intr_inst_nxt;
-reg R_ctrl_jmp_direct;
-wire R_ctrl_jmp_direct_nxt;
-reg R_ctrl_jmp_indirect;
-wire R_ctrl_jmp_indirect_nxt;
-reg R_ctrl_ld;
-reg R_ctrl_ld_ex;
-wire R_ctrl_ld_ex_nxt;
-reg R_ctrl_ld_io;
-wire R_ctrl_ld_io_nxt;
-reg R_ctrl_ld_non_io;
-wire R_ctrl_ld_non_io_nxt;
-wire R_ctrl_ld_nxt;
-reg R_ctrl_ld_signed;
-wire R_ctrl_ld_signed_nxt;
-reg R_ctrl_ld_st_ex;
-wire R_ctrl_ld_st_ex_nxt;
-reg R_ctrl_logic;
-wire R_ctrl_logic_nxt;
-reg R_ctrl_mem16;
-wire R_ctrl_mem16_nxt;
-reg R_ctrl_mem32;
-wire R_ctrl_mem32_nxt;
-reg R_ctrl_mem8;
-wire R_ctrl_mem8_nxt;
-reg R_ctrl_rd_ctl_reg;
-wire R_ctrl_rd_ctl_reg_nxt;
-reg R_ctrl_retaddr;
-wire R_ctrl_retaddr_nxt;
-reg R_ctrl_rot_right;
-wire R_ctrl_rot_right_nxt;
-reg R_ctrl_set_src2_rem_imm;
-wire R_ctrl_set_src2_rem_imm_nxt;
-reg R_ctrl_shift_logical;
-wire R_ctrl_shift_logical_nxt;
-reg R_ctrl_shift_right_arith;
-wire R_ctrl_shift_right_arith_nxt;
-reg R_ctrl_shift_rot;
-wire R_ctrl_shift_rot_nxt;
-reg R_ctrl_shift_rot_right;
-wire R_ctrl_shift_rot_right_nxt;
-reg R_ctrl_signed_imm12;
-wire R_ctrl_signed_imm12_nxt;
-reg R_ctrl_src2_choose_imm;
-wire R_ctrl_src2_choose_imm_nxt;
-reg R_ctrl_src_imm5_shift_rot;
-wire R_ctrl_src_imm5_shift_rot_nxt;
-reg R_ctrl_st;
-reg R_ctrl_st_ex;
-wire R_ctrl_st_ex_nxt;
-wire R_ctrl_st_nxt;
-reg R_ctrl_uncond_cti_non_br;
-wire R_ctrl_uncond_cti_non_br_nxt;
-reg R_ctrl_unsigned_lo_imm16;
-wire R_ctrl_unsigned_lo_imm16_nxt;
-reg R_ctrl_wrctl_inst;
-wire R_ctrl_wrctl_inst_nxt;
-reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
-wire R_en;
-reg [ 1: 0] R_logic_op;
-wire [ 31: 0] R_rf_a;
-wire [ 31: 0] R_rf_a_q;
-wire [ 31: 0] R_rf_b;
-wire [ 31: 0] R_rf_b_q;
-wire [ 31: 0] R_src1;
-wire [ 31: 0] R_src2;
-wire [ 15: 0] R_src2_hi;
-wire [ 15: 0] R_src2_lo;
-reg R_src2_use_imm;
-wire [ 7: 0] R_stb_data;
-wire [ 15: 0] R_sth_data;
-wire [ 31: 0] R_stw_data;
-reg R_valid;
-wire [ 71: 0] R_vinst;
-reg R_wr_dst_reg;
-reg W1_rf_ecc_recoverable_valid;
-reg [ 31: 0] W_alu_result;
-wire W_br_taken;
-reg W_bstatus_reg;
-wire W_bstatus_reg_inst_nxt;
-wire W_bstatus_reg_nxt;
-reg [ 31: 0] W_cdsr_reg;
-reg W_cmp_result;
-reg [ 31: 0] W_control_rd_data;
-wire [ 31: 0] W_cpuid_reg;
-wire [ 4: 0] W_dst_regnum;
-reg W_estatus_reg;
-wire W_estatus_reg_inst_nxt;
-wire W_estatus_reg_nxt;
-reg [ 31: 0] W_ienable_reg;
-wire [ 31: 0] W_ienable_reg_nxt;
-reg [ 31: 0] W_ipending_reg;
-wire [ 31: 0] W_ipending_reg_nxt;
-wire [ 17: 0] W_mem_baddr;
-reg W_rf_ecc_recoverable_valid;
-reg W_rf_ecc_unrecoverable_valid;
-wire W_rf_ecc_valid_any;
-wire [ 31: 0] W_rf_wr_data;
-wire W_rf_wren;
-wire W_status_reg;
-reg W_status_reg_pie;
-wire W_status_reg_pie_inst_nxt;
-wire W_status_reg_pie_nxt;
-reg W_up_ex_mon_state;
-reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
-wire W_valid_from_M;
-wire [ 71: 0] W_vinst;
-wire [ 31: 0] W_wr_data;
-wire [ 31: 0] W_wr_data_non_zero;
-wire av_fill_bit;
-reg [ 1: 0] av_ld_align_cycle;
-wire [ 1: 0] av_ld_align_cycle_nxt;
-wire av_ld_align_one_more_cycle;
-reg av_ld_aligning_data;
-wire av_ld_aligning_data_nxt;
-reg [ 7: 0] av_ld_byte0_data;
-wire [ 7: 0] av_ld_byte0_data_nxt;
-reg [ 7: 0] av_ld_byte1_data;
-wire av_ld_byte1_data_en;
-wire [ 7: 0] av_ld_byte1_data_nxt;
-reg [ 7: 0] av_ld_byte2_data;
-wire [ 7: 0] av_ld_byte2_data_nxt;
-reg [ 7: 0] av_ld_byte3_data;
-wire [ 7: 0] av_ld_byte3_data_nxt;
-wire [ 31: 0] av_ld_data_aligned_filtered;
-wire [ 31: 0] av_ld_data_aligned_unfiltered;
-wire av_ld_done;
-wire av_ld_extend;
-wire av_ld_getting_data;
-wire av_ld_rshift8;
-reg av_ld_waiting_for_data;
-wire av_ld_waiting_for_data_nxt;
-wire av_sign_bit;
-wire [ 17: 0] d_address;
-reg [ 3: 0] d_byteenable;
-reg d_read;
-wire d_read_nxt;
-reg d_write;
-wire d_write_nxt;
-reg [ 31: 0] d_writedata;
-wire debug_mem_slave_clk;
-wire debug_mem_slave_debugaccess_to_roms;
-wire [ 31: 0] debug_mem_slave_readdata;
-wire debug_mem_slave_reset;
-wire debug_mem_slave_waitrequest;
-wire debug_reset_request;
-wire dummy_ci_port;
-reg hbreak_enabled;
-reg hbreak_pending;
-wire hbreak_pending_nxt;
-wire hbreak_req;
-wire [ 17: 0] i_address;
-reg i_read;
-wire i_read_nxt;
-wire [ 31: 0] iactive;
-wire intr_req;
-wire oci_hbreak_req;
-wire [ 31: 0] oci_ienable;
-wire oci_single_step_mode;
-wire oci_tb_hbreak_req;
-wire test_has_ended;
-reg wait_for_one_post_bret_inst;
- //the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench, which is an e_instance
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench
- (
- .D_iw (D_iw),
- .D_iw_op (D_iw_op),
- .D_iw_opx (D_iw_opx),
- .D_valid (D_valid),
- .E_valid (E_valid),
- .F_pcb (F_pcb),
- .F_valid (F_valid),
- .R_ctrl_ld (R_ctrl_ld),
- .R_ctrl_ld_non_io (R_ctrl_ld_non_io),
- .R_dst_regnum (R_dst_regnum),
- .R_wr_dst_reg (R_wr_dst_reg),
- .W_valid (W_valid),
- .W_vinst (W_vinst),
- .W_wr_data (W_wr_data),
- .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
- .av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
- .clk (clk),
- .d_address (d_address),
- .d_byteenable (d_byteenable),
- .d_read (d_read),
- .d_write (d_write),
- .i_address (i_address),
- .i_read (i_read),
- .i_readdata (i_readdata),
- .i_waitrequest (i_waitrequest),
- .reset_n (reset_n),
- .test_has_ended (test_has_ended)
- );
-
- assign F_av_iw_a = F_av_iw[31 : 27];
- assign F_av_iw_b = F_av_iw[26 : 22];
- assign F_av_iw_c = F_av_iw[21 : 17];
- assign F_av_iw_custom_n = F_av_iw[13 : 6];
- assign F_av_iw_custom_readra = F_av_iw[16];
- assign F_av_iw_custom_readrb = F_av_iw[15];
- assign F_av_iw_custom_writerc = F_av_iw[14];
- assign F_av_iw_opx = F_av_iw[16 : 11];
- assign F_av_iw_op = F_av_iw[5 : 0];
- assign F_av_iw_imm5 = F_av_iw[10 : 6];
- assign F_av_iw_imm16 = F_av_iw[21 : 6];
- assign F_av_iw_imm26 = F_av_iw[31 : 6];
- assign F_av_iw_memsz = F_av_iw[4 : 3];
- assign F_av_iw_control_regnum = F_av_iw[10 : 6];
- assign F_av_mem8 = F_av_iw_memsz == 2'b00;
- assign F_av_mem16 = F_av_iw_memsz == 2'b01;
- assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
- assign F_iw_a = F_iw[31 : 27];
- assign F_iw_b = F_iw[26 : 22];
- assign F_iw_c = F_iw[21 : 17];
- assign F_iw_custom_n = F_iw[13 : 6];
- assign F_iw_custom_readra = F_iw[16];
- assign F_iw_custom_readrb = F_iw[15];
- assign F_iw_custom_writerc = F_iw[14];
- assign F_iw_opx = F_iw[16 : 11];
- assign F_iw_op = F_iw[5 : 0];
- assign F_iw_imm5 = F_iw[10 : 6];
- assign F_iw_imm16 = F_iw[21 : 6];
- assign F_iw_imm26 = F_iw[31 : 6];
- assign F_iw_memsz = F_iw[4 : 3];
- assign F_iw_control_regnum = F_iw[10 : 6];
- assign F_mem8 = F_iw_memsz == 2'b00;
- assign F_mem16 = F_iw_memsz == 2'b01;
- assign F_mem32 = F_iw_memsz[1] == 1'b1;
- assign D_iw_a = D_iw[31 : 27];
- assign D_iw_b = D_iw[26 : 22];
- assign D_iw_c = D_iw[21 : 17];
- assign D_iw_custom_n = D_iw[13 : 6];
- assign D_iw_custom_readra = D_iw[16];
- assign D_iw_custom_readrb = D_iw[15];
- assign D_iw_custom_writerc = D_iw[14];
- assign D_iw_opx = D_iw[16 : 11];
- assign D_iw_op = D_iw[5 : 0];
- assign D_iw_imm5 = D_iw[10 : 6];
- assign D_iw_imm16 = D_iw[21 : 6];
- assign D_iw_imm26 = D_iw[31 : 6];
- assign D_iw_memsz = D_iw[4 : 3];
- assign D_iw_control_regnum = D_iw[10 : 6];
- assign D_mem8 = D_iw_memsz == 2'b00;
- assign D_mem16 = D_iw_memsz == 2'b01;
- assign D_mem32 = D_iw_memsz[1] == 1'b1;
- assign F_op_call = F_iw_op == 0;
- assign F_op_jmpi = F_iw_op == 1;
- assign F_op_op_rsv02 = F_iw_op == 2;
- assign F_op_ldbu = F_iw_op == 3;
- assign F_op_addi = F_iw_op == 4;
- assign F_op_stb = F_iw_op == 5;
- assign F_op_br = F_iw_op == 6;
- assign F_op_ldb = F_iw_op == 7;
- assign F_op_cmpgei = F_iw_op == 8;
- assign F_op_op_rsv09 = F_iw_op == 9;
- assign F_op_op_rsv10 = F_iw_op == 10;
- assign F_op_ldhu = F_iw_op == 11;
- assign F_op_andi = F_iw_op == 12;
- assign F_op_sth = F_iw_op == 13;
- assign F_op_bge = F_iw_op == 14;
- assign F_op_ldh = F_iw_op == 15;
- assign F_op_cmplti = F_iw_op == 16;
- assign F_op_op_rsv17 = F_iw_op == 17;
- assign F_op_op_rsv18 = F_iw_op == 18;
- assign F_op_initda = F_iw_op == 19;
- assign F_op_ori = F_iw_op == 20;
- assign F_op_stw = F_iw_op == 21;
- assign F_op_blt = F_iw_op == 22;
- assign F_op_ldw = F_iw_op == 23;
- assign F_op_cmpnei = F_iw_op == 24;
- assign F_op_op_rsv25 = F_iw_op == 25;
- assign F_op_op_rsv26 = F_iw_op == 26;
- assign F_op_flushda = F_iw_op == 27;
- assign F_op_xori = F_iw_op == 28;
- assign F_op_stc = F_iw_op == 29;
- assign F_op_bne = F_iw_op == 30;
- assign F_op_ldl = F_iw_op == 31;
- assign F_op_cmpeqi = F_iw_op == 32;
- assign F_op_op_rsv33 = F_iw_op == 33;
- assign F_op_op_rsv34 = F_iw_op == 34;
- assign F_op_ldbuio = F_iw_op == 35;
- assign F_op_muli = F_iw_op == 36;
- assign F_op_stbio = F_iw_op == 37;
- assign F_op_beq = F_iw_op == 38;
- assign F_op_ldbio = F_iw_op == 39;
- assign F_op_cmpgeui = F_iw_op == 40;
- assign F_op_op_rsv41 = F_iw_op == 41;
- assign F_op_op_rsv42 = F_iw_op == 42;
- assign F_op_ldhuio = F_iw_op == 43;
- assign F_op_andhi = F_iw_op == 44;
- assign F_op_sthio = F_iw_op == 45;
- assign F_op_bgeu = F_iw_op == 46;
- assign F_op_ldhio = F_iw_op == 47;
- assign F_op_cmpltui = F_iw_op == 48;
- assign F_op_op_rsv49 = F_iw_op == 49;
- assign F_op_custom = F_iw_op == 50;
- assign F_op_initd = F_iw_op == 51;
- assign F_op_orhi = F_iw_op == 52;
- assign F_op_stwio = F_iw_op == 53;
- assign F_op_bltu = F_iw_op == 54;
- assign F_op_ldwio = F_iw_op == 55;
- assign F_op_rdprs = F_iw_op == 56;
- assign F_op_op_rsv57 = F_iw_op == 57;
- assign F_op_flushd = F_iw_op == 59;
- assign F_op_xorhi = F_iw_op == 60;
- assign F_op_op_rsv61 = F_iw_op == 61;
- assign F_op_op_rsv62 = F_iw_op == 62;
- assign F_op_op_rsv63 = F_iw_op == 63;
- assign F_op_opx_rsv00 = (F_iw_opx == 0) & F_is_opx_inst;
- assign F_op_eret = (F_iw_opx == 1) & F_is_opx_inst;
- assign F_op_roli = (F_iw_opx == 2) & F_is_opx_inst;
- assign F_op_rol = (F_iw_opx == 3) & F_is_opx_inst;
- assign F_op_flushp = (F_iw_opx == 4) & F_is_opx_inst;
- assign F_op_ret = (F_iw_opx == 5) & F_is_opx_inst;
- assign F_op_nor = (F_iw_opx == 6) & F_is_opx_inst;
- assign F_op_mulxuu = (F_iw_opx == 7) & F_is_opx_inst;
- assign F_op_cmpge = (F_iw_opx == 8) & F_is_opx_inst;
- assign F_op_bret = (F_iw_opx == 9) & F_is_opx_inst;
- assign F_op_opx_rsv10 = (F_iw_opx == 10) & F_is_opx_inst;
- assign F_op_ror = (F_iw_opx == 11) & F_is_opx_inst;
- assign F_op_flushi = (F_iw_opx == 12) & F_is_opx_inst;
- assign F_op_jmp = (F_iw_opx == 13) & F_is_opx_inst;
- assign F_op_and = (F_iw_opx == 14) & F_is_opx_inst;
- assign F_op_opx_rsv15 = (F_iw_opx == 15) & F_is_opx_inst;
- assign F_op_cmplt = (F_iw_opx == 16) & F_is_opx_inst;
- assign F_op_opx_rsv17 = (F_iw_opx == 17) & F_is_opx_inst;
- assign F_op_slli = (F_iw_opx == 18) & F_is_opx_inst;
- assign F_op_sll = (F_iw_opx == 19) & F_is_opx_inst;
- assign F_op_wrprs = (F_iw_opx == 20) & F_is_opx_inst;
- assign F_op_opx_rsv21 = (F_iw_opx == 21) & F_is_opx_inst;
- assign F_op_or = (F_iw_opx == 22) & F_is_opx_inst;
- assign F_op_mulxsu = (F_iw_opx == 23) & F_is_opx_inst;
- assign F_op_cmpne = (F_iw_opx == 24) & F_is_opx_inst;
- assign F_op_opx_rsv25 = (F_iw_opx == 25) & F_is_opx_inst;
- assign F_op_srli = (F_iw_opx == 26) & F_is_opx_inst;
- assign F_op_srl = (F_iw_opx == 27) & F_is_opx_inst;
- assign F_op_nextpc = (F_iw_opx == 28) & F_is_opx_inst;
- assign F_op_callr = (F_iw_opx == 29) & F_is_opx_inst;
- assign F_op_xor = (F_iw_opx == 30) & F_is_opx_inst;
- assign F_op_mulxss = (F_iw_opx == 31) & F_is_opx_inst;
- assign F_op_cmpeq = (F_iw_opx == 32) & F_is_opx_inst;
- assign F_op_opx_rsv33 = (F_iw_opx == 33) & F_is_opx_inst;
- assign F_op_opx_rsv34 = (F_iw_opx == 34) & F_is_opx_inst;
- assign F_op_opx_rsv35 = (F_iw_opx == 35) & F_is_opx_inst;
- assign F_op_divu = (F_iw_opx == 36) & F_is_opx_inst;
- assign F_op_div = (F_iw_opx == 37) & F_is_opx_inst;
- assign F_op_rdctl = (F_iw_opx == 38) & F_is_opx_inst;
- assign F_op_mul = (F_iw_opx == 39) & F_is_opx_inst;
- assign F_op_cmpgeu = (F_iw_opx == 40) & F_is_opx_inst;
- assign F_op_initi = (F_iw_opx == 41) & F_is_opx_inst;
- assign F_op_opx_rsv42 = (F_iw_opx == 42) & F_is_opx_inst;
- assign F_op_opx_rsv43 = (F_iw_opx == 43) & F_is_opx_inst;
- assign F_op_opx_rsv44 = (F_iw_opx == 44) & F_is_opx_inst;
- assign F_op_trap = (F_iw_opx == 45) & F_is_opx_inst;
- assign F_op_wrctl = (F_iw_opx == 46) & F_is_opx_inst;
- assign F_op_opx_rsv47 = (F_iw_opx == 47) & F_is_opx_inst;
- assign F_op_cmpltu = (F_iw_opx == 48) & F_is_opx_inst;
- assign F_op_add = (F_iw_opx == 49) & F_is_opx_inst;
- assign F_op_opx_rsv50 = (F_iw_opx == 50) & F_is_opx_inst;
- assign F_op_opx_rsv51 = (F_iw_opx == 51) & F_is_opx_inst;
- assign F_op_break = (F_iw_opx == 52) & F_is_opx_inst;
- assign F_op_hbreak = (F_iw_opx == 53) & F_is_opx_inst;
- assign F_op_sync = (F_iw_opx == 54) & F_is_opx_inst;
- assign F_op_opx_rsv55 = (F_iw_opx == 55) & F_is_opx_inst;
- assign F_op_opx_rsv56 = (F_iw_opx == 56) & F_is_opx_inst;
- assign F_op_sub = (F_iw_opx == 57) & F_is_opx_inst;
- assign F_op_srai = (F_iw_opx == 58) & F_is_opx_inst;
- assign F_op_sra = (F_iw_opx == 59) & F_is_opx_inst;
- assign F_op_opx_rsv60 = (F_iw_opx == 60) & F_is_opx_inst;
- assign F_op_intr = (F_iw_opx == 61) & F_is_opx_inst;
- assign F_op_crst = (F_iw_opx == 62) & F_is_opx_inst;
- assign F_op_opx_rsv63 = (F_iw_opx == 63) & F_is_opx_inst;
- assign F_is_opx_inst = F_iw_op == 58;
- assign D_op_call = D_iw_op == 0;
- assign D_op_jmpi = D_iw_op == 1;
- assign D_op_op_rsv02 = D_iw_op == 2;
- assign D_op_ldbu = D_iw_op == 3;
- assign D_op_addi = D_iw_op == 4;
- assign D_op_stb = D_iw_op == 5;
- assign D_op_br = D_iw_op == 6;
- assign D_op_ldb = D_iw_op == 7;
- assign D_op_cmpgei = D_iw_op == 8;
- assign D_op_op_rsv09 = D_iw_op == 9;
- assign D_op_op_rsv10 = D_iw_op == 10;
- assign D_op_ldhu = D_iw_op == 11;
- assign D_op_andi = D_iw_op == 12;
- assign D_op_sth = D_iw_op == 13;
- assign D_op_bge = D_iw_op == 14;
- assign D_op_ldh = D_iw_op == 15;
- assign D_op_cmplti = D_iw_op == 16;
- assign D_op_op_rsv17 = D_iw_op == 17;
- assign D_op_op_rsv18 = D_iw_op == 18;
- assign D_op_initda = D_iw_op == 19;
- assign D_op_ori = D_iw_op == 20;
- assign D_op_stw = D_iw_op == 21;
- assign D_op_blt = D_iw_op == 22;
- assign D_op_ldw = D_iw_op == 23;
- assign D_op_cmpnei = D_iw_op == 24;
- assign D_op_op_rsv25 = D_iw_op == 25;
- assign D_op_op_rsv26 = D_iw_op == 26;
- assign D_op_flushda = D_iw_op == 27;
- assign D_op_xori = D_iw_op == 28;
- assign D_op_stc = D_iw_op == 29;
- assign D_op_bne = D_iw_op == 30;
- assign D_op_ldl = D_iw_op == 31;
- assign D_op_cmpeqi = D_iw_op == 32;
- assign D_op_op_rsv33 = D_iw_op == 33;
- assign D_op_op_rsv34 = D_iw_op == 34;
- assign D_op_ldbuio = D_iw_op == 35;
- assign D_op_muli = D_iw_op == 36;
- assign D_op_stbio = D_iw_op == 37;
- assign D_op_beq = D_iw_op == 38;
- assign D_op_ldbio = D_iw_op == 39;
- assign D_op_cmpgeui = D_iw_op == 40;
- assign D_op_op_rsv41 = D_iw_op == 41;
- assign D_op_op_rsv42 = D_iw_op == 42;
- assign D_op_ldhuio = D_iw_op == 43;
- assign D_op_andhi = D_iw_op == 44;
- assign D_op_sthio = D_iw_op == 45;
- assign D_op_bgeu = D_iw_op == 46;
- assign D_op_ldhio = D_iw_op == 47;
- assign D_op_cmpltui = D_iw_op == 48;
- assign D_op_op_rsv49 = D_iw_op == 49;
- assign D_op_custom = D_iw_op == 50;
- assign D_op_initd = D_iw_op == 51;
- assign D_op_orhi = D_iw_op == 52;
- assign D_op_stwio = D_iw_op == 53;
- assign D_op_bltu = D_iw_op == 54;
- assign D_op_ldwio = D_iw_op == 55;
- assign D_op_rdprs = D_iw_op == 56;
- assign D_op_op_rsv57 = D_iw_op == 57;
- assign D_op_flushd = D_iw_op == 59;
- assign D_op_xorhi = D_iw_op == 60;
- assign D_op_op_rsv61 = D_iw_op == 61;
- assign D_op_op_rsv62 = D_iw_op == 62;
- assign D_op_op_rsv63 = D_iw_op == 63;
- assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
- assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
- assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
- assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
- assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
- assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
- assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
- assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
- assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
- assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
- assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
- assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
- assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
- assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
- assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
- assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
- assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
- assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
- assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
- assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
- assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
- assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
- assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
- assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
- assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
- assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
- assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
- assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
- assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
- assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
- assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
- assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
- assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
- assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
- assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
- assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
- assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
- assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
- assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
- assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
- assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
- assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
- assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
- assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
- assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
- assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
- assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
- assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
- assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
- assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
- assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
- assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
- assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
- assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
- assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
- assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
- assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
- assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
- assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
- assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
- assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
- assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
- assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
- assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
- assign D_is_opx_inst = D_iw_op == 58;
- assign R_en = 1'b1;
- assign E_ci_result = 0;
- //custom_instruction_master, which is an e_custom_instruction_master
- assign dummy_ci_port = 1'b0;
- assign E_ci_multi_stall = 1'b0;
- assign iactive = irq[31 : 0] & 32'b00000000000000000000000000001111;
- assign F_pc_sel_nxt = (R_ctrl_exception | W_rf_ecc_unrecoverable_valid) ? 2'b00 :
- R_ctrl_break ? 2'b01 :
- (W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
- 2'b11;
-
- assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 32776 :
- (F_pc_sel_nxt == 2'b01)? 1544 :
- (F_pc_sel_nxt == 2'b10)? E_arith_result[17 : 2] :
- F_pc_plus_one;
-
- assign F_pc_nxt = F_pc_no_crst_nxt;
- assign F_pcb_nxt = {F_pc_nxt, 2'b00};
- assign F_pc_en = W_valid | W_rf_ecc_unrecoverable_valid;
- assign F_pc_plus_one = F_pc + 1;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- F_pc <= 32768;
- else if (F_pc_en)
- F_pc <= F_pc_nxt;
- end
-
-
- assign F_pcb = {F_pc, 2'b00};
- assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
- assign F_valid = i_read & ~i_waitrequest;
- assign i_read_nxt = W_valid | W_rf_ecc_unrecoverable_valid | (i_read & i_waitrequest);
- assign i_address = {F_pc, 2'b00};
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- i_read <= 1'b1;
- else
- i_read <= i_read_nxt;
- end
-
-
- assign oci_tb_hbreak_req = oci_hbreak_req;
- assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
- assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
- : hbreak_req;
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- wait_for_one_post_bret_inst <= 1'b0;
- else
- wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- hbreak_pending <= 1'b0;
- else
- hbreak_pending <= hbreak_pending_nxt;
- end
-
-
- assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
- assign F_av_iw = i_readdata;
- assign F_iw = hbreak_req ? 4040762 :
- 1'b0 ? 127034 :
- intr_req ? 3926074 :
- F_av_iw;
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- D_iw <= 0;
- else if (F_valid)
- D_iw <= F_iw;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- D_valid <= 0;
- else
- D_valid <= F_valid | W1_rf_ecc_recoverable_valid;
- end
-
-
- assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
- D_ctrl_implicit_dst_eretaddr ? 5'd29 :
- D_ctrl_b_is_dst ? D_iw_b :
- D_iw_c;
-
- assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
- assign D_logic_op_raw = D_is_opx_inst ? D_iw_opx[4 : 3] :
- D_iw_op[4 : 3];
-
- assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 :
- D_ctrl_alu_force_and ? 2'b01 :
- D_logic_op_raw;
-
- assign D_compare_op = D_is_opx_inst ? D_iw_opx[4 : 3] :
- D_iw_op[4 : 3];
-
- assign D_jmp_direct_target_waddr = D_iw[31 : 6];
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_valid <= 0;
- else
- R_valid <= D_valid;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_wr_dst_reg <= 0;
- else
- R_wr_dst_reg <= D_wr_dst_reg;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_dst_regnum <= 0;
- else
- R_dst_regnum <= D_dst_regnum;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_logic_op <= 0;
- else
- R_logic_op <= D_logic_op;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_compare_op <= 0;
- else
- R_compare_op <= D_compare_op;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_src2_use_imm <= 0;
- else
- R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
- end
-
-
- assign E_rf_ecc_valid_any = E_rf_ecc_recoverable_valid|E_rf_ecc_unrecoverable_valid;
- assign W_rf_ecc_valid_any = W_rf_ecc_recoverable_valid|W_rf_ecc_unrecoverable_valid;
- assign E_rf_ecc_recoverable_valid = 1'b0;
- assign E_rf_ecc_unrecoverable_valid = 1'b0;
- assign W_dst_regnum = R_dst_regnum;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_rf_ecc_recoverable_valid <= 0;
- else
- W_rf_ecc_recoverable_valid <= E_rf_ecc_recoverable_valid;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W1_rf_ecc_recoverable_valid <= 0;
- else
- W1_rf_ecc_recoverable_valid <= W_rf_ecc_recoverable_valid;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_rf_ecc_unrecoverable_valid <= 0;
- else
- W_rf_ecc_unrecoverable_valid <= E_rf_ecc_unrecoverable_valid & ~E_rf_ecc_recoverable_valid;
- end
-
-
- assign R_rf_a = R_rf_a_q;
- assign R_rf_b = R_rf_b_q;
- assign W_rf_wren = (R_wr_dst_reg & W_valid) | W_rf_ecc_valid_any | ~reset_n;
- assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
-//qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_a, which is an nios_sdp_ram
-qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_a_module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_a
- (
- .clock (clk),
- .data (W_rf_wr_data),
- .q (R_rf_a_q),
- .rdaddress (D_iw_a),
- .wraddress (W_dst_regnum),
- .wren (W_rf_wren)
- );
-
-//synthesis translate_off
-`ifdef NO_PLI
-defparam qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_a.lpm_file = "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_a.dat";
-`else
-defparam qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_a.lpm_file = "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_a.hex";
-`endif
-//synthesis translate_on
-//qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_b, which is an nios_sdp_ram
-qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_b_module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_b
- (
- .clock (clk),
- .data (W_rf_wr_data),
- .q (R_rf_b_q),
- .rdaddress (D_iw_b),
- .wraddress (W_dst_regnum),
- .wren (W_rf_wren)
- );
-
-//synthesis translate_off
-`ifdef NO_PLI
-defparam qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_b.lpm_file = "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_b.dat";
-`else
-defparam qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_register_bank_b.lpm_file = "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_b.hex";
-`endif
-//synthesis translate_on
- assign R_src1 = (((R_ctrl_br & E_valid_from_R) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
- ((R_ctrl_jmp_direct & E_valid_from_R))? {D_jmp_direct_target_waddr, 2'b00} :
- R_rf_a;
-
- assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
- (R_ctrl_src_imm5_shift_rot)? {{11 {1'b0}},D_iw_imm5} :
- (R_src2_use_imm)? D_iw_imm16 :
- R_rf_b[15 : 0];
-
- assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? {16 {D_ctrl_set_src2_rem_imm}} :
- (R_ctrl_hi_imm16)? D_iw_imm16 :
- (R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
- R_rf_b[31 : 16];
-
- assign R_src2 = {R_src2_hi, R_src2_lo};
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_valid_from_R <= 0;
- else
- E_valid_from_R <= R_valid | E_stall;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_new_inst <= 0;
- else
- E_new_inst <= R_valid;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_src1 <= 0;
- else
- E_src1 <= R_src1;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_src2 <= 0;
- else
- E_src2 <= R_src2;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_invert_arith_src_msb <= 0;
- else
- E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_alu_sub <= 0;
- else
- E_alu_sub <= D_ctrl_alu_subtract & R_valid;
- end
-
-
- assign E_valid = E_valid_from_R & ~E_rf_ecc_valid_any;
- assign E_stall = (E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall) & ~(E_rf_ecc_valid_any|W_rf_ecc_valid_any|W1_rf_ecc_recoverable_valid);
- assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
- E_src1[30 : 0]};
-
- assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
- E_src2[30 : 0]};
-
- assign E_arith_result = E_alu_sub ?
- E_arith_src1 - E_arith_src2 :
- E_arith_src1 + E_arith_src2;
-
- assign E_mem_baddr = E_arith_result[17 : 0];
- assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
- (R_logic_op == 2'b01)? (E_src1 & E_src2) :
- (R_logic_op == 2'b10)? (E_src1 | E_src2) :
- (E_src1 ^ E_src2);
-
- assign E_logic_result_is_0 = E_logic_result == 0;
- assign E_eq = E_logic_result_is_0;
- assign E_lt = E_arith_result[32];
- assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
- (R_compare_op == 2'b01)? ~E_lt :
- (R_compare_op == 2'b10)? E_lt :
- ~E_eq;
-
- assign E_shift_rot_shfcnt = E_src2[4 : 0];
- assign E_shift_rot_cnt_nxt = E_new_inst ? E_shift_rot_shfcnt : E_shift_rot_cnt-1;
- assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
- assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
- assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
- (R_ctrl_rot_right ? E_shift_rot_result[0] :
- E_shift_rot_result[31]);
-
- assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
- (R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
- {E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_shift_rot_result <= 0;
- else
- E_shift_rot_result <= E_shift_rot_result_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- E_shift_rot_cnt <= 0;
- else
- E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
- end
-
-
- assign E_control_rd_data = (D_iw_control_regnum == 5'd0)? W_status_reg :
- (D_iw_control_regnum == 5'd1)? W_estatus_reg :
- (D_iw_control_regnum == 5'd2)? W_bstatus_reg :
- (D_iw_control_regnum == 5'd3)? W_ienable_reg :
- (D_iw_control_regnum == 5'd4)? W_ipending_reg :
- (D_iw_control_regnum == 5'd5)? W_cpuid_reg :
- W_cdsr_reg;
-
- assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rd_ctl_reg))? 0 :
- (R_ctrl_shift_rot)? E_shift_rot_result :
- (R_ctrl_logic)? E_logic_result :
- (R_ctrl_custom)? E_ci_result :
- E_arith_result;
-
- assign R_sth_data = R_rf_b[15 : 0];
- assign R_stw_data = R_rf_b[31 : 0];
- assign R_stb_data = R_rf_b[7 : 0];
- assign E_st_data = (D_ctrl_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
- (D_ctrl_mem16)? {R_sth_data, R_sth_data} :
- R_stw_data;
-
- assign E_mem_byte_en = ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0001 :
- ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0010 :
- ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b0100 :
- ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1000 :
- ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b00})? 4'b0011 :
- ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b01})? 4'b0011 :
- ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b10})? 4'b1100 :
- ({D_ctrl_mem16, D_ctrl_mem8, E_mem_baddr[1 : 0]} == {2'b10, 2'b11})? 4'b1100 :
- 4'b1111;
-
- assign d_read_nxt = (R_ctrl_ld & E_new_inst & ~E_rf_ecc_valid_any) | (d_read & d_waitrequest);
- assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
- assign d_write_nxt = ((R_ctrl_st & (~R_ctrl_st_ex | W_up_ex_mon_state)) & E_new_inst & ~E_rf_ecc_valid_any) | (d_write & d_waitrequest);
- assign E_st_stall = d_write_nxt;
- assign d_address = W_mem_baddr;
- assign av_ld_getting_data = d_read & ~d_waitrequest;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- d_read <= 0;
- else
- d_read <= d_read_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- d_writedata <= 0;
- else
- d_writedata <= E_st_data;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- d_byteenable <= 0;
- else
- d_byteenable <= E_mem_byte_en;
- end
-
-
- assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
- assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_ctrl_mem16 ? 2 : 3);
- assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
- ~av_ld_align_one_more_cycle :
- (~D_ctrl_mem32 & av_ld_getting_data);
-
- assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
- ~av_ld_getting_data :
- (R_ctrl_ld & E_new_inst);
-
- assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_ctrl_mem32 | ~av_ld_aligning_data_nxt);
- assign av_ld_rshift8 = av_ld_aligning_data &
- (av_ld_align_cycle < (W_mem_baddr[1 : 0]));
-
- assign av_ld_extend = av_ld_aligning_data;
- assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
- av_ld_extend ? av_ld_byte0_data :d_readdata[7 : 0];
-
- assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
- av_ld_extend ? {8 {av_fill_bit}} :d_readdata[15 : 8];
-
- assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
- av_ld_extend ? {8 {av_fill_bit}} :d_readdata[23 : 16];
-
- assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
- av_ld_extend ? {8 {av_fill_bit}} :d_readdata[31 : 24];
-
- assign av_ld_byte1_data_en = ~(av_ld_extend & D_ctrl_mem16 & ~av_ld_rshift8);
- assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
- av_ld_byte1_data, av_ld_byte0_data};
-
- assign av_sign_bit = D_ctrl_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
- assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- av_ld_align_cycle <= 0;
- else
- av_ld_align_cycle <= av_ld_align_cycle_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- av_ld_waiting_for_data <= 0;
- else
- av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- av_ld_aligning_data <= 0;
- else
- av_ld_aligning_data <= av_ld_aligning_data_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- av_ld_byte0_data <= 0;
- else
- av_ld_byte0_data <= av_ld_byte0_data_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- av_ld_byte1_data <= 0;
- else if (av_ld_byte1_data_en)
- av_ld_byte1_data <= av_ld_byte1_data_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- av_ld_byte2_data <= 0;
- else
- av_ld_byte2_data <= av_ld_byte2_data_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- av_ld_byte3_data <= 0;
- else
- av_ld_byte3_data <= av_ld_byte3_data_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_up_ex_mon_state <= 0;
- else if (R_en)
- W_up_ex_mon_state <= (R_ctrl_ld_ex & W_valid) ? 1'b1 :
- ((D_op_eret & W_valid) | (R_ctrl_st_ex & W_valid)) ? 1'b0 :
- W_up_ex_mon_state;
-
- end
-
-
- assign W_valid_from_M = W_valid;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_valid <= 0;
- else
- W_valid <= E_valid & ~E_stall;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- A_valid_from_M <= 0;
- else
- A_valid_from_M <= E_valid & ~E_stall;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_control_rd_data <= 0;
- else
- W_control_rd_data <= D_ctrl_intr_inst ? W_status_reg : E_control_rd_data;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_cmp_result <= 0;
- else
- W_cmp_result <= E_cmp_result;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_alu_result <= 0;
- else
- W_alu_result <= E_alu_result;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_status_reg_pie <= 0;
- else
- W_status_reg_pie <= W_status_reg_pie_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_estatus_reg <= 0;
- else
- W_estatus_reg <= W_estatus_reg_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_bstatus_reg <= 0;
- else
- W_bstatus_reg <= W_bstatus_reg_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_ienable_reg <= 0;
- else
- W_ienable_reg <= W_ienable_reg_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_ipending_reg <= 0;
- else
- W_ipending_reg <= W_ipending_reg_nxt;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- W_cdsr_reg <= 0;
- else
- W_cdsr_reg <= 0;
- end
-
-
- assign W_cpuid_reg = 0;
- assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
- R_ctrl_rd_ctl_reg ? W_control_rd_data :
- W_alu_result[31 : 0];
-
- assign W_wr_data = W_wr_data_non_zero;
- assign W_br_taken = R_ctrl_br_uncond | (R_ctrl_br & W_cmp_result);
- assign W_mem_baddr = W_alu_result[17 : 0];
- assign W_status_reg = W_status_reg_pie;
- assign E_wrctl_status = R_ctrl_wrctl_inst &
- (D_iw_control_regnum == 5'd0);
-
- assign E_wrctl_estatus = R_ctrl_wrctl_inst &
- (D_iw_control_regnum == 5'd1);
-
- assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
- (D_iw_control_regnum == 5'd2);
-
- assign E_wrctl_ienable = R_ctrl_wrctl_inst &
- (D_iw_control_regnum == 5'd3);
-
- assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst | W_rf_ecc_unrecoverable_valid) ? 1'b0 :
- (D_op_eret) ? W_estatus_reg :
- (D_op_bret) ? W_bstatus_reg :
- (E_wrctl_status) ? E_src1[0] :
- W_status_reg_pie;
-
- assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
- assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
- (R_ctrl_exception|W_rf_ecc_unrecoverable_valid) ? W_status_reg :
- (E_wrctl_estatus) ? E_src1[0] :
- W_estatus_reg;
-
- assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
- assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
- (E_wrctl_bstatus) ? E_src1[0] :
- W_bstatus_reg;
-
- assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
- assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
- E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000001111;
-
- assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000001111;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- hbreak_enabled <= 1'b1;
- else if (E_valid)
- hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- d_write <= 0;
- else
- d_write <= d_write_nxt;
- end
-
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_nios2_oci
- (
- .D_valid (D_valid),
- .E_st_data (E_st_data),
- .E_valid (E_valid),
- .F_pc (F_pc),
- .address_nxt (debug_mem_slave_address),
- .av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
- .byteenable_nxt (debug_mem_slave_byteenable),
- .clk (debug_mem_slave_clk),
- .d_address (d_address),
- .d_read (d_read),
- .d_waitrequest (d_waitrequest),
- .d_write (d_write),
- .debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms),
- .debugaccess_nxt (debug_mem_slave_debugaccess),
- .hbreak_enabled (hbreak_enabled),
- .oci_hbreak_req (oci_hbreak_req),
- .oci_ienable (oci_ienable),
- .oci_single_step_mode (oci_single_step_mode),
- .read_nxt (debug_mem_slave_read),
- .readdata (debug_mem_slave_readdata),
- .reset (debug_mem_slave_reset),
- .reset_n (reset_n),
- .reset_req (reset_req),
- .resetrequest (debug_reset_request),
- .waitrequest (debug_mem_slave_waitrequest),
- .write_nxt (debug_mem_slave_write),
- .writedata_nxt (debug_mem_slave_writedata)
- );
-
- //debug_mem_slave, which is an e_avalon_slave
- assign debug_mem_slave_clk = clk;
- assign debug_mem_slave_reset = ~reset_n;
- assign D_ctrl_custom = 1'b0;
- assign R_ctrl_custom_nxt = D_ctrl_custom;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_custom <= 0;
- else if (R_en)
- R_ctrl_custom <= R_ctrl_custom_nxt;
- end
-
-
- assign D_ctrl_custom_multi = 1'b0;
- assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_custom_multi <= 0;
- else if (R_en)
- R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
- end
-
-
- assign D_ctrl_jmp_indirect = D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
- assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_jmp_indirect <= 0;
- else if (R_en)
- R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
- end
-
-
- assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
- assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_jmp_direct <= 0;
- else if (R_en)
- R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
- end
-
-
- assign D_ctrl_implicit_dst_retaddr = D_op_call;
- assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_implicit_dst_retaddr <= 0;
- else if (R_en)
- R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
- end
-
-
- assign D_ctrl_implicit_dst_eretaddr = D_op_div|
- D_op_divu|
- D_op_mul|
- D_op_muli|
- D_op_mulxss|
- D_op_mulxsu|
- D_op_mulxuu|
- D_op_crst|
- D_op_ldl|
- D_op_op_rsv02|
- D_op_op_rsv09|
- D_op_op_rsv10|
- D_op_op_rsv17|
- D_op_op_rsv18|
- D_op_op_rsv25|
- D_op_op_rsv26|
- D_op_op_rsv33|
- D_op_op_rsv34|
- D_op_op_rsv41|
- D_op_op_rsv42|
- D_op_op_rsv49|
- D_op_op_rsv57|
- D_op_op_rsv61|
- D_op_op_rsv62|
- D_op_op_rsv63|
- D_op_opx_rsv00|
- D_op_opx_rsv10|
- D_op_opx_rsv15|
- D_op_opx_rsv17|
- D_op_opx_rsv21|
- D_op_opx_rsv25|
- D_op_opx_rsv33|
- D_op_opx_rsv34|
- D_op_opx_rsv35|
- D_op_opx_rsv42|
- D_op_opx_rsv43|
- D_op_opx_rsv44|
- D_op_opx_rsv47|
- D_op_opx_rsv50|
- D_op_opx_rsv51|
- D_op_opx_rsv55|
- D_op_opx_rsv56|
- D_op_opx_rsv60|
- D_op_opx_rsv63|
- D_op_rdprs|
- D_op_stc|
- D_op_wrprs;
-
- assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_implicit_dst_eretaddr <= 0;
- else if (R_en)
- R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
- end
-
-
- assign D_ctrl_exception = D_op_trap|
- D_op_opx_rsv44|
- D_op_div|
- D_op_divu|
- D_op_mul|
- D_op_muli|
- D_op_mulxss|
- D_op_mulxsu|
- D_op_mulxuu|
- D_op_crst|
- D_op_ldl|
- D_op_op_rsv02|
- D_op_op_rsv09|
- D_op_op_rsv10|
- D_op_op_rsv17|
- D_op_op_rsv18|
- D_op_op_rsv25|
- D_op_op_rsv26|
- D_op_op_rsv33|
- D_op_op_rsv34|
- D_op_op_rsv41|
- D_op_op_rsv42|
- D_op_op_rsv49|
- D_op_op_rsv57|
- D_op_op_rsv61|
- D_op_op_rsv62|
- D_op_op_rsv63|
- D_op_opx_rsv00|
- D_op_opx_rsv10|
- D_op_opx_rsv15|
- D_op_opx_rsv17|
- D_op_opx_rsv21|
- D_op_opx_rsv25|
- D_op_opx_rsv33|
- D_op_opx_rsv34|
- D_op_opx_rsv35|
- D_op_opx_rsv42|
- D_op_opx_rsv43|
- D_op_opx_rsv47|
- D_op_opx_rsv50|
- D_op_opx_rsv51|
- D_op_opx_rsv55|
- D_op_opx_rsv56|
- D_op_opx_rsv60|
- D_op_opx_rsv63|
- D_op_rdprs|
- D_op_stc|
- D_op_wrprs|
- D_op_intr;
-
- assign R_ctrl_exception_nxt = D_ctrl_exception;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_exception <= 0;
- else if (R_en)
- R_ctrl_exception <= R_ctrl_exception_nxt;
- end
-
-
- assign D_ctrl_break = D_op_break|D_op_hbreak;
- assign R_ctrl_break_nxt = D_ctrl_break;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_break <= 0;
- else if (R_en)
- R_ctrl_break <= R_ctrl_break_nxt;
- end
-
-
- assign D_ctrl_crst = 1'b0;
- assign R_ctrl_crst_nxt = D_ctrl_crst;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_crst <= 0;
- else if (R_en)
- R_ctrl_crst <= R_ctrl_crst_nxt;
- end
-
-
- assign D_ctrl_rd_ctl_reg = D_op_rdctl;
- assign R_ctrl_rd_ctl_reg_nxt = D_ctrl_rd_ctl_reg;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_rd_ctl_reg <= 0;
- else if (R_en)
- R_ctrl_rd_ctl_reg <= R_ctrl_rd_ctl_reg_nxt;
- end
-
-
- assign D_ctrl_uncond_cti_non_br = D_op_call|D_op_jmpi|D_op_eret|D_op_bret|D_op_ret|D_op_jmp|D_op_callr;
- assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_uncond_cti_non_br <= 0;
- else if (R_en)
- R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
- end
-
-
- assign D_ctrl_retaddr = D_op_call|
- D_op_op_rsv02|
- D_op_nextpc|
- D_op_callr|
- D_op_trap|
- D_op_opx_rsv44|
- D_op_div|
- D_op_divu|
- D_op_mul|
- D_op_muli|
- D_op_mulxss|
- D_op_mulxsu|
- D_op_mulxuu|
- D_op_crst|
- D_op_ldl|
- D_op_op_rsv09|
- D_op_op_rsv10|
- D_op_op_rsv17|
- D_op_op_rsv18|
- D_op_op_rsv25|
- D_op_op_rsv26|
- D_op_op_rsv33|
- D_op_op_rsv34|
- D_op_op_rsv41|
- D_op_op_rsv42|
- D_op_op_rsv49|
- D_op_op_rsv57|
- D_op_op_rsv61|
- D_op_op_rsv62|
- D_op_op_rsv63|
- D_op_opx_rsv00|
- D_op_opx_rsv10|
- D_op_opx_rsv15|
- D_op_opx_rsv17|
- D_op_opx_rsv21|
- D_op_opx_rsv25|
- D_op_opx_rsv33|
- D_op_opx_rsv34|
- D_op_opx_rsv35|
- D_op_opx_rsv42|
- D_op_opx_rsv43|
- D_op_opx_rsv47|
- D_op_opx_rsv50|
- D_op_opx_rsv51|
- D_op_opx_rsv55|
- D_op_opx_rsv56|
- D_op_opx_rsv60|
- D_op_opx_rsv63|
- D_op_rdprs|
- D_op_stc|
- D_op_wrprs|
- D_op_intr|
- D_op_break|
- D_op_hbreak;
-
- assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_retaddr <= 0;
- else if (R_en)
- R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
- end
-
-
- assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
- assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_shift_logical <= 0;
- else if (R_en)
- R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
- end
-
-
- assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
- assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_shift_right_arith <= 0;
- else if (R_en)
- R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
- end
-
-
- assign D_ctrl_rot_right = D_op_ror;
- assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_rot_right <= 0;
- else if (R_en)
- R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
- end
-
-
- assign D_ctrl_shift_rot_right = D_op_srli|D_op_srl|D_op_srai|D_op_sra|D_op_ror;
- assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_shift_rot_right <= 0;
- else if (R_en)
- R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
- end
-
-
- assign D_ctrl_shift_rot = D_op_slli|
- D_op_sll|
- D_op_roli|
- D_op_rol|
- D_op_srli|
- D_op_srl|
- D_op_srai|
- D_op_sra|
- D_op_ror;
-
- assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_shift_rot <= 0;
- else if (R_en)
- R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
- end
-
-
- assign D_ctrl_logic = D_op_and|
- D_op_or|
- D_op_xor|
- D_op_nor|
- D_op_andhi|
- D_op_orhi|
- D_op_xorhi|
- D_op_andi|
- D_op_ori|
- D_op_xori;
-
- assign R_ctrl_logic_nxt = D_ctrl_logic;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_logic <= 0;
- else if (R_en)
- R_ctrl_logic <= R_ctrl_logic_nxt;
- end
-
-
- assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
- assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_hi_imm16 <= 0;
- else if (R_en)
- R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
- end
-
-
- assign D_ctrl_set_src2_rem_imm = 1'b0;
- assign R_ctrl_set_src2_rem_imm_nxt = D_ctrl_set_src2_rem_imm;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_set_src2_rem_imm <= 0;
- else if (R_en)
- R_ctrl_set_src2_rem_imm <= R_ctrl_set_src2_rem_imm_nxt;
- end
-
-
- assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
- D_op_cmpltui|
- D_op_andi|
- D_op_ori|
- D_op_xori|
- D_op_roli|
- D_op_slli|
- D_op_srli|
- D_op_srai;
-
- assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_unsigned_lo_imm16 <= 0;
- else if (R_en)
- R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
- end
-
-
- assign D_ctrl_signed_imm12 = 1'b0;
- assign R_ctrl_signed_imm12_nxt = D_ctrl_signed_imm12;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_signed_imm12 <= 0;
- else if (R_en)
- R_ctrl_signed_imm12 <= R_ctrl_signed_imm12_nxt;
- end
-
-
- assign D_ctrl_src_imm5_shift_rot = D_op_roli|D_op_slli|D_op_srli|D_op_srai;
- assign R_ctrl_src_imm5_shift_rot_nxt = D_ctrl_src_imm5_shift_rot;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_src_imm5_shift_rot <= 0;
- else if (R_en)
- R_ctrl_src_imm5_shift_rot <= R_ctrl_src_imm5_shift_rot_nxt;
- end
-
-
- assign D_ctrl_br_uncond = D_op_br;
- assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_br_uncond <= 0;
- else if (R_en)
- R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
- end
-
-
- assign D_ctrl_br = D_op_br|D_op_bge|D_op_blt|D_op_bne|D_op_beq|D_op_bgeu|D_op_bltu;
- assign R_ctrl_br_nxt = D_ctrl_br;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_br <= 0;
- else if (R_en)
- R_ctrl_br <= R_ctrl_br_nxt;
- end
-
-
- assign D_ctrl_alu_subtract = D_op_sub|
- D_op_cmplti|
- D_op_cmpltui|
- D_op_cmplt|
- D_op_cmpltu|
- D_op_blt|
- D_op_bltu|
- D_op_cmpgei|
- D_op_cmpgeui|
- D_op_cmpge|
- D_op_cmpgeu|
- D_op_bge|
- D_op_bgeu;
-
- assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_alu_subtract <= 0;
- else if (R_en)
- R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
- end
-
-
- assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
- assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_alu_signed_comparison <= 0;
- else if (R_en)
- R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
- end
-
-
- assign D_ctrl_br_cmp = D_op_br|
- D_op_bge|
- D_op_blt|
- D_op_bne|
- D_op_beq|
- D_op_bgeu|
- D_op_bltu|
- D_op_cmpgei|
- D_op_cmplti|
- D_op_cmpnei|
- D_op_cmpgeui|
- D_op_cmpltui|
- D_op_cmpeqi|
- D_op_cmpge|
- D_op_cmplt|
- D_op_cmpne|
- D_op_cmpgeu|
- D_op_cmpltu|
- D_op_cmpeq;
-
- assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_br_cmp <= 0;
- else if (R_en)
- R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
- end
-
-
- assign D_ctrl_ld_signed = D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldbio|D_op_ldhio|D_op_ldwio;
- assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_ld_signed <= 0;
- else if (R_en)
- R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
- end
-
-
- assign D_ctrl_ld = D_op_ldb|
- D_op_ldh|
- D_op_ldw|
- D_op_ldbio|
- D_op_ldhio|
- D_op_ldwio|
- D_op_ldbu|
- D_op_ldhu|
- D_op_ldbuio|
- D_op_ldhuio;
-
- assign R_ctrl_ld_nxt = D_ctrl_ld;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_ld <= 0;
- else if (R_en)
- R_ctrl_ld <= R_ctrl_ld_nxt;
- end
-
-
- assign D_ctrl_ld_ex = 1'b0;
- assign R_ctrl_ld_ex_nxt = D_ctrl_ld_ex;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_ld_ex <= 0;
- else if (R_en)
- R_ctrl_ld_ex <= R_ctrl_ld_ex_nxt;
- end
-
-
- assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw;
- assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_ld_non_io <= 0;
- else if (R_en)
- R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
- end
-
-
- assign D_ctrl_st_ex = 1'b0;
- assign R_ctrl_st_ex_nxt = D_ctrl_st_ex;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_st_ex <= 0;
- else if (R_en)
- R_ctrl_st_ex <= R_ctrl_st_ex_nxt;
- end
-
-
- assign D_ctrl_st = D_op_stb|D_op_sth|D_op_stw|D_op_stbio|D_op_sthio|D_op_stwio;
- assign R_ctrl_st_nxt = D_ctrl_st;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_st <= 0;
- else if (R_en)
- R_ctrl_st <= R_ctrl_st_nxt;
- end
-
-
- assign D_ctrl_ld_st_ex = 1'b0;
- assign R_ctrl_ld_st_ex_nxt = D_ctrl_ld_st_ex;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_ld_st_ex <= 0;
- else if (R_en)
- R_ctrl_ld_st_ex <= R_ctrl_ld_st_ex_nxt;
- end
-
-
- assign D_ctrl_mem8 = D_op_ldb|D_op_ldbu|D_op_ldbio|D_op_ldbuio|D_op_stb|D_op_stbio;
- assign R_ctrl_mem8_nxt = D_ctrl_mem8;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_mem8 <= 0;
- else if (R_en)
- R_ctrl_mem8 <= R_ctrl_mem8_nxt;
- end
-
-
- assign D_ctrl_mem16 = D_op_ldhu|D_op_ldh|D_op_ldhio|D_op_ldhuio|D_op_sth|D_op_sthio;
- assign R_ctrl_mem16_nxt = D_ctrl_mem16;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_mem16 <= 0;
- else if (R_en)
- R_ctrl_mem16 <= R_ctrl_mem16_nxt;
- end
-
-
- assign D_ctrl_mem32 = D_op_ldw|D_op_ldwio|D_op_stw|D_op_stwio;
- assign R_ctrl_mem32_nxt = D_ctrl_mem32;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_mem32 <= 0;
- else if (R_en)
- R_ctrl_mem32 <= R_ctrl_mem32_nxt;
- end
-
-
- assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio;
- assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_ld_io <= 0;
- else if (R_en)
- R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
- end
-
-
- assign D_ctrl_b_is_dst = D_op_addi|
- D_op_andhi|
- D_op_orhi|
- D_op_xorhi|
- D_op_andi|
- D_op_ori|
- D_op_xori|
- D_op_call|
- D_op_cmpgei|
- D_op_cmplti|
- D_op_cmpnei|
- D_op_cmpgeui|
- D_op_cmpltui|
- D_op_cmpeqi|
- D_op_jmpi|
- D_op_ldb|
- D_op_ldh|
- D_op_ldw|
- D_op_ldbio|
- D_op_ldhio|
- D_op_ldwio|
- D_op_ldbu|
- D_op_ldhu|
- D_op_ldbuio|
- D_op_ldhuio|
- D_op_initd|
- D_op_initda|
- D_op_flushd|
- D_op_flushda;
-
- assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_b_is_dst <= 0;
- else if (R_en)
- R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
- end
-
-
- assign D_ctrl_ignore_dst = D_op_br|
- D_op_bge|
- D_op_blt|
- D_op_bne|
- D_op_beq|
- D_op_bgeu|
- D_op_bltu|
- D_op_stb|
- D_op_sth|
- D_op_stw|
- D_op_stbio|
- D_op_sthio|
- D_op_stwio|
- D_op_jmpi;
-
- assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_ignore_dst <= 0;
- else if (R_en)
- R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
- end
-
-
- assign D_ctrl_src2_choose_imm = D_op_addi|
- D_op_andhi|
- D_op_orhi|
- D_op_xorhi|
- D_op_andi|
- D_op_ori|
- D_op_xori|
- D_op_call|
- D_op_cmpgei|
- D_op_cmplti|
- D_op_cmpnei|
- D_op_cmpgeui|
- D_op_cmpltui|
- D_op_cmpeqi|
- D_op_jmpi|
- D_op_ldb|
- D_op_ldh|
- D_op_ldw|
- D_op_ldbio|
- D_op_ldhio|
- D_op_ldwio|
- D_op_ldbu|
- D_op_ldhu|
- D_op_ldbuio|
- D_op_ldhuio|
- D_op_initd|
- D_op_initda|
- D_op_flushd|
- D_op_flushda|
- D_op_stb|
- D_op_sth|
- D_op_stw|
- D_op_stbio|
- D_op_sthio|
- D_op_stwio|
- D_op_roli|
- D_op_slli|
- D_op_srli|
- D_op_srai;
-
- assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_src2_choose_imm <= 0;
- else if (R_en)
- R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
- end
-
-
- assign D_ctrl_wrctl_inst = D_op_wrctl;
- assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_wrctl_inst <= 0;
- else if (R_en)
- R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
- end
-
-
- assign D_ctrl_intr_inst = 1'b0;
- assign R_ctrl_intr_inst_nxt = D_ctrl_intr_inst;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_intr_inst <= 0;
- else if (R_en)
- R_ctrl_intr_inst <= R_ctrl_intr_inst_nxt;
- end
-
-
- assign D_ctrl_force_src2_zero = D_op_call|
- D_op_op_rsv02|
- D_op_nextpc|
- D_op_callr|
- D_op_trap|
- D_op_opx_rsv44|
- D_op_crst|
- D_op_ldl|
- D_op_op_rsv09|
- D_op_op_rsv10|
- D_op_op_rsv17|
- D_op_op_rsv18|
- D_op_op_rsv25|
- D_op_op_rsv26|
- D_op_op_rsv33|
- D_op_op_rsv34|
- D_op_op_rsv41|
- D_op_op_rsv42|
- D_op_op_rsv49|
- D_op_op_rsv57|
- D_op_op_rsv61|
- D_op_op_rsv62|
- D_op_op_rsv63|
- D_op_opx_rsv00|
- D_op_opx_rsv10|
- D_op_opx_rsv15|
- D_op_opx_rsv17|
- D_op_opx_rsv21|
- D_op_opx_rsv25|
- D_op_opx_rsv33|
- D_op_opx_rsv34|
- D_op_opx_rsv35|
- D_op_opx_rsv42|
- D_op_opx_rsv43|
- D_op_opx_rsv47|
- D_op_opx_rsv50|
- D_op_opx_rsv51|
- D_op_opx_rsv55|
- D_op_opx_rsv56|
- D_op_opx_rsv60|
- D_op_opx_rsv63|
- D_op_rdprs|
- D_op_stc|
- D_op_wrprs|
- D_op_intr|
- D_op_break|
- D_op_hbreak|
- D_op_eret|
- D_op_bret|
- D_op_ret|
- D_op_jmp|
- D_op_jmpi;
-
- assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_force_src2_zero <= 0;
- else if (R_en)
- R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
- end
-
-
- assign D_ctrl_alu_force_xor = D_op_cmpgei|
- D_op_cmpgeui|
- D_op_cmpeqi|
- D_op_cmpge|
- D_op_cmpgeu|
- D_op_cmpeq|
- D_op_cmpnei|
- D_op_cmpne|
- D_op_bge|
- D_op_bgeu|
- D_op_beq|
- D_op_bne|
- D_op_br;
-
- assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_alu_force_xor <= 0;
- else if (R_en)
- R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
- end
-
-
- assign D_ctrl_alu_force_and = 1'b0;
- assign R_ctrl_alu_force_and_nxt = D_ctrl_alu_force_and;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- R_ctrl_alu_force_and <= 0;
- else if (R_en)
- R_ctrl_alu_force_and <= R_ctrl_alu_force_and_nxt;
- end
-
-
- //data_master, which is an e_avalon_master
- //instruction_master, which is an e_avalon_master
-
-//synthesis translate_off
-//////////////// SIMULATION-ONLY CONTENTS
- assign F_inst = (F_op_call)? 56'h20202063616c6c :
- (F_op_jmpi)? 56'h2020206a6d7069 :
- (F_op_ldbu)? 56'h2020206c646275 :
- (F_op_addi)? 56'h20202061646469 :
- (F_op_stb)? 56'h20202020737462 :
- (F_op_br)? 56'h20202020206272 :
- (F_op_ldb)? 56'h202020206c6462 :
- (F_op_cmpgei)? 56'h20636d70676569 :
- (F_op_ldhu)? 56'h2020206c646875 :
- (F_op_andi)? 56'h202020616e6469 :
- (F_op_sth)? 56'h20202020737468 :
- (F_op_bge)? 56'h20202020626765 :
- (F_op_ldh)? 56'h202020206c6468 :
- (F_op_cmplti)? 56'h20636d706c7469 :
- (F_op_initda)? 56'h20696e69746461 :
- (F_op_ori)? 56'h202020206f7269 :
- (F_op_stw)? 56'h20202020737477 :
- (F_op_blt)? 56'h20202020626c74 :
- (F_op_ldw)? 56'h202020206c6477 :
- (F_op_cmpnei)? 56'h20636d706e6569 :
- (F_op_flushda)? 56'h666c7573686461 :
- (F_op_xori)? 56'h202020786f7269 :
- (F_op_bne)? 56'h20202020626e65 :
- (F_op_cmpeqi)? 56'h20636d70657169 :
- (F_op_ldbuio)? 56'h206c646275696f :
- (F_op_muli)? 56'h2020206d756c69 :
- (F_op_stbio)? 56'h2020737462696f :
- (F_op_beq)? 56'h20202020626571 :
- (F_op_ldbio)? 56'h20206c6462696f :
- (F_op_cmpgeui)? 56'h636d7067657569 :
- (F_op_ldhuio)? 56'h206c646875696f :
- (F_op_andhi)? 56'h2020616e646869 :
- (F_op_sthio)? 56'h2020737468696f :
- (F_op_bgeu)? 56'h20202062676575 :
- (F_op_ldhio)? 56'h20206c6468696f :
- (F_op_cmpltui)? 56'h636d706c747569 :
- (F_op_custom)? 56'h20637573746f6d :
- (F_op_initd)? 56'h2020696e697464 :
- (F_op_orhi)? 56'h2020206f726869 :
- (F_op_stwio)? 56'h2020737477696f :
- (F_op_bltu)? 56'h202020626c7475 :
- (F_op_ldwio)? 56'h20206c6477696f :
- (F_op_flushd)? 56'h20666c75736864 :
- (F_op_xorhi)? 56'h2020786f726869 :
- (F_op_eret)? 56'h20202065726574 :
- (F_op_roli)? 56'h202020726f6c69 :
- (F_op_rol)? 56'h20202020726f6c :
- (F_op_flushp)? 56'h20666c75736870 :
- (F_op_ret)? 56'h20202020726574 :
- (F_op_nor)? 56'h202020206e6f72 :
- (F_op_mulxuu)? 56'h206d756c787575 :
- (F_op_cmpge)? 56'h2020636d706765 :
- (F_op_bret)? 56'h20202062726574 :
- (F_op_ror)? 56'h20202020726f72 :
- (F_op_flushi)? 56'h20666c75736869 :
- (F_op_jmp)? 56'h202020206a6d70 :
- (F_op_and)? 56'h20202020616e64 :
- (F_op_cmplt)? 56'h2020636d706c74 :
- (F_op_slli)? 56'h202020736c6c69 :
- (F_op_sll)? 56'h20202020736c6c :
- (F_op_or)? 56'h20202020206f72 :
- (F_op_mulxsu)? 56'h206d756c787375 :
- (F_op_cmpne)? 56'h2020636d706e65 :
- (F_op_srli)? 56'h20202073726c69 :
- (F_op_srl)? 56'h2020202073726c :
- (F_op_nextpc)? 56'h206e6578747063 :
- (F_op_callr)? 56'h202063616c6c72 :
- (F_op_xor)? 56'h20202020786f72 :
- (F_op_mulxss)? 56'h206d756c787373 :
- (F_op_cmpeq)? 56'h2020636d706571 :
- (F_op_divu)? 56'h20202064697675 :
- (F_op_div)? 56'h20202020646976 :
- (F_op_rdctl)? 56'h2020726463746c :
- (F_op_mul)? 56'h202020206d756c :
- (F_op_cmpgeu)? 56'h20636d70676575 :
- (F_op_initi)? 56'h2020696e697469 :
- (F_op_trap)? 56'h20202074726170 :
- (F_op_wrctl)? 56'h2020777263746c :
- (F_op_cmpltu)? 56'h20636d706c7475 :
- (F_op_add)? 56'h20202020616464 :
- (F_op_break)? 56'h2020627265616b :
- (F_op_hbreak)? 56'h2068627265616b :
- (F_op_sync)? 56'h20202073796e63 :
- (F_op_sub)? 56'h20202020737562 :
- (F_op_srai)? 56'h20202073726169 :
- (F_op_sra)? 56'h20202020737261 :
- (F_op_intr)? 56'h202020696e7472 :
- 56'h20202020424144;
-
- assign D_inst = (D_op_call)? 56'h20202063616c6c :
- (D_op_jmpi)? 56'h2020206a6d7069 :
- (D_op_ldbu)? 56'h2020206c646275 :
- (D_op_addi)? 56'h20202061646469 :
- (D_op_stb)? 56'h20202020737462 :
- (D_op_br)? 56'h20202020206272 :
- (D_op_ldb)? 56'h202020206c6462 :
- (D_op_cmpgei)? 56'h20636d70676569 :
- (D_op_ldhu)? 56'h2020206c646875 :
- (D_op_andi)? 56'h202020616e6469 :
- (D_op_sth)? 56'h20202020737468 :
- (D_op_bge)? 56'h20202020626765 :
- (D_op_ldh)? 56'h202020206c6468 :
- (D_op_cmplti)? 56'h20636d706c7469 :
- (D_op_initda)? 56'h20696e69746461 :
- (D_op_ori)? 56'h202020206f7269 :
- (D_op_stw)? 56'h20202020737477 :
- (D_op_blt)? 56'h20202020626c74 :
- (D_op_ldw)? 56'h202020206c6477 :
- (D_op_cmpnei)? 56'h20636d706e6569 :
- (D_op_flushda)? 56'h666c7573686461 :
- (D_op_xori)? 56'h202020786f7269 :
- (D_op_bne)? 56'h20202020626e65 :
- (D_op_cmpeqi)? 56'h20636d70657169 :
- (D_op_ldbuio)? 56'h206c646275696f :
- (D_op_muli)? 56'h2020206d756c69 :
- (D_op_stbio)? 56'h2020737462696f :
- (D_op_beq)? 56'h20202020626571 :
- (D_op_ldbio)? 56'h20206c6462696f :
- (D_op_cmpgeui)? 56'h636d7067657569 :
- (D_op_ldhuio)? 56'h206c646875696f :
- (D_op_andhi)? 56'h2020616e646869 :
- (D_op_sthio)? 56'h2020737468696f :
- (D_op_bgeu)? 56'h20202062676575 :
- (D_op_ldhio)? 56'h20206c6468696f :
- (D_op_cmpltui)? 56'h636d706c747569 :
- (D_op_custom)? 56'h20637573746f6d :
- (D_op_initd)? 56'h2020696e697464 :
- (D_op_orhi)? 56'h2020206f726869 :
- (D_op_stwio)? 56'h2020737477696f :
- (D_op_bltu)? 56'h202020626c7475 :
- (D_op_ldwio)? 56'h20206c6477696f :
- (D_op_flushd)? 56'h20666c75736864 :
- (D_op_xorhi)? 56'h2020786f726869 :
- (D_op_eret)? 56'h20202065726574 :
- (D_op_roli)? 56'h202020726f6c69 :
- (D_op_rol)? 56'h20202020726f6c :
- (D_op_flushp)? 56'h20666c75736870 :
- (D_op_ret)? 56'h20202020726574 :
- (D_op_nor)? 56'h202020206e6f72 :
- (D_op_mulxuu)? 56'h206d756c787575 :
- (D_op_cmpge)? 56'h2020636d706765 :
- (D_op_bret)? 56'h20202062726574 :
- (D_op_ror)? 56'h20202020726f72 :
- (D_op_flushi)? 56'h20666c75736869 :
- (D_op_jmp)? 56'h202020206a6d70 :
- (D_op_and)? 56'h20202020616e64 :
- (D_op_cmplt)? 56'h2020636d706c74 :
- (D_op_slli)? 56'h202020736c6c69 :
- (D_op_sll)? 56'h20202020736c6c :
- (D_op_or)? 56'h20202020206f72 :
- (D_op_mulxsu)? 56'h206d756c787375 :
- (D_op_cmpne)? 56'h2020636d706e65 :
- (D_op_srli)? 56'h20202073726c69 :
- (D_op_srl)? 56'h2020202073726c :
- (D_op_nextpc)? 56'h206e6578747063 :
- (D_op_callr)? 56'h202063616c6c72 :
- (D_op_xor)? 56'h20202020786f72 :
- (D_op_mulxss)? 56'h206d756c787373 :
- (D_op_cmpeq)? 56'h2020636d706571 :
- (D_op_divu)? 56'h20202064697675 :
- (D_op_div)? 56'h20202020646976 :
- (D_op_rdctl)? 56'h2020726463746c :
- (D_op_mul)? 56'h202020206d756c :
- (D_op_cmpgeu)? 56'h20636d70676575 :
- (D_op_initi)? 56'h2020696e697469 :
- (D_op_trap)? 56'h20202074726170 :
- (D_op_wrctl)? 56'h2020777263746c :
- (D_op_cmpltu)? 56'h20636d706c7475 :
- (D_op_add)? 56'h20202020616464 :
- (D_op_break)? 56'h2020627265616b :
- (D_op_hbreak)? 56'h2068627265616b :
- (D_op_sync)? 56'h20202073796e63 :
- (D_op_sub)? 56'h20202020737562 :
- (D_op_srai)? 56'h20202073726169 :
- (D_op_sra)? 56'h20202020737261 :
- (D_op_intr)? 56'h202020696e7472 :
- 56'h20202020424144;
-
- assign F_vinst = F_valid ? F_inst : {9{8'h2d}};
- assign D_vinst = D_valid ? D_inst : {9{8'h2d}};
- assign R_vinst = R_valid ? D_inst : {9{8'h2d}};
- assign E_vinst = E_valid ? D_inst : {9{8'h2d}};
- assign W_vinst = W_valid ? D_inst : {9{8'h2d}};
-
-//////////////// END SIMULATION-ONLY CONTENTS
-
-//synthesis translate_on
-
-endmodule
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk.v
deleted file mode 100644
index c981abf1e2248124e5b564aa235245175fb3afa3..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk.v
+++ /dev/null
@@ -1,162 +0,0 @@
-//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk (
- // inputs:
- clk,
- ir_in,
- sr,
- vs_udr,
- vs_uir,
-
- // outputs:
- jdo,
- take_action_break_a,
- take_action_break_b,
- take_action_break_c,
- take_action_ocimem_a,
- take_action_ocimem_b,
- take_action_tracectrl,
- take_no_action_break_a,
- take_no_action_break_b,
- take_no_action_break_c,
- take_no_action_ocimem_a
- )
-;
-
- output [ 37: 0] jdo;
- output take_action_break_a;
- output take_action_break_b;
- output take_action_break_c;
- output take_action_ocimem_a;
- output take_action_ocimem_b;
- output take_action_tracectrl;
- output take_no_action_break_a;
- output take_no_action_break_b;
- output take_no_action_break_c;
- output take_no_action_ocimem_a;
- input clk;
- input [ 1: 0] ir_in;
- input [ 37: 0] sr;
- input vs_udr;
- input vs_uir;
-
-
-reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
-reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
-reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
-reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
-reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
-wire sync_udr;
-wire sync_uir;
-wire take_action_break_a;
-wire take_action_break_b;
-wire take_action_break_c;
-wire take_action_ocimem_a;
-wire take_action_ocimem_b;
-wire take_action_tracectrl;
-wire take_no_action_break_a;
-wire take_no_action_break_b;
-wire take_no_action_break_c;
-wire take_no_action_ocimem_a;
-wire unxunused_resetxx3;
-wire unxunused_resetxx4;
-reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
- assign unxunused_resetxx3 = 1'b1;
- altera_std_synchronizer the_altera_std_synchronizer3
- (
- .clk (clk),
- .din (vs_udr),
- .dout (sync_udr),
- .reset_n (unxunused_resetxx3)
- );
-
- defparam the_altera_std_synchronizer3.depth = 2;
-
- assign unxunused_resetxx4 = 1'b1;
- altera_std_synchronizer the_altera_std_synchronizer4
- (
- .clk (clk),
- .din (vs_uir),
- .dout (sync_uir),
- .reset_n (unxunused_resetxx4)
- );
-
- defparam the_altera_std_synchronizer4.depth = 2;
-
- always @(posedge clk)
- begin
- sync2_udr <= sync_udr;
- update_jdo_strobe <= sync_udr & ~sync2_udr;
- enable_action_strobe <= update_jdo_strobe;
- sync2_uir <= sync_uir;
- jxuir <= sync_uir & ~sync2_uir;
- end
-
-
- assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
- ~jdo[35] && jdo[34];
-
- assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
- ~jdo[35] && ~jdo[34];
-
- assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
- jdo[35];
-
- assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
- ~jdo[36] &&
- jdo[37];
-
- assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
- ~jdo[36] &&
- ~jdo[37];
-
- assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
- jdo[36] && ~jdo[35] &&
- jdo[37];
-
- assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
- jdo[36] && ~jdo[35] &&
- ~jdo[37];
-
- assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
- jdo[36] && jdo[35] &&
- jdo[37];
-
- assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
- jdo[36] && jdo[35] &&
- ~jdo[37];
-
- assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
- jdo[15];
-
- always @(posedge clk)
- begin
- if (jxuir)
- ir <= ir_in;
- if (update_jdo_strobe)
- jdo <= sr;
- end
-
-
-
-endmodule
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck.v
deleted file mode 100644
index 95ad4239995b00e48d7dd4e025efe75c46c0bd4b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck.v
+++ /dev/null
@@ -1,239 +0,0 @@
-//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck (
- // inputs:
- MonDReg,
- break_readreg,
- dbrk_hit0_latch,
- dbrk_hit1_latch,
- dbrk_hit2_latch,
- dbrk_hit3_latch,
- debugack,
- ir_in,
- jtag_state_rti,
- monitor_error,
- monitor_ready,
- reset_n,
- resetlatch,
- tck,
- tdi,
- tracemem_on,
- tracemem_trcdata,
- tracemem_tw,
- trc_im_addr,
- trc_on,
- trc_wrap,
- trigbrktype,
- trigger_state_1,
- vs_cdr,
- vs_sdr,
- vs_uir,
-
- // outputs:
- ir_out,
- jrst_n,
- sr,
- st_ready_test_idle,
- tdo
- )
-;
-
- output [ 1: 0] ir_out;
- output jrst_n;
- output [ 37: 0] sr;
- output st_ready_test_idle;
- output tdo;
- input [ 31: 0] MonDReg;
- input [ 31: 0] break_readreg;
- input dbrk_hit0_latch;
- input dbrk_hit1_latch;
- input dbrk_hit2_latch;
- input dbrk_hit3_latch;
- input debugack;
- input [ 1: 0] ir_in;
- input jtag_state_rti;
- input monitor_error;
- input monitor_ready;
- input reset_n;
- input resetlatch;
- input tck;
- input tdi;
- input tracemem_on;
- input [ 35: 0] tracemem_trcdata;
- input tracemem_tw;
- input [ 6: 0] trc_im_addr;
- input trc_on;
- input trc_wrap;
- input trigbrktype;
- input trigger_state_1;
- input vs_cdr;
- input vs_sdr;
- input vs_uir;
-
-
-reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-wire debugack_sync;
-reg [ 1: 0] ir_out;
-wire jrst_n;
-wire monitor_ready_sync;
-reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
-wire st_ready_test_idle;
-wire tdo;
-wire unxcomplemented_resetxx1;
-wire unxcomplemented_resetxx2;
- always @(posedge tck)
- begin
- if (vs_cdr)
- case (ir_in)
-
- 2'b00: begin
- sr[35] <= debugack_sync;
- sr[34] <= monitor_error;
- sr[33] <= resetlatch;
- sr[32 : 1] <= MonDReg;
- sr[0] <= monitor_ready_sync;
- end // 2'b00
-
- 2'b01: begin
- sr[35 : 0] <= tracemem_trcdata;
- sr[37] <= tracemem_tw;
- sr[36] <= tracemem_on;
- end // 2'b01
-
- 2'b10: begin
- sr[37] <= trigger_state_1;
- sr[36] <= dbrk_hit3_latch;
- sr[35] <= dbrk_hit2_latch;
- sr[34] <= dbrk_hit1_latch;
- sr[33] <= dbrk_hit0_latch;
- sr[32 : 1] <= break_readreg;
- sr[0] <= trigbrktype;
- end // 2'b10
-
- 2'b11: begin
- sr[15 : 2] <= trc_im_addr;
- sr[1] <= trc_wrap;
- sr[0] <= trc_on;
- end // 2'b11
-
- endcase // ir_in
- if (vs_sdr)
- case (DRsize)
-
- 3'b000: begin
- sr <= {tdi, sr[37 : 2], tdi};
- end // 3'b000
-
- 3'b001: begin
- sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
- end // 3'b001
-
- 3'b010: begin
- sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
- end // 3'b010
-
- 3'b011: begin
- sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
- end // 3'b011
-
- 3'b100: begin
- sr <= {tdi, sr[37], tdi, sr[35 : 1]};
- end // 3'b100
-
- 3'b101: begin
- sr <= {tdi, sr[37 : 1]};
- end // 3'b101
-
- default: begin
- sr <= {tdi, sr[37 : 2], tdi};
- end // default
-
- endcase // DRsize
- if (vs_uir)
- case (ir_in)
-
- 2'b00: begin
- DRsize <= 3'b100;
- end // 2'b00
-
- 2'b01: begin
- DRsize <= 3'b101;
- end // 2'b01
-
- 2'b10: begin
- DRsize <= 3'b101;
- end // 2'b10
-
- 2'b11: begin
- DRsize <= 3'b010;
- end // 2'b11
-
- endcase // ir_in
- end
-
-
- assign tdo = sr[0];
- assign st_ready_test_idle = jtag_state_rti;
- assign unxcomplemented_resetxx1 = jrst_n;
- altera_std_synchronizer the_altera_std_synchronizer1
- (
- .clk (tck),
- .din (debugack),
- .dout (debugack_sync),
- .reset_n (unxcomplemented_resetxx1)
- );
-
- defparam the_altera_std_synchronizer1.depth = 2;
-
- assign unxcomplemented_resetxx2 = jrst_n;
- altera_std_synchronizer the_altera_std_synchronizer2
- (
- .clk (tck),
- .din (monitor_ready),
- .dout (monitor_ready_sync),
- .reset_n (unxcomplemented_resetxx2)
- );
-
- defparam the_altera_std_synchronizer2.depth = 2;
-
- always @(posedge tck or negedge jrst_n)
- begin
- if (jrst_n == 0)
- ir_out <= 2'b0;
- else
- ir_out <= {debugack_sync, monitor_ready_sync};
- end
-
-
-
-//synthesis translate_off
-//////////////// SIMULATION-ONLY CONTENTS
- assign jrst_n = reset_n;
-
-//////////////// END SIMULATION-ONLY CONTENTS
-
-//synthesis translate_on
-//synthesis read_comments_as_HDL on
-// assign jrst_n = 1;
-//synthesis read_comments_as_HDL off
-
-endmodule
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper.v
deleted file mode 100644
index 036a98f942a3ee874b43b343df346e3cf0f283bb..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper.v
+++ /dev/null
@@ -1,222 +0,0 @@
-//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper (
- // inputs:
- MonDReg,
- break_readreg,
- clk,
- dbrk_hit0_latch,
- dbrk_hit1_latch,
- dbrk_hit2_latch,
- dbrk_hit3_latch,
- debugack,
- monitor_error,
- monitor_ready,
- reset_n,
- resetlatch,
- tracemem_on,
- tracemem_trcdata,
- tracemem_tw,
- trc_im_addr,
- trc_on,
- trc_wrap,
- trigbrktype,
- trigger_state_1,
-
- // outputs:
- jdo,
- jrst_n,
- st_ready_test_idle,
- take_action_break_a,
- take_action_break_b,
- take_action_break_c,
- take_action_ocimem_a,
- take_action_ocimem_b,
- take_action_tracectrl,
- take_no_action_break_a,
- take_no_action_break_b,
- take_no_action_break_c,
- take_no_action_ocimem_a
- )
-;
-
- output [ 37: 0] jdo;
- output jrst_n;
- output st_ready_test_idle;
- output take_action_break_a;
- output take_action_break_b;
- output take_action_break_c;
- output take_action_ocimem_a;
- output take_action_ocimem_b;
- output take_action_tracectrl;
- output take_no_action_break_a;
- output take_no_action_break_b;
- output take_no_action_break_c;
- output take_no_action_ocimem_a;
- input [ 31: 0] MonDReg;
- input [ 31: 0] break_readreg;
- input clk;
- input dbrk_hit0_latch;
- input dbrk_hit1_latch;
- input dbrk_hit2_latch;
- input dbrk_hit3_latch;
- input debugack;
- input monitor_error;
- input monitor_ready;
- input reset_n;
- input resetlatch;
- input tracemem_on;
- input [ 35: 0] tracemem_trcdata;
- input tracemem_tw;
- input [ 6: 0] trc_im_addr;
- input trc_on;
- input trc_wrap;
- input trigbrktype;
- input trigger_state_1;
-
-
-wire [ 37: 0] jdo;
-wire jrst_n;
-wire [ 37: 0] sr;
-wire st_ready_test_idle;
-wire take_action_break_a;
-wire take_action_break_b;
-wire take_action_break_c;
-wire take_action_ocimem_a;
-wire take_action_ocimem_b;
-wire take_action_tracectrl;
-wire take_no_action_break_a;
-wire take_no_action_break_b;
-wire take_no_action_break_c;
-wire take_no_action_ocimem_a;
-wire vji_cdr;
-wire [ 1: 0] vji_ir_in;
-wire [ 1: 0] vji_ir_out;
-wire vji_rti;
-wire vji_sdr;
-wire vji_tck;
-wire vji_tdi;
-wire vji_tdo;
-wire vji_udr;
-wire vji_uir;
- //Change the sld_virtual_jtag_basic's defparams to
- //switch between a regular Nios II or an internally embedded Nios II.
- //For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
- //For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck
- (
- .MonDReg (MonDReg),
- .break_readreg (break_readreg),
- .dbrk_hit0_latch (dbrk_hit0_latch),
- .dbrk_hit1_latch (dbrk_hit1_latch),
- .dbrk_hit2_latch (dbrk_hit2_latch),
- .dbrk_hit3_latch (dbrk_hit3_latch),
- .debugack (debugack),
- .ir_in (vji_ir_in),
- .ir_out (vji_ir_out),
- .jrst_n (jrst_n),
- .jtag_state_rti (vji_rti),
- .monitor_error (monitor_error),
- .monitor_ready (monitor_ready),
- .reset_n (reset_n),
- .resetlatch (resetlatch),
- .sr (sr),
- .st_ready_test_idle (st_ready_test_idle),
- .tck (vji_tck),
- .tdi (vji_tdi),
- .tdo (vji_tdo),
- .tracemem_on (tracemem_on),
- .tracemem_trcdata (tracemem_trcdata),
- .tracemem_tw (tracemem_tw),
- .trc_im_addr (trc_im_addr),
- .trc_on (trc_on),
- .trc_wrap (trc_wrap),
- .trigbrktype (trigbrktype),
- .trigger_state_1 (trigger_state_1),
- .vs_cdr (vji_cdr),
- .vs_sdr (vji_sdr),
- .vs_uir (vji_uir)
- );
-
- qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk the_qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk
- (
- .clk (clk),
- .ir_in (vji_ir_in),
- .jdo (jdo),
- .sr (sr),
- .take_action_break_a (take_action_break_a),
- .take_action_break_b (take_action_break_b),
- .take_action_break_c (take_action_break_c),
- .take_action_ocimem_a (take_action_ocimem_a),
- .take_action_ocimem_b (take_action_ocimem_b),
- .take_action_tracectrl (take_action_tracectrl),
- .take_no_action_break_a (take_no_action_break_a),
- .take_no_action_break_b (take_no_action_break_b),
- .take_no_action_break_c (take_no_action_break_c),
- .take_no_action_ocimem_a (take_no_action_ocimem_a),
- .vs_udr (vji_udr),
- .vs_uir (vji_uir)
- );
-
-
-//synthesis translate_off
-//////////////// SIMULATION-ONLY CONTENTS
- assign vji_tck = 1'b0;
- assign vji_tdi = 1'b0;
- assign vji_sdr = 1'b0;
- assign vji_cdr = 1'b0;
- assign vji_rti = 1'b0;
- assign vji_uir = 1'b0;
- assign vji_udr = 1'b0;
- assign vji_ir_in = 2'b0;
-
-//////////////// END SIMULATION-ONLY CONTENTS
-
-//synthesis translate_on
-//synthesis read_comments_as_HDL on
-// sld_virtual_jtag_basic qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy
-// (
-// .ir_in (vji_ir_in),
-// .ir_out (vji_ir_out),
-// .jtag_state_rti (vji_rti),
-// .tck (vji_tck),
-// .tdi (vji_tdi),
-// .tdo (vji_tdo),
-// .virtual_state_cdr (vji_cdr),
-// .virtual_state_sdr (vji_sdr),
-// .virtual_state_udr (vji_udr),
-// .virtual_state_uir (vji_uir)
-// );
-//
-// defparam qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy.sld_auto_instance_index = "YES",
-// qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy.sld_instance_index = 0,
-// qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy.sld_ir_width = 2,
-// qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy.sld_mfg_id = 70,
-// qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy.sld_sim_action = "",
-// qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy.sld_sim_n_scan = 0,
-// qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy.sld_sim_total_length = 0,
-// qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy.sld_type_id = 34,
-// qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_phy.sld_version = 3;
-//
-//synthesis read_comments_as_HDL off
-
-endmodule
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_default_contents.mif b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_default_contents.mif
deleted file mode 100644
index 2670de9213b12097a77bc5d543144ac1ff2ecd14..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_default_contents.mif
+++ /dev/null
@@ -1,267 +0,0 @@
--- Contents are randomly generated during RTL generation.
-WIDTH=32;
-DEPTH=256;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-
-00 : 5870e850;
-01 : c7a32b0d;
-02 : 6f82d8fd;
-03 : 40bb3819;
-04 : 03c0b473;
-05 : 8f16cf30;
-06 : d708360b;
-07 : 880f36dc;
-08 : d1a275f0;
-09 : 5944e053;
-0a : c1313a53;
-0b : 4cb0c559;
-0c : 528cd209;
-0d : 1ed6d1c2;
-0e : 3fe378c9;
-0f : aa1b9ac8;
-10 : 31d374f0;
-11 : be61ec44;
-12 : 2c7a1043;
-13 : 2641125e;
-14 : 0c46e1e9;
-15 : 9860f4c3;
-16 : d9980c45;
-17 : 85005ae5;
-18 : b156d9cb;
-19 : 8a5321c3;
-1a : b603ed2b;
-1b : 2a1eb3a0;
-1c : f4b7b88b;
-1d : a1ce694f;
-1e : 469d3811;
-1f : 2185240b;
-20 : a745eb3e;
-21 : 3d2ce9c9;
-22 : e4f87c64;
-23 : 4e473b66;
-24 : f25af5e6;
-25 : 5bf0ba5c;
-26 : d9f793ee;
-27 : a5410324;
-28 : 298d0d25;
-29 : e60402c3;
-2a : 97132679;
-2b : bcd9897b;
-2c : 82a038f5;
-2d : 201cbf45;
-2e : fe6ce958;
-2f : c368dfdf;
-30 : 6a3f8ef7;
-31 : 83368a01;
-32 : 65976a6a;
-33 : 821cfabf;
-34 : 20bdc8df;
-35 : 60d97952;
-36 : 73819628;
-37 : 674070d1;
-38 : fc155d79;
-39 : d3a408b1;
-3a : bfdf2c88;
-3b : 22a2fce0;
-3c : 01e7c505;
-3d : e3e78ba0;
-3e : a049e343;
-3f : c0f1b055;
-40 : 877e1ef1;
-41 : ca871fa5;
-42 : 25ab3e85;
-43 : f9f4b822;
-44 : 90aad39a;
-45 : 08f5e44c;
-46 : 39d12cce;
-47 : 80f2ed6f;
-48 : 6a29b7d6;
-49 : 8b913cf5;
-4a : 63815e88;
-4b : 3b598e73;
-4c : 73bfa5d4;
-4d : 77c09ce3;
-4e : 839a407b;
-4f : 6433730b;
-50 : 44284f24;
-51 : f5d5762e;
-52 : b65d636d;
-53 : d1c786b8;
-54 : f3c8d2f5;
-55 : 356dc558;
-56 : 591772eb;
-57 : 79e0fdb4;
-58 : e8932f59;
-59 : 259d108a;
-5a : bb57a7f8;
-5b : 4825e3bc;
-5c : 52cf4522;
-5d : 79e4316b;
-5e : 8c0d6004;
-5f : a754e118;
-60 : 4e281ca2;
-61 : fbbc819a;
-62 : 4aee7640;
-63 : 7d333e63;
-64 : b15aaa9c;
-65 : 4f43ec26;
-66 : 1ec71c75;
-67 : 8836d7ff;
-68 : 03bf3159;
-69 : 64fe92e3;
-6a : 967a0361;
-6b : 52d392c1;
-6c : ed91cb89;
-6d : 576cc97b;
-6e : 6b3ffb6a;
-6f : 35d248a1;
-70 : f9045e40;
-71 : 67ec2a14;
-72 : c6a8d3b4;
-73 : 215bfb86;
-74 : c69c1f66;
-75 : 4244d56d;
-76 : 1b3928f3;
-77 : 731a2236;
-78 : 38d78b27;
-79 : 059c9248;
-7a : 5f87a44a;
-7b : aba5ed2e;
-7c : c0524059;
-7d : 980abb72;
-7e : 7437c9f5;
-7f : 7eceac74;
-80 : e459de2d;
-81 : 70371382;
-82 : 9e5c9169;
-83 : e019ec71;
-84 : 8a8a254a;
-85 : 5d6b1e75;
-86 : b69a1826;
-87 : 1895f4fa;
-88 : f357cacf;
-89 : d52486ab;
-8a : 1e598442;
-8b : d8d4c72d;
-8c : f8973f5f;
-8d : 7df07844;
-8e : 603c0386;
-8f : 5fa48cd0;
-90 : 7dad0b4e;
-91 : d8063146;
-92 : dd06b1d5;
-93 : a42cea93;
-94 : 937d88ca;
-95 : 0c6e9a23;
-96 : b81bdfa3;
-97 : 28077cf0;
-98 : 9aab97aa;
-99 : b6597e34;
-9a : 436fcd2b;
-9b : be8fe3e1;
-9c : dae80c2f;
-9d : e95b81e6;
-9e : 767f7b1b;
-9f : 23d2190d;
-a0 : dbd13b92;
-a1 : ba04bced;
-a2 : c59ab4a9;
-a3 : d18cd97a;
-a4 : fdc9eef9;
-a5 : e5d3431b;
-a6 : 36145dba;
-a7 : 381901fd;
-a8 : 2b84a31d;
-a9 : 56d3b835;
-aa : 82d83a4f;
-ab : 521d2b9a;
-ac : 0224591a;
-ad : 80d7ea50;
-ae : 49815eac;
-af : 9c8177e2;
-b0 : d83c171d;
-b1 : 82d4e894;
-b2 : 2da7a2cf;
-b3 : ae082f05;
-b4 : ea847ea7;
-b5 : c53a36ee;
-b6 : 9044fe8d;
-b7 : dadb18f9;
-b8 : 3631522b;
-b9 : 2bae3746;
-ba : 02d78d99;
-bb : 8e0e2771;
-bc : 2ed189db;
-bd : 63aa82eb;
-be : 754229af;
-bf : a11062b5;
-c0 : e28618e1;
-c1 : fcaf3400;
-c2 : c8a7faac;
-c3 : be56d9b0;
-c4 : 7c3f3063;
-c5 : 4d331f3f;
-c6 : 8cceb16d;
-c7 : 2d352b5d;
-c8 : 0db6cd22;
-c9 : 745ff58e;
-ca : e450c6d2;
-cb : 5567ae51;
-cc : ec2ac609;
-cd : fcced128;
-ce : 193f8e92;
-cf : 5719a6cc;
-d0 : 065cddb6;
-d1 : 04f4e1f9;
-d2 : a95d8a1e;
-d3 : d516bf8e;
-d4 : e30d671e;
-d5 : ebeeb2fe;
-d6 : b48fdd0f;
-d7 : f4b75c46;
-d8 : 4d9c9650;
-d9 : f2df58d8;
-da : 67ace373;
-db : 7ccace3c;
-dc : f4f3f5d5;
-dd : 2be9f598;
-de : f7889908;
-df : f67c2f07;
-e0 : 880a8491;
-e1 : 9c3967d0;
-e2 : d89b44d2;
-e3 : 7c21987c;
-e4 : 495e0377;
-e5 : 1c88706d;
-e6 : bf0b4325;
-e7 : 79fcc944;
-e8 : fd8c1d81;
-e9 : f4f168ae;
-ea : cf67e751;
-eb : 75907b16;
-ec : d859c7c1;
-ed : 05ef2e02;
-ee : 1f5802c9;
-ef : 8cb4928b;
-f0 : 19e65b5f;
-f1 : 9c3b7bab;
-f2 : 22bc8d7d;
-f3 : 03aa0e5f;
-f4 : 7d35f4ff;
-f5 : e5208a6e;
-f6 : 44fdd477;
-f7 : 74a81f1c;
-f8 : 6936d4f1;
-f9 : 375fc2a2;
-fa : 22a07f26;
-fb : 701c1a4d;
-fc : af4d2557;
-fd : bac85a82;
-fe : 29cff602;
-ff : 3e17ccab;
-
-END;
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_a.mif b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_a.mif
deleted file mode 100644
index 644013afb29cdd5b2d0b6a159d40a6a5ee96e2d9..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_a.mif
+++ /dev/null
@@ -1,42 +0,0 @@
-WIDTH=32;
-DEPTH=32;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-
-00 : deadbeef;
-01 : deadbeef;
-02 : deadbeef;
-03 : deadbeef;
-04 : deadbeef;
-05 : deadbeef;
-06 : deadbeef;
-07 : deadbeef;
-08 : deadbeef;
-09 : deadbeef;
-0a : deadbeef;
-0b : deadbeef;
-0c : deadbeef;
-0d : deadbeef;
-0e : deadbeef;
-0f : deadbeef;
-10 : deadbeef;
-11 : deadbeef;
-12 : deadbeef;
-13 : deadbeef;
-14 : deadbeef;
-15 : deadbeef;
-16 : deadbeef;
-17 : deadbeef;
-18 : deadbeef;
-19 : deadbeef;
-1a : deadbeef;
-1b : deadbeef;
-1c : deadbeef;
-1d : deadbeef;
-1e : deadbeef;
-1f : deadbeef;
-
-END;
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_b.mif b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_b.mif
deleted file mode 100644
index 644013afb29cdd5b2d0b6a159d40a6a5ee96e2d9..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_b.mif
+++ /dev/null
@@ -1,42 +0,0 @@
-WIDTH=32;
-DEPTH=32;
-
-ADDRESS_RADIX=HEX;
-DATA_RADIX=HEX;
-
-CONTENT BEGIN
-
-00 : deadbeef;
-01 : deadbeef;
-02 : deadbeef;
-03 : deadbeef;
-04 : deadbeef;
-05 : deadbeef;
-06 : deadbeef;
-07 : deadbeef;
-08 : deadbeef;
-09 : deadbeef;
-0a : deadbeef;
-0b : deadbeef;
-0c : deadbeef;
-0d : deadbeef;
-0e : deadbeef;
-0f : deadbeef;
-10 : deadbeef;
-11 : deadbeef;
-12 : deadbeef;
-13 : deadbeef;
-14 : deadbeef;
-15 : deadbeef;
-16 : deadbeef;
-17 : deadbeef;
-18 : deadbeef;
-19 : deadbeef;
-1a : deadbeef;
-1b : deadbeef;
-1c : deadbeef;
-1d : deadbeef;
-1e : deadbeef;
-1f : deadbeef;
-
-END;
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench.v
deleted file mode 100644
index abde694b7faa29a81eaef0eb0c52dd9c627449a5..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench.v
+++ /dev/null
@@ -1,656 +0,0 @@
-//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench (
- // inputs:
- D_iw,
- D_iw_op,
- D_iw_opx,
- D_valid,
- E_valid,
- F_pcb,
- F_valid,
- R_ctrl_ld,
- R_ctrl_ld_non_io,
- R_dst_regnum,
- R_wr_dst_reg,
- W_valid,
- W_vinst,
- W_wr_data,
- av_ld_data_aligned_unfiltered,
- clk,
- d_address,
- d_byteenable,
- d_read,
- d_write,
- i_address,
- i_read,
- i_readdata,
- i_waitrequest,
- reset_n,
-
- // outputs:
- av_ld_data_aligned_filtered,
- test_has_ended
- )
-;
-
- output [ 31: 0] av_ld_data_aligned_filtered;
- output test_has_ended;
- input [ 31: 0] D_iw;
- input [ 5: 0] D_iw_op;
- input [ 5: 0] D_iw_opx;
- input D_valid;
- input E_valid;
- input [ 17: 0] F_pcb;
- input F_valid;
- input R_ctrl_ld;
- input R_ctrl_ld_non_io;
- input [ 4: 0] R_dst_regnum;
- input R_wr_dst_reg;
- input W_valid;
- input [ 71: 0] W_vinst;
- input [ 31: 0] W_wr_data;
- input [ 31: 0] av_ld_data_aligned_unfiltered;
- input clk;
- input [ 17: 0] d_address;
- input [ 3: 0] d_byteenable;
- input d_read;
- input d_write;
- input [ 17: 0] i_address;
- input i_read;
- input [ 31: 0] i_readdata;
- input i_waitrequest;
- input reset_n;
-
-
-wire D_is_opx_inst;
-wire D_op_add;
-wire D_op_addi;
-wire D_op_and;
-wire D_op_andhi;
-wire D_op_andi;
-wire D_op_beq;
-wire D_op_bge;
-wire D_op_bgeu;
-wire D_op_blt;
-wire D_op_bltu;
-wire D_op_bne;
-wire D_op_br;
-wire D_op_break;
-wire D_op_bret;
-wire D_op_call;
-wire D_op_callr;
-wire D_op_cmpeq;
-wire D_op_cmpeqi;
-wire D_op_cmpge;
-wire D_op_cmpgei;
-wire D_op_cmpgeu;
-wire D_op_cmpgeui;
-wire D_op_cmplt;
-wire D_op_cmplti;
-wire D_op_cmpltu;
-wire D_op_cmpltui;
-wire D_op_cmpne;
-wire D_op_cmpnei;
-wire D_op_crst;
-wire D_op_custom;
-wire D_op_div;
-wire D_op_divu;
-wire D_op_eret;
-wire D_op_flushd;
-wire D_op_flushda;
-wire D_op_flushi;
-wire D_op_flushp;
-wire D_op_hbreak;
-wire D_op_initd;
-wire D_op_initda;
-wire D_op_initi;
-wire D_op_intr;
-wire D_op_jmp;
-wire D_op_jmpi;
-wire D_op_ldb;
-wire D_op_ldbio;
-wire D_op_ldbu;
-wire D_op_ldbuio;
-wire D_op_ldh;
-wire D_op_ldhio;
-wire D_op_ldhu;
-wire D_op_ldhuio;
-wire D_op_ldl;
-wire D_op_ldw;
-wire D_op_ldwio;
-wire D_op_mul;
-wire D_op_muli;
-wire D_op_mulxss;
-wire D_op_mulxsu;
-wire D_op_mulxuu;
-wire D_op_nextpc;
-wire D_op_nor;
-wire D_op_op_rsv02;
-wire D_op_op_rsv09;
-wire D_op_op_rsv10;
-wire D_op_op_rsv17;
-wire D_op_op_rsv18;
-wire D_op_op_rsv25;
-wire D_op_op_rsv26;
-wire D_op_op_rsv33;
-wire D_op_op_rsv34;
-wire D_op_op_rsv41;
-wire D_op_op_rsv42;
-wire D_op_op_rsv49;
-wire D_op_op_rsv57;
-wire D_op_op_rsv61;
-wire D_op_op_rsv62;
-wire D_op_op_rsv63;
-wire D_op_opx_rsv00;
-wire D_op_opx_rsv10;
-wire D_op_opx_rsv15;
-wire D_op_opx_rsv17;
-wire D_op_opx_rsv21;
-wire D_op_opx_rsv25;
-wire D_op_opx_rsv33;
-wire D_op_opx_rsv34;
-wire D_op_opx_rsv35;
-wire D_op_opx_rsv42;
-wire D_op_opx_rsv43;
-wire D_op_opx_rsv44;
-wire D_op_opx_rsv47;
-wire D_op_opx_rsv50;
-wire D_op_opx_rsv51;
-wire D_op_opx_rsv55;
-wire D_op_opx_rsv56;
-wire D_op_opx_rsv60;
-wire D_op_opx_rsv63;
-wire D_op_or;
-wire D_op_orhi;
-wire D_op_ori;
-wire D_op_rdctl;
-wire D_op_rdprs;
-wire D_op_ret;
-wire D_op_rol;
-wire D_op_roli;
-wire D_op_ror;
-wire D_op_sll;
-wire D_op_slli;
-wire D_op_sra;
-wire D_op_srai;
-wire D_op_srl;
-wire D_op_srli;
-wire D_op_stb;
-wire D_op_stbio;
-wire D_op_stc;
-wire D_op_sth;
-wire D_op_sthio;
-wire D_op_stw;
-wire D_op_stwio;
-wire D_op_sub;
-wire D_op_sync;
-wire D_op_trap;
-wire D_op_wrctl;
-wire D_op_wrprs;
-wire D_op_xor;
-wire D_op_xorhi;
-wire D_op_xori;
-wire [ 31: 0] av_ld_data_aligned_filtered;
-wire av_ld_data_aligned_unfiltered_0_is_x;
-wire av_ld_data_aligned_unfiltered_10_is_x;
-wire av_ld_data_aligned_unfiltered_11_is_x;
-wire av_ld_data_aligned_unfiltered_12_is_x;
-wire av_ld_data_aligned_unfiltered_13_is_x;
-wire av_ld_data_aligned_unfiltered_14_is_x;
-wire av_ld_data_aligned_unfiltered_15_is_x;
-wire av_ld_data_aligned_unfiltered_16_is_x;
-wire av_ld_data_aligned_unfiltered_17_is_x;
-wire av_ld_data_aligned_unfiltered_18_is_x;
-wire av_ld_data_aligned_unfiltered_19_is_x;
-wire av_ld_data_aligned_unfiltered_1_is_x;
-wire av_ld_data_aligned_unfiltered_20_is_x;
-wire av_ld_data_aligned_unfiltered_21_is_x;
-wire av_ld_data_aligned_unfiltered_22_is_x;
-wire av_ld_data_aligned_unfiltered_23_is_x;
-wire av_ld_data_aligned_unfiltered_24_is_x;
-wire av_ld_data_aligned_unfiltered_25_is_x;
-wire av_ld_data_aligned_unfiltered_26_is_x;
-wire av_ld_data_aligned_unfiltered_27_is_x;
-wire av_ld_data_aligned_unfiltered_28_is_x;
-wire av_ld_data_aligned_unfiltered_29_is_x;
-wire av_ld_data_aligned_unfiltered_2_is_x;
-wire av_ld_data_aligned_unfiltered_30_is_x;
-wire av_ld_data_aligned_unfiltered_31_is_x;
-wire av_ld_data_aligned_unfiltered_3_is_x;
-wire av_ld_data_aligned_unfiltered_4_is_x;
-wire av_ld_data_aligned_unfiltered_5_is_x;
-wire av_ld_data_aligned_unfiltered_6_is_x;
-wire av_ld_data_aligned_unfiltered_7_is_x;
-wire av_ld_data_aligned_unfiltered_8_is_x;
-wire av_ld_data_aligned_unfiltered_9_is_x;
-wire test_has_ended;
- assign D_op_call = D_iw_op == 0;
- assign D_op_jmpi = D_iw_op == 1;
- assign D_op_op_rsv02 = D_iw_op == 2;
- assign D_op_ldbu = D_iw_op == 3;
- assign D_op_addi = D_iw_op == 4;
- assign D_op_stb = D_iw_op == 5;
- assign D_op_br = D_iw_op == 6;
- assign D_op_ldb = D_iw_op == 7;
- assign D_op_cmpgei = D_iw_op == 8;
- assign D_op_op_rsv09 = D_iw_op == 9;
- assign D_op_op_rsv10 = D_iw_op == 10;
- assign D_op_ldhu = D_iw_op == 11;
- assign D_op_andi = D_iw_op == 12;
- assign D_op_sth = D_iw_op == 13;
- assign D_op_bge = D_iw_op == 14;
- assign D_op_ldh = D_iw_op == 15;
- assign D_op_cmplti = D_iw_op == 16;
- assign D_op_op_rsv17 = D_iw_op == 17;
- assign D_op_op_rsv18 = D_iw_op == 18;
- assign D_op_initda = D_iw_op == 19;
- assign D_op_ori = D_iw_op == 20;
- assign D_op_stw = D_iw_op == 21;
- assign D_op_blt = D_iw_op == 22;
- assign D_op_ldw = D_iw_op == 23;
- assign D_op_cmpnei = D_iw_op == 24;
- assign D_op_op_rsv25 = D_iw_op == 25;
- assign D_op_op_rsv26 = D_iw_op == 26;
- assign D_op_flushda = D_iw_op == 27;
- assign D_op_xori = D_iw_op == 28;
- assign D_op_stc = D_iw_op == 29;
- assign D_op_bne = D_iw_op == 30;
- assign D_op_ldl = D_iw_op == 31;
- assign D_op_cmpeqi = D_iw_op == 32;
- assign D_op_op_rsv33 = D_iw_op == 33;
- assign D_op_op_rsv34 = D_iw_op == 34;
- assign D_op_ldbuio = D_iw_op == 35;
- assign D_op_muli = D_iw_op == 36;
- assign D_op_stbio = D_iw_op == 37;
- assign D_op_beq = D_iw_op == 38;
- assign D_op_ldbio = D_iw_op == 39;
- assign D_op_cmpgeui = D_iw_op == 40;
- assign D_op_op_rsv41 = D_iw_op == 41;
- assign D_op_op_rsv42 = D_iw_op == 42;
- assign D_op_ldhuio = D_iw_op == 43;
- assign D_op_andhi = D_iw_op == 44;
- assign D_op_sthio = D_iw_op == 45;
- assign D_op_bgeu = D_iw_op == 46;
- assign D_op_ldhio = D_iw_op == 47;
- assign D_op_cmpltui = D_iw_op == 48;
- assign D_op_op_rsv49 = D_iw_op == 49;
- assign D_op_custom = D_iw_op == 50;
- assign D_op_initd = D_iw_op == 51;
- assign D_op_orhi = D_iw_op == 52;
- assign D_op_stwio = D_iw_op == 53;
- assign D_op_bltu = D_iw_op == 54;
- assign D_op_ldwio = D_iw_op == 55;
- assign D_op_rdprs = D_iw_op == 56;
- assign D_op_op_rsv57 = D_iw_op == 57;
- assign D_op_flushd = D_iw_op == 59;
- assign D_op_xorhi = D_iw_op == 60;
- assign D_op_op_rsv61 = D_iw_op == 61;
- assign D_op_op_rsv62 = D_iw_op == 62;
- assign D_op_op_rsv63 = D_iw_op == 63;
- assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
- assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
- assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
- assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
- assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
- assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
- assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
- assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
- assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
- assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
- assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
- assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
- assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
- assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
- assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
- assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
- assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
- assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
- assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
- assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
- assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
- assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
- assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
- assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
- assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
- assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
- assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
- assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
- assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
- assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
- assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
- assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
- assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
- assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
- assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
- assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
- assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
- assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
- assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
- assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
- assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
- assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
- assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
- assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
- assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
- assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
- assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
- assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
- assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
- assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
- assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
- assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
- assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
- assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
- assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
- assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
- assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
- assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
- assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
- assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
- assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
- assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
- assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
- assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
- assign D_is_opx_inst = D_iw_op == 58;
- assign test_has_ended = 1'b0;
-
-//synthesis translate_off
-//////////////// SIMULATION-ONLY CONTENTS
- //Clearing 'X' data bits
- assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
-
- assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
- assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
- assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
- assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
- assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
- assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
- assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
- assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
- assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
- assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
- assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
- assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
- assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
- assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
- assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
- assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
- assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
- assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
- assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
- assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
- assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
- assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
- assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
- assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
- assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
- assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
- assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
- assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
- assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
- assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
- assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
- assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
- assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
- assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
- assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
- assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
- assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
- assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
- assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
- assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
- assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
- assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
- assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
- assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
- assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
- assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
- assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
- assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
- assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
- assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
- assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
- assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
- assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
- assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
- assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
- assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
- assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
- assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
- assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
- assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
- assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
- assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
- assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
- always @(posedge clk)
- begin
- if (reset_n)
- if (^(F_valid) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/F_valid is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk)
- begin
- if (reset_n)
- if (^(D_valid) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/D_valid is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk)
- begin
- if (reset_n)
- if (^(E_valid) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/E_valid is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk)
- begin
- if (reset_n)
- if (^(W_valid) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/W_valid is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- end
- else if (W_valid)
- if (^(R_wr_dst_reg) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/R_wr_dst_reg is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- end
- else if (W_valid & R_wr_dst_reg)
- if (^(W_wr_data) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/W_wr_data is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- end
- else if (W_valid & R_wr_dst_reg)
- if (^(R_dst_regnum) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/R_dst_regnum is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk)
- begin
- if (reset_n)
- if (^(d_write) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/d_write is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- end
- else if (d_write)
- if (^(d_byteenable) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/d_byteenable is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- end
- else if (d_write | d_read)
- if (^(d_address) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/d_address is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk)
- begin
- if (reset_n)
- if (^(d_read) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/d_read is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk)
- begin
- if (reset_n)
- if (^(i_read) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/i_read is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- end
- else if (i_read)
- if (^(i_address) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/i_address is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- end
- else if (i_read & ~i_waitrequest)
- if (^(i_readdata) === 1'bx)
- begin
- $write("%0d ns: ERROR: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/i_readdata is 'x'\n", $time);
- $stop;
- end
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- end
- else if (W_valid & R_ctrl_ld)
- if (^(av_ld_data_aligned_unfiltered) === 1'bx)
- begin
- $write("%0d ns: WARNING: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
- end
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- begin
- end
- else if (W_valid & R_wr_dst_reg)
- if (^(W_wr_data) === 1'bx)
- begin
- $write("%0d ns: WARNING: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench/W_wr_data is 'x'\n", $time);
- end
- end
-
-
-
-//////////////// END SIMULATION-ONLY CONTENTS
-
-//synthesis translate_on
-//synthesis read_comments_as_HDL on
-//
-// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
-//
-//synthesis read_comments_as_HDL off
-
-endmodule
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.bsf
deleted file mode 100644
index 50f707283472f2fc982f569ebbef6f322380801e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.bsf
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 544 384)
- (text "qsys_arts_unb2b_sc3_cpu_0" (rect 185 -1 306 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 368 20 380)(font "Arial" ))
- (port
- (pt 0 72)
- (input)
- (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8)))
- (text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 192 72)(line_width 1))
- )
- (port
- (pt 544 160)
- (input)
- (text "d_readdata[31..0]" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "d_readdata[31..0]" (rect 458 149 560 160)(font "Arial" (font_size 8)))
- (line (pt 544 160)(pt 320 160)(line_width 3))
- )
- (port
- (pt 544 176)
- (input)
- (text "d_waitrequest" (rect 0 0 54 12)(font "Arial" (font_size 8)))
- (text "d_waitrequest" (rect 471 165 549 176)(font "Arial" (font_size 8)))
- (line (pt 544 176)(pt 320 176)(line_width 1))
- )
- (port
- (pt 0 112)
- (input)
- (text "debug_mem_slave_address[8..0]" (rect 0 0 135 12)(font "Arial" (font_size 8)))
- (text "debug_mem_slave_address[8..0]" (rect 4 101 178 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 192 112)(line_width 3))
- )
- (port
- (pt 0 128)
- (input)
- (text "debug_mem_slave_byteenable[3..0]" (rect 0 0 146 12)(font "Arial" (font_size 8)))
- (text "debug_mem_slave_byteenable[3..0]" (rect 4 117 196 128)(font "Arial" (font_size 8)))
- (line (pt 0 128)(pt 192 128)(line_width 3))
- )
- (port
- (pt 0 144)
- (input)
- (text "debug_mem_slave_debugaccess" (rect 0 0 135 12)(font "Arial" (font_size 8)))
- (text "debug_mem_slave_debugaccess" (rect 4 133 166 144)(font "Arial" (font_size 8)))
- (line (pt 0 144)(pt 192 144)(line_width 1))
- )
- (port
- (pt 0 160)
- (input)
- (text "debug_mem_slave_read" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "debug_mem_slave_read" (rect 4 149 124 160)(font "Arial" (font_size 8)))
- (line (pt 0 160)(pt 192 160)(line_width 1))
- )
- (port
- (pt 0 208)
- (input)
- (text "debug_mem_slave_write" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "debug_mem_slave_write" (rect 4 197 130 208)(font "Arial" (font_size 8)))
- (line (pt 0 208)(pt 192 208)(line_width 1))
- )
- (port
- (pt 0 224)
- (input)
- (text "debug_mem_slave_writedata[31..0]" (rect 0 0 141 12)(font "Arial" (font_size 8)))
- (text "debug_mem_slave_writedata[31..0]" (rect 4 213 196 224)(font "Arial" (font_size 8)))
- (line (pt 0 224)(pt 192 224)(line_width 3))
- )
- (port
- (pt 544 336)
- (input)
- (text "i_readdata[31..0]" (rect 0 0 64 12)(font "Arial" (font_size 8)))
- (text "i_readdata[31..0]" (rect 462 325 564 336)(font "Arial" (font_size 8)))
- (line (pt 544 336)(pt 320 336)(line_width 3))
- )
- (port
- (pt 544 352)
- (input)
- (text "i_waitrequest" (rect 0 0 50 12)(font "Arial" (font_size 8)))
- (text "i_waitrequest" (rect 475 341 553 352)(font "Arial" (font_size 8)))
- (line (pt 544 352)(pt 320 352)(line_width 1))
- )
- (port
- (pt 0 264)
- (input)
- (text "irq[31..0]" (rect 0 0 33 12)(font "Arial" (font_size 8)))
- (text "irq[31..0]" (rect 4 253 64 264)(font "Arial" (font_size 8)))
- (line (pt 0 264)(pt 192 264)(line_width 3))
- )
- (port
- (pt 0 304)
- (input)
- (text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8)))
- (text "reset_n" (rect 4 293 46 304)(font "Arial" (font_size 8)))
- (line (pt 0 304)(pt 192 304)(line_width 1))
- )
- (port
- (pt 0 320)
- (input)
- (text "reset_req" (rect 0 0 38 12)(font "Arial" (font_size 8)))
- (text "reset_req" (rect 4 309 58 320)(font "Arial" (font_size 8)))
- (line (pt 0 320)(pt 192 320)(line_width 1))
- )
- (port
- (pt 544 72)
- (output)
- (text "dummy_ci_port" (rect 0 0 64 12)(font "Arial" (font_size 8)))
- (text "dummy_ci_port" (rect 467 61 545 72)(font "Arial" (font_size 8)))
- (line (pt 544 72)(pt 320 72)(line_width 1))
- )
- (port
- (pt 544 112)
- (output)
- (text "d_address[17..0]" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "d_address[17..0]" (rect 461 101 557 112)(font "Arial" (font_size 8)))
- (line (pt 544 112)(pt 320 112)(line_width 3))
- )
- (port
- (pt 544 128)
- (output)
- (text "d_byteenable[3..0]" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "d_byteenable[3..0]" (rect 452 117 560 128)(font "Arial" (font_size 8)))
- (line (pt 544 128)(pt 320 128)(line_width 3))
- )
- (port
- (pt 544 144)
- (output)
- (text "d_read" (rect 0 0 28 12)(font "Arial" (font_size 8)))
- (text "d_read" (rect 507 133 543 144)(font "Arial" (font_size 8)))
- (line (pt 544 144)(pt 320 144)(line_width 1))
- )
- (port
- (pt 544 192)
- (output)
- (text "d_write" (rect 0 0 28 12)(font "Arial" (font_size 8)))
- (text "d_write" (rect 504 181 546 192)(font "Arial" (font_size 8)))
- (line (pt 544 192)(pt 320 192)(line_width 1))
- )
- (port
- (pt 544 208)
- (output)
- (text "d_writedata[31..0]" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "d_writedata[31..0]" (rect 455 197 563 208)(font "Arial" (font_size 8)))
- (line (pt 544 208)(pt 320 208)(line_width 3))
- )
- (port
- (pt 544 224)
- (output)
- (text "debug_mem_slave_debugaccess_to_roms" (rect 0 0 175 12)(font "Arial" (font_size 8)))
- (text "debug_mem_slave_debugaccess_to_roms" (rect 330 213 540 224)(font "Arial" (font_size 8)))
- (line (pt 544 224)(pt 320 224)(line_width 1))
- )
- (port
- (pt 0 176)
- (output)
- (text "debug_mem_slave_readdata[31..0]" (rect 0 0 141 12)(font "Arial" (font_size 8)))
- (text "debug_mem_slave_readdata[31..0]" (rect 4 165 190 176)(font "Arial" (font_size 8)))
- (line (pt 0 176)(pt 192 176)(line_width 3))
- )
- (port
- (pt 0 192)
- (output)
- (text "debug_mem_slave_waitrequest" (rect 0 0 127 12)(font "Arial" (font_size 8)))
- (text "debug_mem_slave_waitrequest" (rect 4 181 166 192)(font "Arial" (font_size 8)))
- (line (pt 0 192)(pt 192 192)(line_width 1))
- )
- (port
- (pt 544 264)
- (output)
- (text "debug_reset_request" (rect 0 0 84 12)(font "Arial" (font_size 8)))
- (text "debug_reset_request" (rect 436 253 550 264)(font "Arial" (font_size 8)))
- (line (pt 544 264)(pt 320 264)(line_width 1))
- )
- (port
- (pt 544 304)
- (output)
- (text "i_address[17..0]" (rect 0 0 62 12)(font "Arial" (font_size 8)))
- (text "i_address[17..0]" (rect 465 293 561 304)(font "Arial" (font_size 8)))
- (line (pt 544 304)(pt 320 304)(line_width 3))
- )
- (port
- (pt 544 320)
- (output)
- (text "i_read" (rect 0 0 24 12)(font "Arial" (font_size 8)))
- (text "i_read" (rect 511 309 547 320)(font "Arial" (font_size 8)))
- (line (pt 544 320)(pt 320 320)(line_width 1))
- )
- (drawing
- (text "clk" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 197 67 412 144)(font "Arial" (color 0 0 0)))
- (text "custom_instruction_master" (rect 321 43 792 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "readra" (rect 289 67 614 144)(font "Arial" (color 0 0 0)))
- (text "data_master" (rect 321 83 708 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 283 107 608 224)(font "Arial" (color 0 0 0)))
- (text "byteenable" (rect 271 123 602 256)(font "Arial" (color 0 0 0)))
- (text "read" (rect 298 139 620 288)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 280 155 608 320)(font "Arial" (color 0 0 0)))
- (text "waitrequest" (rect 269 171 604 352)(font "Arial" (color 0 0 0)))
- (text "write" (rect 297 187 624 384)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 279 203 612 416)(font "Arial" (color 0 0 0)))
- (text "debugaccess" (rect 262 219 590 448)(font "Arial" (color 0 0 0)))
- (text "debug_mem_slave" (rect 83 83 256 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 197 107 436 224)(font "Arial" (color 0 0 0)))
- (text "byteenable" (rect 197 123 454 256)(font "Arial" (color 0 0 0)))
- (text "debugaccess" (rect 197 139 460 288)(font "Arial" (color 0 0 0)))
- (text "read" (rect 197 155 418 320)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 197 171 442 352)(font "Arial" (color 0 0 0)))
- (text "waitrequest" (rect 197 187 460 384)(font "Arial" (color 0 0 0)))
- (text "write" (rect 197 203 424 416)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 197 219 448 448)(font "Arial" (color 0 0 0)))
- (text "debug_reset_request" (rect 321 235 756 483)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 295 259 620 528)(font "Arial" (color 0 0 0)))
- (text "instruction_master" (rect 321 275 750 563)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 283 299 608 608)(font "Arial" (color 0 0 0)))
- (text "read" (rect 298 315 620 640)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 280 331 608 672)(font "Arial" (color 0 0 0)))
- (text "waitrequest" (rect 269 347 604 704)(font "Arial" (color 0 0 0)))
- (text "irq" (rect 178 235 374 483)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "irq" (rect 197 259 412 528)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 163 275 356 563)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset_n" (rect 197 299 436 608)(font "Arial" (color 0 0 0)))
- (text "reset_req" (rect 197 315 448 640)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_cpu_0 " (rect 413 368 988 746)(font "Arial" ))
- (line (pt 192 32)(pt 320 32)(line_width 1))
- (line (pt 320 32)(pt 320 368)(line_width 1))
- (line (pt 192 368)(pt 320 368)(line_width 1))
- (line (pt 192 32)(pt 192 368)(line_width 1))
- (line (pt 193 52)(pt 193 76)(line_width 1))
- (line (pt 194 52)(pt 194 76)(line_width 1))
- (line (pt 319 52)(pt 319 76)(line_width 1))
- (line (pt 318 52)(pt 318 76)(line_width 1))
- (line (pt 319 92)(pt 319 228)(line_width 1))
- (line (pt 318 92)(pt 318 228)(line_width 1))
- (line (pt 193 92)(pt 193 228)(line_width 1))
- (line (pt 194 92)(pt 194 228)(line_width 1))
- (line (pt 319 244)(pt 319 268)(line_width 1))
- (line (pt 318 244)(pt 318 268)(line_width 1))
- (line (pt 319 284)(pt 319 356)(line_width 1))
- (line (pt 318 284)(pt 318 356)(line_width 1))
- (line (pt 193 244)(pt 193 268)(line_width 1))
- (line (pt 194 244)(pt 194 268)(line_width 1))
- (line (pt 193 284)(pt 193 324)(line_width 1))
- (line (pt 194 284)(pt 194 324)(line_width 1))
- (line (pt 0 0)(pt 544 0)(line_width 1))
- (line (pt 544 0)(pt 544 384)(line_width 1))
- (line (pt 0 384)(pt 544 384)(line_width 1))
- (line (pt 0 0)(pt 0 384)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.cmp
deleted file mode 100644
index 77987db4a900d48bfd1f1cc20d8e1144e0fb0c29..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.cmp
+++ /dev/null
@@ -1,31 +0,0 @@
- component qsys_arts_unb2b_sc3_cpu_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(17 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
- );
- end component qsys_arts_unb2b_sc3_cpu_0;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.html
deleted file mode 100644
index 29f100a8ffa82f51cc3fbcf6b7631c7d92c641bf..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.html
+++ /dev/null
@@ -1,1055 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_cpu_0</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_cpu_0</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:44:50</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>Processor
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_cpu_0"><b>qsys_arts_unb2b_sc3_cpu_0</b>
- </a> Nios II 17.0
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_cpu_0"><b>qsys_arts_unb2b_sc3_cpu_0</b>
- </a> altera_nios2_gen2 17.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- <td class="mastermodule" colspan="2">
- <a href="#module_qsys_arts_unb2b_sc3_cpu_0"><b>qsys_arts_unb2b_sc3_cpu_0</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="masterl"> data_master</td>
- <td class="masterr"> instruction_master</td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_cpu_0"><b>qsys_arts_unb2b_sc3_cpu_0</b>
- </a>
- </td>
- <td class="empty"></td>
- <td class="empty"></td>
- </tr>
- <tr>
- <td class="slaveb">debug_mem_slave </td>
- <td class="empty"></td>
- <td class="empty"></td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_cpu_0"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_cpu_0</h2>altera_nios2_gen2 v17.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">tmr_enabled</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_disable_tmr_inj</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_showUnpublishedSettings</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_showInternalSettings</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_preciseIllegalMemAccessException</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_exportPCB</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_exportdebuginfo</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_clearXBitsLDNonBypass</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_bigEndian</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_export_large_RAMs</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_asic_enabled</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">register_file_por</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_asic_synopsys_translate_on_off</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_asic_third_party_synthesis</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_asic_add_scan_mode_input</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_oci_version</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">setting_fast_register_read</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_exportHostDebugPort</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_oci_export_jtag_signals</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_avalonDebugPortPresent</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_alwaysEncrypt</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">io_regionbase</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">io_regionsize</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">setting_support31bitdcachebypass</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_activateTrace</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_allow_break_inst</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_activateTestEndChecker</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_ecc_sim_test_ports</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_disableocitrace</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_activateMonitors</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_HDLSimCachesCleared</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_HBreakTest</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_breakslaveoveride</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">mpu_useLimit</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">mpu_enabled</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">mmu_enabled</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">mmu_autoAssignTlbPtrSz</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">cpuReset</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">resetrequest_enabled</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_removeRAMinit</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_tmr_output_disable</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_shadowRegisterSets</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">mpu_numOfInstRegion</td>
- <td class="parametervalue">8</td>
- </tr>
- <tr>
- <td class="parametername">mpu_numOfDataRegion</td>
- <td class="parametervalue">8</td>
- </tr>
- <tr>
- <td class="parametername">mmu_TLBMissExcOffset</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">resetOffset</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">exceptionOffset</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">cpuID</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">breakOffset</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">userDefinedSettings</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">tracefilename</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">resetSlave</td>
- <td class="parametervalue">onchip_memory2_0.s1</td>
- </tr>
- <tr>
- <td class="parametername">mmu_TLBMissExcSlave</td>
- <td class="parametervalue">None</td>
- </tr>
- <tr>
- <td class="parametername">exceptionSlave</td>
- <td class="parametervalue">onchip_memory2_0.s1</td>
- </tr>
- <tr>
- <td class="parametername">breakSlave</td>
- <td class="parametervalue">None</td>
- </tr>
- <tr>
- <td class="parametername">setting_interruptControllerType</td>
- <td class="parametervalue">Internal</td>
- </tr>
- <tr>
- <td class="parametername">setting_branchpredictiontype</td>
- <td class="parametervalue">Dynamic</td>
- </tr>
- <tr>
- <td class="parametername">setting_bhtPtrSz</td>
- <td class="parametervalue">8</td>
- </tr>
- <tr>
- <td class="parametername">cpuArchRev</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">stratix_dspblock_shift_mul</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">shifterType</td>
- <td class="parametervalue">medium_le_shift</td>
- </tr>
- <tr>
- <td class="parametername">multiplierType</td>
- <td class="parametervalue">no_mul</td>
- </tr>
- <tr>
- <td class="parametername">mul_shift_choice</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">mul_32_impl</td>
- <td class="parametervalue">2</td>
- </tr>
- <tr>
- <td class="parametername">mul_64_impl</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">shift_rot_impl</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">dividerType</td>
- <td class="parametervalue">no_div</td>
- </tr>
- <tr>
- <td class="parametername">mpu_minInstRegionSize</td>
- <td class="parametervalue">12</td>
- </tr>
- <tr>
- <td class="parametername">mpu_minDataRegionSize</td>
- <td class="parametervalue">12</td>
- </tr>
- <tr>
- <td class="parametername">mmu_uitlbNumEntries</td>
- <td class="parametervalue">4</td>
- </tr>
- <tr>
- <td class="parametername">mmu_udtlbNumEntries</td>
- <td class="parametervalue">6</td>
- </tr>
- <tr>
- <td class="parametername">mmu_tlbPtrSz</td>
- <td class="parametervalue">7</td>
- </tr>
- <tr>
- <td class="parametername">mmu_tlbNumWays</td>
- <td class="parametervalue">16</td>
- </tr>
- <tr>
- <td class="parametername">mmu_processIDNumBits</td>
- <td class="parametervalue">8</td>
- </tr>
- <tr>
- <td class="parametername">impl</td>
- <td class="parametervalue">Tiny</td>
- </tr>
- <tr>
- <td class="parametername">icache_size</td>
- <td class="parametervalue">4096</td>
- </tr>
- <tr>
- <td class="parametername">fa_cache_line</td>
- <td class="parametervalue">2</td>
- </tr>
- <tr>
- <td class="parametername">fa_cache_linesize</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">icache_tagramBlockType</td>
- <td class="parametervalue">Automatic</td>
- </tr>
- <tr>
- <td class="parametername">icache_ramBlockType</td>
- <td class="parametervalue">Automatic</td>
- </tr>
- <tr>
- <td class="parametername">icache_numTCIM</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">icache_burstType</td>
- <td class="parametervalue">None</td>
- </tr>
- <tr>
- <td class="parametername">dcache_bursts</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">dcache_victim_buf_impl</td>
- <td class="parametervalue">ram</td>
- </tr>
- <tr>
- <td class="parametername">dcache_size</td>
- <td class="parametervalue">2048</td>
- </tr>
- <tr>
- <td class="parametername">dcache_tagramBlockType</td>
- <td class="parametervalue">Automatic</td>
- </tr>
- <tr>
- <td class="parametername">dcache_ramBlockType</td>
- <td class="parametervalue">Automatic</td>
- </tr>
- <tr>
- <td class="parametername">dcache_numTCDM</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">setting_exportvectors</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_usedesignware</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_ecc_present</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_ic_ecc_present</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_rf_ecc_present</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_mmu_ecc_present</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_dc_ecc_present</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_itcm_ecc_present</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">setting_dtcm_ecc_present</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">regfile_ramBlockType</td>
- <td class="parametervalue">Automatic</td>
- </tr>
- <tr>
- <td class="parametername">ocimem_ramBlockType</td>
- <td class="parametervalue">Automatic</td>
- </tr>
- <tr>
- <td class="parametername">ocimem_ramInit</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">mmu_ramBlockType</td>
- <td class="parametervalue">Automatic</td>
- </tr>
- <tr>
- <td class="parametername">bht_ramBlockType</td>
- <td class="parametervalue">Automatic</td>
- </tr>
- <tr>
- <td class="parametername">cdx_enabled</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">mpx_enabled</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">debug_enabled</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">debug_triggerArming</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">debug_debugReqSignals</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">debug_assignJtagInstanceID</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">debug_jtagInstanceID</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">debug_OCIOnchipTrace</td>
- <td class="parametervalue">_128</td>
- </tr>
- <tr>
- <td class="parametername">debug_hwbreakpoint</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">debug_datatrigger</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">debug_traceType</td>
- <td class="parametervalue">none</td>
- </tr>
- <tr>
- <td class="parametername">debug_traceStorage</td>
- <td class="parametervalue">onchip_trace</td>
- </tr>
- <tr>
- <td class="parametername">master_addr_map</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">instruction_master_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">instruction_master_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">flash_instruction_master_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">flash_instruction_master_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">data_master_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">data_master_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_instruction_master_0_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_instruction_master_0_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_instruction_master_1_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_instruction_master_1_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_instruction_master_2_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_instruction_master_2_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_instruction_master_3_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_instruction_master_3_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_data_master_0_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_data_master_0_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_data_master_1_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_data_master_1_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_data_master_2_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_data_master_2_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_data_master_3_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">tightly_coupled_data_master_3_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">instruction_master_high_performance_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">instruction_master_high_performance_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">data_master_high_performance_paddr_base</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">data_master_high_performance_paddr_size</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">resetAbsoluteAddr</td>
- <td class="parametervalue">131072</td>
- </tr>
- <tr>
- <td class="parametername">exceptionAbsoluteAddr</td>
- <td class="parametervalue">131104</td>
- </tr>
- <tr>
- <td class="parametername">breakAbsoluteAddr</td>
- <td class="parametervalue">6176</td>
- </tr>
- <tr>
- <td class="parametername">mmu_TLBMissExcAbsAddr</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">dcache_bursts_derived</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">dcache_size_derived</td>
- <td class="parametervalue">2048</td>
- </tr>
- <tr>
- <td class="parametername">breakSlave_derived</td>
- <td class="parametervalue">cpu_0.debug_mem_slave</td>
- </tr>
- <tr>
- <td class="parametername">dcache_lineSize_derived</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">setting_ioregionBypassDCache</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">setting_bit31BypassDCache</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">translate_on</td>
- <td class="parametervalue"> "synthesis translate_on" </td>
- </tr>
- <tr>
- <td class="parametername">translate_off</td>
- <td class="parametervalue"> "synthesis translate_off" </td>
- </tr>
- <tr>
- <td class="parametername">debug_onchiptrace</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">debug_offchiptrace</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">debug_insttrace</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">debug_datatrace</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">instAddrWidth</td>
- <td class="parametervalue">18</td>
- </tr>
- <tr>
- <td class="parametername">faAddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">dataAddrWidth</td>
- <td class="parametervalue">18</td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledDataMaster0AddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledDataMaster1AddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledDataMaster2AddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledDataMaster3AddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledInstructionMaster0AddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledInstructionMaster1AddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledInstructionMaster2AddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledInstructionMaster3AddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">dataMasterHighPerformanceAddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">instructionMasterHighPerformanceAddrWidth</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">instSlaveMapParam</td>
- <td class="parametervalue"><address-map><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map></td>
- </tr>
- <tr>
- <td class="parametername">faSlaveMapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">dataSlaveMapParam</td>
- <td class="parametervalue"><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' type='null.null' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x80' end='0x100' type='null.null' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x100' end='0x180' type='null.null' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x180' end='0x200' type='null.null' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x200' end='0x280' type='null.null' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x280' end='0x300' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x300' end='0x380' type='null.null' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x380' end='0x400' type='null.null' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x400' end='0x480' type='null.null' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x480' end='0x500' type='null.null' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x500' end='0x580' type='null.null' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x600' type='null.null' datawidth='32' /><slave name='reg_remu.mem' start='0x600' end='0x680' type='null.null' datawidth='32' /><slave name='pio_pps.mem' start='0x680' end='0x700' type='null.null' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x780' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' type='null.null' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x1080' type='null.null' datawidth='32' /><slave name='timer_0.s1' start='0x1080' end='0x10A0' type='null.null' datawidth='16' /><slave name='pio_wdi.s1' start='0x10A0' end='0x10B0' type='null.null' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10B0' end='0x10B8' type='null.null' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' type='null.null' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3080' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map></td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledDataMaster0MapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledDataMaster1MapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledDataMaster2MapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledDataMaster3MapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledInstructionMaster0MapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledInstructionMaster1MapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledInstructionMaster2MapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">tightlyCoupledInstructionMaster3MapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">dataMasterHighPerformanceMapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">instructionMasterHighPerformanceMapParam</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">clockFrequency</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamilyName</td>
- <td class="parametervalue">ARRIA10</td>
- </tr>
- <tr>
- <td class="parametername">internalIrqMaskSystemInfo</td>
- <td class="parametervalue">15</td>
- </tr>
- <tr>
- <td class="parametername">customInstSlavesSystemInfo</td>
- <td class="parametervalue"><info/></td>
- </tr>
- <tr>
- <td class="parametername">customInstSlavesSystemInfo_nios_a</td>
- <td class="parametervalue"><info/></td>
- </tr>
- <tr>
- <td class="parametername">customInstSlavesSystemInfo_nios_b</td>
- <td class="parametervalue"><info/></td>
- </tr>
- <tr>
- <td class="parametername">customInstSlavesSystemInfo_nios_c</td>
- <td class="parametervalue"><info/></td>
- </tr>
- <tr>
- <td class="parametername">deviceFeaturesSystemInfo</td>
- <td class="parametervalue">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_DEVICE</td>
- <td class="parametervalue">10AX115U2F45E1SG</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_DEVICE_SPEEDGRADE</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_CLK_CLOCK_DOMAIN</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_CLK_RESET_DOMAIN</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>
- <table>
- <tr>
- <td class="parametername">BIG_ENDIAN</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">BREAK_ADDR</td>
- <td class="parametervalue">0x00001820</td>
- </tr>
- <tr>
- <td class="parametername">CPU_ARCH_NIOS2_R1</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">CPU_FREQ</td>
- <td class="parametervalue">125000000u</td>
- </tr>
- <tr>
- <td class="parametername">CPU_ID_SIZE</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">CPU_ID_VALUE</td>
- <td class="parametervalue">0x00000000</td>
- </tr>
- <tr>
- <td class="parametername">CPU_IMPLEMENTATION</td>
- <td class="parametervalue">"tiny"</td>
- </tr>
- <tr>
- <td class="parametername">DATA_ADDR_WIDTH</td>
- <td class="parametervalue">18</td>
- </tr>
- <tr>
- <td class="parametername">DCACHE_LINE_SIZE</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">DCACHE_LINE_SIZE_LOG2</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">DCACHE_SIZE</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">EXCEPTION_ADDR</td>
- <td class="parametervalue">0x00020020</td>
- </tr>
- <tr>
- <td class="parametername">FLASH_ACCELERATOR_LINES</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">FLASH_ACCELERATOR_LINE_SIZE</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">FLUSHDA_SUPPORTED</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">HARDWARE_DIVIDE_PRESENT</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">HARDWARE_MULTIPLY_PRESENT</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">HARDWARE_MULX_PRESENT</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">HAS_DEBUG_CORE</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">HAS_DEBUG_STUB</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">HAS_ILLEGAL_INSTRUCTION_EXCEPTION</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">HAS_JMPI_INSTRUCTION</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">ICACHE_LINE_SIZE</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">ICACHE_LINE_SIZE_LOG2</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">ICACHE_SIZE</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">INST_ADDR_WIDTH</td>
- <td class="parametervalue">18</td>
- </tr>
- <tr>
- <td class="parametername">OCI_VERSION</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">RESET_ADDR</td>
- <td class="parametervalue">0x00020000</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.05 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.qgsynthc
deleted file mode 100644
index 6b3808b501be4f07adbc57134b8566e3d05ac48f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.qgsynthc
+++ /dev/null
@@ -1,1676 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_cpu_0</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_cpu_0</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_cpu_0</name>
- <uniqueName>qsys_arts_unb2b_sc3_cpu_0</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_cpu_0</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>bht_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>breakAbsoluteAddr</name>
- <value>6176</value>
- </parameter>
- <parameter>
- <name>breakOffset</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>breakSlave</name>
- <value>None</value>
- </parameter>
- <parameter>
- <name>breakSlave_derived</name>
- <value>cpu_0.debug_mem_slave</value>
- </parameter>
- <parameter>
- <name>cdx_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>clockFrequency</name>
- <value>125000000</value>
- </parameter>
- <parameter>
- <name>cpuArchRev</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>cpuID</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>cpuReset</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>customInstSlavesSystemInfo</name>
- <value><![CDATA[<info/>]]></value>
- </parameter>
- <parameter>
- <name>customInstSlavesSystemInfo_nios_a</name>
- <value><![CDATA[<info/>]]></value>
- </parameter>
- <parameter>
- <name>customInstSlavesSystemInfo_nios_b</name>
- <value><![CDATA[<info/>]]></value>
- </parameter>
- <parameter>
- <name>customInstSlavesSystemInfo_nios_c</name>
- <value><![CDATA[<info/>]]></value>
- </parameter>
- <parameter>
- <name>dataAddrWidth</name>
- <value>18</value>
- </parameter>
- <parameter>
- <name>dataMasterHighPerformanceAddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>dataMasterHighPerformanceMapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>dataSlaveMapParam</name>
- <value><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' type='null.null' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x80' end='0x100' type='null.null' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x100' end='0x180' type='null.null' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x180' end='0x200' type='null.null' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x200' end='0x280' type='null.null' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x280' end='0x300' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x300' end='0x380' type='null.null' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x380' end='0x400' type='null.null' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x400' end='0x480' type='null.null' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x480' end='0x500' type='null.null' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x500' end='0x580' type='null.null' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x600' type='null.null' datawidth='32' /><slave name='reg_remu.mem' start='0x600' end='0x680' type='null.null' datawidth='32' /><slave name='pio_pps.mem' start='0x680' end='0x700' type='null.null' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x780' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' type='null.null' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x1080' type='null.null' datawidth='32' /><slave name='timer_0.s1' start='0x1080' end='0x10A0' type='null.null' datawidth='16' /><slave name='pio_wdi.s1' start='0x10A0' end='0x10B0' type='null.null' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10B0' end='0x10B8' type='null.null' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' type='null.null' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3080' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>]]></value>
- </parameter>
- <parameter>
- <name>data_master_high_performance_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>data_master_high_performance_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>data_master_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>data_master_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>dcache_bursts</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>dcache_bursts_derived</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>dcache_lineSize_derived</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>dcache_numTCDM</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>dcache_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>dcache_size</name>
- <value>2048</value>
- </parameter>
- <parameter>
- <name>dcache_size_derived</name>
- <value>2048</value>
- </parameter>
- <parameter>
- <name>dcache_tagramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>dcache_victim_buf_impl</name>
- <value>ram</value>
- </parameter>
- <parameter>
- <name>debug_OCIOnchipTrace</name>
- <value>_128</value>
- </parameter>
- <parameter>
- <name>debug_assignJtagInstanceID</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_datatrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_datatrigger</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>debug_debugReqSignals</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_enabled</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>debug_hwbreakpoint</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>debug_insttrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_jtagInstanceID</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>debug_offchiptrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_onchiptrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_traceStorage</name>
- <value>onchip_trace</value>
- </parameter>
- <parameter>
- <name>debug_traceType</name>
- <value>none</value>
- </parameter>
- <parameter>
- <name>debug_triggerArming</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>deviceFamilyName</name>
- <value>Arria 10</value>
- </parameter>
- <parameter>
- <name>deviceFeaturesSystemInfo</name>
- <value>ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</value>
- </parameter>
- <parameter>
- <name>dividerType</name>
- <value>no_div</value>
- </parameter>
- <parameter>
- <name>exceptionAbsoluteAddr</name>
- <value>131104</value>
- </parameter>
- <parameter>
- <name>exceptionOffset</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>exceptionSlave</name>
- <value>onchip_memory2_0.s1</value>
- </parameter>
- <parameter>
- <name>faAddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>faSlaveMapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>fa_cache_line</name>
- <value>2</value>
- </parameter>
- <parameter>
- <name>fa_cache_linesize</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>flash_instruction_master_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>flash_instruction_master_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>icache_burstType</name>
- <value>None</value>
- </parameter>
- <parameter>
- <name>icache_numTCIM</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>icache_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>icache_size</name>
- <value>4096</value>
- </parameter>
- <parameter>
- <name>icache_tagramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>impl</name>
- <value>Tiny</value>
- </parameter>
- <parameter>
- <name>instAddrWidth</name>
- <value>18</value>
- </parameter>
- <parameter>
- <name>instSlaveMapParam</name>
- <value><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>]]></value>
- </parameter>
- <parameter>
- <name>instructionMasterHighPerformanceAddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>instructionMasterHighPerformanceMapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>instruction_master_high_performance_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>instruction_master_high_performance_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>instruction_master_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>instruction_master_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>internalIrqMaskSystemInfo</name>
- <value>15</value>
- </parameter>
- <parameter>
- <name>io_regionbase</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>io_regionsize</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>master_addr_map</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>mmu_TLBMissExcAbsAddr</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>mmu_TLBMissExcOffset</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>mmu_TLBMissExcSlave</name>
- <value>None</value>
- </parameter>
- <parameter>
- <name>mmu_autoAssignTlbPtrSz</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>mmu_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>mmu_processIDNumBits</name>
- <value>8</value>
- </parameter>
- <parameter>
- <name>mmu_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>mmu_tlbNumWays</name>
- <value>16</value>
- </parameter>
- <parameter>
- <name>mmu_tlbPtrSz</name>
- <value>7</value>
- </parameter>
- <parameter>
- <name>mmu_udtlbNumEntries</name>
- <value>6</value>
- </parameter>
- <parameter>
- <name>mmu_uitlbNumEntries</name>
- <value>4</value>
- </parameter>
- <parameter>
- <name>mpu_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>mpu_minDataRegionSize</name>
- <value>12</value>
- </parameter>
- <parameter>
- <name>mpu_minInstRegionSize</name>
- <value>12</value>
- </parameter>
- <parameter>
- <name>mpu_numOfDataRegion</name>
- <value>8</value>
- </parameter>
- <parameter>
- <name>mpu_numOfInstRegion</name>
- <value>8</value>
- </parameter>
- <parameter>
- <name>mpu_useLimit</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>mpx_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>mul_32_impl</name>
- <value>2</value>
- </parameter>
- <parameter>
- <name>mul_64_impl</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>mul_shift_choice</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>multiplierType</name>
- <value>no_mul</value>
- </parameter>
- <parameter>
- <name>ocimem_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>ocimem_ramInit</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>regfile_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>register_file_por</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>resetAbsoluteAddr</name>
- <value>131072</value>
- </parameter>
- <parameter>
- <name>resetOffset</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>resetSlave</name>
- <value>onchip_memory2_0.s1</value>
- </parameter>
- <parameter>
- <name>resetrequest_enabled</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_HBreakTest</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_HDLSimCachesCleared</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_activateMonitors</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_activateTestEndChecker</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_activateTrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_allow_break_inst</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_alwaysEncrypt</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_asic_add_scan_mode_input</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_asic_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_asic_synopsys_translate_on_off</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_asic_third_party_synthesis</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_avalonDebugPortPresent</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_bhtPtrSz</name>
- <value>8</value>
- </parameter>
- <parameter>
- <name>setting_bigEndian</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_bit31BypassDCache</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_branchpredictiontype</name>
- <value>Dynamic</value>
- </parameter>
- <parameter>
- <name>setting_breakslaveoveride</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_clearXBitsLDNonBypass</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_dc_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_disable_tmr_inj</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_disableocitrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_dtcm_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_ecc_present</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_ecc_sim_test_ports</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_exportHostDebugPort</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_exportPCB</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_export_large_RAMs</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_exportdebuginfo</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_exportvectors</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_fast_register_read</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_ic_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_interruptControllerType</name>
- <value>Internal</value>
- </parameter>
- <parameter>
- <name>setting_ioregionBypassDCache</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_itcm_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_mmu_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_oci_export_jtag_signals</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_oci_version</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>setting_preciseIllegalMemAccessException</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_removeRAMinit</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_rf_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_shadowRegisterSets</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>setting_showInternalSettings</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_showUnpublishedSettings</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_support31bitdcachebypass</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_tmr_output_disable</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_usedesignware</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>shift_rot_impl</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>shifterType</name>
- <value>medium_le_shift</value>
- </parameter>
- <parameter>
- <name>stratix_dspblock_shift_mul</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster0AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster0MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster1AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster1MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster2AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster2MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster3AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster3MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster0AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster0MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster1AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster1MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster2AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster2MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster3AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster3MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_0_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_0_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_1_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_1_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_2_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_2_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_3_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_3_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_0_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_0_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_1_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_1_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_2_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_2_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_3_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_3_paddr_size</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tmr_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>tracefilename</name>
- <value></value>
- </parameter>
- <parameter>
- <name>translate_off</name>
- <value> "synthesis translate_off" </value>
- </parameter>
- <parameter>
- <name>translate_on</name>
- <value> "synthesis translate_on" </value>
- </parameter>
- <parameter>
- <name>userDefinedSettings</name>
- <value></value>
- </parameter>
- </parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>altera_nios2_gen2</className>
- <version>17.0</version>
- <name>qsys_arts_unb2b_sc3_cpu_0</name>
- <uniqueName>qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_cpu_0.qsys_arts_unb2b_sc3_cpu_0</path>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">reset_bridge</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>ACTIVE_LOW_RESET</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>NUM_RESET_OUTPUTS</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>SYNCHRONOUS_EDGES</name>
- <value>deassert</value>
- </parameter>
- <parameter>
- <name>USE_RESET_REQUEST</name>
- <value>1</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>altera_reset_bridge</className>
- <version>17.0</version>
- <name>reset_bridge</name>
- <uniqueName>qsys_arts_unb2b_sc3_cpu_0_altera_reset_bridge_170_iv4agsa</uniqueName>
- <nonce>0</nonce>
- <incidentConnections>
- <incidentConnection>
- <parameters></parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>reset</className>
- <version>17.0</version>
- <name>reset_bridge.out_reset/cpu.reset</name>
- <end>cpu/reset</end>
- <start>reset_bridge/out_reset</start>
- </incidentConnection>
- <incidentConnection>
- <parameters></parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>clock</className>
- <version>17.0</version>
- <name>clock_bridge.out_clk/reset_bridge.clk</name>
- <end>reset_bridge/clk</end>
- <start>clock_bridge/out_clk</start>
- </incidentConnection>
- </incidentConnections>
- <path>qsys_arts_unb2b_sc3_cpu_0.qsys_arts_unb2b_sc3_cpu_0.reset_bridge</path>
- </instanceData>
- <children></children>
- </node>
- <node>
- <instanceKey xsi:type="xs:string">clock_bridge</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>DERIVED_CLOCK_RATE</name>
- <value>125000000</value>
- </parameter>
- <parameter>
- <name>EXPLICIT_CLOCK_RATE</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>NUM_CLOCK_OUTPUTS</name>
- <value>1</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>altera_clock_bridge</className>
- <version>17.0</version>
- <name>clock_bridge</name>
- <uniqueName>qsys_arts_unb2b_sc3_cpu_0_altera_clock_bridge_170_wbcrk5i</uniqueName>
- <nonce>0</nonce>
- <incidentConnections>
- <incidentConnection>
- <parameters></parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>clock</className>
- <version>17.0</version>
- <name>clock_bridge.out_clk/reset_bridge.clk</name>
- <end>reset_bridge/clk</end>
- <start>clock_bridge/out_clk</start>
- </incidentConnection>
- <incidentConnection>
- <parameters></parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>clock</className>
- <version>17.0</version>
- <name>clock_bridge.out_clk/cpu.clk</name>
- <end>cpu/clk</end>
- <start>clock_bridge/out_clk</start>
- </incidentConnection>
- </incidentConnections>
- <path>qsys_arts_unb2b_sc3_cpu_0.qsys_arts_unb2b_sc3_cpu_0.clock_bridge</path>
- </instanceData>
- <children></children>
- </node>
- <node>
- <instanceKey xsi:type="xs:string">cpu</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>bht_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>breakAbsoluteAddr</name>
- <value>6176</value>
- </parameter>
- <parameter>
- <name>breakOffset</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>breakSlave</name>
- <value>None</value>
- </parameter>
- <parameter>
- <name>breakSlave_derived</name>
- <value>cpu_0.debug_mem_slave</value>
- </parameter>
- <parameter>
- <name>cdx_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>clockFrequency</name>
- <value>125000000</value>
- </parameter>
- <parameter>
- <name>cpuArchRev</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>cpuID</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>cpuReset</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>cpu_name</name>
- <value>cpu</value>
- </parameter>
- <parameter>
- <name>customInstSlavesSystemInfo</name>
- <value><![CDATA[<info/>]]></value>
- </parameter>
- <parameter>
- <name>dataAddrWidth</name>
- <value>18</value>
- </parameter>
- <parameter>
- <name>dataMasterHighPerformanceAddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>dataMasterHighPerformanceMapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>dataSlaveMapParam</name>
- <value><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' type='null.null' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x80' end='0x100' type='null.null' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x100' end='0x180' type='null.null' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x180' end='0x200' type='null.null' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x200' end='0x280' type='null.null' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x280' end='0x300' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x300' end='0x380' type='null.null' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x380' end='0x400' type='null.null' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x400' end='0x480' type='null.null' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x480' end='0x500' type='null.null' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x500' end='0x580' type='null.null' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x600' type='null.null' datawidth='32' /><slave name='reg_remu.mem' start='0x600' end='0x680' type='null.null' datawidth='32' /><slave name='pio_pps.mem' start='0x680' end='0x700' type='null.null' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x780' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' type='null.null' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x1080' type='null.null' datawidth='32' /><slave name='timer_0.s1' start='0x1080' end='0x10A0' type='null.null' datawidth='16' /><slave name='pio_wdi.s1' start='0x10A0' end='0x10B0' type='null.null' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10B0' end='0x10B8' type='null.null' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' type='null.null' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3080' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>]]></value>
- </parameter>
- <parameter>
- <name>data_master_high_performance_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>data_master_high_performance_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>data_master_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>data_master_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>dcache_bursts</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>dcache_bursts_derived</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>dcache_lineSize_derived</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>dcache_numTCDM</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>dcache_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>dcache_size</name>
- <value>2048</value>
- </parameter>
- <parameter>
- <name>dcache_size_derived</name>
- <value>2048</value>
- </parameter>
- <parameter>
- <name>dcache_tagramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>dcache_victim_buf_impl</name>
- <value>ram</value>
- </parameter>
- <parameter>
- <name>debug_OCIOnchipTrace</name>
- <value>_128</value>
- </parameter>
- <parameter>
- <name>debug_assignJtagInstanceID</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_datatrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_datatrigger</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>debug_debugReqSignals</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_enabled</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>debug_hwbreakpoint</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>debug_insttrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_jtagInstanceID</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>debug_offchiptrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_onchiptrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>debug_traceStorage</name>
- <value>onchip_trace</value>
- </parameter>
- <parameter>
- <name>debug_traceType</name>
- <value>none</value>
- </parameter>
- <parameter>
- <name>debug_triggerArming</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>deviceFamilyName</name>
- <value>Arria 10</value>
- </parameter>
- <parameter>
- <name>deviceFeaturesSystemInfo</name>
- <value>ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</value>
- </parameter>
- <parameter>
- <name>dividerType</name>
- <value>no_div</value>
- </parameter>
- <parameter>
- <name>exceptionAbsoluteAddr</name>
- <value>131104</value>
- </parameter>
- <parameter>
- <name>exceptionOffset</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>exceptionSlave</name>
- <value>onchip_memory2_0.s1</value>
- </parameter>
- <parameter>
- <name>faAddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>faSlaveMapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>fa_cache_line</name>
- <value>2</value>
- </parameter>
- <parameter>
- <name>fa_cache_linesize</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>flash_instruction_master_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>flash_instruction_master_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>icache_burstType</name>
- <value>None</value>
- </parameter>
- <parameter>
- <name>icache_numTCIM</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>icache_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>icache_size</name>
- <value>4096</value>
- </parameter>
- <parameter>
- <name>icache_tagramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>impl</name>
- <value>Tiny</value>
- </parameter>
- <parameter>
- <name>instAddrWidth</name>
- <value>18</value>
- </parameter>
- <parameter>
- <name>instSlaveMapParam</name>
- <value><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>]]></value>
- </parameter>
- <parameter>
- <name>instructionMasterHighPerformanceAddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>instructionMasterHighPerformanceMapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>instruction_master_high_performance_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>instruction_master_high_performance_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>instruction_master_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>instruction_master_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>internalIrqMaskSystemInfo</name>
- <value>15</value>
- </parameter>
- <parameter>
- <name>io_regionbase</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>io_regionsize</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>master_addr_map</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>mmu_TLBMissExcAbsAddr</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>mmu_TLBMissExcOffset</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>mmu_TLBMissExcSlave</name>
- <value>None</value>
- </parameter>
- <parameter>
- <name>mmu_autoAssignTlbPtrSz</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>mmu_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>mmu_processIDNumBits</name>
- <value>8</value>
- </parameter>
- <parameter>
- <name>mmu_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>mmu_tlbNumWays</name>
- <value>16</value>
- </parameter>
- <parameter>
- <name>mmu_tlbPtrSz</name>
- <value>7</value>
- </parameter>
- <parameter>
- <name>mmu_udtlbNumEntries</name>
- <value>6</value>
- </parameter>
- <parameter>
- <name>mmu_uitlbNumEntries</name>
- <value>4</value>
- </parameter>
- <parameter>
- <name>mpu_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>mpu_minDataRegionSize</name>
- <value>12</value>
- </parameter>
- <parameter>
- <name>mpu_minInstRegionSize</name>
- <value>12</value>
- </parameter>
- <parameter>
- <name>mpu_numOfDataRegion</name>
- <value>8</value>
- </parameter>
- <parameter>
- <name>mpu_numOfInstRegion</name>
- <value>8</value>
- </parameter>
- <parameter>
- <name>mpu_useLimit</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>mpx_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>multiplierType</name>
- <value>no_mul</value>
- </parameter>
- <parameter>
- <name>ocimem_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>ocimem_ramInit</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>regfile_ramBlockType</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>register_file_por</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>resetAbsoluteAddr</name>
- <value>131072</value>
- </parameter>
- <parameter>
- <name>resetOffset</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>resetSlave</name>
- <value>onchip_memory2_0.s1</value>
- </parameter>
- <parameter>
- <name>resetrequest_enabled</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_HBreakTest</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_HDLSimCachesCleared</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_activateMonitors</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_activateTestEndChecker</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_activateTrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_allow_break_inst</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_alwaysEncrypt</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_asic_add_scan_mode_input</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_asic_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_asic_synopsys_translate_on_off</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_asic_third_party_synthesis</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_avalonDebugPortPresent</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_bhtPtrSz</name>
- <value>8</value>
- </parameter>
- <parameter>
- <name>setting_bigEndian</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_bit31BypassDCache</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_branchPredictionType</name>
- <value>Dynamic</value>
- </parameter>
- <parameter>
- <name>setting_breakslaveoveride</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_clearXBitsLDNonBypass</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_dc_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_disableocitrace</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_dtcm_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_ecc_present</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_ecc_sim_test_ports</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_exportPCB</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_export_large_RAMs</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_exportdebuginfo</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_exportvectors</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_fast_register_read</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_ic_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_interruptControllerType</name>
- <value>Internal</value>
- </parameter>
- <parameter>
- <name>setting_ioregionBypassDCache</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_itcm_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_mmu_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_oci_export_jtag_signals</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_oci_version</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>setting_preciseIllegalMemAccessException</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_removeRAMinit</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_rf_ecc_present</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_shadowRegisterSets</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>setting_showInternalSettings</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_showUnpublishedSettings</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>setting_support31bitdcachebypass</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>setting_usedesignware</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>shifterType</name>
- <value>medium_le_shift</value>
- </parameter>
- <parameter>
- <name>stratix_dspblock_shift_mul</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster0AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster0MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster1AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster1MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster2AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster2MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster3AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledDataMaster3MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster0AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster0MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster1AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster1MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster2AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster2MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster3AddrWidth</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>tightlyCoupledInstructionMaster3MapParam</name>
- <value></value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_0_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_0_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_1_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_1_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_2_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_2_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_3_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_data_master_3_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_0_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_0_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_1_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_1_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_2_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_2_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_3_paddr_base</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tightly_coupled_instruction_master_3_paddr_top</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>tmr_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>tracefilename</name>
- <value></value>
- </parameter>
- <parameter>
- <name>translate_off</name>
- <value> "synthesis translate_off" </value>
- </parameter>
- <parameter>
- <name>translate_on</name>
- <value> "synthesis translate_on" </value>
- </parameter>
- <parameter>
- <name>userDefinedSettings</name>
- <value></value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>altera_nios2_gen2_unit</className>
- <version>17.0</version>
- <name>cpu</name>
- <uniqueName>qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq</uniqueName>
- <nonce>0</nonce>
- <incidentConnections>
- <incidentConnection>
- <parameters></parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>reset</className>
- <version>17.0</version>
- <name>reset_bridge.out_reset/cpu.reset</name>
- <end>cpu/reset</end>
- <start>reset_bridge/out_reset</start>
- </incidentConnection>
- <incidentConnection>
- <parameters></parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>clock</className>
- <version>17.0</version>
- <name>clock_bridge.out_clk/cpu.clk</name>
- <end>cpu/clk</end>
- <start>clock_bridge/out_clk</start>
- </incidentConnection>
- </incidentConnections>
- <path>qsys_arts_unb2b_sc3_cpu_0.qsys_arts_unb2b_sc3_cpu_0.cpu</path>
- </instanceData>
- <children></children>
- </node>
- </children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.qip
deleted file mode 100644
index 04aa4e31f5abbc26f9ca6994cf1c77a4eba9d5d4..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.qip
+++ /dev/null
@@ -1,373 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_cpu_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_cpu_0.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_cpu_0 HAS_SOPCINFO 1 GENERATION_ID 1527684281"
-set_global_assignment -library "qsys_arts_unb2b_sc3_cpu_0" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_cpu_0.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_cpu_0" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_cpu_0.ip"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19jcHVfMF9hbHRlcmFfbmlvczJfZ2VuMl91bml0XzE3MF9pcHZ5eGlx"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_DISPLAY_NAME "TmlvcyBJSSBQcm9jZXNzb3IgVW5pdA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_INTERNAL "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_VERSION "MTcuMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE5pb3MgSUkgVW5pdCBQcm9jZXNzb3I="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Y3B1X25hbWU=::Y3B1::Y3B1X25hbWU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaG93VW5wdWJsaXNoZWRTZXR0aW5ncw==::ZmFsc2U=::U2hvdyBVbnB1Ymxpc2hlZCBTZXR0aW5ncw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaG93SW50ZXJuYWxTZXR0aW5ncw==::ZmFsc2U=::U2hvdyBJbnRlcm5hbCBWZXJpZmljYXRpb24gU2V0dGluZ3M="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19wcmVjaXNlSWxsZWdhbE1lbUFjY2Vzc0V4Y2VwdGlvbg==::ZmFsc2U=::TWlzYWxpZ25lZCBtZW1vcnkgYWNjZXNz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRQQ0I=::ZmFsc2U=::c2V0dGluZ19leHBvcnRQQ0I="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRkZWJ1Z2luZm8=::ZmFsc2U=::RXhwb3J0IEluc3RydWN0aW9uIEV4ZWN1dGlvbiBTdGF0ZXM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19jbGVhclhCaXRzTEROb25CeXBhc3M=::dHJ1ZQ==::Q2xlYXIgWCBkYXRhIGJpdHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaWdFbmRpYW4=::ZmFsc2U=::c2V0dGluZ19iaWdFbmRpYW4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRfbGFyZ2VfUkFNcw==::ZmFsc2U=::RXhwb3J0IExhcmdlIFJBTXM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX2VuYWJsZWQ=::ZmFsc2U=::QVNJQyBlbmFibGVk"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX3N5bm9wc3lzX3RyYW5zbGF0ZV9vbl9vZmY=::ZmFsc2U=::QVNJQyBTeW5vcHN5cyB0cmFuc2xhdGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX3RoaXJkX3BhcnR5X3N5bnRoZXNpcw==::ZmFsc2U=::QVNJQyB0aGlyZCBwYXJ0eSBzeW50aGVzaXM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX2FkZF9zY2FuX21vZGVfaW5wdXQ=::ZmFsc2U=::QVNJQyBhZGQgc2NhbiBtb2RlIGlucHV0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19vY2lfZXhwb3J0X2p0YWdfc2lnbmFscw==::ZmFsc2U=::RXhwb3J0IEpUQUcgc2lnbmFscw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hdmFsb25EZWJ1Z1BvcnRQcmVzZW50::ZmFsc2U=::QXZhbG9uIERlYnVnIFBvcnQgUHJlc2VudA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hbHdheXNFbmNyeXB0::dHJ1ZQ==::QWx3YXlzIGVuY3J5cHQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "cmVnaXN0ZXJfZmlsZV9wb3I=::ZmFsc2U=::UmVnaXN0ZXIgRmlsZSBQT1I="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW9fcmVnaW9uYmFzZQ==::MA==::QmFzZSBBZGRyZXNz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW9fcmVnaW9uc2l6ZQ==::MA==::U2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zdXBwb3J0MzFiaXRkY2FjaGVieXBhc3M=::dHJ1ZQ==::VXNlIG1vc3Qtc2lnbmlmaWNhbnQgYWRkcmVzcyBiaXQgaW4gcHJvY2Vzc29yIHRvIGJ5cGFzcyBkYXRhIGNhY2hl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZVRyYWNl::ZmFsc2U=::R2VuZXJhdGUgdHJhY2UgZmlsZSBkdXJpbmcgUlRMIHNpbXVsYXRpb24="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hbGxvd19icmVha19pbnN0::ZmFsc2U=::QWxsb3cgQnJlYWsgaW5zdHJ1Y3Rpb25z"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZVRlc3RFbmRDaGVja2Vy::ZmFsc2U=::QWN0aXZhdGUgdGVzdCBlbmQgY2hlY2tlcg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19lY2Nfc2ltX3Rlc3RfcG9ydHM=::ZmFsc2U=::RW5hYmxlIEVDQyBzaW11bGF0aW9uIHRlc3QgcG9ydHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kaXNhYmxlb2NpdHJhY2U=::ZmFsc2U=::RGlzYWJsZSBjb21wdHI="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZU1vbml0b3Jz::dHJ1ZQ==::QWN0aXZhdGUgbW9uaXRvcnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19IRExTaW1DYWNoZXNDbGVhcmVk::dHJ1ZQ==::SERMIHNpbXVsYXRpb24gY2FjaGVzIGNsZWFyZWQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19IQnJlYWtUZXN0::ZmFsc2U=::QWRkIEhCcmVhayBSZXF1ZXN0IHBvcnQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19icmVha3NsYXZlb3ZlcmlkZQ==::ZmFsc2U=::TWFudWFsbHkgYXNzaWduIGJyZWFrIHNsYXZl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bXB1X3VzZUxpbWl0::ZmFsc2U=::VXNlIExpbWl0IGZvciByZWdpb24gcmFuZ2U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bXB1X2VuYWJsZWQ=::ZmFsc2U=::SW5jbHVkZSBNUFU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X2VuYWJsZWQ=::ZmFsc2U=::SW5jbHVkZSBNTVU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X2F1dG9Bc3NpZ25UbGJQdHJTeg==::dHJ1ZQ==::T3B0aW1pemUgVExCIGVudHJpZXMgYmFzZSBvbiBkZXZpY2UgZmFtaWx5"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Y3B1UmVzZXQ=::ZmFsc2U=::SW5jbHVkZSBjcHVfcmVzZXRyZXF1ZXN0IGFuZCBjcHVfcmVzZXR0YWtlbiBzaWduYWxz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "cmVzZXRyZXF1ZXN0X2VuYWJsZWQ=::dHJ1ZQ==::SW5jbHVkZSByZXNldF9yZXEgc2lnbmFsIGZvciBPQ0kgUkFNIGFuZCBNdWx0aS1DeWNsZSBDdXN0b20gSW5zdHJ1Y3Rpb25z"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19yZW1vdmVSQU1pbml0::ZmFsc2U=::UmVtb3ZlIFJBTSBJbml0aWFsaXphdGlvbg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaGFkb3dSZWdpc3RlclNldHM=::MA==::TnVtYmVyIG9mIHNoYWRvdyByZWdpc3RlciBzZXRzICgwLTYzKQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bXB1X251bU9mSW5zdFJlZ2lvbg==::OA==::TnVtYmVyIG9mIGluc3RydWN0aW9uIHJlZ2lvbnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bXB1X251bU9mRGF0YVJlZ2lvbg==::OA==::TnVtYmVyIG9mIGRhdGEgcmVnaW9ucw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X1RMQk1pc3NFeGNPZmZzZXQ=::MA==::RmFzdCBUTEIgTWlzcyBFeGNlcHRpb24gdmVjdG9yIG9mZnNldA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "cmVzZXRPZmZzZXQ=::MA==::UmVzZXQgdmVjdG9yIG9mZnNldA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uT2Zmc2V0::MzI=::RXhjZXB0aW9uIHZlY3RvciBvZmZzZXQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Y3B1SUQ=::MA==::Q1BVSUQgY29udHJvbCByZWdpc3RlciB2YWx1ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "YnJlYWtPZmZzZXQ=::MzI=::QnJlYWsgdmVjdG9yIG9mZnNldA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "cmVzZXRTbGF2ZQ==::b25jaGlwX21lbW9yeTJfMC5zMQ==::UmVzZXQgdmVjdG9yIG1lbW9yeQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X1RMQk1pc3NFeGNTbGF2ZQ==::Tm9uZQ==::RmFzdCBUTEIgTWlzcyBFeGNlcHRpb24gdmVjdG9yIG1lbW9yeQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uU2xhdmU=::b25jaGlwX21lbW9yeTJfMC5zMQ==::RXhjZXB0aW9uIHZlY3RvciBtZW1vcnk="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "YnJlYWtTbGF2ZQ==::Tm9uZQ==::QnJlYWsgdmVjdG9yIG1lbW9yeQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pbnRlcnJ1cHRDb250cm9sbGVyVHlwZQ==::SW50ZXJuYWw=::SW50ZXJydXB0IGNvbnRyb2xsZXI="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19icmFuY2hQcmVkaWN0aW9uVHlwZQ==::RHluYW1pYw==::QnJhbmNoIHByZWRpY3Rpb24gdHlwZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaHRQdHJTeg==::OA==::TnVtYmVyIG9mIGVudHJpZXMgKDItYml0cyB3aWRlKQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Y3B1QXJjaFJldg==::MQ==::QXJjaGl0ZWN0dXJlIFJldmlzaW9u"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c3RyYXRpeF9kc3BibG9ja19zaGlmdF9tdWw=::ZmFsc2U=::VXNlIERTUCBCbG9jayBmb3IgU2hpZnRlciBhbmQgTXVsdGlwbGllcg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2hpZnRlclR5cGU=::bWVkaXVtX2xlX3NoaWZ0::U2hpZnRlcg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllclR5cGU=::bm9fbXVs::TXVsdGlwbGllcg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGl2aWRlclR5cGU=::bm9fZGl2::RGl2aWRlcg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bXB1X21pbkluc3RSZWdpb25TaXpl::MTI=::TWluaW11bSBpbnN0cnVjdGlvbiByZWdpb24gc2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bXB1X21pbkRhdGFSZWdpb25TaXpl::MTI=::TWluaW11bSBkYXRhIHJlZ2lvbiBzaXpl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X3VpdGxiTnVtRW50cmllcw==::NA==::TWljcm8gSVRMQiBlbnRyaWVz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X3VkdGxiTnVtRW50cmllcw==::Ng==::TWljcm8gRFRMQiBlbnRyaWVz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X3RsYlB0clN6::Nw==::VExCIGVudHJpZXM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X3RsYk51bVdheXM=::MTY=::VExCIFNldC1Bc3NvY2lhdGl2aXR5"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X3Byb2Nlc3NJRE51bUJpdHM=::OA==::UHJvY2VzcyBJRCAoUElEKSBiaXRz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW1wbA==::VGlueQ==::TmlvcyBJSSBDb3Jl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3NpemU=::NDA5Ng==::U2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZmFfY2FjaGVfbGluZQ==::Mg==::TnVtYmVyIG9mIExpbmVz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZmFfY2FjaGVfbGluZXNpemU=::MA==::TGluZSBTaXpl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3RhZ3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::VGFnIFJBTSBibG9jayB0eXBl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::RGF0YSBSQU0gYmxvY2sgdHlwZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aWNhY2hlX251bVRDSU0=::MA==::TnVtYmVyIG9mIHRpZ2h0bHkgY291cGxlZCBpbnN0cnVjdGlvbiBtYXN0ZXIgcG9ydHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aWNhY2hlX2J1cnN0VHlwZQ==::Tm9uZQ==::QWRkIGJ1cnN0Y291bnQgc2lnbmFsIHRvIGluc3RydWN0aW9uX21hc3Rlcg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2J1cnN0cw==::ZmFsc2U=::QWRkIGJ1cnN0Y291bnQgc2lnbmFsIHRvIGRhdGFfbWFzdGVy"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3ZpY3RpbV9idWZfaW1wbA==::cmFt::VmljdGltIGJ1ZmZlciBpbXBsZW1lbnRhdGlvbg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3NpemU=::MjA0OA==::U2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3RhZ3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::VGFnIFJBTSBibG9jayB0eXBl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::RGF0YSBSQU0gYmxvY2sgdHlwZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX251bVRDRE0=::MA==::TnVtYmVyIG9mIHRpZ2h0bHkgY291cGxlZCBkYXRhIG1hc3RlciBwb3J0cw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnR2ZWN0b3Jz::ZmFsc2U=::RXhwb3J0IFZlY3RvcnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ191c2VkZXNpZ253YXJl::ZmFsc2U=::VXNlIERlc2lnbndhcmUgQ29tcG9uZW50cw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19lY2NfcHJlc2VudA==::ZmFsc2U=::RUNDIFByZXNlbnQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pY19lY2NfcHJlc2VudA==::dHJ1ZQ==::SW5zdHJ1Y3Rpb24gQ2FjaGUgRUNDIFByZXNlbnQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19yZl9lY2NfcHJlc2VudA==::dHJ1ZQ==::UmVnaXN0ZXIgRmlsZSBFQ0MgUHJlc2VudA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19tbXVfZWNjX3ByZXNlbnQ=::dHJ1ZQ==::TU1VIEVDQyBQcmVzZW50"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kY19lY2NfcHJlc2VudA==::dHJ1ZQ==::RGF0YSBDYWNoZSBFQ0MgUHJlc2VudA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pdGNtX2VjY19wcmVzZW50::dHJ1ZQ==::SW5zdHJ1Y3Rpb24gVENNIEVDQyBQcmVzZW50"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kdGNtX2VjY19wcmVzZW50::dHJ1ZQ==::RGF0YSBUQ00gRUNDIFByZXNlbnQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "cmVnZmlsZV9yYW1CbG9ja1R5cGU=::QXV0b21hdGlj::UkFNIGJsb2NrIHR5cGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "b2NpbWVtX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::UkFNIGJsb2NrIHR5cGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "b2NpbWVtX3JhbUluaXQ=::ZmFsc2U=::SW5pdGlhbGl6ZWQgT0NJIFJBTQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::TU1VIFJBTSBibG9jayB0eXBl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Ymh0X3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::QkhUIFJBTSBCbG9jayBUeXBl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Y2R4X2VuYWJsZWQ=::ZmFsc2U=::Q0RYIChDb2RlIERlbnNpdHkgZVh0ZW5zaW9uKSBJbnN0cnVjdGlvbnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bXB4X2VuYWJsZWQ=::ZmFsc2U=::TVBYIChNdWx0aS1Qcm9jZXNzb3IgZVh0ZW5zaW9uKSBJbnN0cnVjdGlvbnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dG1yX2VuYWJsZWQ=::ZmFsc2U=::dG1yX2VuYWJsZWQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfZW5hYmxlZA==::dHJ1ZQ==::SW5jbHVkZSBKVEFHIERlYnVn"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfdHJpZ2dlckFybWluZw==::dHJ1ZQ==::VHJpZ2dlciBBcm1pbmc="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGVidWdSZXFTaWduYWxz::ZmFsc2U=::SW5jbHVkZSBkZWJ1Z3JlcSBhbmQgZGVidWdhY2sgU2lnbmFscw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfYXNzaWduSnRhZ0luc3RhbmNlSUQ=::ZmFsc2U=::QXNzaWduIEpUQUcgSW5zdGFuY2UgSUQgZm9yIGRlYnVnIGNvcmUgbWFudWFsbHk="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfanRhZ0luc3RhbmNlSUQ=::MA==::SlRBRyBJbnN0YW5jZSBJRCB2YWx1ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfT0NJT25jaGlwVHJhY2U=::XzEyOA==::T25jaGlwIFRyYWNlIEZyYW1lIFNpemU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfaHdicmVha3BvaW50::MA==::SGFyZHdhcmUgQnJlYWtwb2ludHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGF0YXRyaWdnZXI=::MA==::RGF0YSBUcmlnZ2Vycw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfdHJhY2VUeXBl::bm9uZQ==::VHJhY2UgVHlwZXM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfdHJhY2VTdG9yYWdl::b25jaGlwX3RyYWNl::VHJhY2UgU3RvcmFnZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19vY2lfdmVyc2lvbg==::MQ==::c2V0dGluZ19vY2lfdmVyc2lvbg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19mYXN0X3JlZ2lzdGVyX3JlYWQ=::ZmFsc2U=::c2V0dGluZ19mYXN0X3JlZ2lzdGVyX3JlYWQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bWFzdGVyX2FkZHJfbWFw::ZmFsc2U=::bWFzdGVyX2FkZHJfbWFw"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U=::MA==::aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3RvcA==::MA==::aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3RvcA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U=::MA==::Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3RvcA==::MA==::Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3RvcA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfcGFkZHJfYmFzZQ==::MA==::ZGF0YV9tYXN0ZXJfcGFkZHJfYmFzZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfcGFkZHJfdG9w::MA==::ZGF0YV9tYXN0ZXJfcGFkZHJfdG9w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX2Jhc2U=::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX2Jhc2U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX3RvcA==::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX3RvcA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX2Jhc2U=::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX2Jhc2U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX3RvcA==::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX3RvcA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX2Jhc2U=::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX2Jhc2U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX3RvcA==::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX3RvcA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX2Jhc2U=::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX2Jhc2U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX3RvcA==::MA==::dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX3RvcA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfYmFzZQ==::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfYmFzZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfdG9w::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfdG9w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfYmFzZQ==::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfYmFzZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfdG9w::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfdG9w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfYmFzZQ==::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfYmFzZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfdG9w::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfdG9w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfYmFzZQ==::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfYmFzZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfdG9w::MA==::dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfdG9w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfYmFzZQ==::MA==::aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfYmFzZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfdG9w::MA==::aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfdG9w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl9iYXNl::MA==::ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl9iYXNl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl90b3A=::MA==::ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl90b3A="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "cmVzZXRBYnNvbHV0ZUFkZHI=::MTMxMDcy::UmVzZXQgdmVjdG9y"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uQWJzb2x1dGVBZGRy::MTMxMTA0::RXhjZXB0aW9uIHZlY3Rvcg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "YnJlYWtBYnNvbHV0ZUFkZHI=::NjE3Ng==::QnJlYWsgdmVjdG9y"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "bW11X1RMQk1pc3NFeGNBYnNBZGRy::MA==::RmFzdCBUTEIgTWlzcyBFeGNlcHRpb24gdmVjdG9y"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2J1cnN0c19kZXJpdmVk::ZmFsc2U=::ZGNhY2hlX2J1cnN0c19kZXJpdmVk"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3NpemVfZGVyaXZlZA==::MjA0OA==::ZGNhY2hlX3NpemVfZGVyaXZlZA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "YnJlYWtTbGF2ZV9kZXJpdmVk::Y3B1XzAuZGVidWdfbWVtX3NsYXZl::YnJlYWtTbGF2ZV9kZXJpdmVk"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2xpbmVTaXplX2Rlcml2ZWQ=::MzI=::ZGNhY2hlX2xpbmVTaXplX2Rlcml2ZWQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pb3JlZ2lvbkJ5cGFzc0RDYWNoZQ==::ZmFsc2U=::c2V0dGluZ19pb3JlZ2lvbkJ5cGFzc0RDYWNoZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaXQzMUJ5cGFzc0RDYWNoZQ==::ZmFsc2U=::c2V0dGluZ19iaXQzMUJ5cGFzc0RDYWNoZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dHJhbnNsYXRlX29u::InN5bnRoZXNpcyB0cmFuc2xhdGVfb24i::dHJhbnNsYXRlX29u"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dHJhbnNsYXRlX29mZg==::InN5bnRoZXNpcyB0cmFuc2xhdGVfb2ZmIg==::dHJhbnNsYXRlX29mZg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfb25jaGlwdHJhY2U=::ZmFsc2U=::ZGVidWdfb25jaGlwdHJhY2U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfb2ZmY2hpcHRyYWNl::ZmFsc2U=::ZGVidWdfb2ZmY2hpcHRyYWNl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfaW5zdHRyYWNl::ZmFsc2U=::ZGVidWdfaW5zdHRyYWNl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGF0YXRyYWNl::ZmFsc2U=::ZGVidWdfZGF0YXRyYWNl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW5zdEFkZHJXaWR0aA==::MTg=::aW5zdEFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZmFBZGRyV2lkdGg=::MQ==::ZmFBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGF0YUFkZHJXaWR0aA==::MTg=::ZGF0YUFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMEFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMEFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMUFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMUFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMkFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMkFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyM0FkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyM0FkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjBBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjBBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjFBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjFBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjJBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjJBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjNBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjNBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdjcHVfMC5kZWJ1Z19tZW1fc2xhdmUnIHN0YXJ0PScweDE4MDAnIGVuZD0nMHgyMDAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J29uY2hpcF9tZW1vcnkyXzAuczEnIHN0YXJ0PScweDIwMDAwJyBlbmQ9JzB4MjEwMDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48L2FkZHJlc3MtbWFwPg==::aW5zdFNsYXZlTWFwUGFyYW0="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdwaW9fc3lzdGVtX2luZm8ubWVtJyBzdGFydD0nMHgwJyBlbmQ9JzB4ODAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncmVnX2lwX2FycmlhMTBfZTFzZ19waHlfMTBnYmFzZV9yXzI0Lm1lbScgc3RhcnQ9JzB4ODAnIGVuZD0nMHgxMDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncmVnX2ZwZ2FfdGVtcF9zZW5zLm1lbScgc3RhcnQ9JzB4MTAwJyBlbmQ9JzB4MTgwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ19mcGdhX3ZvbHRhZ2Vfc2Vucy5tZW0nIHN0YXJ0PScweDE4MCcgZW5kPScweDIwMCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdyZWdfdW5iX3BtYnVzLm1lbScgc3RhcnQ9JzB4MjAwJyBlbmQ9JzB4MjgwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ19ldGgxMGdfcXNmcF9yaW5nLm1lbScgc3RhcnQ9JzB4MjgwJyBlbmQ9JzB4MzAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ190cl8xMEdiRV9xc2ZwX3JpbmcubWVtJyBzdGFydD0nMHgzMDAnIGVuZD0nMHgzODAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncmVnX21tZHBfZGF0YS5tZW0nIHN0YXJ0PScweDM4MCcgZW5kPScweDQwMCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdyZWdfbW1kcF9jdHJsLm1lbScgc3RhcnQ9JzB4NDAwJyBlbmQ9JzB4NDgwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ19kcG1tX2RhdGEubWVtJyBzdGFydD0nMHg0ODAnIGVuZD0nMHg1MDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncmVnX2RwbW1fY3RybC5tZW0nIHN0YXJ0PScweDUwMCcgZW5kPScweDU4MCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdyZWdfZXBjcy5tZW0nIHN0YXJ0PScweDU4MCcgZW5kPScweDYwMCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdyZWdfcmVtdS5tZW0nIHN0YXJ0PScweDYwMCcgZW5kPScweDY4MCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdwaW9fcHBzLm1lbScgc3RhcnQ9JzB4NjgwJyBlbmQ9JzB4NzAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ191bmJfc2Vucy5tZW0nIHN0YXJ0PScweDcwMCcgZW5kPScweDc4MCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdhdnNfZXRoXzEubW1zX3JlZycgc3RhcnQ9JzB4NzgwJyBlbmQ9JzB4N0MwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J2F2c19ldGhfMC5tbXNfcmVnJyBzdGFydD0nMHg3QzAnIGVuZD0nMHg4MDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncm9tX3N5c3RlbV9pbmZvLm1lbScgc3RhcnQ9JzB4MTAwMCcgZW5kPScweDEwODAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ndGltZXJfMC5zMScgc3RhcnQ9JzB4MTA4MCcgZW5kPScweDEwQTAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPScxNicgLz48c2xhdmUgbmFtZT0ncGlvX3dkaS5zMScgc3RhcnQ9JzB4MTBBMCcgZW5kPScweDEwQjAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0nanRhZ191YXJ0XzAuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDEwQjAnIGVuZD0nMHgxMEI4JyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J2NwdV8wLmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MTgwMCcgZW5kPScweDIwMDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0nYXZzX2V0aF8xLm1tc190c2UnIHN0YXJ0PScweDIwMDAnIGVuZD0nMHgzMDAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ193ZGkubWVtJyBzdGFydD0nMHgzMDAwJyBlbmQ9JzB4MzA4MCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdhdnNfZXRoXzAubW1zX3RzZScgc3RhcnQ9JzB4NDAwMCcgZW5kPScweDUwMDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0nYXZzX2V0aF8xLm1tc19yYW0nIHN0YXJ0PScweDUwMDAnIGVuZD0nMHg2MDAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J2F2c19ldGhfMC5tbXNfcmFtJyBzdGFydD0nMHg2MDAwJyBlbmQ9JzB4NzAwMCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdvbmNoaXBfbWVtb3J5Ml8wLnMxJyBzdGFydD0nMHgyMDAwMCcgZW5kPScweDIxMDAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::MTI1MDAwMDAw::Y2xvY2tGcmVxdWVuY3k="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::QXJyaWEgMTA=::ZGV2aWNlRmFtaWx5TmFtZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::MTU=::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv::ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0::ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_GROUP "RW1iZWRkZWQgUHJvY2Vzc29ycw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cDovL3d3dy5hbHRlcmEuY29tL2xpdGVyYXR1cmUvaGIvbmlvczIvbjJjcHVfbmlpNXYxLnBkZg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19jcHVfMF9hbHRlcmFfbmlvczJfZ2VuMl8xNzBfcmVtN3BleQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_DISPLAY_NAME "TmlvcyBJSSBQcm9jZXNzb3I="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_VERSION "MTcuMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIE5pb3MgSUkgUHJvY2Vzc29y"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dG1yX2VuYWJsZWQ=::ZmFsc2U=::TmlvcyBJSSBUcmlwbGUgTW9kZSBSZWR1bmRhbmN5"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kaXNhYmxlX3Rtcl9pbmo=::ZmFsc2U=::RGlzYWJsZWQgVE1SIEVycm9yIEluamVjdGlvbiBQb3J0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaG93VW5wdWJsaXNoZWRTZXR0aW5ncw==::ZmFsc2U=::U2hvdyBVbnB1Ymxpc2hlZCBTZXR0aW5ncw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19zaG93SW50ZXJuYWxTZXR0aW5ncw==::ZmFsc2U=::U2hvdyBJbnRlcm5hbCBWZXJpZmljYXRpb24gU2V0dGluZ3M="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRQQ0I=::ZmFsc2U=::c2V0dGluZ19leHBvcnRQQ0I="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRkZWJ1Z2luZm8=::ZmFsc2U=::RXhwb3J0IEluc3RydWN0aW9uIEV4ZWN1dGlvbiBTdGF0ZXM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19jbGVhclhCaXRzTEROb25CeXBhc3M=::dHJ1ZQ==::Q2xlYXIgWCBkYXRhIGJpdHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaWdFbmRpYW4=::ZmFsc2U=::c2V0dGluZ19iaWdFbmRpYW4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRfbGFyZ2VfUkFNcw==::ZmFsc2U=::RXhwb3J0IExhcmdlIFJBTXM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX2VuYWJsZWQ=::ZmFsc2U=::QVNJQyBlbmFibGVk"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "cmVnaXN0ZXJfZmlsZV9wb3I=::ZmFsc2U=::UmVnaXN0ZXIgRmlsZSBQT1I="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX3N5bm9wc3lzX3RyYW5zbGF0ZV9vbl9vZmY=::ZmFsc2U=::QVNJQyBTeW5vcHN5cyB0cmFuc2xhdGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX3RoaXJkX3BhcnR5X3N5bnRoZXNpcw==::ZmFsc2U=::QVNJQyB0aGlyZCBwYXJ0eSBzeW50aGVzaXM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hc2ljX2FkZF9zY2FuX21vZGVfaW5wdXQ=::ZmFsc2U=::QVNJQyBhZGQgc2NhbiBtb2RlIGlucHV0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19vY2lfdmVyc2lvbg==::MQ==::TmlvcyBJSSBPQ0kgVmVyc2lvbg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19mYXN0X3JlZ2lzdGVyX3JlYWQ=::ZmFsc2U=::RmFzdCBSZWdpc3RlciBSZWFk"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnRIb3N0RGVidWdQb3J0::ZmFsc2U=::RXhwb3J0IERlYnVnIEhvc3QgU2xhdmU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19vY2lfZXhwb3J0X2p0YWdfc2lnbmFscw==::ZmFsc2U=::RXhwb3J0IEpUQUcgc2lnbmFscw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hdmFsb25EZWJ1Z1BvcnRQcmVzZW50::ZmFsc2U=::QXZhbG9uIERlYnVnIFBvcnQgUHJlc2VudA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hbHdheXNFbmNyeXB0::dHJ1ZQ==::QWx3YXlzIGVuY3J5cHQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZVRyYWNl::ZmFsc2U=::R2VuZXJhdGUgdHJhY2UgZmlsZSBkdXJpbmcgUlRMIHNpbXVsYXRpb24="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hbGxvd19icmVha19pbnN0::ZmFsc2U=::QWxsb3cgQnJlYWsgaW5zdHJ1Y3Rpb25z"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZVRlc3RFbmRDaGVja2Vy::ZmFsc2U=::QWN0aXZhdGUgdGVzdCBlbmQgY2hlY2tlcg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19lY2Nfc2ltX3Rlc3RfcG9ydHM=::ZmFsc2U=::RW5hYmxlIEVDQyBzaW11bGF0aW9uIHRlc3QgcG9ydHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kaXNhYmxlb2NpdHJhY2U=::ZmFsc2U=::RGlzYWJsZSBjb21wdHIgZ2VuZXJhdGlvbg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19hY3RpdmF0ZU1vbml0b3Jz::dHJ1ZQ==::QWN0aXZhdGUgbW9uaXRvcnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19IRExTaW1DYWNoZXNDbGVhcmVk::dHJ1ZQ==::SERMIHNpbXVsYXRpb24gY2FjaGVzIGNsZWFyZWQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19IQnJlYWtUZXN0::ZmFsc2U=::QWRkIEhCcmVhayBSZXF1ZXN0IHBvcnQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19icmVha3NsYXZlb3ZlcmlkZQ==::ZmFsc2U=::TWFudWFsbHkgYXNzaWduIGJyZWFrIHNsYXZl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Y3B1UmVzZXQ=::ZmFsc2U=::SW5jbHVkZSBjcHVfcmVzZXRyZXF1ZXN0IGFuZCBjcHVfcmVzZXR0YWtlbiBzaWduYWxz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "cmVzZXRyZXF1ZXN0X2VuYWJsZWQ=::dHJ1ZQ==::SW5jbHVkZSByZXNldF9yZXEgc2lnbmFsIGZvciBPQ0kgUkFNIGFuZCBNdWx0aS1DeWNsZSBDdXN0b20gSW5zdHJ1Y3Rpb25z"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19yZW1vdmVSQU1pbml0::ZmFsc2U=::UmVtb3ZlIFJBTSBJbml0aWFsaXphdGlvbg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ190bXJfb3V0cHV0X2Rpc2FibGU=::ZmFsc2U=::Q3JlYXRlIGEgc2lnbmFsIHRvIGRpc2FibGUgVE1SIG91dHB1dHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "cmVzZXRPZmZzZXQ=::MA==::UmVzZXQgdmVjdG9yIG9mZnNldA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uT2Zmc2V0::MzI=::RXhjZXB0aW9uIHZlY3RvciBvZmZzZXQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Y3B1SUQ=::MA==::Q1BVSUQgY29udHJvbCByZWdpc3RlciB2YWx1ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "YnJlYWtPZmZzZXQ=::MzI=::QnJlYWsgdmVjdG9yIG9mZnNldA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "cmVzZXRTbGF2ZQ==::b25jaGlwX21lbW9yeTJfMC5zMQ==::UmVzZXQgdmVjdG9yIG1lbW9yeQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uU2xhdmU=::b25jaGlwX21lbW9yeTJfMC5zMQ==::RXhjZXB0aW9uIHZlY3RvciBtZW1vcnk="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "YnJlYWtTbGF2ZQ==::Tm9uZQ==::QnJlYWsgdmVjdG9yIG1lbW9yeQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Y3B1QXJjaFJldg==::MQ==::QXJjaGl0ZWN0dXJlIFJldmlzaW9u"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c3RyYXRpeF9kc3BibG9ja19zaGlmdF9tdWw=::ZmFsc2U=::c3RyYXRpeF9kc3BibG9ja19zaGlmdF9tdWw="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2hpZnRlclR5cGU=::bWVkaXVtX2xlX3NoaWZ0::c2hpZnRlclR5cGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "bXVsdGlwbGllclR5cGU=::bm9fbXVs::bXVsdGlwbGllclR5cGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aW1wbA==::VGlueQ==::TmlvcyBJSSBDb3Jl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3RhZ3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::VGFnIFJBTSBibG9jayB0eXBl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aWNhY2hlX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::RGF0YSBSQU0gYmxvY2sgdHlwZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3RhZ3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::VGFnIFJBTSBibG9jayB0eXBl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::RGF0YSBSQU0gYmxvY2sgdHlwZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19leHBvcnR2ZWN0b3Jz::ZmFsc2U=::RXhwb3J0IFZlY3RvcnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ191c2VkZXNpZ253YXJl::ZmFsc2U=::VXNlIERlc2lnbndhcmUgQ29tcG9uZW50cw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19lY2NfcHJlc2VudA==::ZmFsc2U=::RUNDIFByZXNlbnQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pY19lY2NfcHJlc2VudA==::dHJ1ZQ==::SW5zdHJ1Y3Rpb24gQ2FjaGUgRUNDIFByZXNlbnQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19yZl9lY2NfcHJlc2VudA==::dHJ1ZQ==::UmVnaXN0ZXIgRmlsZSBFQ0MgUHJlc2VudA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19tbXVfZWNjX3ByZXNlbnQ=::dHJ1ZQ==::TU1VIEVDQyBQcmVzZW50"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kY19lY2NfcHJlc2VudA==::dHJ1ZQ==::RGF0YSBDYWNoZSBFQ0MgUHJlc2VudA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pdGNtX2VjY19wcmVzZW50::dHJ1ZQ==::SW5zdHJ1Y3Rpb24gVENNIEVDQyBQcmVzZW50"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19kdGNtX2VjY19wcmVzZW50::dHJ1ZQ==::RGF0YSBUQ00gRUNDIFByZXNlbnQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "cmVnZmlsZV9yYW1CbG9ja1R5cGU=::QXV0b21hdGlj::UkFNIGJsb2NrIHR5cGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "b2NpbWVtX3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::UkFNIGJsb2NrIHR5cGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "b2NpbWVtX3JhbUluaXQ=::ZmFsc2U=::SW5pdGlhbGl6ZWQgT0NJIFJBTQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "bW11X3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::TU1VIFJBTSBibG9jayB0eXBl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Ymh0X3JhbUJsb2NrVHlwZQ==::QXV0b21hdGlj::QkhUIFJBTSBCbG9jayBUeXBl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Y2R4X2VuYWJsZWQ=::ZmFsc2U=::Q0RYIChDb2RlIERlbnNpdHkgZVh0ZW5zaW9uKSBJbnN0cnVjdGlvbnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "bXB4X2VuYWJsZWQ=::ZmFsc2U=::bXB4X2VuYWJsZWQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfZW5hYmxlZA==::dHJ1ZQ==::SW5jbHVkZSBKVEFHIERlYnVn"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfdHJpZ2dlckFybWluZw==::dHJ1ZQ==::VHJpZ2dlciBBcm1pbmc="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfYXNzaWduSnRhZ0luc3RhbmNlSUQ=::ZmFsc2U=::QXNzaWduIEpUQUcgSW5zdGFuY2UgSUQgZm9yIGRlYnVnIGNvcmUgbWFudWFsbHk="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfanRhZ0luc3RhbmNlSUQ=::MA==::SlRBRyBJbnN0YW5jZSBJRCB2YWx1ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "bWFzdGVyX2FkZHJfbWFw::ZmFsc2U=::TWFudWFsbHkgU2V0IE1hc3RlciBCYXNlIEFkZHJlc3MgYW5kIFNpemU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U=::MA==::SW5zdHJ1Y3Rpb24gTWFzdGVyIEJhc2UgQWRkcmVzcw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3NpemU=::MA==::SW5zdHJ1Y3Rpb24gTWFzdGVyIFNpemU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX2Jhc2U=::MA==::Rmxhc2ggSW5zdHJ1Y3Rpb24gTWFzdGVyIEJhc2UgQWRkcmVzcw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Zmxhc2hfaW5zdHJ1Y3Rpb25fbWFzdGVyX3BhZGRyX3NpemU=::MA==::Rmxhc2ggSW5zdHJ1Y3Rpb24gTWFzdGVyIFNpemU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfcGFkZHJfYmFzZQ==::MA==::RGF0YSBNYXN0ZXIgQmFzZSBBZGRyZXNz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfcGFkZHJfc2l6ZQ==::MA==::RGF0YSBNYXN0ZXIgU2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX2Jhc2U=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAwIEJhc2UgQWRkcmVzcw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8wX3BhZGRyX3NpemU=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAwIFNpemU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX2Jhc2U=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAxIEJhc2UgQWRkcmVzcw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8xX3BhZGRyX3NpemU=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAxIFNpemU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX2Jhc2U=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAyIEJhc2UgQWRkcmVzcw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8yX3BhZGRyX3NpemU=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAyIFNpemU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX2Jhc2U=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAzIEJhc2UgQWRkcmVzcw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2luc3RydWN0aW9uX21hc3Rlcl8zX3BhZGRyX3NpemU=::MA==::VGlnaHRseSBjb3VwbGVkIEluc3RydWN0aW9uIE1hc3RlciAzIFNpemU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfYmFzZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDAgQmFzZSBBZGRyZXNz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzBfcGFkZHJfc2l6ZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDAgU2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfYmFzZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDEgQmFzZSBBZGRyZXNz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzFfcGFkZHJfc2l6ZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDEgU2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfYmFzZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDIgQmFzZSBBZGRyZXNz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzJfcGFkZHJfc2l6ZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDIgU2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfYmFzZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDMgQmFzZSBBZGRyZXNz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseV9jb3VwbGVkX2RhdGFfbWFzdGVyXzNfcGFkZHJfc2l6ZQ==::MA==::VGlnaHRseSBjb3VwbGVkIERhdGEgTWFzdGVyIDMgU2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfYmFzZQ==::MA==::SW5zdHJ1Y3Rpb24gTWFzdGVyIEhpZ2ggUGVyZm9ybWFuY2UgQmFzZSBBZGRyZXNz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25fbWFzdGVyX2hpZ2hfcGVyZm9ybWFuY2VfcGFkZHJfc2l6ZQ==::MA==::SW5zdHJ1Y3Rpb24gTWFzdGVyIEhpZ2ggUGVyZm9ybWFuY2UgU2l6ZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl9iYXNl::MA==::RGF0YSBNYXN0ZXIgSGlnaCBQZXJmb3JtYW5jZSBCYXNlIEFkZHJlc3M="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGF0YV9tYXN0ZXJfaGlnaF9wZXJmb3JtYW5jZV9wYWRkcl9zaXpl::MA==::RGF0YSBNYXN0ZXIgSGlnaCBQZXJmb3JtYW5jZSBTaXpl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "cmVzZXRBYnNvbHV0ZUFkZHI=::MTMxMDcy::UmVzZXQgdmVjdG9y"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZXhjZXB0aW9uQWJzb2x1dGVBZGRy::MTMxMTA0::RXhjZXB0aW9uIHZlY3Rvcg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "YnJlYWtBYnNvbHV0ZUFkZHI=::NjE3Ng==::QnJlYWsgdmVjdG9y"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "bW11X1RMQk1pc3NFeGNBYnNBZGRy::MA==::RmFzdCBUTEIgTWlzcyBFeGNlcHRpb24gdmVjdG9y"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2J1cnN0c19kZXJpdmVk::ZmFsc2U=::ZGNhY2hlX2J1cnN0c19kZXJpdmVk"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX3NpemVfZGVyaXZlZA==::MjA0OA==::ZGNhY2hlX3NpemVfZGVyaXZlZA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "YnJlYWtTbGF2ZV9kZXJpdmVk::Y3B1XzAuZGVidWdfbWVtX3NsYXZl::YnJlYWtTbGF2ZV9kZXJpdmVk"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGNhY2hlX2xpbmVTaXplX2Rlcml2ZWQ=::MzI=::ZGNhY2hlX2xpbmVTaXplX2Rlcml2ZWQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19pb3JlZ2lvbkJ5cGFzc0RDYWNoZQ==::ZmFsc2U=::c2V0dGluZ19pb3JlZ2lvbkJ5cGFzc0RDYWNoZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "c2V0dGluZ19iaXQzMUJ5cGFzc0RDYWNoZQ==::ZmFsc2U=::c2V0dGluZ19iaXQzMUJ5cGFzc0RDYWNoZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dHJhbnNsYXRlX29u::InN5bnRoZXNpcyB0cmFuc2xhdGVfb24i::dHJhbnNsYXRlX29u"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dHJhbnNsYXRlX29mZg==::InN5bnRoZXNpcyB0cmFuc2xhdGVfb2ZmIg==::dHJhbnNsYXRlX29mZg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfb25jaGlwdHJhY2U=::ZmFsc2U=::ZGVidWdfb25jaGlwdHJhY2U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfb2ZmY2hpcHRyYWNl::ZmFsc2U=::ZGVidWdfb2ZmY2hpcHRyYWNl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfaW5zdHRyYWNl::ZmFsc2U=::ZGVidWdfaW5zdHRyYWNl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGVidWdfZGF0YXRyYWNl::ZmFsc2U=::ZGVidWdfZGF0YXRyYWNl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aW5zdEFkZHJXaWR0aA==::MTg=::aW5zdEFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZmFBZGRyV2lkdGg=::MQ==::ZmFBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGF0YUFkZHJXaWR0aA==::MTg=::ZGF0YUFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMEFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMEFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMUFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMUFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMkFkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyMkFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyM0FkZHJXaWR0aA==::MQ==::dGlnaHRseUNvdXBsZWREYXRhTWFzdGVyM0FkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjBBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjBBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjFBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjFBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjJBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjJBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjNBZGRyV2lkdGg=::MQ==::dGlnaHRseUNvdXBsZWRJbnN0cnVjdGlvbk1hc3RlcjNBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA==::MQ==::ZGF0YU1hc3RlckhpZ2hQZXJmb3JtYW5jZUFkZHJXaWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg=::MQ==::aW5zdHJ1Y3Rpb25NYXN0ZXJIaWdoUGVyZm9ybWFuY2VBZGRyV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aW5zdFNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdjcHVfMC5kZWJ1Z19tZW1fc2xhdmUnIHN0YXJ0PScweDE4MDAnIGVuZD0nMHgyMDAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J29uY2hpcF9tZW1vcnkyXzAuczEnIHN0YXJ0PScweDIwMDAwJyBlbmQ9JzB4MjEwMDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48L2FkZHJlc3MtbWFwPg==::aW5zdFNsYXZlTWFwUGFyYW0="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGF0YVNsYXZlTWFwUGFyYW0=::PGFkZHJlc3MtbWFwPjxzbGF2ZSBuYW1lPSdwaW9fc3lzdGVtX2luZm8ubWVtJyBzdGFydD0nMHgwJyBlbmQ9JzB4ODAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncmVnX2lwX2FycmlhMTBfZTFzZ19waHlfMTBnYmFzZV9yXzI0Lm1lbScgc3RhcnQ9JzB4ODAnIGVuZD0nMHgxMDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncmVnX2ZwZ2FfdGVtcF9zZW5zLm1lbScgc3RhcnQ9JzB4MTAwJyBlbmQ9JzB4MTgwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ19mcGdhX3ZvbHRhZ2Vfc2Vucy5tZW0nIHN0YXJ0PScweDE4MCcgZW5kPScweDIwMCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdyZWdfdW5iX3BtYnVzLm1lbScgc3RhcnQ9JzB4MjAwJyBlbmQ9JzB4MjgwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ19ldGgxMGdfcXNmcF9yaW5nLm1lbScgc3RhcnQ9JzB4MjgwJyBlbmQ9JzB4MzAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ190cl8xMEdiRV9xc2ZwX3JpbmcubWVtJyBzdGFydD0nMHgzMDAnIGVuZD0nMHgzODAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncmVnX21tZHBfZGF0YS5tZW0nIHN0YXJ0PScweDM4MCcgZW5kPScweDQwMCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdyZWdfbW1kcF9jdHJsLm1lbScgc3RhcnQ9JzB4NDAwJyBlbmQ9JzB4NDgwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ19kcG1tX2RhdGEubWVtJyBzdGFydD0nMHg0ODAnIGVuZD0nMHg1MDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncmVnX2RwbW1fY3RybC5tZW0nIHN0YXJ0PScweDUwMCcgZW5kPScweDU4MCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdyZWdfZXBjcy5tZW0nIHN0YXJ0PScweDU4MCcgZW5kPScweDYwMCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdyZWdfcmVtdS5tZW0nIHN0YXJ0PScweDYwMCcgZW5kPScweDY4MCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdwaW9fcHBzLm1lbScgc3RhcnQ9JzB4NjgwJyBlbmQ9JzB4NzAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ191bmJfc2Vucy5tZW0nIHN0YXJ0PScweDcwMCcgZW5kPScweDc4MCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdhdnNfZXRoXzEubW1zX3JlZycgc3RhcnQ9JzB4NzgwJyBlbmQ9JzB4N0MwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J2F2c19ldGhfMC5tbXNfcmVnJyBzdGFydD0nMHg3QzAnIGVuZD0nMHg4MDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ncm9tX3N5c3RlbV9pbmZvLm1lbScgc3RhcnQ9JzB4MTAwMCcgZW5kPScweDEwODAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0ndGltZXJfMC5zMScgc3RhcnQ9JzB4MTA4MCcgZW5kPScweDEwQTAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPScxNicgLz48c2xhdmUgbmFtZT0ncGlvX3dkaS5zMScgc3RhcnQ9JzB4MTBBMCcgZW5kPScweDEwQjAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0nanRhZ191YXJ0XzAuYXZhbG9uX2p0YWdfc2xhdmUnIHN0YXJ0PScweDEwQjAnIGVuZD0nMHgxMEI4JyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J2NwdV8wLmRlYnVnX21lbV9zbGF2ZScgc3RhcnQ9JzB4MTgwMCcgZW5kPScweDIwMDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0nYXZzX2V0aF8xLm1tc190c2UnIHN0YXJ0PScweDIwMDAnIGVuZD0nMHgzMDAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J3JlZ193ZGkubWVtJyBzdGFydD0nMHgzMDAwJyBlbmQ9JzB4MzA4MCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdhdnNfZXRoXzAubW1zX3RzZScgc3RhcnQ9JzB4NDAwMCcgZW5kPScweDUwMDAnIHR5cGU9J251bGwubnVsbCcgZGF0YXdpZHRoPSczMicgLz48c2xhdmUgbmFtZT0nYXZzX2V0aF8xLm1tc19yYW0nIHN0YXJ0PScweDUwMDAnIGVuZD0nMHg2MDAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PHNsYXZlIG5hbWU9J2F2c19ldGhfMC5tbXNfcmFtJyBzdGFydD0nMHg2MDAwJyBlbmQ9JzB4NzAwMCcgdHlwZT0nbnVsbC5udWxsJyBkYXRhd2lkdGg9JzMyJyAvPjxzbGF2ZSBuYW1lPSdvbmNoaXBfbWVtb3J5Ml8wLnMxJyBzdGFydD0nMHgyMDAwMCcgZW5kPScweDIxMDAwJyB0eXBlPSdudWxsLm51bGwnIGRhdGF3aWR0aD0nMzInIC8+PC9hZGRyZXNzLW1hcD4=::ZGF0YVNsYXZlTWFwUGFyYW0="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Y2xvY2tGcmVxdWVuY3k=::MTI1MDAwMDAw::Y2xvY2tGcmVxdWVuY3k="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5TmFtZQ==::QXJyaWEgMTA=::ZGV2aWNlRmFtaWx5TmFtZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw==::MTU=::aW50ZXJuYWxJcnFNYXNrU3lzdGVtSW5mbw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8=::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm8="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19h::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19h"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19i::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19i"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19j::PGluZm8vPg==::Y3VzdG9tSW5zdFNsYXZlc1N5c3RlbUluZm9fbmlvc19j"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv::ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0::ZGV2aWNlRmVhdHVyZXNTeXN0ZW1JbmZv"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::MQ==::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::MQ==::QXV0byBSRVNFVF9ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_GROUP "UHJvY2Vzc29ycyBhbmQgUGVyaXBoZXJhbHMvRW1iZWRkZWQgUHJvY2Vzc29ycw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2lnYTE0MjA0OTg5NDk1MjYvaWdhMTQwOTI1Nzg5MzQzOA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2lnYTE0MjA0OTg5NDk1MjYvaWdhMTQwOTI1Nzg5MzQzOA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5Nzg2NzI5OA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19jcHVfMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDI4MQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19EQVRBX01BU1RFUl9BRERSRVNTX1dJRFRI::LTE=::QXV0byBBRERSRVNTX1dJRFRI"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19JTlNUUlVDVElPTl9NQVNURVJfQUREUkVTU19XSURUSA==::LTE=::QXV0byBBRERSRVNTX1dJRFRI"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0" -library "qsys_arts_unb2b_sc3_cpu_0" -name IP_COMPONENT_PARAMETER "QVVUT19JUlFfSU5URVJSVVBUU19VU0VE::LTE=::QXV0byBJTlRFUlJVUFRTX1VTRUQ="
-
-set_global_assignment -library "altera_nios2_gen2_unit_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.v"]
-set_global_assignment -library "altera_nios2_gen2_unit_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk.v"]
-set_global_assignment -library "altera_nios2_gen2_unit_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper.v"]
-set_global_assignment -library "altera_nios2_gen2_unit_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench.v"]
-set_global_assignment -library "altera_nios2_gen2_unit_170" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_a.mif"]
-set_global_assignment -library "altera_nios2_gen2_unit_170" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_b.mif"]
-set_global_assignment -library "altera_nios2_gen2_unit_170" -name SDC_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.sdc"]
-set_global_assignment -library "altera_nios2_gen2_unit_170" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_default_contents.mif"]
-set_global_assignment -library "altera_nios2_gen2_unit_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck.v"]
-set_global_assignment -library "altera_nios2_gen2_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_nios2_gen2_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey.v"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_cpu_0" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_cpu_0.vhd"]
-
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_TOOL_NAME "altera_nios2_gen2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_TOOL_VERSION "17.0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey" -library "altera_nios2_gen2_170" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_TOOL_NAME "altera_nios2_gen2_unit"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_TOOL_VERSION "17.0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq" -library "altera_nios2_gen2_unit_170" -name IP_TOOL_ENV "QsysPrimePro"
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.sopcinfo
deleted file mode 100644
index 0c903fc1cf647e896afee13037bd80333105f70f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.sopcinfo
+++ /dev/null
@@ -1,3477 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_cpu_0"
- kind="qsys_arts_unb2b_sc3_cpu_0"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:44:48 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684281</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_CLK_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_DATA_MASTER_ADDRESS_MAP">
- <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>data_master</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_DATA_MASTER_ADDRESS_WIDTH">
- <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>data_master</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_INSTRUCTION_MASTER_ADDRESS_MAP">
- <type>com.altera.entityinterfaces.moduleext.AddressMap</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>instruction_master</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_INSTRUCTION_MASTER_ADDRESS_WIDTH">
- <type>com.altera.entityinterfaces.moduleext.AddressWidthType</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>instruction_master</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_IRQ_INTERRUPTS_USED">
- <type>java.math.BigInteger</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>INTERRUPTS_USED</sysinfo_type>
- <sysinfo_arg>irq</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_cpu_0"
- kind="altera_nios2_gen2"
- version="17.0"
- path="qsys_arts_unb2b_sc3_cpu_0">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <assignment>
- <name>debug.hostConnection</name>
- <value>type jtag id 70:34|110:135</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.BIG_ENDIAN</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.BREAK_ADDR</name>
- <value>0x00001820</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</name>
- <value></value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.CPU_FREQ</name>
- <value>125000000u</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.CPU_ID_SIZE</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.CPU_ID_VALUE</name>
- <value>0x00000000</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.CPU_IMPLEMENTATION</name>
- <value>"tiny"</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.DATA_ADDR_WIDTH</name>
- <value>18</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.DCACHE_LINE_SIZE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.DCACHE_LINE_SIZE_LOG2</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.DCACHE_SIZE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.EXCEPTION_ADDR</name>
- <value>0x00020020</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINES</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.FLASH_ACCELERATOR_LINE_SIZE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.FLUSHDA_SUPPORTED</name>
- <value></value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HARDWARE_DIVIDE_PRESENT</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HARDWARE_MULX_PRESENT</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HAS_DEBUG_CORE</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HAS_DEBUG_STUB</name>
- <value></value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HAS_ILLEGAL_INSTRUCTION_EXCEPTION</name>
- <value></value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HAS_JMPI_INSTRUCTION</name>
- <value></value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.ICACHE_LINE_SIZE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.ICACHE_LINE_SIZE_LOG2</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.ICACHE_SIZE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.INST_ADDR_WIDTH</name>
- <value>18</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.OCI_VERSION</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.RESET_ADDR</name>
- <value>0x00020000</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.DataCacheVictimBufImpl</name>
- <value>ram</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.HDLSimCachesCleared</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.breakOffset</name>
- <value>32</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.breakSlave</name>
- <value>cpu_0.debug_mem_slave</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.cpuArchitecture</name>
- <value>Nios II</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.exceptionOffset</name>
- <value>32</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.exceptionSlave</name>
- <value>onchip_memory2_0.s1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.resetOffset</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.resetSlave</name>
- <value>onchip_memory2_0.s1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.compatible</name>
- <value>altr,nios2-1.1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.group</name>
- <value>cpu</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.name</name>
- <value>nios2</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.altr,exception-addr</name>
- <value>0x00020020</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.altr,implementation</name>
- <value>"tiny"</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.altr,reset-addr</name>
- <value>0x00020000</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.clock-frequency</name>
- <value>125000000u</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.dcache-line-size</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.dcache-size</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.icache-line-size</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.icache-size</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.vendor</name>
- <value>altr</value>
- </assignment>
- <parameter name="tmr_enabled">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_disable_tmr_inj">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_showUnpublishedSettings">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_showInternalSettings">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_preciseIllegalMemAccessException">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_exportPCB">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_exportdebuginfo">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_clearXBitsLDNonBypass">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_bigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_export_large_RAMs">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_asic_enabled">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="register_file_por">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_asic_synopsys_translate_on_off">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_asic_third_party_synthesis">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_asic_add_scan_mode_input">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_oci_version">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_fast_register_read">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_exportHostDebugPort">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_oci_export_jtag_signals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_avalonDebugPortPresent">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_alwaysEncrypt">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="io_regionbase">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="io_regionsize">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_support31bitdcachebypass">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_activateTrace">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_allow_break_inst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_activateTestEndChecker">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_ecc_sim_test_ports">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_disableocitrace">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_activateMonitors">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_HDLSimCachesCleared">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_HBreakTest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_breakslaveoveride">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mpu_useLimit">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mpu_enabled">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_enabled">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_autoAssignTlbPtrSz">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="cpuReset">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="resetrequest_enabled">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_removeRAMinit">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_tmr_output_disable">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_shadowRegisterSets">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mpu_numOfInstRegion">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mpu_numOfDataRegion">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_TLBMissExcOffset">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="resetOffset">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="exceptionOffset">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="cpuID">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="breakOffset">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="userDefinedSettings">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tracefilename">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="resetSlave">
- <type>java.lang.String</type>
- <value>onchip_memory2_0.s1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_TLBMissExcSlave">
- <type>java.lang.String</type>
- <value>None</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="exceptionSlave">
- <type>java.lang.String</type>
- <value>onchip_memory2_0.s1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="breakSlave">
- <type>java.lang.String</type>
- <value>None</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_interruptControllerType">
- <type>java.lang.String</type>
- <value>Internal</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_branchpredictiontype">
- <type>java.lang.String</type>
- <value>Dynamic</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_bhtPtrSz">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="cpuArchRev">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="stratix_dspblock_shift_mul">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="shifterType">
- <type>java.lang.String</type>
- <value>medium_le_shift</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="multiplierType">
- <type>java.lang.String</type>
- <value>no_mul</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mul_shift_choice">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mul_32_impl">
- <type>int</type>
- <value>2</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mul_64_impl">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="shift_rot_impl">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dividerType">
- <type>java.lang.String</type>
- <value>no_div</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mpu_minInstRegionSize">
- <type>int</type>
- <value>12</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mpu_minDataRegionSize">
- <type>int</type>
- <value>12</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_uitlbNumEntries">
- <type>int</type>
- <value>4</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_udtlbNumEntries">
- <type>int</type>
- <value>6</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_tlbPtrSz">
- <type>int</type>
- <value>7</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_tlbNumWays">
- <type>int</type>
- <value>16</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_processIDNumBits">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="impl">
- <type>java.lang.String</type>
- <value>Tiny</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="icache_size">
- <type>int</type>
- <value>4096</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="fa_cache_line">
- <type>int</type>
- <value>2</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="fa_cache_linesize">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="icache_tagramBlockType">
- <type>java.lang.String</type>
- <value>Automatic</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="icache_ramBlockType">
- <type>java.lang.String</type>
- <value>Automatic</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="icache_numTCIM">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="icache_burstType">
- <type>java.lang.String</type>
- <value>None</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dcache_bursts">
- <type>java.lang.String</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dcache_victim_buf_impl">
- <type>java.lang.String</type>
- <value>ram</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dcache_size">
- <type>int</type>
- <value>2048</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dcache_tagramBlockType">
- <type>java.lang.String</type>
- <value>Automatic</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dcache_ramBlockType">
- <type>java.lang.String</type>
- <value>Automatic</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dcache_numTCDM">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_exportvectors">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_usedesignware">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_ecc_present">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_ic_ecc_present">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_rf_ecc_present">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_mmu_ecc_present">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_dc_ecc_present">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_itcm_ecc_present">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_dtcm_ecc_present">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="regfile_ramBlockType">
- <type>java.lang.String</type>
- <value>Automatic</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ocimem_ramBlockType">
- <type>java.lang.String</type>
- <value>Automatic</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ocimem_ramInit">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_ramBlockType">
- <type>java.lang.String</type>
- <value>Automatic</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bht_ramBlockType">
- <type>java.lang.String</type>
- <value>Automatic</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="cdx_enabled">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mpx_enabled">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_enabled">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_triggerArming">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_debugReqSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_assignJtagInstanceID">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_jtagInstanceID">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_OCIOnchipTrace">
- <type>java.lang.String</type>
- <value>_128</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_hwbreakpoint">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_datatrigger">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_traceType">
- <type>java.lang.String</type>
- <value>none</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_traceStorage">
- <type>java.lang.String</type>
- <value>onchip_trace</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="master_addr_map">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="instruction_master_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="instruction_master_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="flash_instruction_master_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="flash_instruction_master_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="data_master_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="data_master_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_instruction_master_0_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_instruction_master_0_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_instruction_master_1_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_instruction_master_1_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_instruction_master_2_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_instruction_master_2_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_instruction_master_3_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_instruction_master_3_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_data_master_0_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_data_master_0_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_data_master_1_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_data_master_1_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_data_master_2_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_data_master_2_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_data_master_3_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="tightly_coupled_data_master_3_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="instruction_master_high_performance_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="instruction_master_high_performance_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="data_master_high_performance_paddr_base">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="data_master_high_performance_paddr_size">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="resetAbsoluteAddr">
- <type>int</type>
- <value>131072</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="exceptionAbsoluteAddr">
- <type>int</type>
- <value>131104</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="breakAbsoluteAddr">
- <type>int</type>
- <value>6176</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mmu_TLBMissExcAbsAddr">
- <type>int</type>
- <value>0</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dcache_bursts_derived">
- <type>java.lang.String</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dcache_size_derived">
- <type>int</type>
- <value>2048</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="breakSlave_derived">
- <type>java.lang.String</type>
- <value>cpu_0.debug_mem_slave</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dcache_lineSize_derived">
- <type>int</type>
- <value>32</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_ioregionBypassDCache">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setting_bit31BypassDCache">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="translate_on">
- <type>java.lang.String</type>
- <value> "synthesis translate_on" </value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="translate_off">
- <type>java.lang.String</type>
- <value> "synthesis translate_off" </value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_onchiptrace">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_offchiptrace">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_insttrace">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="debug_datatrace">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="instAddrWidth">
- <type>int</type>
- <value>18</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>instruction_master</sysinfo_arg>
- </parameter>
- <parameter name="faAddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>flash_instruction_master</sysinfo_arg>
- </parameter>
- <parameter name="dataAddrWidth">
- <type>int</type>
- <value>18</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>data_master</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledDataMaster0AddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>tightly_coupled_data_master_0</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledDataMaster1AddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>tightly_coupled_data_master_1</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledDataMaster2AddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>tightly_coupled_data_master_2</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledDataMaster3AddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>tightly_coupled_data_master_3</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledInstructionMaster0AddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>tightly_coupled_instruction_master_0</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledInstructionMaster1AddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>tightly_coupled_instruction_master_1</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledInstructionMaster2AddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>tightly_coupled_instruction_master_2</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledInstructionMaster3AddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>tightly_coupled_instruction_master_3</sysinfo_arg>
- </parameter>
- <parameter name="dataMasterHighPerformanceAddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>data_master_high_performance</sysinfo_arg>
- </parameter>
- <parameter name="instructionMasterHighPerformanceAddrWidth">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_WIDTH</sysinfo_type>
- <sysinfo_arg>instruction_master_high_performance</sysinfo_arg>
- </parameter>
- <parameter name="instSlaveMapParam">
- <type>java.lang.String</type>
- <value><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>]]></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>instruction_master</sysinfo_arg>
- </parameter>
- <parameter name="faSlaveMapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>flash_instruction_master</sysinfo_arg>
- </parameter>
- <parameter name="dataSlaveMapParam">
- <type>java.lang.String</type>
- <value><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' type='null.null' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x80' end='0x100' type='null.null' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x100' end='0x180' type='null.null' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x180' end='0x200' type='null.null' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x200' end='0x280' type='null.null' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x280' end='0x300' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x300' end='0x380' type='null.null' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x380' end='0x400' type='null.null' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x400' end='0x480' type='null.null' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x480' end='0x500' type='null.null' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x500' end='0x580' type='null.null' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x600' type='null.null' datawidth='32' /><slave name='reg_remu.mem' start='0x600' end='0x680' type='null.null' datawidth='32' /><slave name='pio_pps.mem' start='0x680' end='0x700' type='null.null' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x780' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' type='null.null' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x1080' type='null.null' datawidth='32' /><slave name='timer_0.s1' start='0x1080' end='0x10A0' type='null.null' datawidth='16' /><slave name='pio_wdi.s1' start='0x10A0' end='0x10B0' type='null.null' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10B0' end='0x10B8' type='null.null' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' type='null.null' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3080' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>]]></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>data_master</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledDataMaster0MapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>tightly_coupled_data_master_0</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledDataMaster1MapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>tightly_coupled_data_master_1</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledDataMaster2MapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>tightly_coupled_data_master_2</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledDataMaster3MapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>tightly_coupled_data_master_3</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledInstructionMaster0MapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>tightly_coupled_instruction_master_0</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledInstructionMaster1MapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>tightly_coupled_instruction_master_1</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledInstructionMaster2MapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>tightly_coupled_instruction_master_2</sysinfo_arg>
- </parameter>
- <parameter name="tightlyCoupledInstructionMaster3MapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>tightly_coupled_instruction_master_3</sysinfo_arg>
- </parameter>
- <parameter name="dataMasterHighPerformanceMapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>data_master_high_performance</sysinfo_arg>
- </parameter>
- <parameter name="instructionMasterHighPerformanceMapParam">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>ADDRESS_MAP</sysinfo_type>
- <sysinfo_arg>instruction_master_high_performance</sysinfo_arg>
- </parameter>
- <parameter name="clockFrequency">
- <type>long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamilyName">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="internalIrqMaskSystemInfo">
- <type>long</type>
- <value>15</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>INTERRUPTS_USED</sysinfo_type>
- <sysinfo_arg>irq</sysinfo_arg>
- </parameter>
- <parameter name="customInstSlavesSystemInfo">
- <type>java.lang.String</type>
- <value><![CDATA[<info/>]]></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
- <sysinfo_arg>custom_instruction_master</sysinfo_arg>
- </parameter>
- <parameter name="customInstSlavesSystemInfo_nios_a">
- <type>java.lang.String</type>
- <value><![CDATA[<info/>]]></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
- <sysinfo_arg>custom_instruction_master_a</sysinfo_arg>
- </parameter>
- <parameter name="customInstSlavesSystemInfo_nios_b">
- <type>java.lang.String</type>
- <value><![CDATA[<info/>]]></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
- <sysinfo_arg>custom_instruction_master_b</sysinfo_arg>
- </parameter>
- <parameter name="customInstSlavesSystemInfo_nios_c">
- <type>java.lang.String</type>
- <value><![CDATA[<info/>]]></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CUSTOM_INSTRUCTION_SLAVES</sysinfo_type>
- <sysinfo_arg>custom_instruction_master_c</sysinfo_arg>
- </parameter>
- <parameter name="deviceFeaturesSystemInfo">
- <type>java.lang.String</type>
- <value>ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_CLK_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="clk" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface
- name="custom_instruction_master"
- kind="nios_custom_instruction_master"
- version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="CIName">
- <type>java.lang.String</type>
- <value></value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressWidth">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockCycle">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="enabled">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maxAddressWidth">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="opcodeExtension">
- <type>int</type>
- <value>0</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="sharedCombinationalAndMulticycle">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>nios_custom_instruction</type>
- <isStart>true</isStart>
- <port>
- <name>dummy_ci_port</name>
- <direction>Output</direction>
- <width>1</width>
- <role>readra</role>
- </port>
- </interface>
- <interface name="data_master" kind="avalon_master" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>debug.providesServices</name>
- <value>master</value>
- </assignment>
- <parameter name="adaptsTo">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>SYMBOLS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dBSBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="doStreamReads">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="doStreamWrites">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isAsynchronous">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isReadable">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isWriteable">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maxAddressWidth">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>true</isStart>
- <port>
- <name>d_address</name>
- <direction>Output</direction>
- <width>18</width>
- <role>address</role>
- </port>
- <port>
- <name>d_byteenable</name>
- <direction>Output</direction>
- <width>4</width>
- <role>byteenable</role>
- </port>
- <port>
- <name>d_read</name>
- <direction>Output</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>d_readdata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- <port>
- <name>d_waitrequest</name>
- <direction>Input</direction>
- <width>1</width>
- <role>waitrequest</role>
- </port>
- <port>
- <name>d_write</name>
- <direction>Output</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>d_writedata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>debug_mem_slave_debugaccess_to_roms</name>
- <direction>Output</direction>
- <width>1</width>
- <role>debugaccess</role>
- </port>
- </interface>
- <interface name="debug_mem_slave" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.hideDevice</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>qsys.ui.connect</name>
- <value>instruction_master,data_master</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>2048</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>debug_mem_slave_address</name>
- <direction>Input</direction>
- <width>9</width>
- <role>address</role>
- </port>
- <port>
- <name>debug_mem_slave_byteenable</name>
- <direction>Input</direction>
- <width>4</width>
- <role>byteenable</role>
- </port>
- <port>
- <name>debug_mem_slave_debugaccess</name>
- <direction>Input</direction>
- <width>1</width>
- <role>debugaccess</role>
- </port>
- <port>
- <name>debug_mem_slave_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>debug_mem_slave_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- <port>
- <name>debug_mem_slave_waitrequest</name>
- <direction>Output</direction>
- <width>1</width>
- <role>waitrequest</role>
- </port>
- <port>
- <name>debug_mem_slave_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>debug_mem_slave_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- </interface>
- <interface name="debug_reset_request" kind="reset_source" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedDirectReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedResetSinks">
- <type>[Ljava.lang.String;</type>
- <value>none</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>true</isStart>
- <port>
- <name>debug_reset_request</name>
- <direction>Output</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="instruction_master" kind="avalon_master" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="adaptsTo">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>SYMBOLS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dBSBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="doStreamReads">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="doStreamWrites">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isAsynchronous">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isReadable">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isWriteable">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maxAddressWidth">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>true</isStart>
- <port>
- <name>i_address</name>
- <direction>Output</direction>
- <width>18</width>
- <role>address</role>
- </port>
- <port>
- <name>i_read</name>
- <direction>Output</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>i_readdata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- <port>
- <name>i_waitrequest</name>
- <direction>Input</direction>
- <width>1</width>
- <role>waitrequest</role>
- </port>
- </interface>
- <interface name="irq" kind="interrupt_receiver" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedAddressablePoint">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value>qsys_arts_unb2b_sc3_cpu_0.data_master</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="irqMap">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="irqScheme">
- <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
- <value>INDIVIDUAL_REQUESTS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>interrupt</type>
- <isStart>true</isStart>
- <port>
- <name>irq</name>
- <direction>Input</direction>
- <width>32</width>
- <role>irq</role>
- </port>
- </interface>
- <interface name="reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>reset_n</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset_n</role>
- </port>
- <port>
- <name>reset_req</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset_req</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>altera_nios2_gen2</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>Nios II Processor</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>nios_custom_instruction_master</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Custom Instruction Master</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>2</instanceCount>
- <name>avalon_master</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Master</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_source</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Output</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>interrupt_receiver</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Interrupt Receiver</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.xml
deleted file mode 100644
index 2b10dc58c10fde795358d81dd1a7312188bf73ef..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0.xml
+++ /dev/null
@@ -1,862 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:44:58"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DATA_MASTER_ADDRESS_MAP"
- type="AddressMap"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DATA_MASTER_ADDRESS_WIDTH"
- type="AddressWidthType"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_INSTRUCTION_MASTER_ADDRESS_MAP"
- type="AddressMap"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_INSTRUCTION_MASTER_ADDRESS_WIDTH"
- type="AddressWidthType"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_IRQ_INTERRUPTS_USED"
- type="BigInteger"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="clk" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="clk" direction="input" role="clk" width="1" />
- </interface>
- <interface
- name="custom_instruction_master"
- kind="nios_custom_instruction"
- start="1">
- <property name="CIName" value="" />
- <property name="addressWidth" value="8" />
- <property name="clockCycle" value="0" />
- <property name="enabled" value="false" />
- <property name="maxAddressWidth" value="8" />
- <property name="opcodeExtension" value="0" />
- <property name="sharedCombinationalAndMulticycle" value="false" />
- <port name="dummy_ci_port" direction="output" role="readra" width="1" />
- </interface>
- <interface name="data_master" kind="avalon" start="1">
- <property name="adaptsTo" value="" />
- <property name="addressGroup" value="1" />
- <property name="addressUnits" value="SYMBOLS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="clk" />
- <property name="associatedReset" value="reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="burstOnBurstBoundariesOnly" value="true" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="dBSBigEndian" value="false" />
- <property name="doStreamReads" value="false" />
- <property name="doStreamWrites" value="false" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isAsynchronous" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isReadable" value="false" />
- <property name="isWriteable" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maxAddressWidth" value="32" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="prSafe" value="false" />
- <property name="readLatency" value="0" />
- <property name="readWaitTime" value="1" />
- <property name="registerIncomingSignals" value="true" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="waitrequestAllowance" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="d_address" direction="output" role="address" width="18" />
- <port name="d_byteenable" direction="output" role="byteenable" width="4" />
- <port name="d_read" direction="output" role="read" width="1" />
- <port name="d_readdata" direction="input" role="readdata" width="32" />
- <port name="d_waitrequest" direction="input" role="waitrequest" width="1" />
- <port name="d_write" direction="output" role="write" width="1" />
- <port name="d_writedata" direction="output" role="writedata" width="32" />
- <port
- name="debug_mem_slave_debugaccess_to_roms"
- direction="output"
- role="debugaccess"
- width="1" />
- </interface>
- <interface name="debug_mem_slave" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="2048" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="clk" />
- <property name="associatedReset" value="reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="0" />
- <property name="readWaitStates" value="1" />
- <property name="readWaitTime" value="1" />
- <property name="registerIncomingSignals" value="true" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port
- name="debug_mem_slave_address"
- direction="input"
- role="address"
- width="9" />
- <port
- name="debug_mem_slave_byteenable"
- direction="input"
- role="byteenable"
- width="4" />
- <port
- name="debug_mem_slave_debugaccess"
- direction="input"
- role="debugaccess"
- width="1" />
- <port name="debug_mem_slave_read" direction="input" role="read" width="1" />
- <port
- name="debug_mem_slave_readdata"
- direction="output"
- role="readdata"
- width="32" />
- <port
- name="debug_mem_slave_waitrequest"
- direction="output"
- role="waitrequest"
- width="1" />
- <port name="debug_mem_slave_write" direction="input" role="write" width="1" />
- <port
- name="debug_mem_slave_writedata"
- direction="input"
- role="writedata"
- width="32" />
- </interface>
- <interface name="debug_reset_request" kind="reset" start="1">
- <property name="associatedClock" value="clk" />
- <property name="associatedDirectReset" value="" />
- <property name="associatedResetSinks" value="none" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="debug_reset_request" direction="output" role="reset" width="1" />
- </interface>
- <interface name="instruction_master" kind="avalon" start="1">
- <property name="adaptsTo" value="" />
- <property name="addressGroup" value="1" />
- <property name="addressUnits" value="SYMBOLS" />
- <property name="alwaysBurstMaxBurst" value="true" />
- <property name="associatedClock" value="clk" />
- <property name="associatedReset" value="reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="dBSBigEndian" value="false" />
- <property name="doStreamReads" value="false" />
- <property name="doStreamWrites" value="false" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isAsynchronous" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isReadable" value="false" />
- <property name="isWriteable" value="false" />
- <property name="linewrapBursts" value="true" />
- <property name="maxAddressWidth" value="32" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="prSafe" value="false" />
- <property name="readLatency" value="0" />
- <property name="readWaitTime" value="1" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="waitrequestAllowance" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="i_address" direction="output" role="address" width="18" />
- <port name="i_read" direction="output" role="read" width="1" />
- <port name="i_readdata" direction="input" role="readdata" width="32" />
- <port name="i_waitrequest" direction="input" role="waitrequest" width="1" />
- </interface>
- <interface name="irq" kind="interrupt" start="1">
- <property
- name="associatedAddressablePoint"
- value="qsys_arts_unb2b_sc3_cpu_0.data_master" />
- <property name="associatedClock" value="clk" />
- <property name="associatedReset" value="reset" />
- <property name="irqMap" value="" />
- <property name="irqScheme" value="INDIVIDUAL_REQUESTS" />
- <port name="irq" direction="input" role="irq" width="32" />
- </interface>
- <interface name="reset" kind="reset" start="0">
- <property name="associatedClock" value="clk" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="reset_n" direction="input" role="reset_n" width="1" />
- <port name="reset_req" direction="input" role="reset_req" width="1" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_cpu_0"
- version="1.0"
- name="qsys_arts_unb2b_sc3_cpu_0">
- <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_IRQ_INTERRUPTS_USED" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684281" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_INSTRUCTION_MASTER_ADDRESS_MAP" value="" />
- <parameter name="AUTO_DATA_MASTER_ADDRESS_MAP" value="" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <parameter name="AUTO_DATA_MASTER_ADDRESS_WIDTH" value="-1" />
- <parameter name="AUTO_INSTRUCTION_MASTER_ADDRESS_WIDTH" value="-1" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/synth/qsys_arts_unb2b_sc3_cpu_0.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/synth/qsys_arts_unb2b_sc3_cpu_0.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
- <file
- path="/home/software/Altera/17.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_cpu_0">"Generating: qsys_arts_unb2b_sc3_cpu_0"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_cpu_0">"Generating: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_cpu_0">"Generating: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq"</message>
- <message level="Info" culprit="cpu">Starting RTL generation for module 'qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq'</message>
- <message level="Info" culprit="cpu"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64//eperlcmd -I /home/software/Altera/17.0/quartus/linux64//perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq --dir=/tmp/alt7681_6931282645914172388.dir/0010_cpu_gen/ --quartus_bindir=/home/software/Altera/17.0/quartus/linux64/ --verilog --config=/tmp/alt7681_6931282645914172388.dir/0010_cpu_gen//qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_processor_configuration.pl --do_build_sim=0 --pro_version=1 ]</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:53 (*) Starting Nios II generation</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:53 (*) Checking for plaintext license.</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) Plaintext license not found.</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) No license required to generate encrypted Nios II/e.</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) Elaborating CPU configuration settings</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) Creating all objects for CPU</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:55 (*) Generating RTL from CPU objects</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:55 (*) Creating plain-text RTL</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:56 (*) Done Nios II generation</message>
- <message level="Info" culprit="cpu">Done RTL generation for module 'qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq'</message>
- </messages>
- </entity>
- <entity
- kind="altera_nios2_gen2"
- version="17.0"
- name="qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey">
- <parameter name="mpx_enabled" value="false" />
- <parameter name="ocimem_ramBlockType" value="Automatic" />
- <parameter name="dcache_victim_buf_impl" value="ram" />
- <parameter name="setting_exportPCB" value="false" />
- <parameter name="setting_ic_ecc_present" value="true" />
- <parameter name="dcache_size_derived" value="2048" />
- <parameter name="mmu_udtlbNumEntries" value="6" />
- <parameter
- name="deviceFeaturesSystemInfo"
- value="ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0" />
- <parameter name="bht_ramBlockType" value="Automatic" />
- <parameter name="mmu_TLBMissExcSlave" value="None" />
- <parameter name="impl" value="Tiny" />
- <parameter name="setting_branchpredictiontype" value="Dynamic" />
- <parameter name="tightly_coupled_instruction_master_0_paddr_size" value="0" />
- <parameter name="breakOffset" value="32" />
- <parameter name="setting_activateTrace" value="false" />
- <parameter name="debug_offchiptrace" value="false" />
- <parameter name="setting_avalonDebugPortPresent" value="false" />
- <parameter name="dcache_numTCDM" value="0" />
- <parameter name="setting_tmr_output_disable" value="false" />
- <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
- <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
- <parameter name="debug_debugReqSignals" value="false" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="instruction_master_high_performance_paddr_size" value="0" />
- <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
- <parameter name="mmu_processIDNumBits" value="8" />
- <parameter name="debug_onchiptrace" value="false" />
- <parameter name="setting_rf_ecc_present" value="true" />
- <parameter name="ocimem_ramInit" value="false" />
- <parameter name="internalIrqMaskSystemInfo" value="15" />
- <parameter name="tightly_coupled_data_master_0_paddr_size" value="0" />
- <parameter name="exceptionAbsoluteAddr" value="131104" />
- <parameter name="icache_size" value="4096" />
- <parameter
- name="dataSlaveMapParam"
- value="<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' type='null.null' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x80' end='0x100' type='null.null' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x100' end='0x180' type='null.null' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x180' end='0x200' type='null.null' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x200' end='0x280' type='null.null' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x280' end='0x300' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x300' end='0x380' type='null.null' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x380' end='0x400' type='null.null' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x400' end='0x480' type='null.null' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x480' end='0x500' type='null.null' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x500' end='0x580' type='null.null' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x600' type='null.null' datawidth='32' /><slave name='reg_remu.mem' start='0x600' end='0x680' type='null.null' datawidth='32' /><slave name='pio_pps.mem' start='0x680' end='0x700' type='null.null' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x780' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' type='null.null' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x1080' type='null.null' datawidth='32' /><slave name='timer_0.s1' start='0x1080' end='0x10A0' type='null.null' datawidth='16' /><slave name='pio_wdi.s1' start='0x10A0' end='0x10B0' type='null.null' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10B0' end='0x10B8' type='null.null' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' type='null.null' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3080' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>" />
- <parameter name="mpu_enabled" value="false" />
- <parameter name="flash_instruction_master_paddr_size" value="0" />
- <parameter name="setting_ecc_present" value="false" />
- <parameter name="stratix_dspblock_shift_mul" value="false" />
- <parameter name="shift_rot_impl" value="1" />
- <parameter name="setting_ioregionBypassDCache" value="false" />
- <parameter name="register_file_por" value="false" />
- <parameter name="faAddrWidth" value="1" />
- <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
- <parameter name="resetrequest_enabled" value="true" />
- <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
- <parameter name="debug_triggerArming" value="true" />
- <parameter name="debug_OCIOnchipTrace" value="_128" />
- <parameter name="dataAddrWidth" value="18" />
- <parameter name="setting_bit31BypassDCache" value="false" />
- <parameter name="instAddrWidth" value="18" />
- <parameter name="io_regionbase" value="0" />
- <parameter name="mul_32_impl" value="2" />
- <parameter name="translate_on" value=" "synthesis translate_on" " />
- <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
- <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
- <parameter name="instruction_master_paddr_base" value="0" />
- <parameter name="userDefinedSettings" value="" />
- <parameter name="mul_64_impl" value="0" />
- <parameter name="clockFrequency" value="125000000" />
- <parameter name="resetOffset" value="0" />
- <parameter name="dcache_ramBlockType" value="Automatic" />
- <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
- <parameter name="mul_shift_choice" value="0" />
- <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
- <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
- <parameter name="tightly_coupled_data_master_1_paddr_size" value="0" />
- <parameter name="setting_asic_third_party_synthesis" value="false" />
- <parameter name="mpu_minInstRegionSize" value="12" />
- <parameter name="setting_exportdebuginfo" value="false" />
- <parameter name="mmu_tlbPtrSz" value="7" />
- <parameter name="resetSlave" value="onchip_memory2_0.s1" />
- <parameter name="dcache_bursts_derived" value="false" />
- <parameter name="multiplierType" value="no_mul" />
- <parameter name="debug_traceStorage" value="onchip_trace" />
- <parameter name="setting_preciseIllegalMemAccessException" value="false" />
- <parameter name="fa_cache_linesize" value="0" />
- <parameter name="data_master_paddr_size" value="0" />
- <parameter name="setting_HBreakTest" value="false" />
- <parameter name="setting_disableocitrace" value="false" />
- <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
- <parameter name="setting_showInternalSettings" value="false" />
- <parameter name="instructionMasterHighPerformanceMapParam" value="" />
- <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
- <parameter name="debug_datatrigger" value="0" />
- <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
- <parameter name="debug_enabled" value="true" />
- <parameter name="setting_export_large_RAMs" value="false" />
- <parameter name="setting_dc_ecc_present" value="true" />
- <parameter name="dividerType" value="no_div" />
- <parameter name="setting_exportvectors" value="false" />
- <parameter name="breakSlave_derived" value="cpu_0.debug_mem_slave" />
- <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
- <parameter name="mmu_ramBlockType" value="Automatic" />
- <parameter name="cdx_enabled" value="false" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <parameter name="customInstSlavesSystemInfo" value="<info/>" />
- <parameter name="tracefilename" value="" />
- <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
- <parameter name="tightly_coupled_instruction_master_2_paddr_size" value="0" />
- <parameter name="setting_oci_version" value="1" />
- <parameter name="icache_burstType" value="None" />
- <parameter name="data_master_high_performance_paddr_size" value="0" />
- <parameter name="setting_disable_tmr_inj" value="false" />
- <parameter name="instruction_master_high_performance_paddr_base" value="0" />
- <parameter name="tightly_coupled_instruction_master_3_paddr_size" value="0" />
- <parameter name="regfile_ramBlockType" value="Automatic" />
- <parameter name="dcache_size" value="2048" />
- <parameter name="breakSlave" value="None" />
- <parameter name="exceptionOffset" value="32" />
- <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
- <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
- <parameter name="breakAbsoluteAddr" value="6176" />
- <parameter name="setting_ecc_sim_test_ports" value="false" />
- <parameter name="setting_showUnpublishedSettings" value="false" />
- <parameter name="master_addr_map" value="false" />
- <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
- <parameter name="resetAbsoluteAddr" value="131072" />
- <parameter name="cpuArchRev" value="1" />
- <parameter name="setting_dtcm_ecc_present" value="true" />
- <parameter name="customInstSlavesSystemInfo_nios_c" value="<info/>" />
- <parameter name="customInstSlavesSystemInfo_nios_b" value="<info/>" />
- <parameter name="customInstSlavesSystemInfo_nios_a" value="<info/>" />
- <parameter name="setting_interruptControllerType" value="Internal" />
- <parameter name="dcache_tagramBlockType" value="Automatic" />
- <parameter name="debug_insttrace" value="false" />
- <parameter name="setting_itcm_ecc_present" value="true" />
- <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
- <parameter name="mmu_TLBMissExcAbsAddr" value="0" />
- <parameter name="mpu_useLimit" value="false" />
- <parameter name="icache_numTCIM" value="0" />
- <parameter name="setting_usedesignware" value="false" />
- <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
- <parameter name="instruction_master_paddr_size" value="0" />
- <parameter name="mmu_TLBMissExcOffset" value="0" />
- <parameter name="mmu_enabled" value="false" />
- <parameter name="mmu_uitlbNumEntries" value="4" />
- <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
- <parameter name="setting_activateTestEndChecker" value="false" />
- <parameter name="cpuID" value="0" />
- <parameter name="tightly_coupled_data_master_2_paddr_size" value="0" />
- <parameter name="setting_asic_enabled" value="false" />
- <parameter name="setting_HDLSimCachesCleared" value="true" />
- <parameter name="setting_asic_add_scan_mode_input" value="false" />
- <parameter name="setting_shadowRegisterSets" value="0" />
- <parameter name="tightly_coupled_data_master_3_paddr_size" value="0" />
- <parameter name="icache_ramBlockType" value="Automatic" />
- <parameter name="faSlaveMapParam" value="" />
- <parameter name="setting_clearXBitsLDNonBypass" value="true" />
- <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
- <parameter name="fa_cache_line" value="2" />
- <parameter name="debug_assignJtagInstanceID" value="false" />
- <parameter name="setting_activateMonitors" value="true" />
- <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
- <parameter name="setting_allow_break_inst" value="false" />
- <parameter name="io_regionsize" value="0" />
- <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
- <parameter name="translate_off" value=" "synthesis translate_off" " />
- <parameter name="mpu_numOfInstRegion" value="8" />
- <parameter name="flash_instruction_master_paddr_base" value="0" />
- <parameter name="cpuReset" value="false" />
- <parameter name="setting_removeRAMinit" value="false" />
- <parameter name="icache_tagramBlockType" value="Automatic" />
- <parameter name="setting_mmu_ecc_present" value="true" />
- <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
- <parameter name="debug_datatrace" value="false" />
- <parameter name="debug_hwbreakpoint" value="0" />
- <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
- <parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="setting_bigEndian" value="false" />
- <parameter name="mpu_minDataRegionSize" value="12" />
- <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
- <parameter name="debug_jtagInstanceID" value="0" />
- <parameter name="setting_breakslaveoveride" value="false" />
- <parameter name="debug_traceType" value="none" />
- <parameter name="setting_alwaysEncrypt" value="true" />
- <parameter name="setting_oci_export_jtag_signals" value="false" />
- <parameter name="dcache_lineSize_derived" value="32" />
- <parameter name="deviceFamilyName" value="Arria 10" />
- <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
- <parameter name="setting_support31bitdcachebypass" value="true" />
- <parameter
- name="instSlaveMapParam"
- value="<address-map><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>" />
- <parameter name="setting_bhtPtrSz" value="8" />
- <parameter name="setting_exportHostDebugPort" value="false" />
- <parameter name="tmr_enabled" value="false" />
- <parameter name="data_master_paddr_base" value="0" />
- <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
- <parameter name="mpu_numOfDataRegion" value="8" />
- <parameter name="data_master_high_performance_paddr_base" value="0" />
- <parameter name="tightly_coupled_instruction_master_1_paddr_size" value="0" />
- <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
- <parameter name="dcache_bursts" value="false" />
- <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
- <parameter name="setting_fast_register_read" value="false" />
- <parameter name="mmu_tlbNumWays" value="16" />
- <parameter name="shifterType" value="medium_le_shift" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey.v"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey.v"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_hw.tcl" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
- </childSourceFiles>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_cpu_0"
- as="qsys_arts_unb2b_sc3_cpu_0" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_cpu_0">"Generating: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_cpu_0">"Generating: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq"</message>
- <message level="Info" culprit="cpu">Starting RTL generation for module 'qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq'</message>
- <message level="Info" culprit="cpu"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64//eperlcmd -I /home/software/Altera/17.0/quartus/linux64//perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq --dir=/tmp/alt7681_6931282645914172388.dir/0010_cpu_gen/ --quartus_bindir=/home/software/Altera/17.0/quartus/linux64/ --verilog --config=/tmp/alt7681_6931282645914172388.dir/0010_cpu_gen//qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_processor_configuration.pl --do_build_sim=0 --pro_version=1 ]</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:53 (*) Starting Nios II generation</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:53 (*) Checking for plaintext license.</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) Plaintext license not found.</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) No license required to generate encrypted Nios II/e.</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) Elaborating CPU configuration settings</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) Creating all objects for CPU</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:55 (*) Generating RTL from CPU objects</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:55 (*) Creating plain-text RTL</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:56 (*) Done Nios II generation</message>
- <message level="Info" culprit="cpu">Done RTL generation for module 'qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq'</message>
- </messages>
- </entity>
- <entity
- kind="altera_nios2_gen2_unit"
- version="17.0"
- name="qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq">
- <parameter name="icache_burstType" value="None" />
- <parameter name="setting_oci_version" value="1" />
- <parameter name="mpx_enabled" value="false" />
- <parameter name="ocimem_ramBlockType" value="Automatic" />
- <parameter name="dcache_victim_buf_impl" value="ram" />
- <parameter name="setting_exportPCB" value="false" />
- <parameter name="setting_ic_ecc_present" value="true" />
- <parameter name="dcache_size_derived" value="2048" />
- <parameter name="mmu_udtlbNumEntries" value="6" />
- <parameter name="tightly_coupled_instruction_master_3_paddr_top" value="0" />
- <parameter
- name="deviceFeaturesSystemInfo"
- value="ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0" />
- <parameter name="bht_ramBlockType" value="Automatic" />
- <parameter name="instruction_master_high_performance_paddr_base" value="0" />
- <parameter name="mmu_TLBMissExcSlave" value="None" />
- <parameter name="impl" value="Tiny" />
- <parameter name="regfile_ramBlockType" value="Automatic" />
- <parameter name="dcache_size" value="2048" />
- <parameter name="tightly_coupled_data_master_0_paddr_top" value="0" />
- <parameter name="breakOffset" value="32" />
- <parameter name="breakSlave" value="None" />
- <parameter name="setting_branchPredictionType" value="Dynamic" />
- <parameter name="exceptionOffset" value="32" />
- <parameter name="flash_instruction_master_paddr_top" value="0" />
- <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
- <parameter name="cpu_name" value="cpu" />
- <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
- <parameter name="breakAbsoluteAddr" value="6176" />
- <parameter name="setting_activateTrace" value="false" />
- <parameter name="debug_offchiptrace" value="false" />
- <parameter name="setting_avalonDebugPortPresent" value="false" />
- <parameter name="dcache_numTCDM" value="0" />
- <parameter name="setting_ecc_sim_test_ports" value="false" />
- <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
- <parameter name="setting_showUnpublishedSettings" value="false" />
- <parameter name="tightly_coupled_data_master_2_paddr_base" value="0" />
- <parameter name="debug_debugReqSignals" value="false" />
- <parameter name="master_addr_map" value="false" />
- <parameter name="tightly_coupled_instruction_master_2_paddr_base" value="0" />
- <parameter name="mmu_processIDNumBits" value="8" />
- <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
- <parameter name="debug_onchiptrace" value="false" />
- <parameter name="setting_rf_ecc_present" value="true" />
- <parameter name="resetAbsoluteAddr" value="131072" />
- <parameter name="tightly_coupled_data_master_1_paddr_top" value="0" />
- <parameter name="ocimem_ramInit" value="false" />
- <parameter name="internalIrqMaskSystemInfo" value="15" />
- <parameter name="instruction_master_paddr_top" value="0" />
- <parameter name="cpuArchRev" value="1" />
- <parameter name="setting_dtcm_ecc_present" value="true" />
- <parameter name="exceptionAbsoluteAddr" value="131104" />
- <parameter name="setting_interruptControllerType" value="Internal" />
- <parameter name="dcache_tagramBlockType" value="Automatic" />
- <parameter name="debug_insttrace" value="false" />
- <parameter name="icache_size" value="4096" />
- <parameter name="setting_itcm_ecc_present" value="true" />
- <parameter name="tightly_coupled_instruction_master_0_paddr_base" value="0" />
- <parameter
- name="dataSlaveMapParam"
- value="<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' type='null.null' datawidth='32' /><slave name='reg_ip_arria10_e1sg_phy_10gbase_r_24.mem' start='0x80' end='0x100' type='null.null' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0x100' end='0x180' type='null.null' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0x180' end='0x200' type='null.null' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x200' end='0x280' type='null.null' datawidth='32' /><slave name='reg_eth10g_qsfp_ring.mem' start='0x280' end='0x300' type='null.null' datawidth='32' /><slave name='reg_tr_10GbE_qsfp_ring.mem' start='0x300' end='0x380' type='null.null' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x380' end='0x400' type='null.null' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x400' end='0x480' type='null.null' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x480' end='0x500' type='null.null' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x500' end='0x580' type='null.null' datawidth='32' /><slave name='reg_epcs.mem' start='0x580' end='0x600' type='null.null' datawidth='32' /><slave name='reg_remu.mem' start='0x600' end='0x680' type='null.null' datawidth='32' /><slave name='pio_pps.mem' start='0x680' end='0x700' type='null.null' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x700' end='0x780' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_reg' start='0x780' end='0x7C0' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x7C0' end='0x800' type='null.null' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x1080' type='null.null' datawidth='32' /><slave name='timer_0.s1' start='0x1080' end='0x10A0' type='null.null' datawidth='16' /><slave name='pio_wdi.s1' start='0x10A0' end='0x10B0' type='null.null' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x10B0' end='0x10B8' type='null.null' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_tse' start='0x2000' end='0x3000' type='null.null' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3080' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x4000' end='0x5000' type='null.null' datawidth='32' /><slave name='avs_eth_1.mms_ram' start='0x5000' end='0x6000' type='null.null' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>" />
- <parameter name="mpu_enabled" value="false" />
- <parameter name="setting_ecc_present" value="false" />
- <parameter name="mmu_TLBMissExcAbsAddr" value="0" />
- <parameter name="mpu_useLimit" value="false" />
- <parameter name="stratix_dspblock_shift_mul" value="false" />
- <parameter name="icache_numTCIM" value="0" />
- <parameter name="setting_usedesignware" value="false" />
- <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
- <parameter name="instruction_master_high_performance_paddr_top" value="0" />
- <parameter name="setting_ioregionBypassDCache" value="false" />
- <parameter name="mmu_TLBMissExcOffset" value="0" />
- <parameter name="mmu_enabled" value="false" />
- <parameter name="mmu_uitlbNumEntries" value="4" />
- <parameter name="register_file_por" value="false" />
- <parameter name="faAddrWidth" value="1" />
- <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
- <parameter name="tightly_coupled_data_master_3_paddr_top" value="0" />
- <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
- <parameter name="setting_activateTestEndChecker" value="false" />
- <parameter name="cpuID" value="0" />
- <parameter name="resetrequest_enabled" value="true" />
- <parameter name="setting_asic_enabled" value="false" />
- <parameter name="exceptionSlave" value="onchip_memory2_0.s1" />
- <parameter name="setting_HDLSimCachesCleared" value="true" />
- <parameter name="debug_triggerArming" value="true" />
- <parameter name="debug_OCIOnchipTrace" value="_128" />
- <parameter name="dataAddrWidth" value="18" />
- <parameter name="setting_bit31BypassDCache" value="false" />
- <parameter name="instAddrWidth" value="18" />
- <parameter name="setting_asic_add_scan_mode_input" value="false" />
- <parameter name="tightly_coupled_instruction_master_1_paddr_top" value="0" />
- <parameter name="io_regionbase" value="0" />
- <parameter name="setting_shadowRegisterSets" value="0" />
- <parameter name="icache_ramBlockType" value="Automatic" />
- <parameter name="data_master_paddr_top" value="0" />
- <parameter name="translate_on" value=" "synthesis translate_on" " />
- <parameter name="faSlaveMapParam" value="" />
- <parameter name="setting_clearXBitsLDNonBypass" value="true" />
- <parameter name="tightly_coupled_instruction_master_1_paddr_base" value="0" />
- <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
- <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
- <parameter name="fa_cache_line" value="2" />
- <parameter name="debug_assignJtagInstanceID" value="false" />
- <parameter name="instruction_master_paddr_base" value="0" />
- <parameter name="userDefinedSettings" value="" />
- <parameter name="clockFrequency" value="125000000" />
- <parameter name="setting_activateMonitors" value="true" />
- <parameter name="resetOffset" value="0" />
- <parameter name="dcache_ramBlockType" value="Automatic" />
- <parameter name="dataMasterHighPerformanceAddrWidth" value="1" />
- <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
- <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
- <parameter name="tightly_coupled_instruction_master_0_paddr_top" value="0" />
- <parameter name="setting_allow_break_inst" value="false" />
- <parameter name="setting_asic_third_party_synthesis" value="false" />
- <parameter name="io_regionsize" value="0" />
- <parameter name="mpu_minInstRegionSize" value="12" />
- <parameter name="tightly_coupled_data_master_3_paddr_base" value="0" />
- <parameter name="translate_off" value=" "synthesis translate_off" " />
- <parameter name="mpu_numOfInstRegion" value="8" />
- <parameter name="flash_instruction_master_paddr_base" value="0" />
- <parameter name="setting_exportdebuginfo" value="false" />
- <parameter name="mmu_tlbPtrSz" value="7" />
- <parameter name="cpuReset" value="false" />
- <parameter name="resetSlave" value="onchip_memory2_0.s1" />
- <parameter name="dcache_bursts_derived" value="false" />
- <parameter name="multiplierType" value="no_mul" />
- <parameter name="setting_removeRAMinit" value="false" />
- <parameter name="icache_tagramBlockType" value="Automatic" />
- <parameter name="debug_traceStorage" value="onchip_trace" />
- <parameter name="setting_preciseIllegalMemAccessException" value="false" />
- <parameter name="fa_cache_linesize" value="0" />
- <parameter name="setting_mmu_ecc_present" value="true" />
- <parameter name="debug_datatrace" value="false" />
- <parameter name="setting_HBreakTest" value="false" />
- <parameter name="debug_hwbreakpoint" value="0" />
- <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
- <parameter name="dataMasterHighPerformanceMapParam" value="" />
- <parameter name="tightly_coupled_data_master_2_paddr_top" value="0" />
- <parameter name="setting_disableocitrace" value="false" />
- <parameter name="setting_bigEndian" value="false" />
- <parameter name="mpu_minDataRegionSize" value="12" />
- <parameter name="tightly_coupled_data_master_1_paddr_base" value="0" />
- <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
- <parameter name="debug_jtagInstanceID" value="0" />
- <parameter name="setting_showInternalSettings" value="false" />
- <parameter name="setting_breakslaveoveride" value="false" />
- <parameter name="debug_traceType" value="none" />
- <parameter name="instructionMasterHighPerformanceMapParam" value="" />
- <parameter name="tightly_coupled_instruction_master_2_paddr_top" value="0" />
- <parameter name="setting_alwaysEncrypt" value="true" />
- <parameter name="setting_oci_export_jtag_signals" value="false" />
- <parameter name="tightly_coupled_instruction_master_3_paddr_base" value="0" />
- <parameter name="data_master_high_performance_paddr_top" value="0" />
- <parameter name="dcache_lineSize_derived" value="32" />
- <parameter name="deviceFamilyName" value="Arria 10" />
- <parameter name="debug_datatrigger" value="0" />
- <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
- <parameter name="debug_enabled" value="true" />
- <parameter name="setting_export_large_RAMs" value="false" />
- <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
- <parameter name="setting_dc_ecc_present" value="true" />
- <parameter name="setting_support31bitdcachebypass" value="true" />
- <parameter
- name="instSlaveMapParam"
- value="<address-map><slave name='cpu_0.debug_mem_slave' start='0x1800' end='0x2000' type='null.null' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x21000' type='null.null' datawidth='32' /></address-map>" />
- <parameter name="dividerType" value="no_div" />
- <parameter name="setting_bhtPtrSz" value="8" />
- <parameter name="setting_exportvectors" value="false" />
- <parameter name="tmr_enabled" value="false" />
- <parameter name="data_master_paddr_base" value="0" />
- <parameter name="breakSlave_derived" value="cpu_0.debug_mem_slave" />
- <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
- <parameter name="mpu_numOfDataRegion" value="8" />
- <parameter name="tightly_coupled_data_master_0_paddr_base" value="0" />
- <parameter name="mmu_ramBlockType" value="Automatic" />
- <parameter name="data_master_high_performance_paddr_base" value="0" />
- <parameter name="cdx_enabled" value="false" />
- <parameter name="customInstSlavesSystemInfo" value="<info/>" />
- <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
- <parameter name="dcache_bursts" value="false" />
- <parameter name="tracefilename" value="" />
- <parameter name="instructionMasterHighPerformanceAddrWidth" value="1" />
- <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
- <parameter name="setting_fast_register_read" value="false" />
- <parameter name="mmu_tlbNumWays" value="16" />
- <parameter name="shifterType" value="medium_le_shift" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.v"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk.v"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper.v"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench.v"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_a.mif"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_b.mif"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.sdc"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_default_contents.mif"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck.v"
- attributes="" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.v"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_sysclk.v"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_wrapper.v"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_test_bench.v"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_a.mif"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_rf_ram_b.mif"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq.sdc"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_ociram_default_contents.mif"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/altera_nios2_gen2_unit_170/synth/qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_debug_slave_tck.v"
- attributes="" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/nios2_ip/altera_nios2_gen2/altera_nios2_unit_hw.tcl" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey"
- as="cpu" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_cpu_0">"Generating: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq"</message>
- <message level="Info" culprit="cpu">Starting RTL generation for module 'qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq'</message>
- <message level="Info" culprit="cpu"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64//eperlcmd -I /home/software/Altera/17.0/quartus/linux64//perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq --dir=/tmp/alt7681_6931282645914172388.dir/0010_cpu_gen/ --quartus_bindir=/home/software/Altera/17.0/quartus/linux64/ --verilog --config=/tmp/alt7681_6931282645914172388.dir/0010_cpu_gen//qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_processor_configuration.pl --do_build_sim=0 --pro_version=1 ]</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:53 (*) Starting Nios II generation</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:53 (*) Checking for plaintext license.</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) Plaintext license not found.</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) No license required to generate encrypted Nios II/e.</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) Elaborating CPU configuration settings</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:54 (*) Creating all objects for CPU</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:55 (*) Generating RTL from CPU objects</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:55 (*) Creating plain-text RTL</message>
- <message level="Info" culprit="cpu"># 2018.05.30 14:44:56 (*) Done Nios II generation</message>
- <message level="Info" culprit="cpu">Done RTL generation for module 'qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq'</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_bb.v
deleted file mode 100644
index 0874856940116dc9ed0783a29c28f822910b2d4b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_bb.v
+++ /dev/null
@@ -1,56 +0,0 @@
-
-module qsys_arts_unb2b_sc3_cpu_0 (
- clk,
- dummy_ci_port,
- d_address,
- d_byteenable,
- d_read,
- d_readdata,
- d_waitrequest,
- d_write,
- d_writedata,
- debug_mem_slave_debugaccess_to_roms,
- debug_mem_slave_address,
- debug_mem_slave_byteenable,
- debug_mem_slave_debugaccess,
- debug_mem_slave_read,
- debug_mem_slave_readdata,
- debug_mem_slave_waitrequest,
- debug_mem_slave_write,
- debug_mem_slave_writedata,
- debug_reset_request,
- i_address,
- i_read,
- i_readdata,
- i_waitrequest,
- irq,
- reset_n,
- reset_req);
-
- input clk;
- output dummy_ci_port;
- output [17:0] d_address;
- output [3:0] d_byteenable;
- output d_read;
- input [31:0] d_readdata;
- input d_waitrequest;
- output d_write;
- output [31:0] d_writedata;
- output debug_mem_slave_debugaccess_to_roms;
- input [8:0] debug_mem_slave_address;
- input [3:0] debug_mem_slave_byteenable;
- input debug_mem_slave_debugaccess;
- input debug_mem_slave_read;
- output [31:0] debug_mem_slave_readdata;
- output debug_mem_slave_waitrequest;
- input debug_mem_slave_write;
- input [31:0] debug_mem_slave_writedata;
- output debug_reset_request;
- output [17:0] i_address;
- output i_read;
- input [31:0] i_readdata;
- input i_waitrequest;
- input [31:0] irq;
- input reset_n;
- input reset_req;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_generation.rpt
deleted file mode 100644
index b3a8683cb95d8a96cf1e9c85c19e68fc0fc2e42d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_generation.rpt
+++ /dev/null
@@ -1,46 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_cpu_0: "Transforming system: qsys_arts_unb2b_sc3_cpu_0"
-Info: qsys_arts_unb2b_sc3_cpu_0: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_cpu_0: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_cpu_0: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_cpu_0: Running transform generation_view_transform took 0.000s
-Info: clock_bridge: Running transform generation_view_transform
-Info: clock_bridge: Running transform generation_view_transform took 0.000s
-Info: reset_bridge: Running transform generation_view_transform
-Info: reset_bridge: Running transform generation_view_transform took 0.000s
-Info: cpu: Running transform generation_view_transform
-Info: cpu: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_cpu_0: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_cpu_0: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_cpu_0: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_cpu_0: Running transform interconnect_transform_chooser took 0.011s
-Info: qsys_arts_unb2b_sc3_cpu_0: "Naming system components in system: qsys_arts_unb2b_sc3_cpu_0"
-Info: qsys_arts_unb2b_sc3_cpu_0: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_cpu_0: "Generating: qsys_arts_unb2b_sc3_cpu_0"
-Info: qsys_arts_unb2b_sc3_cpu_0: "Generating: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey"
-Info: qsys_arts_unb2b_sc3_cpu_0: "Generating: qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq"
-Info: cpu: Starting RTL generation for module 'qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq'
-Info: cpu: Generation command is [exec /home/software/Altera/17.0/quartus/linux64//eperlcmd -I /home/software/Altera/17.0/quartus/linux64//perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- /home/software/Altera/17.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq --dir=/tmp/alt7681_6931282645914172388.dir/0010_cpu_gen/ --quartus_bindir=/home/software/Altera/17.0/quartus/linux64/ --verilog --config=/tmp/alt7681_6931282645914172388.dir/0010_cpu_gen//qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq_processor_configuration.pl --do_build_sim=0 --pro_version=1 ]
-Info: cpu: # 2018.05.30 14:44:53 (*) Starting Nios II generation
-Info: cpu: # 2018.05.30 14:44:53 (*) Checking for plaintext license.
-Info: cpu: # 2018.05.30 14:44:54 (*) Plaintext license not found.
-Info: cpu: # 2018.05.30 14:44:54 (*) No license required to generate encrypted Nios II/e.
-Info: cpu: # 2018.05.30 14:44:54 (*) Elaborating CPU configuration settings
-Info: cpu: # 2018.05.30 14:44:54 (*) Creating all objects for CPU
-Info: cpu: # 2018.05.30 14:44:55 (*) Generating RTL from CPU objects
-Info: cpu: # 2018.05.30 14:44:55 (*) Creating plain-text RTL
-Info: cpu: # 2018.05.30 14:44:56 (*) Done Nios II generation
-Info: cpu: Done RTL generation for module 'qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_unit_170_ipvyxiq'
-Info: qsys_arts_unb2b_sc3_cpu_0: Done "qsys_arts_unb2b_sc3_cpu_0" with 3 modules, 11 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_cpu_0. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_inst.v
deleted file mode 100644
index 1bf2133b03862b8e712461f620eb09935da6f693..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_inst.v
+++ /dev/null
@@ -1,29 +0,0 @@
- qsys_arts_unb2b_sc3_cpu_0 u0 (
- .clk (_connected_to_clk_), // clk.clk
- .dummy_ci_port (_connected_to_dummy_ci_port_), // custom_instruction_master.readra
- .d_address (_connected_to_d_address_), // data_master.address
- .d_byteenable (_connected_to_d_byteenable_), // .byteenable
- .d_read (_connected_to_d_read_), // .read
- .d_readdata (_connected_to_d_readdata_), // .readdata
- .d_waitrequest (_connected_to_d_waitrequest_), // .waitrequest
- .d_write (_connected_to_d_write_), // .write
- .d_writedata (_connected_to_d_writedata_), // .writedata
- .debug_mem_slave_debugaccess_to_roms (_connected_to_debug_mem_slave_debugaccess_to_roms_), // .debugaccess
- .debug_mem_slave_address (_connected_to_debug_mem_slave_address_), // debug_mem_slave.address
- .debug_mem_slave_byteenable (_connected_to_debug_mem_slave_byteenable_), // .byteenable
- .debug_mem_slave_debugaccess (_connected_to_debug_mem_slave_debugaccess_), // .debugaccess
- .debug_mem_slave_read (_connected_to_debug_mem_slave_read_), // .read
- .debug_mem_slave_readdata (_connected_to_debug_mem_slave_readdata_), // .readdata
- .debug_mem_slave_waitrequest (_connected_to_debug_mem_slave_waitrequest_), // .waitrequest
- .debug_mem_slave_write (_connected_to_debug_mem_slave_write_), // .write
- .debug_mem_slave_writedata (_connected_to_debug_mem_slave_writedata_), // .writedata
- .debug_reset_request (_connected_to_debug_reset_request_), // debug_reset_request.reset
- .i_address (_connected_to_i_address_), // instruction_master.address
- .i_read (_connected_to_i_read_), // .read
- .i_readdata (_connected_to_i_readdata_), // .readdata
- .i_waitrequest (_connected_to_i_waitrequest_), // .waitrequest
- .irq (_connected_to_irq_), // irq.irq
- .reset_n (_connected_to_reset_n_), // reset.reset_n
- .reset_req (_connected_to_reset_req_) // .reset_req
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_inst.vhd
deleted file mode 100644
index 8064fd738e6559cdaac506036115acd091b1076b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/qsys_arts_unb2b_sc3_cpu_0_inst.vhd
+++ /dev/null
@@ -1,61 +0,0 @@
- component qsys_arts_unb2b_sc3_cpu_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(17 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
- );
- end component qsys_arts_unb2b_sc3_cpu_0;
-
- u0 : component qsys_arts_unb2b_sc3_cpu_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
- d_address => CONNECTED_TO_d_address, -- data_master.address
- d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
- d_read => CONNECTED_TO_d_read, -- .read
- d_readdata => CONNECTED_TO_d_readdata, -- .readdata
- d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
- d_write => CONNECTED_TO_d_write, -- .write
- d_writedata => CONNECTED_TO_d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
- debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
- i_address => CONNECTED_TO_i_address, -- instruction_master.address
- i_read => CONNECTED_TO_i_read, -- .read
- i_readdata => CONNECTED_TO_i_readdata, -- .readdata
- i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- reset_req => CONNECTED_TO_reset_req -- .reset_req
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/synth/qsys_arts_unb2b_sc3_cpu_0.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/synth/qsys_arts_unb2b_sc3_cpu_0.vhd
deleted file mode 100644
index 6013f0ca2f39327f72fa508b41aead368c4f0ab7..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0/synth/qsys_arts_unb2b_sc3_cpu_0.vhd
+++ /dev/null
@@ -1,107 +0,0 @@
--- qsys_arts_unb2b_sc3_cpu_0.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library altera_nios2_gen2_170;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_cpu_0 is
- port (
- clk : in std_logic := '0'; -- clk.clk
- dummy_ci_port : out std_logic; -- custom_instruction_master.readra
- d_address : out std_logic_vector(17 downto 0); -- data_master.address
- d_byteenable : out std_logic_vector(3 downto 0); -- .byteenable
- d_read : out std_logic; -- .read
- d_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
- d_waitrequest : in std_logic := '0'; -- .waitrequest
- d_write : out std_logic; -- .write
- d_writedata : out std_logic_vector(31 downto 0); -- .writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- .debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => '0'); -- debug_mem_slave.address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
- debug_mem_slave_debugaccess : in std_logic := '0'; -- .debugaccess
- debug_mem_slave_read : in std_logic := '0'; -- .read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- .readdata
- debug_mem_slave_waitrequest : out std_logic; -- .waitrequest
- debug_mem_slave_write : in std_logic := '0'; -- .write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- debug_reset_request : out std_logic; -- debug_reset_request.reset
- i_address : out std_logic_vector(17 downto 0); -- instruction_master.address
- i_read : out std_logic; -- .read
- i_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
- i_waitrequest : in std_logic := '0'; -- .waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => '0'); -- irq.irq
- reset_n : in std_logic := '0'; -- reset.reset_n
- reset_req : in std_logic := '0' -- .reset_req
- );
-end entity qsys_arts_unb2b_sc3_cpu_0;
-
-architecture rtl of qsys_arts_unb2b_sc3_cpu_0 is
- component qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey_cmp is
- port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(17 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
- );
- end component qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey_cmp;
-
- for qsys_arts_unb2b_sc3_cpu_0 : qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey_cmp
- use entity altera_nios2_gen2_170.qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey;
-begin
-
- qsys_arts_unb2b_sc3_cpu_0 : component qsys_arts_unb2b_sc3_cpu_0_altera_nios2_gen2_170_rem7pey_cmp
- port map (
- clk => clk, -- clk.clk
- dummy_ci_port => dummy_ci_port, -- custom_instruction_master.readra
- d_address => d_address, -- data_master.address
- d_byteenable => d_byteenable, -- .byteenable
- d_read => d_read, -- .read
- d_readdata => d_readdata, -- .readdata
- d_waitrequest => d_waitrequest, -- .waitrequest
- d_write => d_write, -- .write
- d_writedata => d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => debug_mem_slave_writedata, -- .writedata
- debug_reset_request => debug_reset_request, -- debug_reset_request.reset
- i_address => i_address, -- instruction_master.address
- i_read => i_read, -- .read
- i_readdata => i_readdata, -- .readdata
- i_waitrequest => i_waitrequest, -- .waitrequest
- irq => irq, -- irq.irq
- reset_n => reset_n, -- reset.reset_n
- reset_req => reset_req -- .reset_req
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_cpu_0
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/altera_avalon_jtag_uart_170/synth/qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/altera_avalon_jtag_uart_170/synth/qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a.v
deleted file mode 100644
index 4a060e02fc42e1acd1a27deaea539198ddbf4151..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/altera_avalon_jtag_uart_170/synth/qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a.v
+++ /dev/null
@@ -1,588 +0,0 @@
-//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_sim_scfifo_w (
- // inputs:
- clk,
- fifo_wdata,
- fifo_wr,
-
- // outputs:
- fifo_FF,
- r_dat,
- wfifo_empty,
- wfifo_used
- )
-;
-
- output fifo_FF;
- output [ 7: 0] r_dat;
- output wfifo_empty;
- output [ 5: 0] wfifo_used;
- input clk;
- input [ 7: 0] fifo_wdata;
- input fifo_wr;
-
-
-wire fifo_FF;
-wire [ 7: 0] r_dat;
-wire wfifo_empty;
-wire [ 5: 0] wfifo_used;
-
-//synthesis translate_off
-//////////////// SIMULATION-ONLY CONTENTS
- always @(posedge clk)
- begin
- if (fifo_wr)
- $write("%c", fifo_wdata);
- end
-
-
- assign wfifo_used = {6{1'b0}};
- assign r_dat = {8{1'b0}};
- assign fifo_FF = 1'b0;
- assign wfifo_empty = 1'b1;
-
-//////////////// END SIMULATION-ONLY CONTENTS
-
-//synthesis translate_on
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_scfifo_w (
- // inputs:
- clk,
- fifo_clear,
- fifo_wdata,
- fifo_wr,
- rd_wfifo,
-
- // outputs:
- fifo_FF,
- r_dat,
- wfifo_empty,
- wfifo_used
- )
-;
-
- output fifo_FF;
- output [ 7: 0] r_dat;
- output wfifo_empty;
- output [ 5: 0] wfifo_used;
- input clk;
- input fifo_clear;
- input [ 7: 0] fifo_wdata;
- input fifo_wr;
- input rd_wfifo;
-
-
-wire fifo_FF;
-wire [ 7: 0] r_dat;
-wire wfifo_empty;
-wire [ 5: 0] wfifo_used;
-
-//synthesis translate_off
-//////////////// SIMULATION-ONLY CONTENTS
- qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_sim_scfifo_w the_qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_sim_scfifo_w
- (
- .clk (clk),
- .fifo_FF (fifo_FF),
- .fifo_wdata (fifo_wdata),
- .fifo_wr (fifo_wr),
- .r_dat (r_dat),
- .wfifo_empty (wfifo_empty),
- .wfifo_used (wfifo_used)
- );
-
-
-//////////////// END SIMULATION-ONLY CONTENTS
-
-//synthesis translate_on
-//synthesis read_comments_as_HDL on
-// scfifo wfifo
-// (
-// .aclr (fifo_clear),
-// .clock (clk),
-// .data (fifo_wdata),
-// .empty (wfifo_empty),
-// .full (fifo_FF),
-// .q (r_dat),
-// .rdreq (rd_wfifo),
-// .usedw (wfifo_used),
-// .wrreq (fifo_wr)
-// );
-//
-// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
-// wfifo.lpm_numwords = 64,
-// wfifo.lpm_showahead = "OFF",
-// wfifo.lpm_type = "scfifo",
-// wfifo.lpm_width = 8,
-// wfifo.lpm_widthu = 6,
-// wfifo.overflow_checking = "OFF",
-// wfifo.underflow_checking = "OFF",
-// wfifo.use_eab = "ON";
-//
-//synthesis read_comments_as_HDL off
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_sim_scfifo_r (
- // inputs:
- clk,
- fifo_rd,
- rst_n,
-
- // outputs:
- fifo_EF,
- fifo_rdata,
- rfifo_full,
- rfifo_used
- )
-;
-
- output fifo_EF;
- output [ 7: 0] fifo_rdata;
- output rfifo_full;
- output [ 5: 0] rfifo_used;
- input clk;
- input fifo_rd;
- input rst_n;
-
-
-reg [ 31: 0] bytes_left;
-wire fifo_EF;
-reg fifo_rd_d;
-wire [ 7: 0] fifo_rdata;
-wire new_rom;
-wire [ 31: 0] num_bytes;
-wire [ 6: 0] rfifo_entries;
-wire rfifo_full;
-wire [ 5: 0] rfifo_used;
-
-//synthesis translate_off
-//////////////// SIMULATION-ONLY CONTENTS
- // Generate rfifo_entries for simulation
- always @(posedge clk or negedge rst_n)
- begin
- if (rst_n == 0)
- begin
- bytes_left <= 32'h0;
- fifo_rd_d <= 1'b0;
- end
- else
- begin
- fifo_rd_d <= fifo_rd;
- // decrement on read
- if (fifo_rd_d)
- bytes_left <= bytes_left - 1'b1;
- // catch new contents
- if (new_rom)
- bytes_left <= num_bytes;
- end
- end
-
-
- assign fifo_EF = bytes_left == 32'b0;
- assign rfifo_full = bytes_left > 7'h40;
- assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
- assign rfifo_used = rfifo_entries[5 : 0];
- assign new_rom = 1'b0;
- assign num_bytes = 32'b0;
- assign fifo_rdata = 8'b0;
-
-//////////////// END SIMULATION-ONLY CONTENTS
-
-//synthesis translate_on
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_scfifo_r (
- // inputs:
- clk,
- fifo_clear,
- fifo_rd,
- rst_n,
- t_dat,
- wr_rfifo,
-
- // outputs:
- fifo_EF,
- fifo_rdata,
- rfifo_full,
- rfifo_used
- )
-;
-
- output fifo_EF;
- output [ 7: 0] fifo_rdata;
- output rfifo_full;
- output [ 5: 0] rfifo_used;
- input clk;
- input fifo_clear;
- input fifo_rd;
- input rst_n;
- input [ 7: 0] t_dat;
- input wr_rfifo;
-
-
-wire fifo_EF;
-wire [ 7: 0] fifo_rdata;
-wire rfifo_full;
-wire [ 5: 0] rfifo_used;
-
-//synthesis translate_off
-//////////////// SIMULATION-ONLY CONTENTS
- qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_sim_scfifo_r the_qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_sim_scfifo_r
- (
- .clk (clk),
- .fifo_EF (fifo_EF),
- .fifo_rd (fifo_rd),
- .fifo_rdata (fifo_rdata),
- .rfifo_full (rfifo_full),
- .rfifo_used (rfifo_used),
- .rst_n (rst_n)
- );
-
-
-//////////////// END SIMULATION-ONLY CONTENTS
-
-//synthesis translate_on
-//synthesis read_comments_as_HDL on
-// scfifo rfifo
-// (
-// .aclr (fifo_clear),
-// .clock (clk),
-// .data (t_dat),
-// .empty (fifo_EF),
-// .full (rfifo_full),
-// .q (fifo_rdata),
-// .rdreq (fifo_rd),
-// .usedw (rfifo_used),
-// .wrreq (wr_rfifo)
-// );
-//
-// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
-// rfifo.lpm_numwords = 64,
-// rfifo.lpm_showahead = "OFF",
-// rfifo.lpm_type = "scfifo",
-// rfifo.lpm_width = 8,
-// rfifo.lpm_widthu = 6,
-// rfifo.overflow_checking = "OFF",
-// rfifo.underflow_checking = "OFF",
-// rfifo.use_eab = "ON";
-//
-//synthesis read_comments_as_HDL off
-
-endmodule
-
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a (
- // inputs:
- av_address,
- av_chipselect,
- av_read_n,
- av_write_n,
- av_writedata,
- clk,
- rst_n,
-
- // outputs:
- av_irq,
- av_readdata,
- av_waitrequest,
- dataavailable,
- readyfordata
- )
- /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
-
- output av_irq;
- output [ 31: 0] av_readdata;
- output av_waitrequest;
- output dataavailable;
- output readyfordata;
- input av_address;
- input av_chipselect;
- input av_read_n;
- input av_write_n;
- input [ 31: 0] av_writedata;
- input clk;
- input rst_n;
-
-
-reg ac;
-wire activity;
-wire av_irq;
-wire [ 31: 0] av_readdata;
-reg av_waitrequest;
-reg dataavailable;
-reg fifo_AE;
-reg fifo_AF;
-wire fifo_EF;
-wire fifo_FF;
-wire fifo_clear;
-wire fifo_rd;
-wire [ 7: 0] fifo_rdata;
-wire [ 7: 0] fifo_wdata;
-reg fifo_wr;
-reg ien_AE;
-reg ien_AF;
-wire ipen_AE;
-wire ipen_AF;
-reg pause_irq;
-wire [ 7: 0] r_dat;
-wire r_ena;
-reg r_val;
-wire rd_wfifo;
-reg read_0;
-reg readyfordata;
-wire rfifo_full;
-wire [ 5: 0] rfifo_used;
-reg rvalid;
-reg sim_r_ena;
-reg sim_t_dat;
-reg sim_t_ena;
-reg sim_t_pause;
-wire [ 7: 0] t_dat;
-reg t_dav;
-wire t_ena;
-wire t_pause;
-wire wfifo_empty;
-wire [ 5: 0] wfifo_used;
-reg woverflow;
-wire wr_rfifo;
- //avalon_jtag_slave, which is an e_avalon_slave
- assign rd_wfifo = r_ena & ~wfifo_empty;
- assign wr_rfifo = t_ena & ~rfifo_full;
- assign fifo_clear = ~rst_n;
- qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_scfifo_w the_qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_scfifo_w
- (
- .clk (clk),
- .fifo_FF (fifo_FF),
- .fifo_clear (fifo_clear),
- .fifo_wdata (fifo_wdata),
- .fifo_wr (fifo_wr),
- .r_dat (r_dat),
- .rd_wfifo (rd_wfifo),
- .wfifo_empty (wfifo_empty),
- .wfifo_used (wfifo_used)
- );
-
- qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_scfifo_r the_qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_scfifo_r
- (
- .clk (clk),
- .fifo_EF (fifo_EF),
- .fifo_clear (fifo_clear),
- .fifo_rd (fifo_rd),
- .fifo_rdata (fifo_rdata),
- .rfifo_full (rfifo_full),
- .rfifo_used (rfifo_used),
- .rst_n (rst_n),
- .t_dat (t_dat),
- .wr_rfifo (wr_rfifo)
- );
-
- assign ipen_AE = ien_AE & fifo_AE;
- assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
- assign av_irq = ipen_AE | ipen_AF;
- assign activity = t_pause | t_ena;
- always @(posedge clk or negedge rst_n)
- begin
- if (rst_n == 0)
- pause_irq <= 1'b0;
- else // only if fifo is not empty...
- if (t_pause & ~fifo_EF)
- pause_irq <= 1'b1;
- else if (read_0)
- pause_irq <= 1'b0;
- end
-
-
- always @(posedge clk or negedge rst_n)
- begin
- if (rst_n == 0)
- begin
- r_val <= 1'b0;
- t_dav <= 1'b1;
- end
- else
- begin
- r_val <= r_ena & ~wfifo_empty;
- t_dav <= ~rfifo_full;
- end
- end
-
-
- always @(posedge clk or negedge rst_n)
- begin
- if (rst_n == 0)
- begin
- fifo_AE <= 1'b0;
- fifo_AF <= 1'b0;
- fifo_wr <= 1'b0;
- rvalid <= 1'b0;
- read_0 <= 1'b0;
- ien_AE <= 1'b0;
- ien_AF <= 1'b0;
- ac <= 1'b0;
- woverflow <= 1'b0;
- av_waitrequest <= 1'b1;
- end
- else
- begin
- fifo_AE <= {fifo_FF,wfifo_used} <= 8;
- fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
- fifo_wr <= 1'b0;
- read_0 <= 1'b0;
- av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
- if (activity)
- ac <= 1'b1;
- // write
- if (av_chipselect & ~av_write_n & av_waitrequest)
- // addr 1 is control; addr 0 is data
- if (av_address)
- begin
- ien_AF <= av_writedata[0];
- ien_AE <= av_writedata[1];
- if (av_writedata[10] & ~activity)
- ac <= 1'b0;
- end
- else
- begin
- fifo_wr <= ~fifo_FF;
- woverflow <= fifo_FF;
- end
- // read
- if (av_chipselect & ~av_read_n & av_waitrequest)
- begin
- // addr 1 is interrupt; addr 0 is data
- if (~av_address)
- rvalid <= ~fifo_EF;
- read_0 <= ~av_address;
- end
- end
- end
-
-
- assign fifo_wdata = av_writedata[7 : 0];
- assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
- assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
- always @(posedge clk or negedge rst_n)
- begin
- if (rst_n == 0)
- readyfordata <= 0;
- else
- readyfordata <= ~fifo_FF;
- end
-
-
-
-//synthesis translate_off
-//////////////// SIMULATION-ONLY CONTENTS
- // Tie off Atlantic Interface signals not used for simulation
- always @(posedge clk)
- begin
- sim_t_pause <= 1'b0;
- sim_t_ena <= 1'b0;
- sim_t_dat <= t_dav ? r_dat : {8{r_val}};
- sim_r_ena <= 1'b0;
- end
-
-
- assign r_ena = sim_r_ena;
- assign t_ena = sim_t_ena;
- assign t_dat = sim_t_dat;
- assign t_pause = sim_t_pause;
- always @(fifo_EF)
- begin
- dataavailable = ~fifo_EF;
- end
-
-
-
-//////////////// END SIMULATION-ONLY CONTENTS
-
-//synthesis translate_on
-//synthesis read_comments_as_HDL on
-// alt_jtag_atlantic qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_alt_jtag_atlantic
-// (
-// .clk (clk),
-// .r_dat (r_dat),
-// .r_ena (r_ena),
-// .r_val (r_val),
-// .rst_n (rst_n),
-// .t_dat (t_dat),
-// .t_dav (t_dav),
-// .t_ena (t_ena),
-// .t_pause (t_pause)
-// );
-//
-// defparam qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_alt_jtag_atlantic.INSTANCE_ID = 0,
-// qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
-// qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
-// qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
-//
-// always @(posedge clk or negedge rst_n)
-// begin
-// if (rst_n == 0)
-// dataavailable <= 0;
-// else
-// dataavailable <= ~fifo_EF;
-// end
-//
-//
-//synthesis read_comments_as_HDL off
-
-endmodule
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.bsf
deleted file mode 100644
index 36f9121c6145ef849c777ccd06d00bff6d42b765..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.bsf
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 304 280)
- (text "qsys_arts_unb2b_sc3_jtag_uart_0" (rect 50 -1 191 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 264 20 276)(font "Arial" ))
- (port
- (pt 0 72)
- (input)
- (text "av_chipselect" (rect 0 0 54 12)(font "Arial" (font_size 8)))
- (text "av_chipselect" (rect 4 61 82 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 112 72)(line_width 1))
- )
- (port
- (pt 0 88)
- (input)
- (text "av_address" (rect 0 0 48 12)(font "Arial" (font_size 8)))
- (text "av_address" (rect 4 77 64 88)(font "Arial" (font_size 8)))
- (line (pt 0 88)(pt 112 88)(line_width 1))
- )
- (port
- (pt 0 104)
- (input)
- (text "av_read_n" (rect 0 0 44 12)(font "Arial" (font_size 8)))
- (text "av_read_n" (rect 4 93 58 104)(font "Arial" (font_size 8)))
- (line (pt 0 104)(pt 112 104)(line_width 1))
- )
- (port
- (pt 0 136)
- (input)
- (text "av_write_n" (rect 0 0 44 12)(font "Arial" (font_size 8)))
- (text "av_write_n" (rect 4 125 64 136)(font "Arial" (font_size 8)))
- (line (pt 0 136)(pt 112 136)(line_width 1))
- )
- (port
- (pt 0 152)
- (input)
- (text "av_writedata[31..0]" (rect 0 0 74 12)(font "Arial" (font_size 8)))
- (text "av_writedata[31..0]" (rect 4 141 118 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 112 152)(line_width 3))
- )
- (port
- (pt 0 208)
- (input)
- (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8)))
- (text "clk" (rect 4 197 22 208)(font "Arial" (font_size 8)))
- (line (pt 0 208)(pt 112 208)(line_width 1))
- )
- (port
- (pt 0 248)
- (input)
- (text "rst_n" (rect 0 0 21 12)(font "Arial" (font_size 8)))
- (text "rst_n" (rect 4 237 34 248)(font "Arial" (font_size 8)))
- (line (pt 0 248)(pt 112 248)(line_width 1))
- )
- (port
- (pt 0 120)
- (output)
- (text "av_readdata[31..0]" (rect 0 0 74 12)(font "Arial" (font_size 8)))
- (text "av_readdata[31..0]" (rect 4 109 112 120)(font "Arial" (font_size 8)))
- (line (pt 0 120)(pt 112 120)(line_width 3))
- )
- (port
- (pt 0 168)
- (output)
- (text "av_waitrequest" (rect 0 0 60 12)(font "Arial" (font_size 8)))
- (text "av_waitrequest" (rect 4 157 88 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 112 168)(line_width 1))
- )
- (port
- (pt 304 72)
- (output)
- (text "av_irq" (rect 0 0 25 12)(font "Arial" (font_size 8)))
- (text "av_irq" (rect 271 61 307 72)(font "Arial" (font_size 8)))
- (line (pt 304 72)(pt 192 72)(line_width 1))
- )
- (drawing
- (text "avalon_jtag_slave" (rect 9 43 120 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "chipselect" (rect 117 67 294 144)(font "Arial" (color 0 0 0)))
- (text "address" (rect 117 83 276 176)(font "Arial" (color 0 0 0)))
- (text "read_n" (rect 117 99 270 208)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 117 115 282 240)(font "Arial" (color 0 0 0)))
- (text "write_n" (rect 117 131 276 272)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 117 147 288 304)(font "Arial" (color 0 0 0)))
- (text "waitrequest" (rect 117 163 300 336)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 97 179 212 371)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 117 203 252 416)(font "Arial" (color 0 0 0)))
- (text "irq" (rect 193 43 404 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "irq" (rect 178 67 374 144)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 83 219 196 451)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset_n" (rect 117 243 276 496)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_jtag_uart_0 " (rect 150 264 498 538)(font "Arial" ))
- (line (pt 112 32)(pt 192 32)(line_width 1))
- (line (pt 192 32)(pt 192 264)(line_width 1))
- (line (pt 112 264)(pt 192 264)(line_width 1))
- (line (pt 112 32)(pt 112 264)(line_width 1))
- (line (pt 113 52)(pt 113 172)(line_width 1))
- (line (pt 114 52)(pt 114 172)(line_width 1))
- (line (pt 113 188)(pt 113 212)(line_width 1))
- (line (pt 114 188)(pt 114 212)(line_width 1))
- (line (pt 191 52)(pt 191 76)(line_width 1))
- (line (pt 190 52)(pt 190 76)(line_width 1))
- (line (pt 113 228)(pt 113 252)(line_width 1))
- (line (pt 114 228)(pt 114 252)(line_width 1))
- (line (pt 0 0)(pt 304 0)(line_width 1))
- (line (pt 304 0)(pt 304 280)(line_width 1))
- (line (pt 0 280)(pt 304 280)(line_width 1))
- (line (pt 0 0)(pt 0 280)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.cmp
deleted file mode 100644
index 30f70a6aaa55dd0b98ed5a6880f40d55f0289221..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.cmp
+++ /dev/null
@@ -1,15 +0,0 @@
- component qsys_arts_unb2b_sc3_jtag_uart_0 is
- port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
- );
- end component qsys_arts_unb2b_sc3_jtag_uart_0;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.html
deleted file mode 100644
index 661906652046134babb20eef5f812e56d78f1556..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.html
+++ /dev/null
@@ -1,228 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_jtag_uart_0</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_jtag_uart_0</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:38:14</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_jtag_uart_0"><b>qsys_arts_unb2b_sc3_jtag_uart_0</b>
- </a> altera_avalon_jtag_uart 17.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_jtag_uart_0"><b>qsys_arts_unb2b_sc3_jtag_uart_0</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">avalon_jtag_slave </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_jtag_uart_0"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_jtag_uart_0</h2>altera_avalon_jtag_uart v17.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">allowMultipleConnections</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">hubInstanceID</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">readBufferDepth</td>
- <td class="parametervalue">64</td>
- </tr>
- <tr>
- <td class="parametername">readIRQThreshold</td>
- <td class="parametervalue">8</td>
- </tr>
- <tr>
- <td class="parametername">simInputCharacterStream</td>
- <td class="parametervalue"></td>
- </tr>
- <tr>
- <td class="parametername">simInteractiveOptions</td>
- <td class="parametervalue">NO_INTERACTIVE_WINDOWS</td>
- </tr>
- <tr>
- <td class="parametername">useRegistersForReadBuffer</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">useRegistersForWriteBuffer</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">useRelativePathForSimFile</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">writeBufferDepth</td>
- <td class="parametervalue">64</td>
- </tr>
- <tr>
- <td class="parametername">writeIRQThreshold</td>
- <td class="parametervalue">8</td>
- </tr>
- <tr>
- <td class="parametername">clkFreq</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">avalonSpec</td>
- <td class="parametervalue">2.0</td>
- </tr>
- <tr>
- <td class="parametername">legacySignalAllow</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">enableInteractiveInput</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">enableInteractiveOutput</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>
- <table>
- <tr>
- <td class="parametername">READ_DEPTH</td>
- <td class="parametervalue">64</td>
- </tr>
- <tr>
- <td class="parametername">READ_THRESHOLD</td>
- <td class="parametervalue">8</td>
- </tr>
- <tr>
- <td class="parametername">WRITE_DEPTH</td>
- <td class="parametervalue">64</td>
- </tr>
- <tr>
- <td class="parametername">WRITE_THRESHOLD</td>
- <td class="parametervalue">8</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.qgsynthc
deleted file mode 100644
index 3a7e9069f0483df82c87e79742be38ca04c64723..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.qgsynthc
+++ /dev/null
@@ -1,105 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_jtag_uart_0</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_jtag_uart_0</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_jtag_uart_0</name>
- <uniqueName>qsys_arts_unb2b_sc3_jtag_uart_0</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_jtag_uart_0</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>allowMultipleConnections</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>avalonSpec</name>
- <value>2.0</value>
- </parameter>
- <parameter>
- <name>clkFreq</name>
- <value>125000000</value>
- </parameter>
- <parameter>
- <name>enableInteractiveInput</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>enableInteractiveOutput</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>hubInstanceID</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>legacySignalAllow</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>readBufferDepth</name>
- <value>64</value>
- </parameter>
- <parameter>
- <name>readIRQThreshold</name>
- <value>8</value>
- </parameter>
- <parameter>
- <name>simInputCharacterStream</name>
- <value></value>
- </parameter>
- <parameter>
- <name>simInteractiveOptions</name>
- <value>NO_INTERACTIVE_WINDOWS</value>
- </parameter>
- <parameter>
- <name>useRegistersForReadBuffer</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>useRegistersForWriteBuffer</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>useRelativePathForSimFile</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>writeBufferDepth</name>
- <value>64</value>
- </parameter>
- <parameter>
- <name>writeIRQThreshold</name>
- <value>8</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>altera_avalon_jtag_uart</className>
- <version>17.0</version>
- <name>qsys_arts_unb2b_sc3_jtag_uart_0</name>
- <uniqueName>qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_jtag_uart_0.qsys_arts_unb2b_sc3_jtag_uart_0</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.qip
deleted file mode 100644
index 78fab6cc3bc3b90126b7d39c7a8401262e3d9423..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.qip
+++ /dev/null
@@ -1,55 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_jtag_uart_0.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_jtag_uart_0 HAS_SOPCINFO 1 GENERATION_ID 1527683892"
-set_global_assignment -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_jtag_uart_0.cmp"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name SLD_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_jtag_uart_0.regmap"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_jtag_uart_0.ip"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19qdGFnX3VhcnRfMF9hbHRlcmFfYXZhbG9uX2p0YWdfdWFydF8xNzBfeWR5Zmw3YQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_DISPLAY_NAME "SlRBRyBVQVJU"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_VERSION "MTcuMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "YWxsb3dNdWx0aXBsZUNvbm5lY3Rpb25z::ZmFsc2U=::QWxsb3cgbXVsdGlwbGUgY29ubmVjdGlvbnMgdG8gQXZhbG9uIEpUQUcgc2xhdmU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "aHViSW5zdGFuY2VJRA==::MA==::aHViSW5zdGFuY2VJRA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "cmVhZEJ1ZmZlckRlcHRo::NjQ=::QnVmZmVyIGRlcHRoIChieXRlcyk="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "cmVhZElSUVRocmVzaG9sZA==::OA==::SVJRIHRocmVzaG9sZA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "c2ltSW50ZXJhY3RpdmVPcHRpb25z::Tk9fSU5URVJBQ1RJVkVfV0lORE9XUw==::T3B0aW9ucw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "dXNlUmVnaXN0ZXJzRm9yUmVhZEJ1ZmZlcg==::ZmFsc2U=::Q29uc3RydWN0IHVzaW5nIHJlZ2lzdGVycyBpbnN0ZWFkIG9mIG1lbW9yeSBibG9ja3M="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "dXNlUmVnaXN0ZXJzRm9yV3JpdGVCdWZmZXI=::ZmFsc2U=::Q29uc3RydWN0IHVzaW5nIHJlZ2lzdGVycyBpbnN0ZWFkIG9mIG1lbW9yeSBibG9ja3M="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "dXNlUmVsYXRpdmVQYXRoRm9yU2ltRmlsZQ==::ZmFsc2U=::dXNlUmVsYXRpdmVQYXRoRm9yU2ltRmlsZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "d3JpdGVCdWZmZXJEZXB0aA==::NjQ=::QnVmZmVyIGRlcHRoIChieXRlcyk="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "d3JpdGVJUlFUaHJlc2hvbGQ=::OA==::SVJRIHRocmVzaG9sZA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "Y2xrRnJlcQ==::MTI1MDAwMDAw::Y2xrRnJlcQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "YXZhbG9uU3BlYw==::Mi4w::YXZhbG9uU3BlYw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "bGVnYWN5U2lnbmFsQWxsb3c=::ZmFsc2U=::bGVnYWN5U2lnbmFsQWxsb3c="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "ZW5hYmxlSW50ZXJhY3RpdmVJbnB1dA==::ZmFsc2U=::ZW5hYmxlSW50ZXJhY3RpdmVJbnB1dA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_PARAMETER "ZW5hYmxlSW50ZXJhY3RpdmVPdXRwdXQ=::ZmFsc2U=::ZW5hYmxlSW50ZXJhY3RpdmVPdXRwdXQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_GROUP "SW50ZXJmYWNlIFByb3RvY29scy9TZXJpYWw="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL3NmbzE0MDA3ODc5NTI5MzIvaWdhMTQwMTMxNzExMjEzOA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5NzY4OTMwMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19qdGFnX3VhcnRfMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4Mzg5Mg==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0" -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "altera_avalon_jtag_uart_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_jtag_uart_170/synth/qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a.v"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_jtag_uart_0" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_jtag_uart_0.vhd"]
-
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_TOOL_NAME "altera_avalon_jtag_uart"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_TOOL_VERSION "17.0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a" -library "altera_avalon_jtag_uart_170" -name IP_TOOL_ENV "QsysPrimePro"
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.regmap b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.regmap
deleted file mode 100644
index 1506631c356a4a599c3735cbb4d0361544e5505c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.regmap
+++ /dev/null
@@ -1,182 +0,0 @@
-<?xml version="1.0"?>
-<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
-<name>qsys_arts_unb2b_sc3_jtag_uart_0</name>
-<peripherals>
-<peripheral>
- <name>qsys_arts_unb2b_sc3_jtag_uart_0_avalon_jtag_slave_altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>8</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DATA</name>
- <displayName>Data</displayName>
- <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>data</name>
- <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>rvalid</name>
- <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description>
- <bitOffset>0xf</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>ravail</name>
- <description>The number of characters remaining in the read FIFO (after the current read).</description>
- <bitOffset>0x10</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CONTROL</name>
- <displayName>Control</displayName>
- <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>re</name>
- <description>Interrupt-enable bit for read interrupts.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>we</name>
- <description>Interrupt-enable bit for write interrupts</description>
- <bitOffset>0x1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>ri</name>
- <description>Indicates that the read interrupt is pending.</description>
- <bitOffset>0x8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>wi</name>
- <description>Indicates that the write interrupt is pending.</description>
- <bitOffset>0x9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>ac</name>
- <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description>
- <bitOffset>0xa</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>wspace</name>
- <description>The number of spaces available in the write FIFO</description>
- <bitOffset>0x10</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>qsys_arts_unb2b_sc3_jtag_uart_0_qsys_arts_unb2b_sc3_jtag_uart_0_avalon_jtag_slave_altera_avalon_jtag_uart</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>8</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DATA</name>
- <displayName>Data</displayName>
- <description>Embedded software accesses the read and write FIFOs via the data register. A read from the data register returns the first character from the FIFO (if one is available) in the DATA field. Reading also returns information about the number of characters remaining in the FIFO in the RAVAIL field. A write to the data register stores the value of the DATA field in the write FIFO. If the write FIFO is full, the character is lost.</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>data</name>
- <description>The value to transfer to/from the JTAG core. When writing, the DATA field holds a character to be written to the write FIFO. When reading, the DATA field holds a character read from the read FIFO.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>rvalid</name>
- <description>Indicates whether the DATA field is valid. If RVALID=1, the DATA field is valid, otherwise DATA is undefined.</description>
- <bitOffset>0xf</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>ravail</name>
- <description>The number of characters remaining in the read FIFO (after the current read).</description>
- <bitOffset>0x10</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CONTROL</name>
- <displayName>Control</displayName>
- <description>Embedded software controls the JTAG UART core's interrupt generation and reads status information via the control register. A read from the control register returns the status of the read and write FIFOs. Writes to the register can be used to enable/disable interrupts, or clear the AC bit.</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>re</name>
- <description>Interrupt-enable bit for read interrupts.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>we</name>
- <description>Interrupt-enable bit for write interrupts</description>
- <bitOffset>0x1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>ri</name>
- <description>Indicates that the read interrupt is pending.</description>
- <bitOffset>0x8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>wi</name>
- <description>Indicates that the write interrupt is pending.</description>
- <bitOffset>0x9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field><name>ac</name>
- <description>Indicates that there has been JTAG activity since the bit was cleared. Writing 1 to AC clears it to 0.</description>
- <bitOffset>0xa</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field><name>wspace</name>
- <description>The number of spaces available in the write FIFO</description>
- <bitOffset>0x10</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.sopcinfo
deleted file mode 100644
index b7b5c2c2e60e5abf53743df2dc8873bbbf7745de..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.sopcinfo
+++ /dev/null
@@ -1,923 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_jtag_uart_0"
- kind="qsys_arts_unb2b_sc3_jtag_uart_0"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:38:12 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527683892</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_CLK_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_jtag_uart_0"
- kind="altera_avalon_jtag_uart"
- version="17.0"
- path="qsys_arts_unb2b_sc3_jtag_uart_0">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <assignment>
- <name>embeddedsw.CMacro.READ_DEPTH</name>
- <value>64</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.READ_THRESHOLD</name>
- <value>8</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.WRITE_DEPTH</name>
- <value>64</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.WRITE_THRESHOLD</name>
- <value>8</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.compatible</name>
- <value>altr,juart-1.0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.group</name>
- <value>serial</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.name</name>
- <value>juart</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.vendor</name>
- <value>altr</value>
- </assignment>
- <parameter name="allowMultipleConnections">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="hubInstanceID">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readBufferDepth">
- <type>int</type>
- <value>64</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readIRQThreshold">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="simInputCharacterStream">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="simInteractiveOptions">
- <type>java.lang.String</type>
- <value>NO_INTERACTIVE_WINDOWS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="useRegistersForReadBuffer">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="useRegistersForWriteBuffer">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="useRelativePathForSimFile">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeBufferDepth">
- <type>int</type>
- <value>64</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeIRQThreshold">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clkFreq">
- <type>long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="avalonSpec">
- <type>java.lang.String</type>
- <value>2.0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>AVALON_SPEC</sysinfo_type>
- </parameter>
- <parameter name="legacySignalAllow">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="enableInteractiveInput">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="enableInteractiveOutput">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="clk" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>rst_n</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset_n</role>
- </port>
- </interface>
- <interface name="avalon_jtag_slave" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isFlash</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>1</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>NATIVE</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>2</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>av_chipselect</name>
- <direction>Input</direction>
- <width>1</width>
- <role>chipselect</role>
- </port>
- <port>
- <name>av_address</name>
- <direction>Input</direction>
- <width>1</width>
- <role>address</role>
- </port>
- <port>
- <name>av_read_n</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read_n</role>
- </port>
- <port>
- <name>av_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- <port>
- <name>av_write_n</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write_n</role>
- </port>
- <port>
- <name>av_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>av_waitrequest</name>
- <direction>Output</direction>
- <width>1</width>
- <role>waitrequest</role>
- </port>
- </interface>
- <interface name="irq" kind="interrupt_sender" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedAddressablePoint">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value>qsys_arts_unb2b_sc3_jtag_uart_0.avalon_jtag_slave</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedReceiverOffset">
- <type>java.lang.Integer</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToReceiver">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="irqScheme">
- <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
- <value>NONE</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>interrupt</type>
- <isStart>false</isStart>
- <port>
- <name>av_irq</name>
- <direction>Output</direction>
- <width>1</width>
- <role>irq</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>altera_avalon_jtag_uart</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>JTAG UART</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>interrupt_sender</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Interrupt Sender</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.xml
deleted file mode 100644
index 9438c8de88f9003928556e1d83adc5e20eda8d89..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0.xml
+++ /dev/null
@@ -1,210 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:38:16"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="avalon_jtag_slave" kind="avalon" start="0">
- <property name="addressAlignment" value="NATIVE" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="2" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="clk" />
- <property name="associatedReset" value="reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="true" />
- <property name="readLatency" value="0" />
- <property name="readWaitStates" value="1" />
- <property name="readWaitTime" value="1" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="av_chipselect" direction="input" role="chipselect" width="1" />
- <port name="av_address" direction="input" role="address" width="1" />
- <port name="av_read_n" direction="input" role="read_n" width="1" />
- <port name="av_readdata" direction="output" role="readdata" width="32" />
- <port name="av_write_n" direction="input" role="write_n" width="1" />
- <port name="av_writedata" direction="input" role="writedata" width="32" />
- <port name="av_waitrequest" direction="output" role="waitrequest" width="1" />
- </interface>
- <interface name="clk" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="irq" kind="interrupt" start="0">
- <property
- name="associatedAddressablePoint"
- value="qsys_arts_unb2b_sc3_jtag_uart_0.avalon_jtag_slave" />
- <property name="associatedClock" value="clk" />
- <property name="associatedReset" value="reset" />
- <property name="bridgedReceiverOffset" value="0" />
- <property name="bridgesToReceiver" value="" />
- <property name="irqScheme" value="NONE" />
- <port name="av_irq" direction="output" role="irq" width="1" />
- </interface>
- <interface name="reset" kind="reset" start="0">
- <property name="associatedClock" value="clk" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="rst_n" direction="input" role="reset_n" width="1" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_jtag_uart_0"
- version="1.0"
- name="qsys_arts_unb2b_sc3_jtag_uart_0">
- <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527683892" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/synth/qsys_arts_unb2b_sc3_jtag_uart_0.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/synth/qsys_arts_unb2b_sc3_jtag_uart_0.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_jtag_uart_0">"Generating: qsys_arts_unb2b_sc3_jtag_uart_0"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_jtag_uart_0">"Generating: qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_jtag_uart_0">Starting RTL generation for module 'qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a'</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_jtag_uart_0"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a --dir=/tmp/alt7681_6931282645914172388.dir/0006_qsys_arts_unb2b_sc3_jtag_uart_0_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0006_qsys_arts_unb2b_sc3_jtag_uart_0_gen//qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_component_configuration.pl --do_build_sim=0 ]</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_jtag_uart_0">Done RTL generation for module 'qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a'</message>
- </messages>
- </entity>
- <entity
- kind="altera_avalon_jtag_uart"
- version="17.0"
- name="qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a">
- <parameter name="readBufferDepth" value="64" />
- <parameter name="clkFreq" value="125000000" />
- <parameter name="useRelativePathForSimFile" value="false" />
- <parameter name="hubInstanceID" value="0" />
- <parameter name="enableInteractiveInput" value="false" />
- <parameter name="avalonSpec" value="2.0" />
- <parameter name="simInputCharacterStream" value="" />
- <parameter name="readIRQThreshold" value="8" />
- <parameter name="useRegistersForWriteBuffer" value="false" />
- <parameter name="useRegistersForReadBuffer" value="false" />
- <parameter name="simInteractiveOptions" value="NO_INTERACTIVE_WINDOWS" />
- <parameter name="enableInteractiveOutput" value="false" />
- <parameter name="writeIRQThreshold" value="8" />
- <parameter name="writeBufferDepth" value="64" />
- <parameter name="allowMultipleConnections" value="false" />
- <parameter name="legacySignalAllow" value="false" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/altera_avalon_jtag_uart_170/synth/qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a.v"
- attributes="" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/altera_avalon_jtag_uart_170/synth/qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a.v"
- attributes="" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/altera_avalon_jtag_uart_hw.tcl" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_jtag_uart_0"
- as="qsys_arts_unb2b_sc3_jtag_uart_0" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_jtag_uart_0">"Generating: qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_jtag_uart_0">Starting RTL generation for module 'qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a'</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_jtag_uart_0"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a --dir=/tmp/alt7681_6931282645914172388.dir/0006_qsys_arts_unb2b_sc3_jtag_uart_0_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0006_qsys_arts_unb2b_sc3_jtag_uart_0_gen//qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_component_configuration.pl --do_build_sim=0 ]</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_jtag_uart_0">Done RTL generation for module 'qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a'</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_bb.v
deleted file mode 100644
index a10dd4cb0034487ac98b1f2a53e25eefc6d9c449..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_bb.v
+++ /dev/null
@@ -1,24 +0,0 @@
-
-module qsys_arts_unb2b_sc3_jtag_uart_0 (
- av_chipselect,
- av_address,
- av_read_n,
- av_readdata,
- av_write_n,
- av_writedata,
- av_waitrequest,
- clk,
- av_irq,
- rst_n);
-
- input av_chipselect;
- input av_address;
- input av_read_n;
- output [31:0] av_readdata;
- input av_write_n;
- input [31:0] av_writedata;
- output av_waitrequest;
- input clk;
- output av_irq;
- input rst_n;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_generation.rpt
deleted file mode 100644
index 942a9a7ae6aa28f4ceae5754cedc06a756e73133..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_generation.rpt
+++ /dev/null
@@ -1,30 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_jtag_uart_0.qsys_arts_unb2b_sc3_jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_jtag_uart_0.qsys_arts_unb2b_sc3_jtag_uart_0: JTAG UART IP input clock need to be at least double (2x) the operating frequency of JTAG TCK on board
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: "Transforming system: qsys_arts_unb2b_sc3_jtag_uart_0"
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Running transform interconnect_transform_chooser took 0.008s
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: "Naming system components in system: qsys_arts_unb2b_sc3_jtag_uart_0"
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: "Generating: qsys_arts_unb2b_sc3_jtag_uart_0"
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: "Generating: qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a"
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Starting RTL generation for module 'qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a'
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_jtag_uart/generate_rtl.pl --name=qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a --dir=/tmp/alt7681_6931282645914172388.dir/0006_qsys_arts_unb2b_sc3_jtag_uart_0_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0006_qsys_arts_unb2b_sc3_jtag_uart_0_gen//qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_component_configuration.pl --do_build_sim=0 ]
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Done RTL generation for module 'qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a'
-Info: qsys_arts_unb2b_sc3_jtag_uart_0: Done "qsys_arts_unb2b_sc3_jtag_uart_0" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_jtag_uart_0. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_inst.v
deleted file mode 100644
index 2ada99b05fcc8b1aaf5a5649b9d7622806caf33b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_inst.v
+++ /dev/null
@@ -1,13 +0,0 @@
- qsys_arts_unb2b_sc3_jtag_uart_0 u0 (
- .av_chipselect (_connected_to_av_chipselect_), // avalon_jtag_slave.chipselect
- .av_address (_connected_to_av_address_), // .address
- .av_read_n (_connected_to_av_read_n_), // .read_n
- .av_readdata (_connected_to_av_readdata_), // .readdata
- .av_write_n (_connected_to_av_write_n_), // .write_n
- .av_writedata (_connected_to_av_writedata_), // .writedata
- .av_waitrequest (_connected_to_av_waitrequest_), // .waitrequest
- .clk (_connected_to_clk_), // clk.clk
- .av_irq (_connected_to_av_irq_), // irq.irq
- .rst_n (_connected_to_rst_n_) // reset.reset_n
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_inst.vhd
deleted file mode 100644
index 01c4a56208711317ef49e4f9cd2b9b4f732bf3f2..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/qsys_arts_unb2b_sc3_jtag_uart_0_inst.vhd
+++ /dev/null
@@ -1,29 +0,0 @@
- component qsys_arts_unb2b_sc3_jtag_uart_0 is
- port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
- );
- end component qsys_arts_unb2b_sc3_jtag_uart_0;
-
- u0 : component qsys_arts_unb2b_sc3_jtag_uart_0
- port map (
- av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => CONNECTED_TO_av_address, -- .address
- av_read_n => CONNECTED_TO_av_read_n, -- .read_n
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_write_n => CONNECTED_TO_av_write_n, -- .write_n
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
- clk => CONNECTED_TO_clk, -- clk.clk
- av_irq => CONNECTED_TO_av_irq, -- irq.irq
- rst_n => CONNECTED_TO_rst_n -- reset.reset_n
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/synth/qsys_arts_unb2b_sc3_jtag_uart_0.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/synth/qsys_arts_unb2b_sc3_jtag_uart_0.vhd
deleted file mode 100644
index 461aaf8a48ec626e2b80b9e8a5eb6fc2d5bd9049..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0/synth/qsys_arts_unb2b_sc3_jtag_uart_0.vhd
+++ /dev/null
@@ -1,59 +0,0 @@
--- qsys_arts_unb2b_sc3_jtag_uart_0.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library altera_avalon_jtag_uart_170;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_jtag_uart_0 is
- port (
- av_chipselect : in std_logic := '0'; -- avalon_jtag_slave.chipselect
- av_address : in std_logic := '0'; -- .address
- av_read_n : in std_logic := '0'; -- .read_n
- av_readdata : out std_logic_vector(31 downto 0); -- .readdata
- av_write_n : in std_logic := '0'; -- .write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- av_waitrequest : out std_logic; -- .waitrequest
- clk : in std_logic := '0'; -- clk.clk
- av_irq : out std_logic; -- irq.irq
- rst_n : in std_logic := '0' -- reset.reset_n
- );
-end entity qsys_arts_unb2b_sc3_jtag_uart_0;
-
-architecture rtl of qsys_arts_unb2b_sc3_jtag_uart_0 is
- component qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_cmp is
- port (
- clk : in std_logic := 'X'; -- clk
- rst_n : in std_logic := 'X'; -- reset_n
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- av_irq : out std_logic -- irq
- );
- end component qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_cmp;
-
- for qsys_arts_unb2b_sc3_jtag_uart_0 : qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_cmp
- use entity altera_avalon_jtag_uart_170.qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a;
-begin
-
- qsys_arts_unb2b_sc3_jtag_uart_0 : component qsys_arts_unb2b_sc3_jtag_uart_0_altera_avalon_jtag_uart_170_ydyfl7a_cmp
- port map (
- clk => clk, -- clk.clk
- rst_n => rst_n, -- reset.reset_n
- av_chipselect => av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => av_address, -- .address
- av_read_n => av_read_n, -- .read_n
- av_readdata => av_readdata, -- .readdata
- av_write_n => av_write_n, -- .write_n
- av_writedata => av_writedata, -- .writedata
- av_waitrequest => av_waitrequest, -- .waitrequest
- av_irq => av_irq -- irq.irq
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_jtag_uart_0
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0.ip
index 288d58f5abe3216b59866ae788e44c704f0e114e..b13664f4902f0559c48c5bdb522da1a4eda01e96 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0.ip
@@ -148,7 +148,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">131072</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -203,7 +203,7 @@
<spirit:parameter>
<spirit:name>explicitAddressSpan</spirit:name>
<spirit:displayName>Explicit address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">4096</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">131072</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>holdTime</spirit:name>
@@ -395,7 +395,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>9</spirit:right>
+ <spirit:right>14</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -567,7 +567,7 @@
<spirit:parameter>
<spirit:name>initializationFileName</spirit:name>
<spirit:displayName>User created initialization file</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="initializationFileName">onchip_mem.hex</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="initializationFileName">onchip_memory2_0.hex</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>enPRInitMode</spirit:name>
@@ -582,7 +582,7 @@
<spirit:parameter>
<spirit:name>memorySize</spirit:name>
<spirit:displayName>Total memory size</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="memorySize">4096</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="memorySize">131072</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>readDuringWriteMode</spirit:name>
@@ -622,7 +622,7 @@
<spirit:parameter>
<spirit:name>useNonDefaultInitFile</spirit:name>
<spirit:displayName>Enable non-default initialization file</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="useNonDefaultInitFile">false</spirit:value>
+ <spirit:value spirit:format="bool" spirit:id="useNonDefaultInitFile">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>copyInitFile</spirit:name>
@@ -667,12 +667,12 @@
<spirit:parameter>
<spirit:name>derived_set_addr_width</spirit:name>
<spirit:displayName>Slave 1 address width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="derived_set_addr_width">10</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="derived_set_addr_width">15</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>derived_set_addr_width2</spirit:name>
<spirit:displayName>Slave 2 address width</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="derived_set_addr_width2">10</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="derived_set_addr_width2">15</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>derived_set_data_width</spirit:name>
@@ -697,7 +697,7 @@
<spirit:parameter>
<spirit:name>derived_init_file_name</spirit:name>
<spirit:displayName>derived_init_file_name</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="derived_init_file_name">qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="derived_init_file_name">onchip_memory2_0.hex</spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_module_parameters>
@@ -725,7 +725,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.INIT_CONTENTS_FILE</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.INIT_CONTENTS_FILE">qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.INIT_CONTENTS_FILE">onchip_memory2_0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.INIT_MEM_CONTENT</spirit:name>
@@ -737,7 +737,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED">0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.RAM_BLOCK_TYPE</spirit:name>
@@ -757,7 +757,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.SIZE_VALUE</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SIZE_VALUE">4096</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SIZE_VALUE">131072</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.WRITABLE</spirit:name>
@@ -789,7 +789,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.MEM_INIT_FILENAME">qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.memoryInfo.MEM_INIT_FILENAME">onchip_memory2_0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>postgeneration.simulation.init_file.param_name</spirit:name>
@@ -916,7 +916,7 @@
<name>address</name>
<role>address</role>
<direction>Input</direction>
- <width>10</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1001,7 +1001,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>4096</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1044,7 +1044,7 @@
</entry>
<entry>
<key>explicitAddressSpan</key>
- <value>4096</value>
+ <value>131072</value>
</entry>
<entry>
<key>holdTime</key>
@@ -1173,11 +1173,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='s1' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='s1' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>12</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq.v
deleted file mode 100644
index dd9d1e103d173afa883aeaba2f1c3d679d68b83a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq.v
+++ /dev/null
@@ -1,89 +0,0 @@
-//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq (
- // inputs:
- address,
- byteenable,
- chipselect,
- clk,
- clken,
- freeze,
- reset,
- reset_req,
- write,
- writedata,
-
- // outputs:
- readdata
- )
-;
-
- parameter INIT_FILE = "qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex";
-
-
- output [ 31: 0] readdata;
- input [ 9: 0] address;
- input [ 3: 0] byteenable;
- input chipselect;
- input clk;
- input clken;
- input freeze;
- input reset;
- input reset_req;
- input write;
- input [ 31: 0] writedata;
-
-
-wire clocken0;
-wire [ 31: 0] readdata;
-wire wren;
- assign wren = chipselect & write;
- assign clocken0 = clken & ~reset_req;
- altsyncram the_altsyncram
- (
- .address_a (address),
- .byteena_a (byteenable),
- .clock0 (clk),
- .clocken0 (clocken0),
- .data_a (writedata),
- .q_a (readdata),
- .wren_a (wren)
- );
-
- defparam the_altsyncram.byte_size = 8,
- the_altsyncram.init_file = INIT_FILE,
- the_altsyncram.lpm_type = "altsyncram",
- the_altsyncram.maximum_depth = 1024,
- the_altsyncram.numwords_a = 1024,
- the_altsyncram.operation_mode = "SINGLE_PORT",
- the_altsyncram.outdata_reg_a = "UNREGISTERED",
- the_altsyncram.ram_block_type = "AUTO",
- the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
- the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
- the_altsyncram.width_a = 32,
- the_altsyncram.width_byteena_a = 4,
- the_altsyncram.widthad_a = 10;
-
- //s1, which is an e_avalon_slave
- //s2, which is an e_avalon_slave
-
-endmodule
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex
deleted file mode 100644
index 4de6020da721920569bb985cf8b09cf1cc03c51c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex
+++ /dev/null
@@ -1,1025 +0,0 @@
-:0400000000000000FC
-:0400010000000000FB
-:0400020000000000FA
-:0400030000000000F9
-:0400040000000000F8
-:0400050000000000F7
-:0400060000000000F6
-:0400070000000000F5
-:0400080000000000F4
-:0400090000000000F3
-:04000A0000000000F2
-:04000B0000000000F1
-:04000C0000000000F0
-:04000D0000000000EF
-:04000E0000000000EE
-:04000F0000000000ED
-:0400100000000000EC
-:0400110000000000EB
-:0400120000000000EA
-:0400130000000000E9
-:0400140000000000E8
-:0400150000000000E7
-:0400160000000000E6
-:0400170000000000E5
-:0400180000000000E4
-:0400190000000000E3
-:04001A0000000000E2
-:04001B0000000000E1
-:04001C0000000000E0
-:04001D0000000000DF
-:04001E0000000000DE
-:04001F0000000000DD
-:0400200000000000DC
-:0400210000000000DB
-:0400220000000000DA
-:0400230000000000D9
-:0400240000000000D8
-:0400250000000000D7
-:0400260000000000D6
-:0400270000000000D5
-:0400280000000000D4
-:0400290000000000D3
-:04002A0000000000D2
-:04002B0000000000D1
-:04002C0000000000D0
-:04002D0000000000CF
-:04002E0000000000CE
-:04002F0000000000CD
-:0400300000000000CC
-:0400310000000000CB
-:0400320000000000CA
-:0400330000000000C9
-:0400340000000000C8
-:0400350000000000C7
-:0400360000000000C6
-:0400370000000000C5
-:0400380000000000C4
-:0400390000000000C3
-:04003A0000000000C2
-:04003B0000000000C1
-:04003C0000000000C0
-:04003D0000000000BF
-:04003E0000000000BE
-:04003F0000000000BD
-:0400400000000000BC
-:0400410000000000BB
-:0400420000000000BA
-:0400430000000000B9
-:0400440000000000B8
-:0400450000000000B7
-:0400460000000000B6
-:0400470000000000B5
-:0400480000000000B4
-:0400490000000000B3
-:04004A0000000000B2
-:04004B0000000000B1
-:04004C0000000000B0
-:04004D0000000000AF
-:04004E0000000000AE
-:04004F0000000000AD
-:0400500000000000AC
-:0400510000000000AB
-:0400520000000000AA
-:0400530000000000A9
-:0400540000000000A8
-:0400550000000000A7
-:0400560000000000A6
-:0400570000000000A5
-:0400580000000000A4
-:0400590000000000A3
-:04005A0000000000A2
-:04005B0000000000A1
-:04005C0000000000A0
-:04005D00000000009F
-:04005E00000000009E
-:04005F00000000009D
-:04006000000000009C
-:04006100000000009B
-:04006200000000009A
-:040063000000000099
-:040064000000000098
-:040065000000000097
-:040066000000000096
-:040067000000000095
-:040068000000000094
-:040069000000000093
-:04006A000000000092
-:04006B000000000091
-:04006C000000000090
-:04006D00000000008F
-:04006E00000000008E
-:04006F00000000008D
-:04007000000000008C
-:04007100000000008B
-:04007200000000008A
-:040073000000000089
-:040074000000000088
-:040075000000000087
-:040076000000000086
-:040077000000000085
-:040078000000000084
-:040079000000000083
-:04007A000000000082
-:04007B000000000081
-:04007C000000000080
-:04007D00000000007F
-:04007E00000000007E
-:04007F00000000007D
-:04008000000000007C
-:04008100000000007B
-:04008200000000007A
-:040083000000000079
-:040084000000000078
-:040085000000000077
-:040086000000000076
-:040087000000000075
-:040088000000000074
-:040089000000000073
-:04008A000000000072
-:04008B000000000071
-:04008C000000000070
-:04008D00000000006F
-:04008E00000000006E
-:04008F00000000006D
-:04009000000000006C
-:04009100000000006B
-:04009200000000006A
-:040093000000000069
-:040094000000000068
-:040095000000000067
-:040096000000000066
-:040097000000000065
-:040098000000000064
-:040099000000000063
-:04009A000000000062
-:04009B000000000061
-:04009C000000000060
-:04009D00000000005F
-:04009E00000000005E
-:04009F00000000005D
-:0400A000000000005C
-:0400A100000000005B
-:0400A200000000005A
-:0400A3000000000059
-:0400A4000000000058
-:0400A5000000000057
-:0400A6000000000056
-:0400A7000000000055
-:0400A8000000000054
-:0400A9000000000053
-:0400AA000000000052
-:0400AB000000000051
-:0400AC000000000050
-:0400AD00000000004F
-:0400AE00000000004E
-:0400AF00000000004D
-:0400B000000000004C
-:0400B100000000004B
-:0400B200000000004A
-:0400B3000000000049
-:0400B4000000000048
-:0400B5000000000047
-:0400B6000000000046
-:0400B7000000000045
-:0400B8000000000044
-:0400B9000000000043
-:0400BA000000000042
-:0400BB000000000041
-:0400BC000000000040
-:0400BD00000000003F
-:0400BE00000000003E
-:0400BF00000000003D
-:0400C000000000003C
-:0400C100000000003B
-:0400C200000000003A
-:0400C3000000000039
-:0400C4000000000038
-:0400C5000000000037
-:0400C6000000000036
-:0400C7000000000035
-:0400C8000000000034
-:0400C9000000000033
-:0400CA000000000032
-:0400CB000000000031
-:0400CC000000000030
-:0400CD00000000002F
-:0400CE00000000002E
-:0400CF00000000002D
-:0400D000000000002C
-:0400D100000000002B
-:0400D200000000002A
-:0400D3000000000029
-:0400D4000000000028
-:0400D5000000000027
-:0400D6000000000026
-:0400D7000000000025
-:0400D8000000000024
-:0400D9000000000023
-:0400DA000000000022
-:0400DB000000000021
-:0400DC000000000020
-:0400DD00000000001F
-:0400DE00000000001E
-:0400DF00000000001D
-:0400E000000000001C
-:0400E100000000001B
-:0400E200000000001A
-:0400E3000000000019
-:0400E4000000000018
-:0400E5000000000017
-:0400E6000000000016
-:0400E7000000000015
-:0400E8000000000014
-:0400E9000000000013
-:0400EA000000000012
-:0400EB000000000011
-:0400EC000000000010
-:0400ED00000000000F
-:0400EE00000000000E
-:0400EF00000000000D
-:0400F000000000000C
-:0400F100000000000B
-:0400F200000000000A
-:0400F3000000000009
-:0400F4000000000008
-:0400F5000000000007
-:0400F6000000000006
-:0400F7000000000005
-:0400F8000000000004
-:0400F9000000000003
-:0400FA000000000002
-:0400FB000000000001
-:0400FC000000000000
-:0400FD0000000000FF
-:0400FE0000000000FE
-:0400FF0000000000FD
-:0401000000000000FB
-:0401010000000000FA
-:0401020000000000F9
-:0401030000000000F8
-:0401040000000000F7
-:0401050000000000F6
-:0401060000000000F5
-:0401070000000000F4
-:0401080000000000F3
-:0401090000000000F2
-:04010A0000000000F1
-:04010B0000000000F0
-:04010C0000000000EF
-:04010D0000000000EE
-:04010E0000000000ED
-:04010F0000000000EC
-:0401100000000000EB
-:0401110000000000EA
-:0401120000000000E9
-:0401130000000000E8
-:0401140000000000E7
-:0401150000000000E6
-:0401160000000000E5
-:0401170000000000E4
-:0401180000000000E3
-:0401190000000000E2
-:04011A0000000000E1
-:04011B0000000000E0
-:04011C0000000000DF
-:04011D0000000000DE
-:04011E0000000000DD
-:04011F0000000000DC
-:0401200000000000DB
-:0401210000000000DA
-:0401220000000000D9
-:0401230000000000D8
-:0401240000000000D7
-:0401250000000000D6
-:0401260000000000D5
-:0401270000000000D4
-:0401280000000000D3
-:0401290000000000D2
-:04012A0000000000D1
-:04012B0000000000D0
-:04012C0000000000CF
-:04012D0000000000CE
-:04012E0000000000CD
-:04012F0000000000CC
-:0401300000000000CB
-:0401310000000000CA
-:0401320000000000C9
-:0401330000000000C8
-:0401340000000000C7
-:0401350000000000C6
-:0401360000000000C5
-:0401370000000000C4
-:0401380000000000C3
-:0401390000000000C2
-:04013A0000000000C1
-:04013B0000000000C0
-:04013C0000000000BF
-:04013D0000000000BE
-:04013E0000000000BD
-:04013F0000000000BC
-:0401400000000000BB
-:0401410000000000BA
-:0401420000000000B9
-:0401430000000000B8
-:0401440000000000B7
-:0401450000000000B6
-:0401460000000000B5
-:0401470000000000B4
-:0401480000000000B3
-:0401490000000000B2
-:04014A0000000000B1
-:04014B0000000000B0
-:04014C0000000000AF
-:04014D0000000000AE
-:04014E0000000000AD
-:04014F0000000000AC
-:0401500000000000AB
-:0401510000000000AA
-:0401520000000000A9
-:0401530000000000A8
-:0401540000000000A7
-:0401550000000000A6
-:0401560000000000A5
-:0401570000000000A4
-:0401580000000000A3
-:0401590000000000A2
-:04015A0000000000A1
-:04015B0000000000A0
-:04015C00000000009F
-:04015D00000000009E
-:04015E00000000009D
-:04015F00000000009C
-:04016000000000009B
-:04016100000000009A
-:040162000000000099
-:040163000000000098
-:040164000000000097
-:040165000000000096
-:040166000000000095
-:040167000000000094
-:040168000000000093
-:040169000000000092
-:04016A000000000091
-:04016B000000000090
-:04016C00000000008F
-:04016D00000000008E
-:04016E00000000008D
-:04016F00000000008C
-:04017000000000008B
-:04017100000000008A
-:040172000000000089
-:040173000000000088
-:040174000000000087
-:040175000000000086
-:040176000000000085
-:040177000000000084
-:040178000000000083
-:040179000000000082
-:04017A000000000081
-:04017B000000000080
-:04017C00000000007F
-:04017D00000000007E
-:04017E00000000007D
-:04017F00000000007C
-:04018000000000007B
-:04018100000000007A
-:040182000000000079
-:040183000000000078
-:040184000000000077
-:040185000000000076
-:040186000000000075
-:040187000000000074
-:040188000000000073
-:040189000000000072
-:04018A000000000071
-:04018B000000000070
-:04018C00000000006F
-:04018D00000000006E
-:04018E00000000006D
-:04018F00000000006C
-:04019000000000006B
-:04019100000000006A
-:040192000000000069
-:040193000000000068
-:040194000000000067
-:040195000000000066
-:040196000000000065
-:040197000000000064
-:040198000000000063
-:040199000000000062
-:04019A000000000061
-:04019B000000000060
-:04019C00000000005F
-:04019D00000000005E
-:04019E00000000005D
-:04019F00000000005C
-:0401A000000000005B
-:0401A100000000005A
-:0401A2000000000059
-:0401A3000000000058
-:0401A4000000000057
-:0401A5000000000056
-:0401A6000000000055
-:0401A7000000000054
-:0401A8000000000053
-:0401A9000000000052
-:0401AA000000000051
-:0401AB000000000050
-:0401AC00000000004F
-:0401AD00000000004E
-:0401AE00000000004D
-:0401AF00000000004C
-:0401B000000000004B
-:0401B100000000004A
-:0401B2000000000049
-:0401B3000000000048
-:0401B4000000000047
-:0401B5000000000046
-:0401B6000000000045
-:0401B7000000000044
-:0401B8000000000043
-:0401B9000000000042
-:0401BA000000000041
-:0401BB000000000040
-:0401BC00000000003F
-:0401BD00000000003E
-:0401BE00000000003D
-:0401BF00000000003C
-:0401C000000000003B
-:0401C100000000003A
-:0401C2000000000039
-:0401C3000000000038
-:0401C4000000000037
-:0401C5000000000036
-:0401C6000000000035
-:0401C7000000000034
-:0401C8000000000033
-:0401C9000000000032
-:0401CA000000000031
-:0401CB000000000030
-:0401CC00000000002F
-:0401CD00000000002E
-:0401CE00000000002D
-:0401CF00000000002C
-:0401D000000000002B
-:0401D100000000002A
-:0401D2000000000029
-:0401D3000000000028
-:0401D4000000000027
-:0401D5000000000026
-:0401D6000000000025
-:0401D7000000000024
-:0401D8000000000023
-:0401D9000000000022
-:0401DA000000000021
-:0401DB000000000020
-:0401DC00000000001F
-:0401DD00000000001E
-:0401DE00000000001D
-:0401DF00000000001C
-:0401E000000000001B
-:0401E100000000001A
-:0401E2000000000019
-:0401E3000000000018
-:0401E4000000000017
-:0401E5000000000016
-:0401E6000000000015
-:0401E7000000000014
-:0401E8000000000013
-:0401E9000000000012
-:0401EA000000000011
-:0401EB000000000010
-:0401EC00000000000F
-:0401ED00000000000E
-:0401EE00000000000D
-:0401EF00000000000C
-:0401F000000000000B
-:0401F100000000000A
-:0401F2000000000009
-:0401F3000000000008
-:0401F4000000000007
-:0401F5000000000006
-:0401F6000000000005
-:0401F7000000000004
-:0401F8000000000003
-:0401F9000000000002
-:0401FA000000000001
-:0401FB000000000000
-:0401FC0000000000FF
-:0401FD0000000000FE
-:0401FE0000000000FD
-:0401FF0000000000FC
-:0402000000000000FA
-:0402010000000000F9
-:0402020000000000F8
-:0402030000000000F7
-:0402040000000000F6
-:0402050000000000F5
-:0402060000000000F4
-:0402070000000000F3
-:0402080000000000F2
-:0402090000000000F1
-:04020A0000000000F0
-:04020B0000000000EF
-:04020C0000000000EE
-:04020D0000000000ED
-:04020E0000000000EC
-:04020F0000000000EB
-:0402100000000000EA
-:0402110000000000E9
-:0402120000000000E8
-:0402130000000000E7
-:0402140000000000E6
-:0402150000000000E5
-:0402160000000000E4
-:0402170000000000E3
-:0402180000000000E2
-:0402190000000000E1
-:04021A0000000000E0
-:04021B0000000000DF
-:04021C0000000000DE
-:04021D0000000000DD
-:04021E0000000000DC
-:04021F0000000000DB
-:0402200000000000DA
-:0402210000000000D9
-:0402220000000000D8
-:0402230000000000D7
-:0402240000000000D6
-:0402250000000000D5
-:0402260000000000D4
-:0402270000000000D3
-:0402280000000000D2
-:0402290000000000D1
-:04022A0000000000D0
-:04022B0000000000CF
-:04022C0000000000CE
-:04022D0000000000CD
-:04022E0000000000CC
-:04022F0000000000CB
-:0402300000000000CA
-:0402310000000000C9
-:0402320000000000C8
-:0402330000000000C7
-:0402340000000000C6
-:0402350000000000C5
-:0402360000000000C4
-:0402370000000000C3
-:0402380000000000C2
-:0402390000000000C1
-:04023A0000000000C0
-:04023B0000000000BF
-:04023C0000000000BE
-:04023D0000000000BD
-:04023E0000000000BC
-:04023F0000000000BB
-:0402400000000000BA
-:0402410000000000B9
-:0402420000000000B8
-:0402430000000000B7
-:0402440000000000B6
-:0402450000000000B5
-:0402460000000000B4
-:0402470000000000B3
-:0402480000000000B2
-:0402490000000000B1
-:04024A0000000000B0
-:04024B0000000000AF
-:04024C0000000000AE
-:04024D0000000000AD
-:04024E0000000000AC
-:04024F0000000000AB
-:0402500000000000AA
-:0402510000000000A9
-:0402520000000000A8
-:0402530000000000A7
-:0402540000000000A6
-:0402550000000000A5
-:0402560000000000A4
-:0402570000000000A3
-:0402580000000000A2
-:0402590000000000A1
-:04025A0000000000A0
-:04025B00000000009F
-:04025C00000000009E
-:04025D00000000009D
-:04025E00000000009C
-:04025F00000000009B
-:04026000000000009A
-:040261000000000099
-:040262000000000098
-:040263000000000097
-:040264000000000096
-:040265000000000095
-:040266000000000094
-:040267000000000093
-:040268000000000092
-:040269000000000091
-:04026A000000000090
-:04026B00000000008F
-:04026C00000000008E
-:04026D00000000008D
-:04026E00000000008C
-:04026F00000000008B
-:04027000000000008A
-:040271000000000089
-:040272000000000088
-:040273000000000087
-:040274000000000086
-:040275000000000085
-:040276000000000084
-:040277000000000083
-:040278000000000082
-:040279000000000081
-:04027A000000000080
-:04027B00000000007F
-:04027C00000000007E
-:04027D00000000007D
-:04027E00000000007C
-:04027F00000000007B
-:04028000000000007A
-:040281000000000079
-:040282000000000078
-:040283000000000077
-:040284000000000076
-:040285000000000075
-:040286000000000074
-:040287000000000073
-:040288000000000072
-:040289000000000071
-:04028A000000000070
-:04028B00000000006F
-:04028C00000000006E
-:04028D00000000006D
-:04028E00000000006C
-:04028F00000000006B
-:04029000000000006A
-:040291000000000069
-:040292000000000068
-:040293000000000067
-:040294000000000066
-:040295000000000065
-:040296000000000064
-:040297000000000063
-:040298000000000062
-:040299000000000061
-:04029A000000000060
-:04029B00000000005F
-:04029C00000000005E
-:04029D00000000005D
-:04029E00000000005C
-:04029F00000000005B
-:0402A000000000005A
-:0402A1000000000059
-:0402A2000000000058
-:0402A3000000000057
-:0402A4000000000056
-:0402A5000000000055
-:0402A6000000000054
-:0402A7000000000053
-:0402A8000000000052
-:0402A9000000000051
-:0402AA000000000050
-:0402AB00000000004F
-:0402AC00000000004E
-:0402AD00000000004D
-:0402AE00000000004C
-:0402AF00000000004B
-:0402B000000000004A
-:0402B1000000000049
-:0402B2000000000048
-:0402B3000000000047
-:0402B4000000000046
-:0402B5000000000045
-:0402B6000000000044
-:0402B7000000000043
-:0402B8000000000042
-:0402B9000000000041
-:0402BA000000000040
-:0402BB00000000003F
-:0402BC00000000003E
-:0402BD00000000003D
-:0402BE00000000003C
-:0402BF00000000003B
-:0402C000000000003A
-:0402C1000000000039
-:0402C2000000000038
-:0402C3000000000037
-:0402C4000000000036
-:0402C5000000000035
-:0402C6000000000034
-:0402C7000000000033
-:0402C8000000000032
-:0402C9000000000031
-:0402CA000000000030
-:0402CB00000000002F
-:0402CC00000000002E
-:0402CD00000000002D
-:0402CE00000000002C
-:0402CF00000000002B
-:0402D000000000002A
-:0402D1000000000029
-:0402D2000000000028
-:0402D3000000000027
-:0402D4000000000026
-:0402D5000000000025
-:0402D6000000000024
-:0402D7000000000023
-:0402D8000000000022
-:0402D9000000000021
-:0402DA000000000020
-:0402DB00000000001F
-:0402DC00000000001E
-:0402DD00000000001D
-:0402DE00000000001C
-:0402DF00000000001B
-:0402E000000000001A
-:0402E1000000000019
-:0402E2000000000018
-:0402E3000000000017
-:0402E4000000000016
-:0402E5000000000015
-:0402E6000000000014
-:0402E7000000000013
-:0402E8000000000012
-:0402E9000000000011
-:0402EA000000000010
-:0402EB00000000000F
-:0402EC00000000000E
-:0402ED00000000000D
-:0402EE00000000000C
-:0402EF00000000000B
-:0402F000000000000A
-:0402F1000000000009
-:0402F2000000000008
-:0402F3000000000007
-:0402F4000000000006
-:0402F5000000000005
-:0402F6000000000004
-:0402F7000000000003
-:0402F8000000000002
-:0402F9000000000001
-:0402FA000000000000
-:0402FB0000000000FF
-:0402FC0000000000FE
-:0402FD0000000000FD
-:0402FE0000000000FC
-:0402FF0000000000FB
-:0403000000000000F9
-:0403010000000000F8
-:0403020000000000F7
-:0403030000000000F6
-:0403040000000000F5
-:0403050000000000F4
-:0403060000000000F3
-:0403070000000000F2
-:0403080000000000F1
-:0403090000000000F0
-:04030A0000000000EF
-:04030B0000000000EE
-:04030C0000000000ED
-:04030D0000000000EC
-:04030E0000000000EB
-:04030F0000000000EA
-:0403100000000000E9
-:0403110000000000E8
-:0403120000000000E7
-:0403130000000000E6
-:0403140000000000E5
-:0403150000000000E4
-:0403160000000000E3
-:0403170000000000E2
-:0403180000000000E1
-:0403190000000000E0
-:04031A0000000000DF
-:04031B0000000000DE
-:04031C0000000000DD
-:04031D0000000000DC
-:04031E0000000000DB
-:04031F0000000000DA
-:0403200000000000D9
-:0403210000000000D8
-:0403220000000000D7
-:0403230000000000D6
-:0403240000000000D5
-:0403250000000000D4
-:0403260000000000D3
-:0403270000000000D2
-:0403280000000000D1
-:0403290000000000D0
-:04032A0000000000CF
-:04032B0000000000CE
-:04032C0000000000CD
-:04032D0000000000CC
-:04032E0000000000CB
-:04032F0000000000CA
-:0403300000000000C9
-:0403310000000000C8
-:0403320000000000C7
-:0403330000000000C6
-:0403340000000000C5
-:0403350000000000C4
-:0403360000000000C3
-:0403370000000000C2
-:0403380000000000C1
-:0403390000000000C0
-:04033A0000000000BF
-:04033B0000000000BE
-:04033C0000000000BD
-:04033D0000000000BC
-:04033E0000000000BB
-:04033F0000000000BA
-:0403400000000000B9
-:0403410000000000B8
-:0403420000000000B7
-:0403430000000000B6
-:0403440000000000B5
-:0403450000000000B4
-:0403460000000000B3
-:0403470000000000B2
-:0403480000000000B1
-:0403490000000000B0
-:04034A0000000000AF
-:04034B0000000000AE
-:04034C0000000000AD
-:04034D0000000000AC
-:04034E0000000000AB
-:04034F0000000000AA
-:0403500000000000A9
-:0403510000000000A8
-:0403520000000000A7
-:0403530000000000A6
-:0403540000000000A5
-:0403550000000000A4
-:0403560000000000A3
-:0403570000000000A2
-:0403580000000000A1
-:0403590000000000A0
-:04035A00000000009F
-:04035B00000000009E
-:04035C00000000009D
-:04035D00000000009C
-:04035E00000000009B
-:04035F00000000009A
-:040360000000000099
-:040361000000000098
-:040362000000000097
-:040363000000000096
-:040364000000000095
-:040365000000000094
-:040366000000000093
-:040367000000000092
-:040368000000000091
-:040369000000000090
-:04036A00000000008F
-:04036B00000000008E
-:04036C00000000008D
-:04036D00000000008C
-:04036E00000000008B
-:04036F00000000008A
-:040370000000000089
-:040371000000000088
-:040372000000000087
-:040373000000000086
-:040374000000000085
-:040375000000000084
-:040376000000000083
-:040377000000000082
-:040378000000000081
-:040379000000000080
-:04037A00000000007F
-:04037B00000000007E
-:04037C00000000007D
-:04037D00000000007C
-:04037E00000000007B
-:04037F00000000007A
-:040380000000000079
-:040381000000000078
-:040382000000000077
-:040383000000000076
-:040384000000000075
-:040385000000000074
-:040386000000000073
-:040387000000000072
-:040388000000000071
-:040389000000000070
-:04038A00000000006F
-:04038B00000000006E
-:04038C00000000006D
-:04038D00000000006C
-:04038E00000000006B
-:04038F00000000006A
-:040390000000000069
-:040391000000000068
-:040392000000000067
-:040393000000000066
-:040394000000000065
-:040395000000000064
-:040396000000000063
-:040397000000000062
-:040398000000000061
-:040399000000000060
-:04039A00000000005F
-:04039B00000000005E
-:04039C00000000005D
-:04039D00000000005C
-:04039E00000000005B
-:04039F00000000005A
-:0403A0000000000059
-:0403A1000000000058
-:0403A2000000000057
-:0403A3000000000056
-:0403A4000000000055
-:0403A5000000000054
-:0403A6000000000053
-:0403A7000000000052
-:0403A8000000000051
-:0403A9000000000050
-:0403AA00000000004F
-:0403AB00000000004E
-:0403AC00000000004D
-:0403AD00000000004C
-:0403AE00000000004B
-:0403AF00000000004A
-:0403B0000000000049
-:0403B1000000000048
-:0403B2000000000047
-:0403B3000000000046
-:0403B4000000000045
-:0403B5000000000044
-:0403B6000000000043
-:0403B7000000000042
-:0403B8000000000041
-:0403B9000000000040
-:0403BA00000000003F
-:0403BB00000000003E
-:0403BC00000000003D
-:0403BD00000000003C
-:0403BE00000000003B
-:0403BF00000000003A
-:0403C0000000000039
-:0403C1000000000038
-:0403C2000000000037
-:0403C3000000000036
-:0403C4000000000035
-:0403C5000000000034
-:0403C6000000000033
-:0403C7000000000032
-:0403C8000000000031
-:0403C9000000000030
-:0403CA00000000002F
-:0403CB00000000002E
-:0403CC00000000002D
-:0403CD00000000002C
-:0403CE00000000002B
-:0403CF00000000002A
-:0403D0000000000029
-:0403D1000000000028
-:0403D2000000000027
-:0403D3000000000026
-:0403D4000000000025
-:0403D5000000000024
-:0403D6000000000023
-:0403D7000000000022
-:0403D8000000000021
-:0403D9000000000020
-:0403DA00000000001F
-:0403DB00000000001E
-:0403DC00000000001D
-:0403DD00000000001C
-:0403DE00000000001B
-:0403DF00000000001A
-:0403E0000000000019
-:0403E1000000000018
-:0403E2000000000017
-:0403E3000000000016
-:0403E4000000000015
-:0403E5000000000014
-:0403E6000000000013
-:0403E7000000000012
-:0403E8000000000011
-:0403E9000000000010
-:0403EA00000000000F
-:0403EB00000000000E
-:0403EC00000000000D
-:0403ED00000000000C
-:0403EE00000000000B
-:0403EF00000000000A
-:0403F0000000000009
-:0403F1000000000008
-:0403F2000000000007
-:0403F3000000000006
-:0403F4000000000005
-:0403F5000000000004
-:0403F6000000000003
-:0403F7000000000002
-:0403F8000000000001
-:0403F9000000000000
-:0403FA0000000000FF
-:0403FB0000000000FE
-:0403FC0000000000FD
-:0403FD0000000000FC
-:0403FE0000000000FB
-:0403FF0000000000FA
-:00000001ff
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.bsf
deleted file mode 100644
index dfb329698d7b0cc5ce8574ad9f2bd62da3fa868f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.bsf
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 280 296)
- (text "qsys_arts_unb2b_sc3_onchip_memory2_0" (rect 13 -1 191 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 280 20 292)(font "Arial" ))
- (port
- (pt 0 72)
- (input)
- (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8)))
- (text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 96 72)(line_width 1))
- )
- (port
- (pt 0 112)
- (input)
- (text "reset" (rect 0 0 20 12)(font "Arial" (font_size 8)))
- (text "reset" (rect 4 101 34 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 96 112)(line_width 1))
- )
- (port
- (pt 0 128)
- (input)
- (text "reset_req" (rect 0 0 38 12)(font "Arial" (font_size 8)))
- (text "reset_req" (rect 4 117 58 128)(font "Arial" (font_size 8)))
- (line (pt 0 128)(pt 96 128)(line_width 1))
- )
- (port
- (pt 0 168)
- (input)
- (text "address[9..0]" (rect 0 0 51 12)(font "Arial" (font_size 8)))
- (text "address[9..0]" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 96 168)(line_width 3))
- )
- (port
- (pt 0 184)
- (input)
- (text "clken" (rect 0 0 20 12)(font "Arial" (font_size 8)))
- (text "clken" (rect 4 173 34 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 96 184)(line_width 1))
- )
- (port
- (pt 0 200)
- (input)
- (text "chipselect" (rect 0 0 37 12)(font "Arial" (font_size 8)))
- (text "chipselect" (rect 4 189 64 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 96 200)(line_width 1))
- )
- (port
- (pt 0 216)
- (input)
- (text "write" (rect 0 0 17 12)(font "Arial" (font_size 8)))
- (text "write" (rect 4 205 34 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 96 216)(line_width 1))
- )
- (port
- (pt 0 248)
- (input)
- (text "writedata[31..0]" (rect 0 0 57 12)(font "Arial" (font_size 8)))
- (text "writedata[31..0]" (rect 4 237 100 248)(font "Arial" (font_size 8)))
- (line (pt 0 248)(pt 96 248)(line_width 3))
- )
- (port
- (pt 0 264)
- (input)
- (text "byteenable[3..0]" (rect 0 0 62 12)(font "Arial" (font_size 8)))
- (text "byteenable[3..0]" (rect 4 253 100 264)(font "Arial" (font_size 8)))
- (line (pt 0 264)(pt 96 264)(line_width 3))
- )
- (port
- (pt 0 232)
- (output)
- (text "readdata[31..0]" (rect 0 0 57 12)(font "Arial" (font_size 8)))
- (text "readdata[31..0]" (rect 4 221 94 232)(font "Arial" (font_size 8)))
- (line (pt 0 232)(pt 96 232)(line_width 3))
- )
- (drawing
- (text "clk1" (rect 76 43 176 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 101 67 220 144)(font "Arial" (color 0 0 0)))
- (text "reset1" (rect 62 83 160 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 101 107 232 224)(font "Arial" (color 0 0 0)))
- (text "reset_req" (rect 101 123 256 256)(font "Arial" (color 0 0 0)))
- (text "s1" (rect 85 139 182 291)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 101 163 244 336)(font "Arial" (color 0 0 0)))
- (text "clken" (rect 101 179 232 368)(font "Arial" (color 0 0 0)))
- (text "chipselect" (rect 101 195 262 400)(font "Arial" (color 0 0 0)))
- (text "write" (rect 101 211 232 432)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 101 227 250 464)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 101 243 256 496)(font "Arial" (color 0 0 0)))
- (text "byteenable" (rect 101 259 262 528)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_onchip_memory2_0 " (rect 66 280 360 570)(font "Arial" ))
- (line (pt 96 32)(pt 160 32)(line_width 1))
- (line (pt 160 32)(pt 160 280)(line_width 1))
- (line (pt 96 280)(pt 160 280)(line_width 1))
- (line (pt 96 32)(pt 96 280)(line_width 1))
- (line (pt 97 52)(pt 97 76)(line_width 1))
- (line (pt 98 52)(pt 98 76)(line_width 1))
- (line (pt 97 92)(pt 97 132)(line_width 1))
- (line (pt 98 92)(pt 98 132)(line_width 1))
- (line (pt 97 148)(pt 97 268)(line_width 1))
- (line (pt 98 148)(pt 98 268)(line_width 1))
- (line (pt 0 0)(pt 280 0)(line_width 1))
- (line (pt 280 0)(pt 280 296)(line_width 1))
- (line (pt 0 296)(pt 280 296)(line_width 1))
- (line (pt 0 0)(pt 0 296)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.cmp
deleted file mode 100644
index 0f1ac06507b799dcd1c945bbbd6da92c0281c633..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.cmp
+++ /dev/null
@@ -1,15 +0,0 @@
- component qsys_arts_unb2b_sc3_onchip_memory2_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
- );
- end component qsys_arts_unb2b_sc3_onchip_memory2_0;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.html
deleted file mode 100644
index e218ab3e950844636031e531f99420412e7541b7..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.html
+++ /dev/null
@@ -1,344 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_onchip_memory2_0</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_onchip_memory2_0</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:38:47</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_onchip_memory2_0"><b>qsys_arts_unb2b_sc3_onchip_memory2_0</b>
- </a> altera_avalon_onchip_memory2 17.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_onchip_memory2_0"><b>qsys_arts_unb2b_sc3_onchip_memory2_0</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">s1 </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_onchip_memory2_0"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_onchip_memory2_0</h2>altera_avalon_onchip_memory2 v17.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">allowInSystemMemoryContentEditor</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">blockType</td>
- <td class="parametervalue">AUTO</td>
- </tr>
- <tr>
- <td class="parametername">dataWidth</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">dataWidth2</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">dualPort</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">enableDiffWidth</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">derived_enableDiffWidth</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">initMemContent</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">initializationFileName</td>
- <td class="parametervalue">onchip_mem.hex</td>
- </tr>
- <tr>
- <td class="parametername">enPRInitMode</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">instanceID</td>
- <td class="parametervalue">NONE</td>
- </tr>
- <tr>
- <td class="parametername">memorySize</td>
- <td class="parametervalue">4096</td>
- </tr>
- <tr>
- <td class="parametername">readDuringWriteMode</td>
- <td class="parametervalue">DONT_CARE</td>
- </tr>
- <tr>
- <td class="parametername">simAllowMRAMContentsFile</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">simMemInitOnlyFilename</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">singleClockOperation</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">derived_singleClockOperation</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">slave1Latency</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">slave2Latency</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">useNonDefaultInitFile</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">copyInitFile</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">useShallowMemBlocks</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">writable</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">ecc_enabled</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">resetrequest_enabled</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">autoInitializationFileName</td>
- <td class="parametervalue">qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">ARRIA10</td>
- </tr>
- <tr>
- <td class="parametername">deviceFeatures</td>
- <td class="parametervalue">ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</td>
- </tr>
- <tr>
- <td class="parametername">derived_set_addr_width</td>
- <td class="parametervalue">10</td>
- </tr>
- <tr>
- <td class="parametername">derived_set_addr_width2</td>
- <td class="parametervalue">10</td>
- </tr>
- <tr>
- <td class="parametername">derived_set_data_width</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">derived_set_data_width2</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">derived_gui_ram_block_type</td>
- <td class="parametervalue">Automatic</td>
- </tr>
- <tr>
- <td class="parametername">derived_is_hardcopy</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">derived_init_file_name</td>
- <td class="parametervalue">qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>
- <table>
- <tr>
- <td class="parametername">ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">CONTENTS_INFO</td>
- <td class="parametervalue">""</td>
- </tr>
- <tr>
- <td class="parametername">DUAL_PORT</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">GUI_RAM_BLOCK_TYPE</td>
- <td class="parametervalue">AUTO</td>
- </tr>
- <tr>
- <td class="parametername">INIT_CONTENTS_FILE</td>
- <td class="parametervalue">qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0</td>
- </tr>
- <tr>
- <td class="parametername">INIT_MEM_CONTENT</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">INSTANCE_ID</td>
- <td class="parametervalue">NONE</td>
- </tr>
- <tr>
- <td class="parametername">NON_DEFAULT_INIT_FILE_ENABLED</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">RAM_BLOCK_TYPE</td>
- <td class="parametervalue">AUTO</td>
- </tr>
- <tr>
- <td class="parametername">READ_DURING_WRITE_MODE</td>
- <td class="parametervalue">DONT_CARE</td>
- </tr>
- <tr>
- <td class="parametername">SINGLE_CLOCK_OP</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">SIZE_MULTIPLE</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">SIZE_VALUE</td>
- <td class="parametervalue">4096</td>
- </tr>
- <tr>
- <td class="parametername">WRITABLE</td>
- <td class="parametervalue">1</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 2.25 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.qgsynthc
deleted file mode 100644
index 7d9f8cb81ec503caca1471ab65afe1a4ddc8272e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.qgsynthc
+++ /dev/null
@@ -1,181 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_onchip_memory2_0</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_onchip_memory2_0</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_onchip_memory2_0</name>
- <uniqueName>qsys_arts_unb2b_sc3_onchip_memory2_0</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_onchip_memory2_0</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>allowInSystemMemoryContentEditor</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>autoInitializationFileName</name>
- <value>qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0</value>
- </parameter>
- <parameter>
- <name>blockType</name>
- <value>AUTO</value>
- </parameter>
- <parameter>
- <name>copyInitFile</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>dataWidth</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>dataWidth2</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>derived_enableDiffWidth</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>derived_gui_ram_block_type</name>
- <value>Automatic</value>
- </parameter>
- <parameter>
- <name>derived_init_file_name</name>
- <value>qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex</value>
- </parameter>
- <parameter>
- <name>derived_is_hardcopy</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>derived_set_addr_width</name>
- <value>10</value>
- </parameter>
- <parameter>
- <name>derived_set_addr_width2</name>
- <value>10</value>
- </parameter>
- <parameter>
- <name>derived_set_data_width</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>derived_set_data_width2</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>derived_singleClockOperation</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>deviceFamily</name>
- <value>Arria 10</value>
- </parameter>
- <parameter>
- <name>deviceFeatures</name>
- <value>ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</value>
- </parameter>
- <parameter>
- <name>dualPort</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>ecc_enabled</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>enPRInitMode</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>enableDiffWidth</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>initMemContent</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>initializationFileName</name>
- <value>onchip_mem.hex</value>
- </parameter>
- <parameter>
- <name>instanceID</name>
- <value>NONE</value>
- </parameter>
- <parameter>
- <name>memorySize</name>
- <value>4096</value>
- </parameter>
- <parameter>
- <name>readDuringWriteMode</name>
- <value>DONT_CARE</value>
- </parameter>
- <parameter>
- <name>resetrequest_enabled</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>simAllowMRAMContentsFile</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>simMemInitOnlyFilename</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>singleClockOperation</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>slave1Latency</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>slave2Latency</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>useNonDefaultInitFile</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>useShallowMemBlocks</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>writable</name>
- <value>true</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>altera_avalon_onchip_memory2</className>
- <version>17.0</version>
- <name>qsys_arts_unb2b_sc3_onchip_memory2_0</name>
- <uniqueName>qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_onchip_memory2_0.qsys_arts_unb2b_sc3_onchip_memory2_0</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.qip
deleted file mode 100644
index e8631f69d2a86041d78cc82670119bfc864a41a5..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.qip
+++ /dev/null
@@ -1,67 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_onchip_memory2_0.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_onchip_memory2_0 HAS_SOPCINFO 1 GENERATION_ID 1527683927"
-set_global_assignment -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_onchip_memory2_0.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_onchip_memory2_0.ip"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19vbmNoaXBfbWVtb3J5Ml8wX2FsdGVyYV9hdmFsb25fb25jaGlwX21lbW9yeTJfMTcwX2h0cWNqaHE="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_DISPLAY_NAME "T24tQ2hpcCBNZW1vcnkgKFJBTSBvciBST00p"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_VERSION "MTcuMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "YWxsb3dJblN5c3RlbU1lbW9yeUNvbnRlbnRFZGl0b3I=::ZmFsc2U=::RW5hYmxlIEluLVN5c3RlbSBNZW1vcnkgQ29udGVudCBFZGl0b3IgZmVhdHVyZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "YmxvY2tUeXBl::QVVUTw==::QmxvY2sgdHlwZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGF0YVdpZHRo::MzI=::U2xhdmUgUzEgRGF0YSB3aWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGF0YVdpZHRoMg==::MzI=::U2xhdmUgUzIgRGF0YSB3aWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZHVhbFBvcnQ=::ZmFsc2U=::RHVhbC1wb3J0IGFjY2Vzcw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9lbmFibGVEaWZmV2lkdGg=::ZmFsc2U=::ZGVyaXZlZF9lbmFibGVEaWZmV2lkdGg="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "aW5pdE1lbUNvbnRlbnQ=::dHJ1ZQ==::SW5pdGlhbGl6ZSBtZW1vcnkgY29udGVudA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZW5QUkluaXRNb2Rl::ZmFsc2U=::RW5hYmxlIFBhcnRpYWwgUmVjb25maWd1cmF0aW9uIEluaXRpYWxpemF0aW9uIE1vZGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "bWVtb3J5U2l6ZQ==::NDA5Ng==::VG90YWwgbWVtb3J5IHNpemU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "c2ltQWxsb3dNUkFNQ29udGVudHNGaWxl::ZmFsc2U=::QWxsb3cgTVJBTSBjb250ZW50cyBmaWxlIGZvciBzaW11bGF0aW9u"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "c2ltTWVtSW5pdE9ubHlGaWxlbmFtZQ==::MA==::U2ltdWxhdGlvbiBtZW1pbml0IG9ubHkgaGFzIGZpbGVuYW1l"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zaW5nbGVDbG9ja09wZXJhdGlvbg==::ZmFsc2U=::ZGVyaXZlZF9zaW5nbGVDbG9ja09wZXJhdGlvbg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "c2xhdmUxTGF0ZW5jeQ==::MQ==::U2xhdmUgczEgTGF0ZW5jeQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "dXNlTm9uRGVmYXVsdEluaXRGaWxl::ZmFsc2U=::RW5hYmxlIG5vbi1kZWZhdWx0IGluaXRpYWxpemF0aW9uIGZpbGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "d3JpdGFibGU=::dHJ1ZQ==::VHlwZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZWNjX2VuYWJsZWQ=::ZmFsc2U=::RXh0ZW5kIHRoZSBkYXRhIHdpZHRoIHRvIHN1cHBvcnQgRUNDIGJpdHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "cmVzZXRyZXF1ZXN0X2VuYWJsZWQ=::dHJ1ZQ==::UmVzZXQgUmVxdWVzdA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU=::cXN5c19hcnRzX3VuYjJiX3NjM19vbmNoaXBfbWVtb3J5Ml8wX3FzeXNfYXJ0c191bmIyYl9zYzNfb25jaGlwX21lbW9yeTJfMA==::YXV0b0luaXRpYWxpemF0aW9uRmlsZU5hbWU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmFtaWx5::QXJyaWEgMTA=::ZGV2aWNlRmFtaWx5"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGV2aWNlRmVhdHVyZXM=::ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0::ZGV2aWNlRmVhdHVyZXM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfYWRkcl93aWR0aA==::MTA=::U2xhdmUgMSBhZGRyZXNzIHdpZHRo"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfYWRkcl93aWR0aDI=::MTA=::U2xhdmUgMiBhZGRyZXNzIHdpZHRo"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfZGF0YV93aWR0aA==::MzI=::U2xhdmUgMSBkYXRhIHdpZHRo"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9zZXRfZGF0YV93aWR0aDI=::MzI=::U2xhdmUgMiBkYXRhIHdpZHRo"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9ndWlfcmFtX2Jsb2NrX3R5cGU=::QXV0b21hdGlj::ZGVyaXZlZF9ndWlfcmFtX2Jsb2NrX3R5cGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pc19oYXJkY29weQ==::ZmFsc2U=::ZGVyaXZlZF9pc19oYXJkY29weQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pbml0X2ZpbGVfbmFtZQ==::cXN5c19hcnRzX3VuYjJiX3NjM19vbmNoaXBfbWVtb3J5Ml8wX3FzeXNfYXJ0c191bmIyYl9zYzNfb25jaGlwX21lbW9yeTJfMC5oZXg=::ZGVyaXZlZF9pbml0X2ZpbGVfbmFtZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_GROUP "QmFzaWMgRnVuY3Rpb25zL09uIENoaXAgTWVtb3J5"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly93d3cuYWx0ZXJhLmNvbS9jb250ZW50L2RhbS9hbHRlcmEtd3d3L2dsb2JhbC9lbl9VUy9wZGZzL2xpdGVyYXR1cmUvdWcvdWdfc29wY19idWlsZGVyLnBkZg=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MTY4MzYxNDU1NTUvaGNvMTQxNjgzNjY1MzIyMQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19vbmNoaXBfbWVtb3J5Ml8w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4MzkyNw==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEsxX0NMT0NLX1JBVEU=::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEsxX0NMT0NLX0RPTUFJTg==::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0" -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEsxX1JFU0VUX0RPTUFJTg==::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "altera_avalon_onchip_memory2_170" -name SOURCE_FILE [file join $::quartus(qip_path) "altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex"]
-set_global_assignment -library "altera_avalon_onchip_memory2_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq.v"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_onchip_memory2_0" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_onchip_memory2_0.vhd"]
-
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_TOOL_NAME "altera_avalon_onchip_memory2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_TOOL_VERSION "17.0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq" -library "altera_avalon_onchip_memory2_170" -name IP_TOOL_ENV "QsysPrimePro"
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.sopcinfo
deleted file mode 100644
index 81d4ee1e5d003a0e88b533d5c7a92f7245d48e5a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.sopcinfo
+++ /dev/null
@@ -1,1036 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_onchip_memory2_0"
- kind="qsys_arts_unb2b_sc3_onchip_memory2_0"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:38:47 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527683927</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_CLK1_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk1</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK1_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk1</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK1_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk1</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_onchip_memory2_0"
- kind="altera_avalon_onchip_memory2"
- version="17.0"
- path="qsys_arts_unb2b_sc3_onchip_memory2_0">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <assignment>
- <name>embeddedsw.CMacro.ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.CONTENTS_INFO</name>
- <value>""</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.DUAL_PORT</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.GUI_RAM_BLOCK_TYPE</name>
- <value>AUTO</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.INIT_CONTENTS_FILE</name>
- <value>qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.INIT_MEM_CONTENT</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.INSTANCE_ID</name>
- <value>NONE</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.NON_DEFAULT_INIT_FILE_ENABLED</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.RAM_BLOCK_TYPE</name>
- <value>AUTO</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.READ_DURING_WRITE_MODE</name>
- <value>DONT_CARE</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.SINGLE_CLOCK_OP</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.SIZE_MULTIPLE</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.SIZE_VALUE</name>
- <value>4096</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.WRITABLE</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR</name>
- <value>SIM_DIR</value>
- </assignment>
- <assignment>
- <name>embeddedsw.memoryInfo.GENERATE_DAT_SYM</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.memoryInfo.GENERATE_HEX</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.memoryInfo.HAS_BYTE_LANE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.memoryInfo.HEX_INSTALL_DIR</name>
- <value>QPF_DIR</value>
- </assignment>
- <assignment>
- <name>embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH</name>
- <value>32</value>
- </assignment>
- <assignment>
- <name>embeddedsw.memoryInfo.MEM_INIT_FILENAME</name>
- <value>qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0</value>
- </assignment>
- <assignment>
- <name>postgeneration.simulation.init_file.param_name</name>
- <value>INIT_FILE</value>
- </assignment>
- <assignment>
- <name>postgeneration.simulation.init_file.type</name>
- <value>MEM_INIT</value>
- </assignment>
- <parameter name="allowInSystemMemoryContentEditor">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="blockType">
- <type>java.lang.String</type>
- <value>AUTO</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dataWidth">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dataWidth2">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="dualPort">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="enableDiffWidth">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_enableDiffWidth">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="initMemContent">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="initializationFileName">
- <type>java.lang.String</type>
- <value>onchip_mem.hex</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="enPRInitMode">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="instanceID">
- <type>java.lang.String</type>
- <value>NONE</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="memorySize">
- <type>long</type>
- <value>4096</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readDuringWriteMode">
- <type>java.lang.String</type>
- <value>DONT_CARE</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="simAllowMRAMContentsFile">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="simMemInitOnlyFilename">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="singleClockOperation">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_singleClockOperation">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="slave1Latency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="slave2Latency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="useNonDefaultInitFile">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="copyInitFile">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="useShallowMemBlocks">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writable">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ecc_enabled">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="resetrequest_enabled">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="autoInitializationFileName">
- <type>java.lang.String</type>
- <value>qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="deviceFeatures">
- <type>java.lang.String</type>
- <value>ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FEATURES</sysinfo_type>
- </parameter>
- <parameter name="derived_set_addr_width">
- <type>int</type>
- <value>10</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_set_addr_width2">
- <type>int</type>
- <value>10</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_set_data_width">
- <type>int</type>
- <value>32</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_set_data_width2">
- <type>int</type>
- <value>32</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_gui_ram_block_type">
- <type>java.lang.String</type>
- <value>Automatic</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_is_hardcopy">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_init_file_name">
- <type>java.lang.String</type>
- <value>qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="clk1" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="s1" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isFlash</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>0</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>4096</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>4096</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>address</name>
- <direction>Input</direction>
- <width>10</width>
- <role>address</role>
- </port>
- <port>
- <name>clken</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clken</role>
- </port>
- <port>
- <name>chipselect</name>
- <direction>Input</direction>
- <width>1</width>
- <role>chipselect</role>
- </port>
- <port>
- <name>write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- <port>
- <name>writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>byteenable</name>
- <direction>Input</direction>
- <width>4</width>
- <role>byteenable</role>
- </port>
- </interface>
- <interface name="reset1" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- <port>
- <name>reset_req</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset_req</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>altera_avalon_onchip_memory2</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>On-Chip Memory (RAM or ROM)</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.xml
deleted file mode 100644
index 19f03ed87a3339d824fcd2013c8fde9184d1c6cf..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0.xml
+++ /dev/null
@@ -1,231 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:38:50"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK1_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK1_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK1_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="clk1" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="reset1" kind="reset" start="0">
- <property name="associatedClock" value="clk1" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="reset" direction="input" role="reset" width="1" />
- <port name="reset_req" direction="input" role="reset_req" width="1" />
- </interface>
- <interface name="s1" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="4096" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="clk1" />
- <property name="associatedReset" value="reset1" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="4096" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="true" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="address" direction="input" role="address" width="10" />
- <port name="clken" direction="input" role="clken" width="1" />
- <port name="chipselect" direction="input" role="chipselect" width="1" />
- <port name="write" direction="input" role="write" width="1" />
- <port name="readdata" direction="output" role="readdata" width="32" />
- <port name="writedata" direction="input" role="writedata" width="32" />
- <port name="byteenable" direction="input" role="byteenable" width="4" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_onchip_memory2_0"
- version="1.0"
- name="qsys_arts_unb2b_sc3_onchip_memory2_0">
- <parameter name="AUTO_GENERATION_ID" value="1527683927" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_CLK1_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_CLK1_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <parameter name="AUTO_CLK1_CLOCK_RATE" value="-1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/synth/qsys_arts_unb2b_sc3_onchip_memory2_0.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/synth/qsys_arts_unb2b_sc3_onchip_memory2_0.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_onchip_memory2_0">"Generating: qsys_arts_unb2b_sc3_onchip_memory2_0"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_onchip_memory2_0">"Generating: qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_onchip_memory2_0">Starting RTL generation for module 'qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq'</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_onchip_memory2_0"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq --dir=/tmp/alt7681_6931282645914172388.dir/0007_qsys_arts_unb2b_sc3_onchip_memory2_0_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0007_qsys_arts_unb2b_sc3_onchip_memory2_0_gen//qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq_component_configuration.pl --do_build_sim=0 ]</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_onchip_memory2_0">Done RTL generation for module 'qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq'</message>
- </messages>
- </entity>
- <entity
- kind="altera_avalon_onchip_memory2"
- version="17.0"
- name="qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq">
- <parameter name="derived_singleClockOperation" value="false" />
- <parameter name="derived_is_hardcopy" value="false" />
- <parameter
- name="deviceFeatures"
- value="ADDRESS_STALL 0 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 0 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PHYSICAL_DESIGN_PLANNER 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 0 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 1 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 1 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 1 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BCM_PIN_BASED_AIOT_SUPPORT 0 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 1 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 0 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 0 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 1 HAS_DDB_FDI_SUPPORT 1 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 0 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 1 HAS_ERROR_DETECTION_SUPPORT 1 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 0 HAS_FITTER_ECO_SUPPORT 0 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 1 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 1 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIER_PARTIAL_RECONFIG_SUPPORT 1 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 0 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 1 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 0 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 0 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 1 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 1 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 1 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 1 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 1 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 1 HAS_RAPID_RECOMPILE_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 0 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPEED_GRADE_OFFSET 1 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 0 HAS_SYNTHESIS_ON_ATOMS 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 1 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 1 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 1 HAS_USE_FITTER_INFO_SUPPORT 0 HAS_VCCPD_POWER_RAIL 1 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_REVE_SILICON 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 1 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 1 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 0 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 0 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 1 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 0 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 0 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 0 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 1 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 1 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 1 USES_SECOND_GENERATION_PART_INFO 1 USES_SECOND_GENERATION_POWER_ANALYZER 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 1 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 1 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 1 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0" />
- <parameter
- name="autoInitializationFileName"
- value="qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0" />
- <parameter name="derived_gui_ram_block_type" value="Automatic" />
- <parameter name="enPRInitMode" value="false" />
- <parameter name="useShallowMemBlocks" value="false" />
- <parameter name="writable" value="true" />
- <parameter name="dualPort" value="false" />
- <parameter name="derived_set_addr_width2" value="10" />
- <parameter name="dataWidth" value="32" />
- <parameter name="allowInSystemMemoryContentEditor" value="false" />
- <parameter name="derived_set_addr_width" value="10" />
- <parameter
- name="derived_init_file_name"
- value="qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex" />
- <parameter name="initializationFileName" value="onchip_mem.hex" />
- <parameter name="singleClockOperation" value="false" />
- <parameter name="derived_set_data_width2" value="32" />
- <parameter name="readDuringWriteMode" value="DONT_CARE" />
- <parameter name="blockType" value="AUTO" />
- <parameter name="derived_enableDiffWidth" value="false" />
- <parameter name="useNonDefaultInitFile" value="false" />
- <parameter name="resetrequest_enabled" value="true" />
- <parameter name="simMemInitOnlyFilename" value="0" />
- <parameter name="copyInitFile" value="false" />
- <parameter name="deviceFamily" value="Arria 10" />
- <parameter name="simAllowMRAMContentsFile" value="false" />
- <parameter name="ecc_enabled" value="false" />
- <parameter name="derived_set_data_width" value="32" />
- <parameter name="instanceID" value="NONE" />
- <parameter name="memorySize" value="4096" />
- <parameter name="dataWidth2" value="32" />
- <parameter name="enableDiffWidth" value="false" />
- <parameter name="initMemContent" value="true" />
- <parameter name="slave1Latency" value="1" />
- <parameter name="slave2Latency" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq.v"
- attributes="" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_qsys_arts_unb2b_sc3_onchip_memory2_0.hex"
- attributes="" />
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/altera_avalon_onchip_memory2_170/synth/qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq.v"
- attributes="" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/altera_avalon_onchip_memory2_hw.tcl" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_onchip_memory2_0"
- as="qsys_arts_unb2b_sc3_onchip_memory2_0" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_onchip_memory2_0">"Generating: qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_onchip_memory2_0">Starting RTL generation for module 'qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq'</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_onchip_memory2_0"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq --dir=/tmp/alt7681_6931282645914172388.dir/0007_qsys_arts_unb2b_sc3_onchip_memory2_0_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0007_qsys_arts_unb2b_sc3_onchip_memory2_0_gen//qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq_component_configuration.pl --do_build_sim=0 ]</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_onchip_memory2_0">Done RTL generation for module 'qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq'</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_bb.v
deleted file mode 100644
index 30072c7d86b1392f8f2218eece65c822cacb4105..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_bb.v
+++ /dev/null
@@ -1,24 +0,0 @@
-
-module qsys_arts_unb2b_sc3_onchip_memory2_0 (
- clk,
- reset,
- reset_req,
- address,
- clken,
- chipselect,
- write,
- readdata,
- writedata,
- byteenable);
-
- input clk;
- input reset;
- input reset_req;
- input [9:0] address;
- input clken;
- input chipselect;
- input write;
- output [31:0] readdata;
- input [31:0] writedata;
- input [3:0] byteenable;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_generation.rpt
deleted file mode 100644
index 1f9670f2526cae679e209d9b452d5b3a3f5da4e1..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_generation.rpt
+++ /dev/null
@@ -1,28 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: "Transforming system: qsys_arts_unb2b_sc3_onchip_memory2_0"
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: "Naming system components in system: qsys_arts_unb2b_sc3_onchip_memory2_0"
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: "Generating: qsys_arts_unb2b_sc3_onchip_memory2_0"
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: "Generating: qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq"
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Starting RTL generation for module 'qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq'
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq --dir=/tmp/alt7681_6931282645914172388.dir/0007_qsys_arts_unb2b_sc3_onchip_memory2_0_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0007_qsys_arts_unb2b_sc3_onchip_memory2_0_gen//qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq_component_configuration.pl --do_build_sim=0 ]
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Done RTL generation for module 'qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq'
-Info: qsys_arts_unb2b_sc3_onchip_memory2_0: Done "qsys_arts_unb2b_sc3_onchip_memory2_0" with 2 modules, 3 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_onchip_memory2_0. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_inst.v
deleted file mode 100644
index 3a3a6c45d4e73c1592d78939f816e4aa8ca8a0db..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_inst.v
+++ /dev/null
@@ -1,13 +0,0 @@
- qsys_arts_unb2b_sc3_onchip_memory2_0 u0 (
- .clk (_connected_to_clk_), // clk1.clk
- .reset (_connected_to_reset_), // reset1.reset
- .reset_req (_connected_to_reset_req_), // .reset_req
- .address (_connected_to_address_), // s1.address
- .clken (_connected_to_clken_), // .clken
- .chipselect (_connected_to_chipselect_), // .chipselect
- .write (_connected_to_write_), // .write
- .readdata (_connected_to_readdata_), // .readdata
- .writedata (_connected_to_writedata_), // .writedata
- .byteenable (_connected_to_byteenable_) // .byteenable
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_inst.vhd
deleted file mode 100644
index 07fd84fba748a5b4b9acbc3e0dc8993ef6e2d3d9..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/qsys_arts_unb2b_sc3_onchip_memory2_0_inst.vhd
+++ /dev/null
@@ -1,29 +0,0 @@
- component qsys_arts_unb2b_sc3_onchip_memory2_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
- );
- end component qsys_arts_unb2b_sc3_onchip_memory2_0;
-
- u0 : component qsys_arts_unb2b_sc3_onchip_memory2_0
- port map (
- clk => CONNECTED_TO_clk, -- clk1.clk
- reset => CONNECTED_TO_reset, -- reset1.reset
- reset_req => CONNECTED_TO_reset_req, -- .reset_req
- address => CONNECTED_TO_address, -- s1.address
- clken => CONNECTED_TO_clken, -- .clken
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write => CONNECTED_TO_write, -- .write
- readdata => CONNECTED_TO_readdata, -- .readdata
- writedata => CONNECTED_TO_writedata, -- .writedata
- byteenable => CONNECTED_TO_byteenable -- .byteenable
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/synth/qsys_arts_unb2b_sc3_onchip_memory2_0.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/synth/qsys_arts_unb2b_sc3_onchip_memory2_0.vhd
deleted file mode 100644
index 338ad857ed59ff2599b9aeebb2fd89ed754a743e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0/synth/qsys_arts_unb2b_sc3_onchip_memory2_0.vhd
+++ /dev/null
@@ -1,61 +0,0 @@
--- qsys_arts_unb2b_sc3_onchip_memory2_0.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library altera_avalon_onchip_memory2_170;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_onchip_memory2_0 is
- port (
- clk : in std_logic := '0'; -- clk1.clk
- reset : in std_logic := '0'; -- reset1.reset
- reset_req : in std_logic := '0'; -- .reset_req
- address : in std_logic_vector(9 downto 0) := (others => '0'); -- s1.address
- clken : in std_logic := '0'; -- .clken
- chipselect : in std_logic := '0'; -- .chipselect
- write : in std_logic := '0'; -- .write
- readdata : out std_logic_vector(31 downto 0); -- .readdata
- writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => '0') -- .byteenable
- );
-end entity qsys_arts_unb2b_sc3_onchip_memory2_0;
-
-architecture rtl of qsys_arts_unb2b_sc3_onchip_memory2_0 is
- component qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq_cmp is
- port (
- clk : in std_logic := 'X'; -- clk
- address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- freeze : in std_logic := 'X' -- freeze
- );
- end component qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq_cmp;
-
- for qsys_arts_unb2b_sc3_onchip_memory2_0 : qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq_cmp
- use entity altera_avalon_onchip_memory2_170.qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq;
-begin
-
- qsys_arts_unb2b_sc3_onchip_memory2_0 : component qsys_arts_unb2b_sc3_onchip_memory2_0_altera_avalon_onchip_memory2_170_htqcjhq_cmp
- port map (
- clk => clk, -- clk1.clk
- address => address, -- s1.address
- clken => clken, -- .clken
- chipselect => chipselect, -- .chipselect
- write => write, -- .write
- readdata => readdata, -- .readdata
- writedata => writedata, -- .writedata
- byteenable => byteenable, -- .byteenable
- reset => reset, -- reset1.reset
- reset_req => reset_req, -- .reset_req
- freeze => '0' -- (terminated)
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_onchip_memory2_0
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps.ip
index 477e28dc01cf651996fe3ba76babd0fa5b208ce7..9a8aff203736ddbdbdf75b7a12c7564e24c06251 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,10 +605,6 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -701,10 +697,6 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -783,7 +775,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +833,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +897,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +966,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1361,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.bsf
deleted file mode 100644
index 5d344a3c2ddee1f8af496fe120f13ed1243f00cf..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_pio_pps" (rect 84 -1 211 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_pio_pps " (rect 214 512 602 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.cmp
deleted file mode 100644
index d8d1bc6cc1e521d3a3ca93693c59f857995f3cc9..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_pio_pps is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_pio_pps;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.html
deleted file mode 100644
index 03bbe73f814c277380d26817ef87678cb1c03261..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_pio_pps</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_pio_pps</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:39:06</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_pio_pps"><b>qsys_arts_unb2b_sc3_pio_pps</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_pio_pps"><b>qsys_arts_unb2b_sc3_pio_pps</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_pio_pps"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_pio_pps</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.qgsynthc
deleted file mode 100644
index fcdb7d00786dd5f10c927eef3070e64cb96ee3c3..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_pio_pps</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_pio_pps</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_pio_pps</name>
- <uniqueName>qsys_arts_unb2b_sc3_pio_pps</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_pio_pps</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_pio_pps</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_pio_pps.qsys_arts_unb2b_sc3_pio_pps</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.qip
deleted file mode 100644
index 3eb3d7179217336f78dd55bd6f0d9f57dc4576b9..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_pps" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_pio_pps.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_pio_pps HAS_SOPCINFO 1 GENERATION_ID 1527683946"
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_pps" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_pio_pps.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_pps" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_pio_pps.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19waW9fcHBz"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4Mzk0Ng==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_pps" -library "qsys_arts_unb2b_sc3_pio_pps" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_pps" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_pio_pps.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.sopcinfo
deleted file mode 100644
index 376dcd37661c9c2990173c9bd3c03e53dbe3ba5d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_pio_pps"
- kind="qsys_arts_unb2b_sc3_pio_pps"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:39:06 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527683946</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_pio_pps"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_pio_pps">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.xml
deleted file mode 100644
index 5a25884e16396c06feaae2d6c47e92c4c9c2ee6d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:39:06"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_pio_pps"
- version="1.0"
- name="qsys_arts_unb2b_sc3_pio_pps">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527683946" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/synth/qsys_arts_unb2b_sc3_pio_pps.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/synth/qsys_arts_unb2b_sc3_pio_pps.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_pps">"Generating: qsys_arts_unb2b_sc3_pio_pps"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_pps">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_pio_pps"
- as="qsys_arts_unb2b_sc3_pio_pps" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_pps">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_bb.v
deleted file mode 100644
index 762288e0f5b0cb8ec582640d04f390b21e72e6b8..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_pio_pps (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_generation.rpt
deleted file mode 100644
index 8cf74b0a4cd1d2b3dfc591163dcd0ac185b465d1..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_pio_pps: "Transforming system: qsys_arts_unb2b_sc3_pio_pps"
-Info: qsys_arts_unb2b_sc3_pio_pps: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_pio_pps: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_pio_pps: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_pio_pps: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_pio_pps: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_pio_pps: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_pio_pps: "Naming system components in system: qsys_arts_unb2b_sc3_pio_pps"
-Info: qsys_arts_unb2b_sc3_pio_pps: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_pio_pps: "Generating: qsys_arts_unb2b_sc3_pio_pps"
-Info: qsys_arts_unb2b_sc3_pio_pps: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_pio_pps: Done "qsys_arts_unb2b_sc3_pio_pps" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_pio_pps. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_inst.v
deleted file mode 100644
index 9f7f3fe5fe6e92b33212bc03e254a72a4c1ba2e2..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_pio_pps u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_inst.vhd
deleted file mode 100644
index 2e630aac1e6f848cc91faa7535a161125b4c43f6..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/qsys_arts_unb2b_sc3_pio_pps_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_pio_pps is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_pio_pps;
-
- u0 : component qsys_arts_unb2b_sc3_pio_pps
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/synth/qsys_arts_unb2b_sc3_pio_pps.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/synth/qsys_arts_unb2b_sc3_pio_pps.vhd
deleted file mode 100644
index ba423961693d6801226176f0f2f54a828af0fabd..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps/synth/qsys_arts_unb2b_sc3_pio_pps.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_pio_pps.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_pio_pps is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_pio_pps;
-
-architecture rtl of qsys_arts_unb2b_sc3_pio_pps is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_pio_pps : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_pio_pps : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_pio_pps
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.bsf
deleted file mode 100644
index 00aa7aff1004f45b38be3e712e4f75a1231dde7b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_pio_system_info" (rect 58 -1 222 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_pio_system_info " (rect 175 512 572 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.cmp
deleted file mode 100644
index d60479f2d90e268ec1396149b4d3f6506d580193..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_pio_system_info is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_pio_system_info;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.html
deleted file mode 100644
index 4accfda914b1160f2ea4e06721baf7bfe1178e2f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_pio_system_info</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_pio_system_info</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:38:31</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_pio_system_info"><b>qsys_arts_unb2b_sc3_pio_system_info</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_pio_system_info"><b>qsys_arts_unb2b_sc3_pio_system_info</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_pio_system_info"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_pio_system_info</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.qgsynthc
deleted file mode 100644
index 453eeaf462522fcd41edeaf79e4eb8837f79667d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_pio_system_info</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_pio_system_info</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_pio_system_info</name>
- <uniqueName>qsys_arts_unb2b_sc3_pio_system_info</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_pio_system_info</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_pio_system_info</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_pio_system_info.qsys_arts_unb2b_sc3_pio_system_info</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.qip
deleted file mode 100644
index 5a33f088400d47aa262378580464e3d394b34851..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_system_info" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_pio_system_info.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_pio_system_info HAS_SOPCINFO 1 GENERATION_ID 1527683909"
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_system_info" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_pio_system_info.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_system_info" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_pio_system_info.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19waW9fc3lzdGVtX2luZm8="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4MzkwOQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_system_info" -library "qsys_arts_unb2b_sc3_pio_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_system_info" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_pio_system_info.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.sopcinfo
deleted file mode 100644
index 28a7714b297e657a6ce62a8667b2acb04f44705f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_pio_system_info"
- kind="qsys_arts_unb2b_sc3_pio_system_info"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:38:29 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527683909</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_pio_system_info"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_pio_system_info">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.xml
deleted file mode 100644
index 496faec01401e95d5d82036fd94d4e9e8daded38..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:38:31"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_pio_system_info"
- version="1.0"
- name="qsys_arts_unb2b_sc3_pio_system_info">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527683909" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/synth/qsys_arts_unb2b_sc3_pio_system_info.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/synth/qsys_arts_unb2b_sc3_pio_system_info.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_system_info">"Generating: qsys_arts_unb2b_sc3_pio_system_info"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_system_info">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_pio_system_info"
- as="qsys_arts_unb2b_sc3_pio_system_info" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_system_info">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_bb.v
deleted file mode 100644
index 134a22c7faad26671fab8c25562dc3e65e9742cc..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_pio_system_info (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_generation.rpt
deleted file mode 100644
index a6e0a2b412bc04a8682cbc5efc77f6a8e9647601..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_pio_system_info: "Transforming system: qsys_arts_unb2b_sc3_pio_system_info"
-Info: qsys_arts_unb2b_sc3_pio_system_info: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_pio_system_info: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_pio_system_info: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_pio_system_info: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_pio_system_info: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_pio_system_info: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_pio_system_info: "Naming system components in system: qsys_arts_unb2b_sc3_pio_system_info"
-Info: qsys_arts_unb2b_sc3_pio_system_info: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_pio_system_info: "Generating: qsys_arts_unb2b_sc3_pio_system_info"
-Info: qsys_arts_unb2b_sc3_pio_system_info: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_pio_system_info: Done "qsys_arts_unb2b_sc3_pio_system_info" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_pio_system_info. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_inst.v
deleted file mode 100644
index 7c33f8da4bfe385620f4ae63c44c6ddec531dc99..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_pio_system_info u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_inst.vhd
deleted file mode 100644
index 4d8dafd9a7e7f38e3065e07d158ac9edfe4be088..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/qsys_arts_unb2b_sc3_pio_system_info_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_pio_system_info is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_pio_system_info;
-
- u0 : component qsys_arts_unb2b_sc3_pio_system_info
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/synth/qsys_arts_unb2b_sc3_pio_system_info.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/synth/qsys_arts_unb2b_sc3_pio_system_info.vhd
deleted file mode 100644
index 505d456e6b5c02ab28ddc9238804055434c3975b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info/synth/qsys_arts_unb2b_sc3_pio_system_info.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_pio_system_info.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_pio_system_info is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_pio_system_info;
-
-architecture rtl of qsys_arts_unb2b_sc3_pio_system_info is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_pio_system_info : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_pio_system_info : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_pio_system_info
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi.ip
index 73664f640cd7eb9d0cee16ce7bd081ae96691939..6a3da7e5540af166f1811618b5e5abf2e4483198 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi.ip
@@ -485,13 +485,9 @@
<spirit:name>out_port</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>7</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
- <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
<spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
@@ -561,7 +557,7 @@
<spirit:parameter>
<spirit:name>width</spirit:name>
<spirit:displayName>Width (1-32 bits)</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="width">8</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="width">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>clockRate</spirit:name>
@@ -626,7 +622,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.DATA_WIDTH</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_WIDTH">8</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.DATA_WIDTH">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</spirit:name>
@@ -678,7 +674,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.dts.params.altr,gpio-bank-width</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.altr,gpio-bank-width">8</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.altr,gpio-bank-width">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.dts.params.resetvalue</spirit:name>
@@ -767,9 +763,9 @@
<name>out_port</name>
<role>export</role>
<direction>Output</direction>
- <width>8</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
- <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ <vhdlType>STD_LOGIC</vhdlType>
</port>
</ports>
<assignments>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/altera_avalon_pio_170/synth/qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/altera_avalon_pio_170/synth/qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy.v
deleted file mode 100644
index a5447d9ea1957ee4730be9829fa762e791217e72..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/altera_avalon_pio_170/synth/qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy.v
+++ /dev/null
@@ -1,67 +0,0 @@
-//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy (
- // inputs:
- address,
- chipselect,
- clk,
- reset_n,
- write_n,
- writedata,
-
- // outputs:
- out_port,
- readdata
- )
-;
-
- output [ 7: 0] out_port;
- output [ 31: 0] readdata;
- input [ 1: 0] address;
- input chipselect;
- input clk;
- input reset_n;
- input write_n;
- input [ 31: 0] writedata;
-
-
-wire clk_en;
-reg [ 7: 0] data_out;
-wire [ 7: 0] out_port;
-wire [ 7: 0] read_mux_out;
-wire [ 31: 0] readdata;
- assign clk_en = 1;
- //s1, which is an e_avalon_slave
- assign read_mux_out = {8 {(address == 0)}} & data_out;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- data_out <= 0;
- else if (chipselect && ~write_n && (address == 0))
- data_out <= writedata[7 : 0];
- end
-
-
- assign readdata = {32'b0 | read_mux_out};
- assign out_port = data_out;
-
-endmodule
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.bsf
deleted file mode 100644
index 7e8f7d386e3449dca9e7ff4525fcbfdf9d4523fe..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.bsf
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 320 288)
- (text "qsys_arts_unb2b_sc3_pio_wdi" (rect 69 -1 194 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 272 20 284)(font "Arial" ))
- (port
- (pt 0 72)
- (input)
- (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8)))
- (text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 128 72)(line_width 1))
- )
- (port
- (pt 0 152)
- (input)
- (text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8)))
- (text "reset_n" (rect 4 141 46 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 128 152)(line_width 1))
- )
- (port
- (pt 0 192)
- (input)
- (text "address[1..0]" (rect 0 0 50 12)(font "Arial" (font_size 8)))
- (text "address[1..0]" (rect 4 181 82 192)(font "Arial" (font_size 8)))
- (line (pt 0 192)(pt 128 192)(line_width 3))
- )
- (port
- (pt 0 208)
- (input)
- (text "write_n" (rect 0 0 28 12)(font "Arial" (font_size 8)))
- (text "write_n" (rect 4 197 46 208)(font "Arial" (font_size 8)))
- (line (pt 0 208)(pt 128 208)(line_width 1))
- )
- (port
- (pt 0 224)
- (input)
- (text "writedata[31..0]" (rect 0 0 57 12)(font "Arial" (font_size 8)))
- (text "writedata[31..0]" (rect 4 213 100 224)(font "Arial" (font_size 8)))
- (line (pt 0 224)(pt 128 224)(line_width 3))
- )
- (port
- (pt 0 240)
- (input)
- (text "chipselect" (rect 0 0 37 12)(font "Arial" (font_size 8)))
- (text "chipselect" (rect 4 229 64 240)(font "Arial" (font_size 8)))
- (line (pt 0 240)(pt 128 240)(line_width 1))
- )
- (port
- (pt 0 112)
- (output)
- (text "out_port[7..0]" (rect 0 0 53 12)(font "Arial" (font_size 8)))
- (text "out_port[7..0]" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 128 112)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "readdata[31..0]" (rect 0 0 57 12)(font "Arial" (font_size 8)))
- (text "readdata[31..0]" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 128 256)(line_width 3))
- )
- (drawing
- (text "clk" (rect 113 43 244 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 133 67 284 144)(font "Arial" (color 0 0 0)))
- (text "external_connection" (rect 14 83 142 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 133 107 302 224)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 99 123 228 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset_n" (rect 133 147 308 304)(font "Arial" (color 0 0 0)))
- (text "s1" (rect 117 163 246 339)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 133 187 308 384)(font "Arial" (color 0 0 0)))
- (text "write_n" (rect 133 203 308 416)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 133 219 320 448)(font "Arial" (color 0 0 0)))
- (text "chipselect" (rect 133 235 326 480)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 133 251 314 512)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_pio_wdi " (rect 184 272 542 554)(font "Arial" ))
- (line (pt 128 32)(pt 192 32)(line_width 1))
- (line (pt 192 32)(pt 192 272)(line_width 1))
- (line (pt 128 272)(pt 192 272)(line_width 1))
- (line (pt 128 32)(pt 128 272)(line_width 1))
- (line (pt 129 52)(pt 129 76)(line_width 1))
- (line (pt 130 52)(pt 130 76)(line_width 1))
- (line (pt 129 92)(pt 129 116)(line_width 1))
- (line (pt 130 92)(pt 130 116)(line_width 1))
- (line (pt 129 132)(pt 129 156)(line_width 1))
- (line (pt 130 132)(pt 130 156)(line_width 1))
- (line (pt 129 172)(pt 129 260)(line_width 1))
- (line (pt 130 172)(pt 130 260)(line_width 1))
- (line (pt 0 0)(pt 320 0)(line_width 1))
- (line (pt 320 0)(pt 320 288)(line_width 1))
- (line (pt 0 288)(pt 320 288)(line_width 1))
- (line (pt 0 0)(pt 0 288)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.cmp
deleted file mode 100644
index 39bf2d595b30905dd5adc8beef65fbe522ffb8a3..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.cmp
+++ /dev/null
@@ -1,13 +0,0 @@
- component qsys_arts_unb2b_sc3_pio_wdi is
- port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic_vector(7 downto 0); -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
- );
- end component qsys_arts_unb2b_sc3_pio_wdi;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.html
deleted file mode 100644
index a05756ba50f1f8b8b7cbc08d5e4daafb2ffd3b6b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.html
+++ /dev/null
@@ -1,280 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_pio_wdi</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_pio_wdi</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:42:23</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_pio_wdi"><b>qsys_arts_unb2b_sc3_pio_wdi</b>
- </a> altera_avalon_pio 17.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_pio_wdi"><b>qsys_arts_unb2b_sc3_pio_wdi</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">s1 </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_pio_wdi"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_pio_wdi</h2>altera_avalon_pio v17.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">bitClearingEdgeCapReg</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">bitModifyingOutReg</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">captureEdge</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">direction</td>
- <td class="parametervalue">Output</td>
- </tr>
- <tr>
- <td class="parametername">edgeType</td>
- <td class="parametervalue">RISING</td>
- </tr>
- <tr>
- <td class="parametername">generateIRQ</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">irqType</td>
- <td class="parametervalue">LEVEL</td>
- </tr>
- <tr>
- <td class="parametername">resetValue</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">simDoTestBenchWiring</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">simDrivenValue</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">width</td>
- <td class="parametervalue">8</td>
- </tr>
- <tr>
- <td class="parametername">clockRate</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">derived_has_tri</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">derived_has_out</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">derived_has_in</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">derived_do_test_bench_wiring</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">derived_capture</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">derived_edge_type</td>
- <td class="parametervalue">NONE</td>
- </tr>
- <tr>
- <td class="parametername">derived_irq_type</td>
- <td class="parametervalue">NONE</td>
- </tr>
- <tr>
- <td class="parametername">derived_has_irq</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>
- <table>
- <tr>
- <td class="parametername">BIT_CLEARING_EDGE_REGISTER</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">BIT_MODIFYING_OUTPUT_REGISTER</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">CAPTURE</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">DATA_WIDTH</td>
- <td class="parametervalue">8</td>
- </tr>
- <tr>
- <td class="parametername">DO_TEST_BENCH_WIRING</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">DRIVEN_SIM_VALUE</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">EDGE_TYPE</td>
- <td class="parametervalue">NONE</td>
- </tr>
- <tr>
- <td class="parametername">FREQ</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">HAS_IN</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">HAS_OUT</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">HAS_TRI</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">IRQ_TYPE</td>
- <td class="parametervalue">NONE</td>
- </tr>
- <tr>
- <td class="parametername">RESET_VALUE</td>
- <td class="parametervalue">0</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.qgsynthc
deleted file mode 100644
index 5948dcdbfb72ab13658959dcf405a712796af906..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.qgsynthc
+++ /dev/null
@@ -1,121 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_pio_wdi</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_pio_wdi</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_pio_wdi</name>
- <uniqueName>qsys_arts_unb2b_sc3_pio_wdi</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_pio_wdi</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>bitClearingEdgeCapReg</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>bitModifyingOutReg</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>captureEdge</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>clockRate</name>
- <value>125000000</value>
- </parameter>
- <parameter>
- <name>derived_capture</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>derived_do_test_bench_wiring</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>derived_edge_type</name>
- <value>NONE</value>
- </parameter>
- <parameter>
- <name>derived_has_in</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>derived_has_irq</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>derived_has_out</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>derived_has_tri</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>derived_irq_type</name>
- <value>NONE</value>
- </parameter>
- <parameter>
- <name>direction</name>
- <value>Output</value>
- </parameter>
- <parameter>
- <name>edgeType</name>
- <value>RISING</value>
- </parameter>
- <parameter>
- <name>generateIRQ</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>irqType</name>
- <value>LEVEL</value>
- </parameter>
- <parameter>
- <name>resetValue</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>simDoTestBenchWiring</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>simDrivenValue</name>
- <value>0</value>
- </parameter>
- <parameter>
- <name>width</name>
- <value>8</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>altera_avalon_pio</className>
- <version>17.0</version>
- <name>qsys_arts_unb2b_sc3_pio_wdi</name>
- <uniqueName>qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_pio_wdi.qsys_arts_unb2b_sc3_pio_wdi</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.qip
deleted file mode 100644
index 00759333675de9c8253c2982482de164b3d8757e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.qip
+++ /dev/null
@@ -1,53 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_wdi" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_pio_wdi.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_pio_wdi HAS_SOPCINFO 1 GENERATION_ID 1527684141"
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_wdi" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_pio_wdi.cmp"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_wdi" -name SLD_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_pio_wdi.regmap"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_wdi" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_pio_wdi.ip"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19waW9fd2RpX2FsdGVyYV9hdmFsb25fcGlvXzE3MF83d2pncXB5"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_DISPLAY_NAME "UElPIChQYXJhbGxlbCBJL08p"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_VERSION "MTcuMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "Yml0TW9kaWZ5aW5nT3V0UmVn::ZmFsc2U=::RW5hYmxlIGluZGl2aWR1YWwgYml0IHNldHRpbmcvY2xlYXJpbmc="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "ZGlyZWN0aW9u::T3V0cHV0::RGlyZWN0aW9u"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "cmVzZXRWYWx1ZQ==::MA==::T3V0cHV0IFBvcnQgUmVzZXQgVmFsdWU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "d2lkdGg=::OA==::V2lkdGggKDEtMzIgYml0cyk="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "Y2xvY2tSYXRl::MTI1MDAwMDAw::Y2xvY2tSYXRl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfdHJp::ZmFsc2U=::ZGVyaXZlZF9oYXNfdHJp"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfb3V0::dHJ1ZQ==::ZGVyaXZlZF9oYXNfb3V0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaW4=::ZmFsc2U=::ZGVyaXZlZF9oYXNfaW4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw==::ZmFsc2U=::ZGVyaXZlZF9kb190ZXN0X2JlbmNoX3dpcmluZw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9jYXB0dXJl::ZmFsc2U=::ZGVyaXZlZF9jYXB0dXJl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9lZGdlX3R5cGU=::Tk9ORQ==::ZGVyaXZlZF9lZGdlX3R5cGU="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9pcnFfdHlwZQ==::Tk9ORQ==::ZGVyaXZlZF9pcnFfdHlwZQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_PARAMETER "ZGVyaXZlZF9oYXNfaXJx::ZmFsc2U=::ZGVyaXZlZF9oYXNfaXJx"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_GROUP "UHJvY2Vzc29ycyBhbmQgUGVyaXBoZXJhbHMvUGVyaXBoZXJhbHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL3NmbzE0MDA3ODc5NTI5MzIvaWdhMTQwMTM5NDgyNTkxMQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5NzY4OTMwMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19waW9fd2Rp"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDE0MQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi" -library "qsys_arts_unb2b_sc3_pio_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "altera_avalon_pio_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_pio_170/synth/qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy.v"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_pio_wdi" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_pio_wdi.vhd"]
-
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_TOOL_NAME "altera_avalon_pio"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_TOOL_VERSION "17.0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy" -library "altera_avalon_pio_170" -name IP_TOOL_ENV "QsysPrimePro"
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.regmap b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.regmap
deleted file mode 100644
index 1dfd79b7917b82231cff7e373b2e4b3bacde0454..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.regmap
+++ /dev/null
@@ -1,242 +0,0 @@
-<?xml version="1.0"?>
-<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
-<name>qsys_arts_unb2b_sc3_pio_wdi</name>
-<peripherals>
-<peripheral>
- <name>qsys_arts_unb2b_sc3_pio_wdi_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>32</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DATA</name>
- <displayName>Data</displayName>
- <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>data</name>
- <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DIRECTION</name>
- <displayName>Direction</displayName>
- <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>direction</name>
- <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>IRQ_MASK</name>
- <displayName>Interrupt mask</displayName>
- <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>interruptmask</name>
- <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>EDGE_CAP</name>
- <displayName>Edge capture</displayName>
- <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
- <addressOffset>0xc</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>edgecapture</name>
- <description>Edge detection for each input port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SET_BIT</name>
- <displayName>Outset</displayName>
- <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
- <addressOffset>0x10</addressOffset>
- <size>32</size>
- <access>write-only</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>outset</name>
- <description>Specifies which bit of the output port to set.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>write-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CLEAR_BITS</name>
- <displayName>Outclear</displayName>
- <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
- <addressOffset>0x14</addressOffset>
- <size>32</size>
- <access>write-only</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>outclear</name>
- <description>Specifies which output bit to clear.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>write-only</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>qsys_arts_unb2b_sc3_pio_wdi_qsys_arts_unb2b_sc3_pio_wdi_s1_altera_avalon_pio</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>32</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DATA</name>
- <displayName>Data</displayName>
- <description>Reading from data returns the value present at the input ports. If the PIO core hardware is configured in output-only mode, reading from data returns an undefined value. Writing to data stores the value to a register that drives the output ports. If the PIO core hardware is configured in input-only mode, writing to data has no effect. If the PIO core hardware is in bidirectional mode, the registered value appears on an output port only when the corresponding bit in the direction register is set to 1 (output).</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>data</name>
- <description>Reads: Data value currently on PIO inputs. Writes: New value to drive on PIO outputs.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DIRECTION</name>
- <displayName>Direction</displayName>
- <description>The direction register controls the data direction for each PIO port, assuming the port is bidirectional. When bit n in direction is set to 1, port n drives out the value in the corresponding bit of the data register The direction register only exists when the PIO core hardware is configured in bidirectional mode. The mode (input, output, or bidirectional) is specified at system generation time, and cannot be changed at runtime. In input-only or output-only mode, the direction register does not exist. In this case, reading direction returns an undefined value, writing direction has no effect. After reset, all bits of direction are 0, so that all bidirectional I/O ports are configured as inputs. If those PIO ports are connected to device pins, the pins are held in a high-impedance state. In bi-directional mode, to change the direction of the PIO port, reprogram the direction register.</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>direction</name>
- <description>Individual direction control for each I/O port. A value of 0 sets the direction to input; 1 sets the direction to output.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>IRQ_MASK</name>
- <displayName>Interrupt mask</displayName>
- <description>Setting a bit in the interruptmask register to 1 enables interrupts for the corresponding PIO input port. Interrupt behavior depends on the hardware configuration of the PIO core. The interruptmask register only exists when the hardware is configured to generate IRQs. If the core cannot generate IRQs, reading interruptmask returns an undefined value, and writing to interruptmask has no effect. After reset, all bits of interruptmask are zero, so that interrupts are disabled for all PIO ports.</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>interruptmask</name>
- <description>IRQ enable/disable for each input port. Setting a bit to 1 enables interrupts for the corresponding port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>EDGE_CAP</name>
- <displayName>Edge capture</displayName>
- <description>Bit n in the edgecapture register is set to 1 whenever an edge is detected on input port n. An Avalon-MM master peripheral can read the edgecapture register to determine if an edge has occurred on any of the PIO input ports. If the option Enable bit-clearing for edge capture register is turned off, writing any value to the edgecapture register clears all bits in the register. Otherwise, writing a 1 to a particular bit in the register clears only that bit. The type of edge(s) to detect is fixed in hardware at system generation time. The edgecapture register only exists when the hardware is configured to capture edges. If the core is not configured to capture edges, reading from edgecapture returns an undefined value, and writing to edgecapture has no effect.</description>
- <addressOffset>0xc</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>edgecapture</name>
- <description>Edge detection for each input port.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SET_BIT</name>
- <displayName>Outset</displayName>
- <description>You can use the outset register to set individual bits of the output port. For example, to set bit 6 of the output port, write 0x40 to the outset register. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
- <addressOffset>0x10</addressOffset>
- <size>32</size>
- <access>write-only</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>outset</name>
- <description>Specifies which bit of the output port to set.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>write-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CLEAR_BITS</name>
- <displayName>Outclear</displayName>
- <description>You can use the outclear register to clear individual bits of the output port. For example, writing 0x08 to the outclear register clears bit 3 of the output port. This register is only present when the option Enable individual bit set/clear output register is turned on.</description>
- <addressOffset>0x14</addressOffset>
- <size>32</size>
- <access>write-only</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffffffff</resetMask>
- <fields>
- <field><name>outclear</name>
- <description>Specifies which output bit to clear.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>32</bitWidth>
- <access>write-only</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.sopcinfo
deleted file mode 100644
index 7b2bd264bf9984be41ad821d4921b25ba19142b8..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.sopcinfo
+++ /dev/null
@@ -1,962 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_pio_wdi"
- kind="qsys_arts_unb2b_sc3_pio_wdi"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:42:21 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684141</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_CLK_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_pio_wdi"
- kind="altera_avalon_pio"
- version="17.0"
- path="qsys_arts_unb2b_sc3_pio_wdi">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <assignment>
- <name>embeddedsw.CMacro.BIT_CLEARING_EDGE_REGISTER</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.BIT_MODIFYING_OUTPUT_REGISTER</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.CAPTURE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.DATA_WIDTH</name>
- <value>8</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.DO_TEST_BENCH_WIRING</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.DRIVEN_SIM_VALUE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.EDGE_TYPE</name>
- <value>NONE</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.FREQ</name>
- <value>125000000</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HAS_IN</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HAS_OUT</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.HAS_TRI</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.IRQ_TYPE</name>
- <value>NONE</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.RESET_VALUE</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.compatible</name>
- <value>altr,pio-1.0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.group</name>
- <value>gpio</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.name</name>
- <value>pio</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.altr,gpio-bank-width</name>
- <value>8</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.resetvalue</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.vendor</name>
- <value>altr</value>
- </assignment>
- <parameter name="bitClearingEdgeCapReg">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitModifyingOutReg">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="captureEdge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="direction">
- <type>java.lang.String</type>
- <value>Output</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="edgeType">
- <type>java.lang.String</type>
- <value>RISING</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateIRQ">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="irqType">
- <type>java.lang.String</type>
- <value>LEVEL</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="resetValue">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="simDoTestBenchWiring">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="simDrivenValue">
- <type>long</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="width">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="derived_has_tri">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_has_out">
- <type>boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_has_in">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_do_test_bench_wiring">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_capture">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_edge_type">
- <type>java.lang.String</type>
- <value>NONE</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_irq_type">
- <type>java.lang.String</type>
- <value>NONE</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="derived_has_irq">
- <type>boolean</type>
- <value>false</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="clk" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>reset_n</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset_n</role>
- </port>
- </interface>
- <interface name="s1" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isFlash</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>0</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>NATIVE</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>4</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>address</name>
- <direction>Input</direction>
- <width>2</width>
- <role>address</role>
- </port>
- <port>
- <name>write_n</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write_n</role>
- </port>
- <port>
- <name>writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>chipselect</name>
- <direction>Input</direction>
- <width>1</width>
- <role>chipselect</role>
- </port>
- <port>
- <name>readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="external_connection" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>out_port</name>
- <direction>Output</direction>
- <width>8</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>altera_avalon_pio</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>PIO (Parallel I/O)</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.xml
deleted file mode 100644
index b3d92f2750645699a02a062b9790295a01ecd457..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi.xml
+++ /dev/null
@@ -1,207 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:42:25"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="clk" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="external_connection" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="out_port" direction="output" role="export" width="8" />
- </interface>
- <interface name="reset" kind="reset" start="0">
- <property name="associatedClock" value="clk" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="reset_n" direction="input" role="reset_n" width="1" />
- </interface>
- <interface name="s1" kind="avalon" start="0">
- <property name="addressAlignment" value="NATIVE" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="4" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="clk" />
- <property name="associatedReset" value="reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="0" />
- <property name="readWaitStates" value="1" />
- <property name="readWaitTime" value="1" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="address" direction="input" role="address" width="2" />
- <port name="write_n" direction="input" role="write_n" width="1" />
- <port name="writedata" direction="input" role="writedata" width="32" />
- <port name="chipselect" direction="input" role="chipselect" width="1" />
- <port name="readdata" direction="output" role="readdata" width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_pio_wdi"
- version="1.0"
- name="qsys_arts_unb2b_sc3_pio_wdi">
- <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684141" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/synth/qsys_arts_unb2b_sc3_pio_wdi.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/synth/qsys_arts_unb2b_sc3_pio_wdi.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_wdi">"Generating: qsys_arts_unb2b_sc3_pio_wdi"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_wdi">"Generating: qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_wdi">Starting RTL generation for module 'qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy'</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_wdi"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy --dir=/tmp/alt7681_6931282645914172388.dir/0009_qsys_arts_unb2b_sc3_pio_wdi_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0009_qsys_arts_unb2b_sc3_pio_wdi_gen//qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy_component_configuration.pl --do_build_sim=0 ]</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_wdi">Done RTL generation for module 'qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy'</message>
- </messages>
- </entity>
- <entity
- kind="altera_avalon_pio"
- version="17.0"
- name="qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy">
- <parameter name="derived_do_test_bench_wiring" value="false" />
- <parameter name="generateIRQ" value="false" />
- <parameter name="derived_has_irq" value="false" />
- <parameter name="captureEdge" value="false" />
- <parameter name="clockRate" value="125000000" />
- <parameter name="derived_has_out" value="true" />
- <parameter name="derived_has_in" value="false" />
- <parameter name="resetValue" value="0" />
- <parameter name="derived_has_tri" value="false" />
- <parameter name="derived_capture" value="false" />
- <parameter name="simDoTestBenchWiring" value="false" />
- <parameter name="bitModifyingOutReg" value="false" />
- <parameter name="simDrivenValue" value="0" />
- <parameter name="derived_edge_type" value="NONE" />
- <parameter name="irqType" value="LEVEL" />
- <parameter name="derived_irq_type" value="NONE" />
- <parameter name="edgeType" value="RISING" />
- <parameter name="width" value="8" />
- <parameter name="bitClearingEdgeCapReg" value="false" />
- <parameter name="direction" value="Output" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/altera_avalon_pio_170/synth/qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy.v"
- attributes="" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/altera_avalon_pio_170/synth/qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy.v"
- attributes="" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/sopc_builder_ip/altera_avalon_pio/altera_avalon_pio_hw.tcl" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_pio_wdi"
- as="qsys_arts_unb2b_sc3_pio_wdi" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_wdi">"Generating: qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_wdi">Starting RTL generation for module 'qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy'</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_wdi"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy --dir=/tmp/alt7681_6931282645914172388.dir/0009_qsys_arts_unb2b_sc3_pio_wdi_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0009_qsys_arts_unb2b_sc3_pio_wdi_gen//qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy_component_configuration.pl --do_build_sim=0 ]</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_pio_wdi">Done RTL generation for module 'qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy'</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_bb.v
deleted file mode 100644
index 9c0ec6da9a9a001d7859c654c8097e8f6d6af0bf..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_bb.v
+++ /dev/null
@@ -1,20 +0,0 @@
-
-module qsys_arts_unb2b_sc3_pio_wdi (
- clk,
- out_port,
- reset_n,
- address,
- write_n,
- writedata,
- chipselect,
- readdata);
-
- input clk;
- output [7:0] out_port;
- input reset_n;
- input [1:0] address;
- input write_n;
- input [31:0] writedata;
- input chipselect;
- output [31:0] readdata;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_generation.rpt
deleted file mode 100644
index 79b3f0b17891ba8012b5d3308bd64cc98fcf6ce0..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_generation.rpt
+++ /dev/null
@@ -1,28 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_pio_wdi: "Transforming system: qsys_arts_unb2b_sc3_pio_wdi"
-Info: qsys_arts_unb2b_sc3_pio_wdi: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_pio_wdi: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_pio_wdi: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_pio_wdi: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_pio_wdi: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_pio_wdi: Running transform interconnect_transform_chooser took 0.008s
-Info: qsys_arts_unb2b_sc3_pio_wdi: "Naming system components in system: qsys_arts_unb2b_sc3_pio_wdi"
-Info: qsys_arts_unb2b_sc3_pio_wdi: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_pio_wdi: "Generating: qsys_arts_unb2b_sc3_pio_wdi"
-Info: qsys_arts_unb2b_sc3_pio_wdi: "Generating: qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy"
-Info: qsys_arts_unb2b_sc3_pio_wdi: Starting RTL generation for module 'qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy'
-Info: qsys_arts_unb2b_sc3_pio_wdi: Generation command is [exec /home/software/Altera/17.0/quartus/linux64/perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64/perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy --dir=/tmp/alt7681_6931282645914172388.dir/0009_qsys_arts_unb2b_sc3_pio_wdi_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0009_qsys_arts_unb2b_sc3_pio_wdi_gen//qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy_component_configuration.pl --do_build_sim=0 ]
-Info: qsys_arts_unb2b_sc3_pio_wdi: Done RTL generation for module 'qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy'
-Info: qsys_arts_unb2b_sc3_pio_wdi: Done "qsys_arts_unb2b_sc3_pio_wdi" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_pio_wdi. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_inst.v
deleted file mode 100644
index 2a6e899b20a3baa72fc738a21c5236b4f24e0a9c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_inst.v
+++ /dev/null
@@ -1,11 +0,0 @@
- qsys_arts_unb2b_sc3_pio_wdi u0 (
- .clk (_connected_to_clk_), // clk.clk
- .out_port (_connected_to_out_port_), // external_connection.export
- .reset_n (_connected_to_reset_n_), // reset.reset_n
- .address (_connected_to_address_), // s1.address
- .write_n (_connected_to_write_n_), // .write_n
- .writedata (_connected_to_writedata_), // .writedata
- .chipselect (_connected_to_chipselect_), // .chipselect
- .readdata (_connected_to_readdata_) // .readdata
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_inst.vhd
deleted file mode 100644
index a5720bf900ea7e0671ed040f90cddabbdba62124..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/qsys_arts_unb2b_sc3_pio_wdi_inst.vhd
+++ /dev/null
@@ -1,25 +0,0 @@
- component qsys_arts_unb2b_sc3_pio_wdi is
- port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic_vector(7 downto 0); -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
- );
- end component qsys_arts_unb2b_sc3_pio_wdi;
-
- u0 : component qsys_arts_unb2b_sc3_pio_wdi
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- out_port => CONNECTED_TO_out_port, -- external_connection.export
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- write_n => CONNECTED_TO_write_n, -- .write_n
- writedata => CONNECTED_TO_writedata, -- .writedata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- readdata => CONNECTED_TO_readdata -- .readdata
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/synth/qsys_arts_unb2b_sc3_pio_wdi.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/synth/qsys_arts_unb2b_sc3_pio_wdi.vhd
deleted file mode 100644
index 351f282023ab1c1c7f1aff0e29980307f98dd161..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi/synth/qsys_arts_unb2b_sc3_pio_wdi.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
--- qsys_arts_unb2b_sc3_pio_wdi.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library altera_avalon_pio_170;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_pio_wdi is
- port (
- clk : in std_logic := '0'; -- clk.clk
- out_port : out std_logic_vector(7 downto 0); -- external_connection.export
- reset_n : in std_logic := '0'; -- reset.reset_n
- address : in std_logic_vector(1 downto 0) := (others => '0'); -- s1.address
- write_n : in std_logic := '0'; -- .write_n
- writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- chipselect : in std_logic := '0'; -- .chipselect
- readdata : out std_logic_vector(31 downto 0) -- .readdata
- );
-end entity qsys_arts_unb2b_sc3_pio_wdi;
-
-architecture rtl of qsys_arts_unb2b_sc3_pio_wdi is
- component qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy_cmp is
- port (
- clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0); -- readdata
- out_port : out std_logic_vector(7 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy_cmp;
-
- for qsys_arts_unb2b_sc3_pio_wdi : qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy_cmp
- use entity altera_avalon_pio_170.qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy;
-begin
-
- qsys_arts_unb2b_sc3_pio_wdi : component qsys_arts_unb2b_sc3_pio_wdi_altera_avalon_pio_170_7wjgqpy_cmp
- port map (
- clk => clk, -- clk.clk
- reset_n => reset_n, -- reset.reset_n
- address => address, -- s1.address
- write_n => write_n, -- .write_n
- writedata => writedata, -- .writedata
- chipselect => chipselect, -- .chipselect
- readdata => readdata, -- .readdata
- out_port => out_port -- external_connection.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_pio_wdi
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.ip
index 970612e5fbd133294e96fea10206816f8462163b..b2f10111021305fdf45131da65a4d45ffd74943b 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,10 +605,6 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -701,10 +697,6 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -783,7 +775,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +833,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +897,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +966,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1361,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.bsf
deleted file mode 100644
index 48ade735c9bb990f05de58c91160aa17e309ae0d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" (rect 62 -1 221 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_dpmm_ctrl " (rect 181 512 572 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.cmp
deleted file mode 100644
index d8aa803460e465e4a5a751e704320d74d14e8f61..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_dpmm_ctrl is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_dpmm_ctrl;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.html
deleted file mode 100644
index 01f7f0db129bc90202f4400712044f604ee246ec..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_dpmm_ctrl</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_dpmm_ctrl</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:43:05</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_dpmm_ctrl"><b>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_dpmm_ctrl"><b>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_dpmm_ctrl"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.qgsynthc
deleted file mode 100644
index 494056f7309308bc7accb0716d9ee16891c03fa8..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_dpmm_ctrl</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_dpmm_ctrl</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_dpmm_ctrl.qsys_arts_unb2b_sc3_reg_dpmm_ctrl</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.qip
deleted file mode 100644
index 00cc62576735a1f74254f9a67ec1b420d1fd0de6..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_dpmm_ctrl.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_dpmm_ctrl HAS_SOPCINFO 1 GENERATION_ID 1527684185"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_dpmm_ctrl.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_dpmm_ctrl.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfZHBtbV9jdHJs"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDE4NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.sopcinfo
deleted file mode 100644
index 29d21179ea4d9d6109098722dc80b5c3aff34329..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_dpmm_ctrl"
- kind="qsys_arts_unb2b_sc3_reg_dpmm_ctrl"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:43:05 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684185</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_dpmm_ctrl"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_dpmm_ctrl">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.xml
deleted file mode 100644
index 4b0dba2872024e203c1c13bd6aff3e36fb9c48ef..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:43:07"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_dpmm_ctrl"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_dpmm_ctrl">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684185" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/synth/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/synth/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_dpmm_ctrl">"Generating: qsys_arts_unb2b_sc3_reg_dpmm_ctrl"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_dpmm_ctrl">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_dpmm_ctrl"
- as="qsys_arts_unb2b_sc3_reg_dpmm_ctrl" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_dpmm_ctrl">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_bb.v
deleted file mode 100644
index 55b03e311526e78ff57f4a660b67eecbe0e31930..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_dpmm_ctrl (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_generation.rpt
deleted file mode 100644
index 06c9c0bc5f49ef9475cc6592c683ba42bac7ca3a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: "Transforming system: qsys_arts_unb2b_sc3_reg_dpmm_ctrl"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: "Naming system components in system: qsys_arts_unb2b_sc3_reg_dpmm_ctrl"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: "Generating: qsys_arts_unb2b_sc3_reg_dpmm_ctrl"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_ctrl: Done "qsys_arts_unb2b_sc3_reg_dpmm_ctrl" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_dpmm_ctrl. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_inst.v
deleted file mode 100644
index 5a34f743fb8588e5446a0af2090d68bafb2d32d3..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_dpmm_ctrl u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_inst.vhd
deleted file mode 100644
index 88709f7d7cd155234af8202481b20b88e585401c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_dpmm_ctrl is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_dpmm_ctrl;
-
- u0 : component qsys_arts_unb2b_sc3_reg_dpmm_ctrl
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/synth/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/synth/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.vhd
deleted file mode 100644
index d2635f97489c7e28408484fdfce45d9f569c8d70..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl/synth/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_dpmm_ctrl.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_dpmm_ctrl is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_dpmm_ctrl;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_dpmm_ctrl is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_dpmm_ctrl : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_dpmm_ctrl : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_dpmm_ctrl
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data.ip
index a1c8b7797e5965918bc79459cacf188eb0fcc196..e84f0ce287d7b40684bba6edbfcf5d2d340659d4 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,10 +605,6 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -701,10 +697,6 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -783,7 +775,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +833,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +897,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +966,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1361,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.bsf
deleted file mode 100644
index e1f552679cd9a1cfaee53347961f479147d50ce6..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_dpmm_data" (rect 59 -1 223 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_dpmm_data " (rect 177 512 564 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.cmp
deleted file mode 100644
index e166d41b111b2f1bc23c778cc314ef25ccdb763d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_dpmm_data is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_dpmm_data;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.html
deleted file mode 100644
index 29085c0bb6132fdc18709a42a96dcabe251d334a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_dpmm_data</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_dpmm_data</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:37:57</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_dpmm_data"><b>qsys_arts_unb2b_sc3_reg_dpmm_data</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_dpmm_data"><b>qsys_arts_unb2b_sc3_reg_dpmm_data</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_dpmm_data"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_dpmm_data</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.qgsynthc
deleted file mode 100644
index 5a61d3d26af11299fa827f94396c86246b05da50..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_dpmm_data</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_dpmm_data</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_dpmm_data</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_dpmm_data</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_dpmm_data</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_dpmm_data</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_dpmm_data.qsys_arts_unb2b_sc3_reg_dpmm_data</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.qip
deleted file mode 100644
index e7a3bf85fe673567e9a22a3550e6a5294e9c8f72..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_dpmm_data.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_dpmm_data HAS_SOPCINFO 1 GENERATION_ID 1527683875"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_dpmm_data.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_dpmm_data.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfZHBtbV9kYXRh"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4Mzg3NQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_dpmm_data" -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_dpmm_data" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_dpmm_data.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.sopcinfo
deleted file mode 100644
index b403a1dcf322113eb3043b4e660ed2191cdb01df..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_dpmm_data"
- kind="qsys_arts_unb2b_sc3_reg_dpmm_data"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:37:55 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527683875</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_dpmm_data"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_dpmm_data">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.xml
deleted file mode 100644
index 5feff55a94caa7cb2157ea3f500a178c80f4d5ea..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:37:57"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_dpmm_data"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_dpmm_data">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527683875" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/synth/qsys_arts_unb2b_sc3_reg_dpmm_data.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/synth/qsys_arts_unb2b_sc3_reg_dpmm_data.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_dpmm_data">"Generating: qsys_arts_unb2b_sc3_reg_dpmm_data"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_dpmm_data">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_dpmm_data"
- as="qsys_arts_unb2b_sc3_reg_dpmm_data" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_dpmm_data">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_bb.v
deleted file mode 100644
index ac9c530f0ca2dc9f55f36ba6cdc3005705ef2843..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_dpmm_data (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_generation.rpt
deleted file mode 100644
index 3b0e3b6e13fe9af0870a0dbf9e8fee685cd22110..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: "Transforming system: qsys_arts_unb2b_sc3_reg_dpmm_data"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: "Naming system components in system: qsys_arts_unb2b_sc3_reg_dpmm_data"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: "Generating: qsys_arts_unb2b_sc3_reg_dpmm_data"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_dpmm_data: Done "qsys_arts_unb2b_sc3_reg_dpmm_data" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_dpmm_data. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_inst.v
deleted file mode 100644
index cf71f5c7e18f13e239440e46b4c5c039126c3518..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_dpmm_data u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_inst.vhd
deleted file mode 100644
index 2b45cb582ca9626339e9537c555e9ff4570bf553..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/qsys_arts_unb2b_sc3_reg_dpmm_data_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_dpmm_data is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_dpmm_data;
-
- u0 : component qsys_arts_unb2b_sc3_reg_dpmm_data
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/synth/qsys_arts_unb2b_sc3_reg_dpmm_data.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/synth/qsys_arts_unb2b_sc3_reg_dpmm_data.vhd
deleted file mode 100644
index 4292fa907bd73e49821878574cbb005b5c392c1d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data/synth/qsys_arts_unb2b_sc3_reg_dpmm_data.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_dpmm_data.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_dpmm_data is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_dpmm_data;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_dpmm_data is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_dpmm_data : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_dpmm_data : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_dpmm_data
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs.ip
index 1f74bcc923c8ff652781054cd868a79d0dd3ae73..f3e35353a6789a0c7c9447109e7be37fcecd05d7 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>2</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>2</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +905,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +974,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1369,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.bsf
deleted file mode 100644
index 35a9585a515641308649198ee98c4ee399761771..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_epcs" (rect 80 -1 214 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_epcs " (rect 207 512 594 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.cmp
deleted file mode 100644
index 7bbfcfb090fef79efcdcfd9ce230de7791296681..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_epcs is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_epcs;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.html
deleted file mode 100644
index e8be02df2844ff5d535ac57d5dd8bdb00572e611..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_epcs</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_epcs</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:40:38</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_epcs"><b>qsys_arts_unb2b_sc3_reg_epcs</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_epcs"><b>qsys_arts_unb2b_sc3_reg_epcs</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_epcs"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_epcs</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.qgsynthc
deleted file mode 100644
index 3f481f295511adb8088cec259d03fb5721cf2a03..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_epcs</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_epcs</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_epcs</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_epcs</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_epcs</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_epcs</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_epcs.qsys_arts_unb2b_sc3_reg_epcs</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.qip
deleted file mode 100644
index 3a2432fe1e7656b1fd73d0ccbeb231a7628f946c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_epcs" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_epcs.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_epcs HAS_SOPCINFO 1 GENERATION_ID 1527684036"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_epcs" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_epcs.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_epcs" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_epcs.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfZXBjcw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDAzNg==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_epcs" -library "qsys_arts_unb2b_sc3_reg_epcs" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_epcs" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_epcs.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.sopcinfo
deleted file mode 100644
index 548676734c97325131ec2ffdb865ebf1b0b68ddc..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_epcs"
- kind="qsys_arts_unb2b_sc3_reg_epcs"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:40:36 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684036</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_epcs"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_epcs">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.xml
deleted file mode 100644
index e0a767e94e235c3b2e590d8de45905c608942e4e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:40:38"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_epcs"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_epcs">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684036" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/synth/qsys_arts_unb2b_sc3_reg_epcs.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/synth/qsys_arts_unb2b_sc3_reg_epcs.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_epcs">"Generating: qsys_arts_unb2b_sc3_reg_epcs"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_epcs">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_epcs"
- as="qsys_arts_unb2b_sc3_reg_epcs" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_epcs">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_bb.v
deleted file mode 100644
index 7a2765a051a434a1db53afd28573728cd6f0a9c8..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_epcs (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_generation.rpt
deleted file mode 100644
index 344af4e0ae33aac81036ee10b82d603a2ca17ec5..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_epcs: "Transforming system: qsys_arts_unb2b_sc3_reg_epcs"
-Info: qsys_arts_unb2b_sc3_reg_epcs: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_epcs: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_epcs: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_epcs: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_epcs: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_epcs: Running transform interconnect_transform_chooser took 0.008s
-Info: qsys_arts_unb2b_sc3_reg_epcs: "Naming system components in system: qsys_arts_unb2b_sc3_reg_epcs"
-Info: qsys_arts_unb2b_sc3_reg_epcs: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_epcs: "Generating: qsys_arts_unb2b_sc3_reg_epcs"
-Info: qsys_arts_unb2b_sc3_reg_epcs: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_epcs: Done "qsys_arts_unb2b_sc3_reg_epcs" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_epcs. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_inst.v
deleted file mode 100644
index 8b672b465a503cb1219d4c2c7f100d06addc3ccf..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_epcs u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_inst.vhd
deleted file mode 100644
index d5a72f5f5c517fd18a23a2021b227a169b000235..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/qsys_arts_unb2b_sc3_reg_epcs_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_epcs is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_epcs;
-
- u0 : component qsys_arts_unb2b_sc3_reg_epcs
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/synth/qsys_arts_unb2b_sc3_reg_epcs.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/synth/qsys_arts_unb2b_sc3_reg_epcs.vhd
deleted file mode 100644
index e57140d4c44b0a979702d32327f36c1bdbd7a4f7..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs/synth/qsys_arts_unb2b_sc3_reg_epcs.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_epcs.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_epcs is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_epcs;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_epcs is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_epcs : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_epcs : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_epcs
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.ip
index cc01b6e3018c0a1573ab8d78fd1a9d393cf9ab05..02086d52aae589f6950e9ca2c60d7b3c626e58dc 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">512</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>6</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>6</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">7</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +905,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>7</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +974,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>512</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1369,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>9</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.bsf
deleted file mode 100644
index dce24a44b96af70c523d539142e50bed1c8789bd..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" (rect 43 -1 227 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring " (rect 153 512 558 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.cmp
deleted file mode 100644
index 5fc47b82009c26370b5824b45f735895a5280f45..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.html
deleted file mode 100644
index 4495e54089caf5f66334ad6244e21a0e133ae19a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:43:25</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"><b>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"><b>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 2.05 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.qgsynthc
deleted file mode 100644
index 1d77f9d0b06e5e3c182ca814bd15ebbb401453e9..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.qip
deleted file mode 100644
index 5510a6d34da6b38c7da2eabe0b09a0eb9f785b97..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring HAS_SOPCINFO 1 GENERATION_ID 1527684205"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfZXRoMTBnX3FzZnBfcmluZw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDIwNQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.sopcinfo
deleted file mode 100644
index 66817f040e6fa7d78644c476516b106165419dba..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"
- kind="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:43:25 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684205</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.xml
deleted file mode 100644
index 440303883d930d7e957686f5210c0fc58d39345c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:43:27"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684205" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring">"Generating: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"
- as="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_bb.v
deleted file mode 100644
index e4122481fe03181aeff5b2598cb83bd50d57b4f5..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_generation.rpt
deleted file mode 100644
index eda1edbb257be690ceed34e59080baf542b94c7a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: "Transforming system: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: Running transform interconnect_transform_chooser took 0.008s
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: "Naming system components in system: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: "Generating: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring"
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring: Done "qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_inst.v
deleted file mode 100644
index 2ae14355e91b91315b4d941bc7bd06516fe1d90e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_inst.vhd
deleted file mode 100644
index 9509c2fc462d9c105ded9ef9aefe424089da5ec1..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring;
-
- u0 : component qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.vhd
deleted file mode 100644
index e5b9acfa351592c989bd560710622980a287d8e9..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip
index 24ea7977444c012f19416f20502c33f19d06782f..a22a79e8c5ebbd781ea9fc33831d524fcf846483 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>2</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>2</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +905,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +974,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1369,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.bsf
deleted file mode 100644
index d0f3d188ae4ba067ddc12fdda485e5ed21c8fc90..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" (rect 44 -1 228 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_fpga_temp_sens " (rect 155 512 550 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.cmp
deleted file mode 100644
index e5e9a6f3f69207b4880d349afbd449f1930177a2..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_fpga_temp_sens is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_fpga_temp_sens;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.html
deleted file mode 100644
index dbe896c0ac4ad93fb5b2464d203fe0a5e0936b06..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_fpga_temp_sens</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_fpga_temp_sens</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:45:18</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_fpga_temp_sens"><b>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_fpga_temp_sens"><b>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_fpga_temp_sens"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.qgsynthc
deleted file mode 100644
index 5f78d0a300c41ed01884bc90a2b4870609118ffd..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_fpga_temp_sens</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_fpga_temp_sens</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_fpga_temp_sens.qsys_arts_unb2b_sc3_reg_fpga_temp_sens</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.qip
deleted file mode 100644
index aeef2177d64a2964cf0eaf1f2def13a117c30105..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_fpga_temp_sens.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_fpga_temp_sens HAS_SOPCINFO 1 GENERATION_ID 1527684316"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_fpga_temp_sens.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfZnBnYV90ZW1wX3NlbnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDMxNg==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.sopcinfo
deleted file mode 100644
index de127139123ff039ed20ad669e9ec667cba8e10f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_fpga_temp_sens"
- kind="qsys_arts_unb2b_sc3_reg_fpga_temp_sens"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:45:16 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684316</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_fpga_temp_sens"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_fpga_temp_sens">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.xml
deleted file mode 100644
index 19e46018c55f04f3c5dcfe0a5a09fa4ce62426bf..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:45:18"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_fpga_temp_sens"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_fpga_temp_sens">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684316" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_fpga_temp_sens">"Generating: qsys_arts_unb2b_sc3_reg_fpga_temp_sens"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_fpga_temp_sens">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_fpga_temp_sens"
- as="qsys_arts_unb2b_sc3_reg_fpga_temp_sens" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_fpga_temp_sens">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_bb.v
deleted file mode 100644
index 2f0519f2f97bb67847614fb06504d45a33ea6e36..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_fpga_temp_sens (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_generation.rpt
deleted file mode 100644
index ac584cd451fa71ee965f0fddfae6fd53dfbf5285..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: "Transforming system: qsys_arts_unb2b_sc3_reg_fpga_temp_sens"
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: "Naming system components in system: qsys_arts_unb2b_sc3_reg_fpga_temp_sens"
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: "Generating: qsys_arts_unb2b_sc3_reg_fpga_temp_sens"
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_fpga_temp_sens: Done "qsys_arts_unb2b_sc3_reg_fpga_temp_sens" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_fpga_temp_sens. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_inst.v
deleted file mode 100644
index 4c14d12767b726d588a0c73020e32980381941b7..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_fpga_temp_sens u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_inst.vhd
deleted file mode 100644
index db7f2beb04cfd4749f3dc648ec30f1a685a4d319..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_fpga_temp_sens is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_fpga_temp_sens;
-
- u0 : component qsys_arts_unb2b_sc3_reg_fpga_temp_sens
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.vhd
deleted file mode 100644
index 668d0654837360b632e9470c34aae6d12a6995f1..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_fpga_temp_sens.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_fpga_temp_sens is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_fpga_temp_sens;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_fpga_temp_sens is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_fpga_temp_sens : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_fpga_temp_sens : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_fpga_temp_sens
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip
index a5994fb1ec1fe3889b18c03b95d7237ce85b74cd..08a6b2a7d0d03d4bed22026a742ac549c4b1aec1 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +905,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +974,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1369,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.bsf
deleted file mode 100644
index 46aed93a0121c925e7866fb34959fe31cfef3bd8..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" (rect 38 -1 230 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_fpga_voltage_sens " (rect 145 512 548 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.cmp
deleted file mode 100644
index 27852daedd912a3eeef21f6c256d00b8a11a1585..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_fpga_voltage_sens is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_fpga_voltage_sens;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.html
deleted file mode 100644
index 0771a2bba16c5ff977d67865c8a475c9a3e1a065..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:40:20</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"><b>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"><b>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.qgsynthc
deleted file mode 100644
index 7abaaedc6990179fbb900dcaf0572bc43c245901..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.qip
deleted file mode 100644
index f2c610e8bcb4813f5c45c581c86962e6e06026a0..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_fpga_voltage_sens HAS_SOPCINFO 1 GENERATION_ID 1527684018"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfZnBnYV92b2x0YWdlX3NlbnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDAxOA==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.sopcinfo
deleted file mode 100644
index bd8e9c628b2262d98a7804de0949c84bf53daf73..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"
- kind="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:40:18 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684018</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.xml
deleted file mode 100644
index 27ac07f34f95656a75a94c0804cf46b172a16255..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:40:20"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684018" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens">"Generating: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"
- as="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_fpga_voltage_sens">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_bb.v
deleted file mode 100644
index c74d7fbd73c6b54d24b844b9a9e66b2b3c60cc32..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_fpga_voltage_sens (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_generation.rpt
deleted file mode 100644
index e54a146992606f1f5b4f2ba8ae2a15904f6bb4fb..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: "Transforming system: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: "Naming system components in system: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: "Generating: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens"
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_fpga_voltage_sens: Done "qsys_arts_unb2b_sc3_reg_fpga_voltage_sens" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_fpga_voltage_sens. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_inst.v
deleted file mode 100644
index e971c525ee2e5e0cc47187a39ff4fcb303ffbf7d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_fpga_voltage_sens u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_inst.vhd
deleted file mode 100644
index 8bf16e25dcd104aab636bf53ceef82334587d792..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_fpga_voltage_sens is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_fpga_voltage_sens;
-
- u0 : component qsys_arts_unb2b_sc3_reg_fpga_voltage_sens
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.vhd
deleted file mode 100644
index 07bcbfa155a216196de4c48d09a4a79e6cfcb9fd..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens/synth/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_fpga_voltage_sens is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_fpga_voltage_sens;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_fpga_voltage_sens is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_fpga_voltage_sens : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_fpga_voltage_sens : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_fpga_voltage_sens
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
index 1a0c181d9362a3df7ee42949217fb7a6f8c1c3ed..28a252ba3786f6d4062f656bacfa80582aa5a814 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip
@@ -137,7 +137,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">131072</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -647,7 +647,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>14</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -755,7 +755,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>14</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -847,7 +847,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">15</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -905,7 +905,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -969,7 +969,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>15</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1046,7 +1046,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>131072</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1473,11 +1473,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>17</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd
deleted file mode 100644
index a88010137b64a7aa30985bb6814e8be7ffa69a0c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: Same function as avs_common_mm.vhd, but with the read latency set
--- to 0 instead of 1 in the hardware description TCL file.
--- Description:
--- The avs_common_mm_readlatency0_hw.tcl determines the read latency. This
--- component wraps the default avs_common_mm which has readlatency 1 in its
--- avs_common_mm_hw.tcl.
--- Read latency 0 implies that the MM bus needs to use the waitrequest signal.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm_readlatency0 IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_waitrequest : OUT STD_LOGIC;
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_waitrequest_export : IN STD_LOGIC := '0'
- );
-END avs_common_mm_readlatency0;
-
-
-ARCHITECTURE wrap OF avs_common_mm_readlatency0 IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
- avs_mem_waitrequest <= coe_waitrequest_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.bsf
deleted file mode 100644
index 9d82f310c5666f648ac74754d0114c02100ab6c5..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.bsf
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 400 584)
- (text "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" (rect 13 -1 274 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 568 20 580)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 312)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 301 160 312)(font "Arial" (font_size 8)))
- (line (pt 0 312)(pt 144 312)(line_width 3))
- )
- (port
- (pt 0 392)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 381 88 392)(font "Arial" (font_size 8)))
- (line (pt 0 392)(pt 144 392)(line_width 1))
- )
- (port
- (pt 0 432)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 421 100 432)(font "Arial" (font_size 8)))
- (line (pt 0 432)(pt 144 432)(line_width 1))
- )
- (port
- (pt 0 472)
- (input)
- (text "coe_waitrequest_export" (rect 0 0 94 12)(font "Arial" (font_size 8)))
- (text "coe_waitrequest_export" (rect 4 461 136 472)(font "Arial" (font_size 8)))
- (line (pt 0 472)(pt 144 472)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 232)
- (output)
- (text "avs_mem_waitrequest" (rect 0 0 92 12)(font "Arial" (font_size 8)))
- (text "avs_mem_waitrequest" (rect 4 221 118 232)(font "Arial" (font_size 8)))
- (line (pt 0 232)(pt 144 232)(line_width 1))
- )
- (port
- (pt 0 272)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 261 94 272)(font "Arial" (font_size 8)))
- (line (pt 0 272)(pt 144 272)(line_width 1))
- )
- (port
- (pt 0 352)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 341 100 352)(font "Arial" (font_size 8)))
- (line (pt 0 352)(pt 144 352)(line_width 1))
- )
- (port
- (pt 0 512)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 501 100 512)(font "Arial" (font_size 8)))
- (line (pt 0 512)(pt 144 512)(line_width 1))
- )
- (port
- (pt 0 552)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 541 166 552)(font "Arial" (font_size 8)))
- (line (pt 0 552)(pt 144 552)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "waitrequest" (rect 149 227 364 464)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 243 262 499)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 267 334 544)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 283 236 579)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 307 334 624)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 323 260 659)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 347 334 704)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 363 242 739)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 387 316 784)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 403 202 819)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 427 328 864)(font "Arial" (color 0 0 0)))
- (text "waitrequest" (rect 77 443 220 899)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 467 334 944)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 483 262 979)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 507 334 1024)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 523 236 1059)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 547 334 1104)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 " (rect 71 568 490 1146)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 568)(line_width 1))
- (line (pt 144 568)(pt 208 568)(line_width 1))
- (line (pt 144 32)(pt 144 568)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 236)(line_width 1))
- (line (pt 146 132)(pt 146 236)(line_width 1))
- (line (pt 145 252)(pt 145 276)(line_width 1))
- (line (pt 146 252)(pt 146 276)(line_width 1))
- (line (pt 145 292)(pt 145 316)(line_width 1))
- (line (pt 146 292)(pt 146 316)(line_width 1))
- (line (pt 145 332)(pt 145 356)(line_width 1))
- (line (pt 146 332)(pt 146 356)(line_width 1))
- (line (pt 145 372)(pt 145 396)(line_width 1))
- (line (pt 146 372)(pt 146 396)(line_width 1))
- (line (pt 145 412)(pt 145 436)(line_width 1))
- (line (pt 146 412)(pt 146 436)(line_width 1))
- (line (pt 145 452)(pt 145 476)(line_width 1))
- (line (pt 146 452)(pt 146 476)(line_width 1))
- (line (pt 145 492)(pt 145 516)(line_width 1))
- (line (pt 146 492)(pt 146 516)(line_width 1))
- (line (pt 145 532)(pt 145 556)(line_width 1))
- (line (pt 146 532)(pt 146 556)(line_width 1))
- (line (pt 0 0)(pt 401 0)(line_width 1))
- (line (pt 401 0)(pt 401 584)(line_width 1))
- (line (pt 0 584)(pt 401 584)(line_width 1))
- (line (pt 0 0)(pt 0 584)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.cmp
deleted file mode 100644
index 127e38103c32f4fcc12e162e8a136b0073e90867..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.cmp
+++ /dev/null
@@ -1,21 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- avs_mem_waitrequest : out std_logic; -- waitrequest
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_waitrequest_export : in std_logic := 'X'; -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.html
deleted file mode 100644
index 00dba26d69dc6cc9752e2c1686e45d0e60dcbd0e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.html
+++ /dev/null
@@ -1,160 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:42:44</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a
- href="#module_qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"><b>qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</b>
- </a> avs_common_mm_readlatency0 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a
- href="#module_qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"><b>qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a
- name="module_qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</h2>avs_common_mm_readlatency0 v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 2.06 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.qgsynthc
deleted file mode 100644
index 5712ea5b4aaab415958b7c5c70cd1972794251a1..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm_readlatency0</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</name>
- <uniqueName>avs_common_mm_readlatency0</uniqueName>
- <fixedName>avs_common_mm_readlatency0</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.qip
deleted file mode 100644
index 11b5feeae193a0e048f704a493fd19c4d89871df..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 HAS_SOPCINFO 1 GENERATION_ID 1527684164"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip"]
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbV9yZWFkbGF0ZW5jeTA="
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbV9yZWFkbGF0ZW5jeTA="
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggd2FpdHJlcXVlc3QsIHNvIHJlYWQgbGF0ZW5jeSAw"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfaXBfYXJyaWExMF9lMXNnX3BoeV8xMGdiYXNlX3JfMjQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDE2NA==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_readlatency0_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.sopcinfo
deleted file mode 100644
index 15a31f962c3f850903630b9d91da81dd6033fa64..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.sopcinfo
+++ /dev/null
@@ -1,1123 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"
- kind="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:42:44 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684164</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"
- kind="avs_common_mm_readlatency0"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- <port>
- <name>avs_mem_waitrequest</name>
- <direction>Output</direction>
- <width>1</width>
- <role>waitrequest</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="waitrequest" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_waitrequest_export</name>
- <direction>Input</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm_readlatency0</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm_readlatency0</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>8</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.xml
deleted file mode 100644
index 6a0d761776f6e80f4d691c0e3b1af1d6cae2c0ab..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.xml
+++ /dev/null
@@ -1,249 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:42:46"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="0" />
- <property name="readWaitStates" value="1" />
- <property name="readWaitTime" value="1" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- <port
- name="avs_mem_waitrequest"
- direction="output"
- role="waitrequest"
- width="1" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="waitrequest" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_waitrequest_export"
- direction="input"
- role="export"
- width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684164" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/synth/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/synth/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0.vhd" />
- </childSourceFiles>
- <messages>
- <message
- level="Info"
- culprit="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24">"Generating: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"</message>
- <message
- level="Info"
- culprit="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24">"Generating: avs_common_mm_readlatency0"</message>
- </messages>
- </entity>
- <entity
- kind="avs_common_mm_readlatency0"
- version="1.0"
- name="avs_common_mm_readlatency0">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"
- as="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" />
- <messages>
- <message
- level="Info"
- culprit="qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24">"Generating: avs_common_mm_readlatency0"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_bb.v
deleted file mode 100644
index 6c3930dee083d93c04e2f8157e6beefe870b76d3..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_bb.v
+++ /dev/null
@@ -1,36 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- avs_mem_waitrequest,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_waitrequest_export,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output avs_mem_waitrequest;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- input coe_waitrequest_export;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_generation.rpt
deleted file mode 100644
index 5971870e7fe195242f594c3010c1a0e897db9513..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: "Transforming system: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: Running transform interconnect_transform_chooser took 0.011s
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: "Naming system components in system: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: "Generating: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24"
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: "Generating: avs_common_mm_readlatency0"
-Info: qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24: Done "qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_inst.v
deleted file mode 100644
index d6d594057280e76fef3c399f5730ee2790caf8e1..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_inst.v
+++ /dev/null
@@ -1,19 +0,0 @@
- qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .avs_mem_waitrequest (_connected_to_avs_mem_waitrequest_), // .waitrequest
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_waitrequest_export (_connected_to_coe_waitrequest_export_), // waitrequest.export
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_inst.vhd
deleted file mode 100644
index 4adc4ae1b91a2314aa1835a372357213c0954db2..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24_inst.vhd
+++ /dev/null
@@ -1,41 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- avs_mem_waitrequest : out std_logic; -- waitrequest
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_waitrequest_export : in std_logic := 'X'; -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24;
-
- u0 : component qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- avs_mem_waitrequest => CONNECTED_TO_avs_mem_waitrequest, -- .waitrequest
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_waitrequest_export => CONNECTED_TO_coe_waitrequest_export, -- waitrequest.export
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/synth/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/synth/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.vhd
deleted file mode 100644
index 74ab54b2dcff0da98e1685a0a09714cb9e2b57af..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24/synth/qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.vhd
+++ /dev/null
@@ -1,85 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_readlatency0_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- avs_mem_waitrequest : out std_logic; -- .waitrequest
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_waitrequest_export : in std_logic := '0'; -- waitrequest.export
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 is
- component avs_common_mm_readlatency0_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- avs_mem_waitrequest : out std_logic; -- waitrequest
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_waitrequest_export : in std_logic := 'X' -- export
- );
- end component avs_common_mm_readlatency0_cmp;
-
- for qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 : avs_common_mm_readlatency0_cmp
- use entity avs_common_mm_readlatency0_10.avs_common_mm_readlatency0;
-begin
-
- qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24 : component avs_common_mm_readlatency0_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- avs_mem_waitrequest => avs_mem_waitrequest, -- .waitrequest
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export, -- readdata.export
- coe_waitrequest_export => coe_waitrequest_export -- waitrequest.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_ip_arria10_e1sg_phy_10gbase_r_24
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip
index e322db698777756dbca15cfa3f2f5013a1a59ebd..62b15a9f5488d0fc3a2019a75b37d2732752a23f 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,10 +605,6 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -701,10 +697,6 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -783,7 +775,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +833,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +897,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +966,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1361,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.bsf
deleted file mode 100644
index d15ea3def26770358b225b8ace77035facd0689a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" (rect 62 -1 221 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_mmdp_ctrl " (rect 181 512 572 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.cmp
deleted file mode 100644
index eae41987a3098caf80290cd96a038b3f66103eef..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_mmdp_ctrl is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_mmdp_ctrl;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.html
deleted file mode 100644
index 67126c3518062bbde2de006cc6f9c06955b5dd63..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_mmdp_ctrl</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_mmdp_ctrl</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:43:48</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_mmdp_ctrl"><b>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_mmdp_ctrl"><b>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_mmdp_ctrl"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.qgsynthc
deleted file mode 100644
index 621fa6a5c5dd9aa0e62d922c4ffe3d7c10927f20..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_mmdp_ctrl</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_mmdp_ctrl</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_mmdp_ctrl.qsys_arts_unb2b_sc3_reg_mmdp_ctrl</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.qip
deleted file mode 100644
index 95b86a60afba7127d5799716070af6a62ecbd546..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_mmdp_ctrl.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_mmdp_ctrl HAS_SOPCINFO 1 GENERATION_ID 1527684225"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_mmdp_ctrl.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfbW1kcF9jdHJs"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDIyNQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.sopcinfo
deleted file mode 100644
index 7e91e53ff328b6a31a508094c0c98c8f63588a2c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_mmdp_ctrl"
- kind="qsys_arts_unb2b_sc3_reg_mmdp_ctrl"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:43:46 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684225</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_mmdp_ctrl"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_mmdp_ctrl">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.xml
deleted file mode 100644
index ac188cf71721b825a04086799d784da58f7ece5b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:43:48"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_mmdp_ctrl"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_mmdp_ctrl">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684225" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/synth/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/synth/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_mmdp_ctrl">"Generating: qsys_arts_unb2b_sc3_reg_mmdp_ctrl"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_mmdp_ctrl">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_mmdp_ctrl"
- as="qsys_arts_unb2b_sc3_reg_mmdp_ctrl" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_mmdp_ctrl">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_bb.v
deleted file mode 100644
index 4db3a32afbdb0a4687651980080602a3b2cb06ac..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_mmdp_ctrl (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_generation.rpt
deleted file mode 100644
index 3f2e0f83f2fae5d4de77ddfa3345d1b0e9cfaf89..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: "Transforming system: qsys_arts_unb2b_sc3_reg_mmdp_ctrl"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: "Naming system components in system: qsys_arts_unb2b_sc3_reg_mmdp_ctrl"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: "Generating: qsys_arts_unb2b_sc3_reg_mmdp_ctrl"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_ctrl: Done "qsys_arts_unb2b_sc3_reg_mmdp_ctrl" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_mmdp_ctrl. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_inst.v
deleted file mode 100644
index 9f5723ecd5942119776e566a9d716abc650a876c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_mmdp_ctrl u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_inst.vhd
deleted file mode 100644
index b5280a86914b4a8ae7f7fad925d167871efad14f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_mmdp_ctrl is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_mmdp_ctrl;
-
- u0 : component qsys_arts_unb2b_sc3_reg_mmdp_ctrl
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/synth/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/synth/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.vhd
deleted file mode 100644
index 29adfc180fc7e5c12f4e2c06f5ce3581f9c796e6..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl/synth/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_mmdp_ctrl.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_mmdp_ctrl is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_mmdp_ctrl;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_mmdp_ctrl is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_mmdp_ctrl : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_mmdp_ctrl : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_mmdp_ctrl
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data.ip
index 43bbe7dd189652a0ed2736a54f5a7a95493d1c6f..3bae013e20bb5f9d748b5288eefb779d8cd34f6f 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,10 +605,6 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -701,10 +697,6 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -783,7 +775,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +833,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +897,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +966,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1361,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.bsf
deleted file mode 100644
index b316a1a164765112e0d74be1e3deb496bc66f83b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_mmdp_data" (rect 59 -1 223 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_mmdp_data " (rect 177 512 564 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.cmp
deleted file mode 100644
index 62d7f2d6e8bd39971375aa1051990aea9ca2cd9b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_mmdp_data is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_mmdp_data;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.html
deleted file mode 100644
index 49acb4fe6fb49d3882a8d5331b282e398b532f46..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_mmdp_data</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_mmdp_data</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:37:43</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_mmdp_data"><b>qsys_arts_unb2b_sc3_reg_mmdp_data</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_mmdp_data"><b>qsys_arts_unb2b_sc3_reg_mmdp_data</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_mmdp_data"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_mmdp_data</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.qgsynthc
deleted file mode 100644
index e855f81edbfc007f995e62cd0720ee794881d71f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_mmdp_data</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_mmdp_data</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_mmdp_data</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_mmdp_data</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_mmdp_data</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_mmdp_data</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_mmdp_data.qsys_arts_unb2b_sc3_reg_mmdp_data</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.qip
deleted file mode 100644
index e17613b460f83e3bfb3c36cf79f6af0000767e84..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_mmdp_data.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_mmdp_data HAS_SOPCINFO 1 GENERATION_ID 1527683861"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_mmdp_data.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_mmdp_data.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfbW1kcF9kYXRh"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4Mzg2MQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_mmdp_data" -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_mmdp_data" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_mmdp_data.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.sopcinfo
deleted file mode 100644
index 0afa015ab4a056a3b7fbf3f81dfe3f16b63db459..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_mmdp_data"
- kind="qsys_arts_unb2b_sc3_reg_mmdp_data"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:37:43 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527683861</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_mmdp_data"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_mmdp_data">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.xml
deleted file mode 100644
index 32f872cf08f2c9e03a6290bb6422a9305c30e6fa..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:37:43"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_mmdp_data"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_mmdp_data">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527683861" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/synth/qsys_arts_unb2b_sc3_reg_mmdp_data.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/synth/qsys_arts_unb2b_sc3_reg_mmdp_data.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_mmdp_data">"Generating: qsys_arts_unb2b_sc3_reg_mmdp_data"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_mmdp_data">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_mmdp_data"
- as="qsys_arts_unb2b_sc3_reg_mmdp_data" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_mmdp_data">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_bb.v
deleted file mode 100644
index dcb066cac450b2de9aaf218d5039717cfea0655e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_mmdp_data (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_generation.rpt
deleted file mode 100644
index d20adf5775ed51df85118a89bfd3106f2824852d..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: "Transforming system: qsys_arts_unb2b_sc3_reg_mmdp_data"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: "Naming system components in system: qsys_arts_unb2b_sc3_reg_mmdp_data"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: "Generating: qsys_arts_unb2b_sc3_reg_mmdp_data"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_mmdp_data: Done "qsys_arts_unb2b_sc3_reg_mmdp_data" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_mmdp_data. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_inst.v
deleted file mode 100644
index 032fe0ed924251d1a9aad596dbd3f61645e26c54..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_mmdp_data u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_inst.vhd
deleted file mode 100644
index b87c4f2d280e598c6b2fbb24d1f9fcaf056b27be..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/qsys_arts_unb2b_sc3_reg_mmdp_data_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_mmdp_data is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_mmdp_data;
-
- u0 : component qsys_arts_unb2b_sc3_reg_mmdp_data
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/synth/qsys_arts_unb2b_sc3_reg_mmdp_data.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/synth/qsys_arts_unb2b_sc3_reg_mmdp_data.vhd
deleted file mode 100644
index 12246edc7c08e1d4e9c4eccbc683d04ee038d4f3..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data/synth/qsys_arts_unb2b_sc3_reg_mmdp_data.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_mmdp_data.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_mmdp_data is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_mmdp_data;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_mmdp_data is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_mmdp_data : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_mmdp_data : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_mmdp_data
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu.ip
index b8d09d8adf3120c8557ea47d60b2873e86323049..6301ed4e693fc3d49853ef8804f81109f84ba366 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">32</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>2</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>2</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">3</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +905,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +974,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1369,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.bsf
deleted file mode 100644
index 8f4f49dff75bbba2c55d7eb2e4a2b17f5566cdbe..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_remu" (rect 79 -1 215 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_remu " (rect 205 512 590 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.cmp
deleted file mode 100644
index d72e516736f3cca872c53e1f33ef7831bc975f37..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_remu is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_remu;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.html
deleted file mode 100644
index b435a112826421cc3c8bcdd8b45821f9ee60c57e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_remu</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_remu</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:40:58</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_remu"><b>qsys_arts_unb2b_sc3_reg_remu</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_remu"><b>qsys_arts_unb2b_sc3_reg_remu</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_remu"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_remu</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.qgsynthc
deleted file mode 100644
index 5fc82147f2e84efe9171d61612511ecf2328cfcb..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_remu</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_remu</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_remu</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_remu</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_remu</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_remu</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_remu.qsys_arts_unb2b_sc3_reg_remu</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.qip
deleted file mode 100644
index 3076449db83b0293bb5f7d440c321ad5da942b6e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_remu" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_remu.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_remu HAS_SOPCINFO 1 GENERATION_ID 1527684058"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_remu" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_remu.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_remu" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_remu.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfcmVtdQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDA1OA==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_remu" -library "qsys_arts_unb2b_sc3_reg_remu" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_remu" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_remu.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.sopcinfo
deleted file mode 100644
index f0fd95f37a053261492d4839289a76f496a306e5..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_remu"
- kind="qsys_arts_unb2b_sc3_reg_remu"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:40:58 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684058</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_remu"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_remu">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.xml
deleted file mode 100644
index eec8fe0286905aaca3c1c8e36e53a439ee621f5a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:40:58"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_remu"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_remu">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684058" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/synth/qsys_arts_unb2b_sc3_reg_remu.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/synth/qsys_arts_unb2b_sc3_reg_remu.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_remu">"Generating: qsys_arts_unb2b_sc3_reg_remu"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_remu">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_remu"
- as="qsys_arts_unb2b_sc3_reg_remu" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_remu">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_bb.v
deleted file mode 100644
index 8506c8ab5f22d37adebeb70521475b7f537250a4..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_remu (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_generation.rpt
deleted file mode 100644
index baae9da71d294135a5d39709f85b0226ed7317dc..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_remu: "Transforming system: qsys_arts_unb2b_sc3_reg_remu"
-Info: qsys_arts_unb2b_sc3_reg_remu: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_remu: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_remu: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_remu: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_remu: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_remu: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_reg_remu: "Naming system components in system: qsys_arts_unb2b_sc3_reg_remu"
-Info: qsys_arts_unb2b_sc3_reg_remu: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_remu: "Generating: qsys_arts_unb2b_sc3_reg_remu"
-Info: qsys_arts_unb2b_sc3_reg_remu: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_remu: Done "qsys_arts_unb2b_sc3_reg_remu" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_remu. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_inst.v
deleted file mode 100644
index 9b6e2f3698d79fbfba0f3caf4bd3527cff288e2e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_remu u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_inst.vhd
deleted file mode 100644
index ef0c6361a48a4f8d435f90e67002cfd332a607e3..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/qsys_arts_unb2b_sc3_reg_remu_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_remu is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_remu;
-
- u0 : component qsys_arts_unb2b_sc3_reg_remu
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/synth/qsys_arts_unb2b_sc3_reg_remu.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/synth/qsys_arts_unb2b_sc3_reg_remu.vhd
deleted file mode 100644
index f362129230f2789fb9e1f4e679a1e8cba1860d45..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu/synth/qsys_arts_unb2b_sc3_reg_remu.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_remu.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_remu is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_remu;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_remu is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_remu : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_remu : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_remu
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.ip
index 56459e69f4482a02fcfb94a6210a0db2b53a0538..f380389b6086ba81369b96c8305bef906f11a129 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.ip
@@ -137,7 +137,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">2097152</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -647,7 +647,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>18</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -755,7 +755,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>18</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -847,7 +847,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">19</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -905,7 +905,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>19</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -969,7 +969,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>19</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -1046,7 +1046,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>2097152</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1473,11 +1473,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x200000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>21</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd
deleted file mode 100644
index a88010137b64a7aa30985bb6814e8be7ffa69a0c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: Same function as avs_common_mm.vhd, but with the read latency set
--- to 0 instead of 1 in the hardware description TCL file.
--- Description:
--- The avs_common_mm_readlatency0_hw.tcl determines the read latency. This
--- component wraps the default avs_common_mm which has readlatency 1 in its
--- avs_common_mm_hw.tcl.
--- Read latency 0 implies that the MM bus needs to use the waitrequest signal.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm_readlatency0 IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_waitrequest : OUT STD_LOGIC;
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_waitrequest_export : IN STD_LOGIC := '0'
- );
-END avs_common_mm_readlatency0;
-
-
-ARCHITECTURE wrap OF avs_common_mm_readlatency0 IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
- avs_mem_waitrequest <= coe_waitrequest_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.bsf
deleted file mode 100644
index 9cd0be95e10f36f9b883d8869edefa96c7597c7c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.bsf
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 584)
- (text "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" (rect 34 -1 232 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 568 20 580)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 312)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 301 160 312)(font "Arial" (font_size 8)))
- (line (pt 0 312)(pt 144 312)(line_width 3))
- )
- (port
- (pt 0 392)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 381 88 392)(font "Arial" (font_size 8)))
- (line (pt 0 392)(pt 144 392)(line_width 1))
- )
- (port
- (pt 0 432)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 421 100 432)(font "Arial" (font_size 8)))
- (line (pt 0 432)(pt 144 432)(line_width 1))
- )
- (port
- (pt 0 472)
- (input)
- (text "coe_waitrequest_export" (rect 0 0 94 12)(font "Arial" (font_size 8)))
- (text "coe_waitrequest_export" (rect 4 461 136 472)(font "Arial" (font_size 8)))
- (line (pt 0 472)(pt 144 472)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 232)
- (output)
- (text "avs_mem_waitrequest" (rect 0 0 92 12)(font "Arial" (font_size 8)))
- (text "avs_mem_waitrequest" (rect 4 221 118 232)(font "Arial" (font_size 8)))
- (line (pt 0 232)(pt 144 232)(line_width 1))
- )
- (port
- (pt 0 272)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 261 94 272)(font "Arial" (font_size 8)))
- (line (pt 0 272)(pt 144 272)(line_width 1))
- )
- (port
- (pt 0 352)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 341 100 352)(font "Arial" (font_size 8)))
- (line (pt 0 352)(pt 144 352)(line_width 1))
- )
- (port
- (pt 0 512)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 501 100 512)(font "Arial" (font_size 8)))
- (line (pt 0 512)(pt 144 512)(line_width 1))
- )
- (port
- (pt 0 552)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 541 166 552)(font "Arial" (font_size 8)))
- (line (pt 0 552)(pt 144 552)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "waitrequest" (rect 149 227 364 464)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 243 262 499)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 267 334 544)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 283 236 579)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 307 334 624)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 323 260 659)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 347 334 704)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 363 242 739)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 387 316 784)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 403 202 819)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 427 328 864)(font "Arial" (color 0 0 0)))
- (text "waitrequest" (rect 77 443 220 899)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 467 334 944)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 483 262 979)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 507 334 1024)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 523 236 1059)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 547 334 1104)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring " (rect 139 568 542 1146)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 568)(line_width 1))
- (line (pt 144 568)(pt 208 568)(line_width 1))
- (line (pt 144 32)(pt 144 568)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 236)(line_width 1))
- (line (pt 146 132)(pt 146 236)(line_width 1))
- (line (pt 145 252)(pt 145 276)(line_width 1))
- (line (pt 146 252)(pt 146 276)(line_width 1))
- (line (pt 145 292)(pt 145 316)(line_width 1))
- (line (pt 146 292)(pt 146 316)(line_width 1))
- (line (pt 145 332)(pt 145 356)(line_width 1))
- (line (pt 146 332)(pt 146 356)(line_width 1))
- (line (pt 145 372)(pt 145 396)(line_width 1))
- (line (pt 146 372)(pt 146 396)(line_width 1))
- (line (pt 145 412)(pt 145 436)(line_width 1))
- (line (pt 146 412)(pt 146 436)(line_width 1))
- (line (pt 145 452)(pt 145 476)(line_width 1))
- (line (pt 146 452)(pt 146 476)(line_width 1))
- (line (pt 145 492)(pt 145 516)(line_width 1))
- (line (pt 146 492)(pt 146 516)(line_width 1))
- (line (pt 145 532)(pt 145 556)(line_width 1))
- (line (pt 146 532)(pt 146 556)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 584)(line_width 1))
- (line (pt 0 584)(pt 352 584)(line_width 1))
- (line (pt 0 0)(pt 0 584)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.cmp
deleted file mode 100644
index fcaeabe78700e5abf36ea03c8157e041e497ac34..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.cmp
+++ /dev/null
@@ -1,21 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- avs_mem_waitrequest : out std_logic; -- waitrequest
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_waitrequest_export : in std_logic := 'X'; -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.html
deleted file mode 100644
index 36bc536521e5362b0517919c9cdc325dade4ac69..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:41:36</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"><b>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</b>
- </a> avs_common_mm_readlatency0 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"><b>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</h2>avs_common_mm_readlatency0 v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.qgsynthc
deleted file mode 100644
index 2e57923fe4dd3c86f1164e04df8be0072a1d2961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm_readlatency0</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</name>
- <uniqueName>avs_common_mm_readlatency0</uniqueName>
- <fixedName>avs_common_mm_readlatency0</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.qip
deleted file mode 100644
index 66d5db57b193eaa3a1b3c9717e9ee9e0885692d4..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring HAS_SOPCINFO 1 GENERATION_ID 1527684094"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.ip"]
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbV9yZWFkbGF0ZW5jeTA="
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbV9yZWFkbGF0ZW5jeTA="
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggd2FpdHJlcXVlc3QsIHNvIHJlYWQgbGF0ZW5jeSAw"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm_readlatency0" -library "avs_common_mm_readlatency0_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfdHJfMTBHYkVfcXNmcF9yaW5n"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDA5NA==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_readlatency0_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.sopcinfo
deleted file mode 100644
index 47e0a30e0032ada2528689c90960807597d29beb..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.sopcinfo
+++ /dev/null
@@ -1,1123 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"
- kind="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:41:34 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684094</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"
- kind="avs_common_mm_readlatency0"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- <port>
- <name>avs_mem_waitrequest</name>
- <direction>Output</direction>
- <width>1</width>
- <role>waitrequest</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="waitrequest" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_waitrequest_export</name>
- <direction>Input</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm_readlatency0</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm_readlatency0</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>8</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.xml
deleted file mode 100644
index 254ceb32770a1d2e7fadad9eb7a6dd124ab2d72a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.xml
+++ /dev/null
@@ -1,243 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:41:36"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="0" />
- <property name="readWaitStates" value="1" />
- <property name="readWaitTime" value="1" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- <port
- name="avs_mem_waitrequest"
- direction="output"
- role="waitrequest"
- width="1" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="waitrequest" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_waitrequest_export"
- direction="input"
- role="export"
- width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684094" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring">"Generating: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring">"Generating: avs_common_mm_readlatency0"</message>
- </messages>
- </entity>
- <entity
- kind="avs_common_mm_readlatency0"
- version="1.0"
- name="avs_common_mm_readlatency0">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/avs_common_mm_readlatency0_10/synth/avs_common_mm_readlatency0.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_readlatency0.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"
- as="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring">"Generating: avs_common_mm_readlatency0"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_bb.v
deleted file mode 100644
index 7849fa67336ca20c0e40db346e71bc55913d3410..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_bb.v
+++ /dev/null
@@ -1,36 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- avs_mem_waitrequest,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_waitrequest_export,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output avs_mem_waitrequest;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- input coe_waitrequest_export;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_generation.rpt
deleted file mode 100644
index c8db95f6e8bab0159747af0935e68644f0fb282a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: "Transforming system: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: "Naming system components in system: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: "Generating: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring"
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: "Generating: avs_common_mm_readlatency0"
-Info: qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring: Done "qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_inst.v
deleted file mode 100644
index 2801019dfa053b36be9fbc353ca6fdd947e0e080..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_inst.v
+++ /dev/null
@@ -1,19 +0,0 @@
- qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .avs_mem_waitrequest (_connected_to_avs_mem_waitrequest_), // .waitrequest
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_waitrequest_export (_connected_to_coe_waitrequest_export_), // waitrequest.export
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_inst.vhd
deleted file mode 100644
index e542d50860f84bd1c123e06d51e6d044122c2729..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_inst.vhd
+++ /dev/null
@@ -1,41 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- avs_mem_waitrequest : out std_logic; -- waitrequest
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_waitrequest_export : in std_logic := 'X'; -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring;
-
- u0 : component qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- avs_mem_waitrequest => CONNECTED_TO_avs_mem_waitrequest, -- .waitrequest
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_waitrequest_export => CONNECTED_TO_coe_waitrequest_export, -- waitrequest.export
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.vhd
deleted file mode 100644
index d043727e1f37b3733cfa99fbe2c6b3b9d6c0846b..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring/synth/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.vhd
+++ /dev/null
@@ -1,85 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_readlatency0_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- avs_mem_waitrequest : out std_logic; -- .waitrequest
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_waitrequest_export : in std_logic := '0'; -- waitrequest.export
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring is
- component avs_common_mm_readlatency0_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- avs_mem_waitrequest : out std_logic; -- waitrequest
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_waitrequest_export : in std_logic := 'X' -- export
- );
- end component avs_common_mm_readlatency0_cmp;
-
- for qsys_arts_unb2b_sc3_reg_tr_10gbe_qsfp_ring : avs_common_mm_readlatency0_cmp
- use entity avs_common_mm_readlatency0_10.avs_common_mm_readlatency0;
-begin
-
- qsys_arts_unb2b_sc3_reg_tr_10gbe_qsfp_ring : component avs_common_mm_readlatency0_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- avs_mem_waitrequest => avs_mem_waitrequest, -- .waitrequest
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export, -- readdata.export
- coe_waitrequest_export => coe_waitrequest_export -- waitrequest.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_pmbus.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_pmbus.ip
index 1ff04a6938a54e6a08bf928e61032d57f2aa787f..b35fe73a3c9196216f4f405a1766f3af6f7b093c 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_pmbus.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_pmbus.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>5</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>5</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -793,7 +793,7 @@
<spirit:parameter>
<spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
<spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">125000000</spirit:value>
</spirit:parameter>
</spirit:parameters>
</altera:altera_module_parameters>
@@ -841,7 +841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +905,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +974,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1369,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -1389,7 +1389,7 @@
<suppliedSystemInfos>
<entry>
<key>CLOCK_RATE</key>
- <value>-1</value>
+ <value>125000000</value>
</entry>
</suppliedSystemInfos>
<consumedSystemInfos/>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip
index 474c4078bcc35bb6010d04135091f8be2e39fce6..a4310820ab25f538fcc90a3f3d50de6c1972fe66 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">256</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>5</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>5</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">6</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +905,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>6</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +974,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>256</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1369,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>8</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.bsf
deleted file mode 100644
index 6b05419a847d1a69e4ee09efeeacfc7d8dc3f916..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_unb_sens" (rect 65 -1 219 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_unb_sens " (rect 186 512 576 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.cmp
deleted file mode 100644
index 2f6b0630df59dc51d4b530b637cdfb55d2647df1..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_unb_sens is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_unb_sens;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.html
deleted file mode 100644
index a86b98f88efb918ed480f026248019c12bccf5cd..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_unb_sens</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_unb_sens</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:40:01</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_unb_sens"><b>qsys_arts_unb2b_sc3_reg_unb_sens</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_unb_sens"><b>qsys_arts_unb2b_sc3_reg_unb_sens</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_unb_sens"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_unb_sens</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.qgsynthc
deleted file mode 100644
index 6dce0030f6b9bb180117e0f6c1eb02bdaba0f342..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_unb_sens</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_unb_sens</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_unb_sens</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_unb_sens</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_unb_sens</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_unb_sens</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_unb_sens.qsys_arts_unb2b_sc3_reg_unb_sens</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.qip
deleted file mode 100644
index 561d0ada23fb32e629dcb17746ef8aa20e5436df..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_unb_sens.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_unb_sens HAS_SOPCINFO 1 GENERATION_ID 1527683999"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_unb_sens.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_unb_sens.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfdW5iX3NlbnM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4Mzk5OQ==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_unb_sens" -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_unb_sens" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_unb_sens.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.sopcinfo
deleted file mode 100644
index fcc2d1fa305fda2c7dc4399451a4d7f21e1f8c48..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_unb_sens"
- kind="qsys_arts_unb2b_sc3_reg_unb_sens"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:39:59 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527683999</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_unb_sens"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_unb_sens">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.xml
deleted file mode 100644
index f855ad5027ef2ed1fd3fc803f9e843858263241f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:40:01"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_unb_sens"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_unb_sens">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527683999" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/synth/qsys_arts_unb2b_sc3_reg_unb_sens.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/synth/qsys_arts_unb2b_sc3_reg_unb_sens.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_unb_sens">"Generating: qsys_arts_unb2b_sc3_reg_unb_sens"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_unb_sens">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_unb_sens"
- as="qsys_arts_unb2b_sc3_reg_unb_sens" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_unb_sens">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_bb.v
deleted file mode 100644
index 73f501e6f4f4bd1a99191c468b00bb29a60f2f77..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_unb_sens (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_generation.rpt
deleted file mode 100644
index 32c96d88411c85d7cdee5d61aae51efb21ac5e21..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_generation.rpt
+++ /dev/null
@@ -1,14 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens --family="Arria 10" --part=10AX115U2F45E1SG
-Info: Skipping generation of qsys_arts_unb2b_sc3_reg_unb_sens: files already generated.
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_unb_sens. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_generation_previous.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_generation_previous.rpt
deleted file mode 100644
index 2b6f5c2abd83e998147505d31c9e42d238d6b97a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_generation_previous.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: "Transforming system: qsys_arts_unb2b_sc3_reg_unb_sens"
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: Running transform interconnect_transform_chooser took 0.009s
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: "Naming system components in system: qsys_arts_unb2b_sc3_reg_unb_sens"
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: "Generating: qsys_arts_unb2b_sc3_reg_unb_sens"
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_unb_sens: Done "qsys_arts_unb2b_sc3_reg_unb_sens" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_unb_sens. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_inst.v
deleted file mode 100644
index 4068d4c9d96576faa3e66f556d7e18a9e30ab7fa..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_unb_sens u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_inst.vhd
deleted file mode 100644
index bc65742e81f1c59d918e931717974c3278c3b688..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/qsys_arts_unb2b_sc3_reg_unb_sens_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_unb_sens is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_unb_sens;
-
- u0 : component qsys_arts_unb2b_sc3_reg_unb_sens
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/synth/qsys_arts_unb2b_sc3_reg_unb_sens.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/synth/qsys_arts_unb2b_sc3_reg_unb_sens.vhd
deleted file mode 100644
index 8c707081c56fb8998043dc0bef76fb4020da6913..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens/synth/qsys_arts_unb2b_sc3_reg_unb_sens.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_unb_sens.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_unb_sens is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_unb_sens;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_unb_sens is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_unb_sens : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_unb_sens : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_unb_sens
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi.ip
index fb21d6b8040df453107cc519b88b52bb56f635f9..567b7cb83d71ae79856bef20b34c87e0d9832953 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -605,10 +605,6 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -701,10 +697,6 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
- <spirit:vector>
- <spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
- </spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
@@ -783,7 +775,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +833,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +897,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +966,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1361,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.bsf
deleted file mode 100644
index 69726f3a5a0a21d50dfeb9be745fab8059c7970e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_reg_wdi" (rect 84 -1 211 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_reg_wdi " (rect 214 512 602 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.cmp
deleted file mode 100644
index eee4bbdb3bc57b2215a37aca9dabe99988f820bc..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_wdi is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_wdi;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.html
deleted file mode 100644
index a5cc2aa458988d43532f1a7b4f893779586df210..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_reg_wdi</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_reg_wdi</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:39:43</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_reg_wdi"><b>qsys_arts_unb2b_sc3_reg_wdi</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_reg_wdi"><b>qsys_arts_unb2b_sc3_reg_wdi</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_reg_wdi"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_reg_wdi</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.00 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.qgsynthc
deleted file mode 100644
index 2a8505943f07cf207b651836699f320c83945a8f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_wdi</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_reg_wdi</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_wdi</name>
- <uniqueName>qsys_arts_unb2b_sc3_reg_wdi</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_reg_wdi</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_reg_wdi</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_reg_wdi.qsys_arts_unb2b_sc3_reg_wdi</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.qip
deleted file mode 100644
index 97712ecd10986d5863f043b4a9278f65eb0c1023..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_wdi" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_wdi.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_reg_wdi HAS_SOPCINFO 1 GENERATION_ID 1527683980"
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_wdi" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_reg_wdi.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_wdi" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_reg_wdi.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yZWdfd2Rp"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4Mzk4MA==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_reg_wdi" -library "qsys_arts_unb2b_sc3_reg_wdi" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_reg_wdi" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_reg_wdi.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.sopcinfo
deleted file mode 100644
index 9e745c8966face2399aa842ac9e7cbbfeb5aadc8..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_reg_wdi"
- kind="qsys_arts_unb2b_sc3_reg_wdi"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:39:43 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527683980</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_reg_wdi"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_reg_wdi">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.xml
deleted file mode 100644
index de0648aacb7fd7d339af37218372fc1318ec5aea..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:39:43"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_reg_wdi"
- version="1.0"
- name="qsys_arts_unb2b_sc3_reg_wdi">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527683980" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/synth/qsys_arts_unb2b_sc3_reg_wdi.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/synth/qsys_arts_unb2b_sc3_reg_wdi.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_wdi">"Generating: qsys_arts_unb2b_sc3_reg_wdi"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_wdi">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_reg_wdi"
- as="qsys_arts_unb2b_sc3_reg_wdi" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_reg_wdi">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_bb.v
deleted file mode 100644
index 2cc63c95097036d53eb4041459c0b74e97c929b4..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_reg_wdi (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_generation.rpt
deleted file mode 100644
index 62b9643b05315b72b407193f0e9c79232dd41b4f..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_reg_wdi: "Transforming system: qsys_arts_unb2b_sc3_reg_wdi"
-Info: qsys_arts_unb2b_sc3_reg_wdi: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_wdi: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_wdi: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_reg_wdi: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_reg_wdi: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_reg_wdi: Running transform interconnect_transform_chooser took 0.010s
-Info: qsys_arts_unb2b_sc3_reg_wdi: "Naming system components in system: qsys_arts_unb2b_sc3_reg_wdi"
-Info: qsys_arts_unb2b_sc3_reg_wdi: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_reg_wdi: "Generating: qsys_arts_unb2b_sc3_reg_wdi"
-Info: qsys_arts_unb2b_sc3_reg_wdi: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_reg_wdi: Done "qsys_arts_unb2b_sc3_reg_wdi" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_reg_wdi. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_inst.v
deleted file mode 100644
index 04039b1e9d7ba17efc157fc221c6c1fe2b09b5e7..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_reg_wdi u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_inst.vhd
deleted file mode 100644
index afeb1d7a693b53873fd75e68cf5a1c82f9ab8086..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/qsys_arts_unb2b_sc3_reg_wdi_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_reg_wdi is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_reg_wdi;
-
- u0 : component qsys_arts_unb2b_sc3_reg_wdi
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/synth/qsys_arts_unb2b_sc3_reg_wdi.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/synth/qsys_arts_unb2b_sc3_reg_wdi.vhd
deleted file mode 100644
index ec95d8965e2bc4da4a66ed7c98e4c480ac4da659..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi/synth/qsys_arts_unb2b_sc3_reg_wdi.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_reg_wdi.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_reg_wdi is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_reg_wdi;
-
-architecture rtl of qsys_arts_unb2b_sc3_reg_wdi is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_reg_wdi : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_reg_wdi : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_reg_wdi
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info.ip
index 2c41e940f6087dc8ddb1cfd7da1c968c2db3f10e..9c775d744b6c474cd439f7775163fc61704b2ac8 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info.ip
@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="addressSpan">128</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">4096</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
@@ -607,7 +607,7 @@
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>9</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -703,7 +703,7 @@
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
- <spirit:right>4</spirit:right>
+ <spirit:right>9</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
@@ -783,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="g_adr_w">5</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">10</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
@@ -841,7 +841,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>5</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -905,7 +905,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>5</width>
+ <width>10</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -974,7 +974,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>128</value>
+ <value>4096</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -1369,11 +1369,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x80' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x1000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>7</value>
+ <value>12</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
deleted file mode 100644
index c25498a59c25a892e6bf917251abc66cbe6fc961..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ /dev/null
@@ -1,77 +0,0 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2011
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: AVS wrapper to make a MM slave port available as conduit
--- Description:
--- Via this wrapper any MM slave register or RAM component can be made
--- accessible to SOPC Builder. This avoids having to make a dedicated
--- *_hw.tcl for each module or component that has MM slave ports.
--- Remark:
--- . The avs_common_mm_hw.tcl will determines the read latency, which is
--- typically 1.
-
-LIBRARY IEEE;
-USE IEEE.STD_LOGIC_1164.ALL;
-
-ENTITY avs_common_mm IS
- GENERIC (
- g_adr_w : NATURAL := 5;
- g_dat_w : NATURAL := 32
- );
- PORT (
- -- MM side
- csi_system_reset : IN STD_LOGIC;
- csi_system_clk : IN STD_LOGIC;
-
- avs_mem_address : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- avs_mem_write : IN STD_LOGIC;
- avs_mem_writedata : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- avs_mem_read : IN STD_LOGIC;
- avs_mem_readdata : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
-
- -- User side
- coe_reset_export : OUT STD_LOGIC;
- coe_clk_export : OUT STD_LOGIC;
-
- coe_address_export : OUT STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
- coe_write_export : OUT STD_LOGIC;
- coe_writedata_export : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
- coe_read_export : OUT STD_LOGIC;
- coe_readdata_export : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
- );
-END avs_common_mm;
-
-
-ARCHITECTURE wrap OF avs_common_mm IS
-BEGIN
-
- -- wires
- coe_reset_export <= csi_system_reset;
- coe_clk_export <= csi_system_clk;
-
- coe_address_export <= avs_mem_address;
- coe_write_export <= avs_mem_write;
- coe_writedata_export <= avs_mem_writedata;
- coe_read_export <= avs_mem_read;
- avs_mem_readdata <= coe_readdata_export;
-
-END wrap;
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.bsf
deleted file mode 100644
index 196a01e03b71bd957af58c9c11cd34c81e26ac22..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.bsf
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 352 528)
- (text "qsys_arts_unb2b_sc3_rom_system_info" (rect 55 -1 224 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 512 20 524)(font "Arial" ))
- (port
- (pt 0 152)
- (input)
- (text "avs_mem_address[4..0]" (rect 0 0 101 12)(font "Arial" (font_size 8)))
- (text "avs_mem_address[4..0]" (rect 4 141 130 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 144 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "avs_mem_write" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_write" (rect 4 157 82 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 144 168)(line_width 1))
- )
- (port
- (pt 0 184)
- (input)
- (text "avs_mem_writedata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_writedata[31..0]" (rect 4 173 148 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 144 184)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "avs_mem_read" (rect 0 0 66 12)(font "Arial" (font_size 8)))
- (text "avs_mem_read" (rect 4 189 76 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 144 200)(line_width 1))
- )
- (port
- (pt 0 296)
- (input)
- (text "coe_readdata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_readdata_export[31..0]" (rect 4 285 160 296)(font "Arial" (font_size 8)))
- (line (pt 0 296)(pt 144 296)(line_width 3))
- )
- (port
- (pt 0 376)
- (input)
- (text "csi_system_clk" (rect 0 0 63 12)(font "Arial" (font_size 8)))
- (text "csi_system_clk" (rect 4 365 88 376)(font "Arial" (font_size 8)))
- (line (pt 0 376)(pt 144 376)(line_width 1))
- )
- (port
- (pt 0 416)
- (input)
- (text "csi_system_reset" (rect 0 0 73 12)(font "Arial" (font_size 8)))
- (text "csi_system_reset" (rect 4 405 100 416)(font "Arial" (font_size 8)))
- (line (pt 0 416)(pt 144 416)(line_width 1))
- )
- (port
- (pt 0 72)
- (output)
- (text "coe_address_export[4..0]" (rect 0 0 103 12)(font "Arial" (font_size 8)))
- (text "coe_address_export[4..0]" (rect 4 61 148 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 144 72)(line_width 3))
- )
- (port
- (pt 0 112)
- (output)
- (text "coe_clk_export" (rect 0 0 61 12)(font "Arial" (font_size 8)))
- (text "coe_clk_export" (rect 4 101 88 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 144 112)(line_width 1))
- )
- (port
- (pt 0 216)
- (output)
- (text "avs_mem_readdata[31..0]" (rect 0 0 106 12)(font "Arial" (font_size 8)))
- (text "avs_mem_readdata[31..0]" (rect 4 205 142 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 144 216)(line_width 3))
- )
- (port
- (pt 0 256)
- (output)
- (text "coe_read_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_read_export" (rect 4 245 94 256)(font "Arial" (font_size 8)))
- (line (pt 0 256)(pt 144 256)(line_width 1))
- )
- (port
- (pt 0 336)
- (output)
- (text "coe_reset_export" (rect 0 0 70 12)(font "Arial" (font_size 8)))
- (text "coe_reset_export" (rect 4 325 100 336)(font "Arial" (font_size 8)))
- (line (pt 0 336)(pt 144 336)(line_width 1))
- )
- (port
- (pt 0 456)
- (output)
- (text "coe_write_export" (rect 0 0 68 12)(font "Arial" (font_size 8)))
- (text "coe_write_export" (rect 4 445 100 456)(font "Arial" (font_size 8)))
- (line (pt 0 456)(pt 144 456)(line_width 1))
- )
- (port
- (pt 0 496)
- (output)
- (text "coe_writedata_export[31..0]" (rect 0 0 108 12)(font "Arial" (font_size 8)))
- (text "coe_writedata_export[31..0]" (rect 4 485 166 496)(font "Arial" (font_size 8)))
- (line (pt 0 496)(pt 144 496)(line_width 3))
- )
- (drawing
- (text "address" (rect 98 43 238 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 67 334 144)(font "Arial" (color 0 0 0)))
- (text "clk" (rect 129 83 276 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 107 334 224)(font "Arial" (color 0 0 0)))
- (text "mem" (rect 116 123 250 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 149 147 340 304)(font "Arial" (color 0 0 0)))
- (text "write" (rect 149 163 328 336)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 149 179 352 368)(font "Arial" (color 0 0 0)))
- (text "read" (rect 149 195 322 400)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 149 211 346 432)(font "Arial" (color 0 0 0)))
- (text "read" (rect 119 227 262 467)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 251 334 512)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 94 267 236 547)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 291 334 592)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 115 307 260 627)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 331 334 672)(font "Arial" (color 0 0 0)))
- (text "system" (rect 103 347 242 707)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 149 371 316 752)(font "Arial" (color 0 0 0)))
- (text "system_reset" (rect 65 387 202 787)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset" (rect 149 411 328 832)(font "Arial" (color 0 0 0)))
- (text "write" (rect 116 427 262 867)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 451 334 912)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 91 467 236 947)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "export" (rect 149 491 334 992)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_rom_system_info " (rect 170 512 562 1034)(font "Arial" ))
- (line (pt 144 32)(pt 208 32)(line_width 1))
- (line (pt 208 32)(pt 208 512)(line_width 1))
- (line (pt 144 512)(pt 208 512)(line_width 1))
- (line (pt 144 32)(pt 144 512)(line_width 1))
- (line (pt 145 52)(pt 145 76)(line_width 1))
- (line (pt 146 52)(pt 146 76)(line_width 1))
- (line (pt 145 92)(pt 145 116)(line_width 1))
- (line (pt 146 92)(pt 146 116)(line_width 1))
- (line (pt 145 132)(pt 145 220)(line_width 1))
- (line (pt 146 132)(pt 146 220)(line_width 1))
- (line (pt 145 236)(pt 145 260)(line_width 1))
- (line (pt 146 236)(pt 146 260)(line_width 1))
- (line (pt 145 276)(pt 145 300)(line_width 1))
- (line (pt 146 276)(pt 146 300)(line_width 1))
- (line (pt 145 316)(pt 145 340)(line_width 1))
- (line (pt 146 316)(pt 146 340)(line_width 1))
- (line (pt 145 356)(pt 145 380)(line_width 1))
- (line (pt 146 356)(pt 146 380)(line_width 1))
- (line (pt 145 396)(pt 145 420)(line_width 1))
- (line (pt 146 396)(pt 146 420)(line_width 1))
- (line (pt 145 436)(pt 145 460)(line_width 1))
- (line (pt 146 436)(pt 146 460)(line_width 1))
- (line (pt 145 476)(pt 145 500)(line_width 1))
- (line (pt 146 476)(pt 146 500)(line_width 1))
- (line (pt 0 0)(pt 352 0)(line_width 1))
- (line (pt 352 0)(pt 352 528)(line_width 1))
- (line (pt 0 528)(pt 352 528)(line_width 1))
- (line (pt 0 0)(pt 0 528)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.cmp
deleted file mode 100644
index 8d044f560ab08584cd71dbea36927d98e591241a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.cmp
+++ /dev/null
@@ -1,19 +0,0 @@
- component qsys_arts_unb2b_sc3_rom_system_info is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_rom_system_info;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.html
deleted file mode 100644
index b3604744547ad3bb35a9d175ee1703cdba8d61a0..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.html
+++ /dev/null
@@ -1,157 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_rom_system_info</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_rom_system_info</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:45:56</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_rom_system_info"><b>qsys_arts_unb2b_sc3_rom_system_info</b>
- </a> avs_common_mm 1.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_rom_system_info"><b>qsys_arts_unb2b_sc3_rom_system_info</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">mem </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_rom_system_info"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_rom_system_info</h2>avs_common_mm v1.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">g_adr_w</td>
- <td class="parametervalue">5</td>
- </tr>
- <tr>
- <td class="parametername">g_dat_w</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">AUTO_SYSTEM_CLOCK_RATE</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>(none)</td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 2.06 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.qgsynthc
deleted file mode 100644
index 96998fa949b04d88962237fb79f2ef8afc54b4d1..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.qgsynthc
+++ /dev/null
@@ -1,50 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_rom_system_info</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_rom_system_info</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_rom_system_info</name>
- <uniqueName>qsys_arts_unb2b_sc3_rom_system_info</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_rom_system_info</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>g_adr_w</name>
- <value>5</value>
- </parameter>
- <parameter>
- <name>g_dat_w</name>
- <value>32</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>avs_common_mm</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_rom_system_info</name>
- <uniqueName>avs_common_mm</uniqueName>
- <fixedName>avs_common_mm</fixedName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_rom_system_info.qsys_arts_unb2b_sc3_rom_system_info</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.qip
deleted file mode 100644
index 94136ec59da35b85e726045e80c7856b46a9cddd..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.qip
+++ /dev/null
@@ -1,37 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_rom_system_info" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_rom_system_info.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_rom_system_info HAS_SOPCINFO 1 GENERATION_ID 1527684356"
-set_global_assignment -library "qsys_arts_unb2b_sc3_rom_system_info" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_rom_system_info.cmp"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_rom_system_info" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_rom_system_info.ip"]
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DISPLAY_NAME "YXZzX2NvbW1vbl9tbQ=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_AUTHOR "QVNUUk9O"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_DESCRIPTION "TU0gc2xhdmUgcG9ydCB0byBjb25kdWl0IHdpdGggcmVhZCBsYXRlbmN5IDE="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19hZHJfdw==::NQ==::Z19hZHJfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "Z19kYXRfdw==::MzI=::Z19kYXRfdw=="
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::MTI1MDAwMDAw::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "avs_common_mm" -library "avs_common_mm_10" -name IP_COMPONENT_GROUP "VW5pYm9hcmQ="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM19yb21fc3lzdGVtX2luZm8="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDM1Ng==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_rom_system_info" -library "qsys_arts_unb2b_sc3_rom_system_info" -name IP_COMPONENT_PARAMETER "QVVUT19TWVNURU1fUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "avs_common_mm_10" -name VHDL_FILE [file join $::quartus(qip_path) "avs_common_mm_10/synth/avs_common_mm.vhd"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_rom_system_info" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_rom_system_info.vhd"]
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.sopcinfo
deleted file mode 100644
index 5001c97d98a76cf1809d2bde46df8da1c7359aec..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.sopcinfo
+++ /dev/null
@@ -1,1064 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_rom_system_info"
- kind="qsys_arts_unb2b_sc3_rom_system_info"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:45:56 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684356</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_rom_system_info"
- kind="avs_common_mm"
- version="1.0"
- path="qsys_arts_unb2b_sc3_rom_system_info">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <parameter name="g_adr_w">
- <type>int</type>
- <value>5</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="g_dat_w">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="AUTO_SYSTEM_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>system</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="system" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="system_reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>csi_system_reset</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset</role>
- </port>
- </interface>
- <interface name="mem" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>false</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>false</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>DYNAMIC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>128</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>system</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>system_reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>avs_mem_address</name>
- <direction>Input</direction>
- <width>5</width>
- <role>address</role>
- </port>
- <port>
- <name>avs_mem_write</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write</role>
- </port>
- <port>
- <name>avs_mem_writedata</name>
- <direction>Input</direction>
- <width>32</width>
- <role>writedata</role>
- </port>
- <port>
- <name>avs_mem_read</name>
- <direction>Input</direction>
- <width>1</width>
- <role>read</role>
- </port>
- <port>
- <name>avs_mem_readdata</name>
- <direction>Output</direction>
- <width>32</width>
- <role>readdata</role>
- </port>
- </interface>
- <interface name="reset" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_reset_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="clk" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_clk_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="address" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_address_export</name>
- <direction>Output</direction>
- <width>5</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="write" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_write_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="writedata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_writedata_export</name>
- <direction>Output</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="read" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_read_export</name>
- <direction>Output</direction>
- <width>1</width>
- <role>export</role>
- </port>
- </interface>
- <interface name="readdata" kind="conduit_end" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>conduit</type>
- <isStart>false</isStart>
- <port>
- <name>coe_readdata_export</name>
- <direction>Input</direction>
- <width>32</width>
- <role>export</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avs_common_mm</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>avs_common_mm</displayName>
- <version>1.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>7</instanceCount>
- <name>conduit_end</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Conduit</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.xml
deleted file mode 100644
index a6fd66b1b9936880ce53e701629383f0e1809745..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info.xml
+++ /dev/null
@@ -1,225 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:45:58"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_SYSTEM_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="address" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_address_export" direction="output" role="export" width="5" />
- </interface>
- <interface name="clk" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_clk_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="mem" kind="avalon" start="0">
- <property name="addressAlignment" value="DYNAMIC" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="128" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="system" />
- <property name="associatedReset" value="system_reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="1" />
- <property name="readWaitStates" value="0" />
- <property name="readWaitTime" value="0" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="avs_mem_address" direction="input" role="address" width="5" />
- <port name="avs_mem_write" direction="input" role="write" width="1" />
- <port
- name="avs_mem_writedata"
- direction="input"
- role="writedata"
- width="32" />
- <port name="avs_mem_read" direction="input" role="read" width="1" />
- <port name="avs_mem_readdata" direction="output" role="readdata" width="32" />
- </interface>
- <interface name="read" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_read_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="readdata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_readdata_export" direction="input" role="export" width="32" />
- </interface>
- <interface name="reset" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_reset_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="system" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="csi_system_clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="system_reset" kind="reset" start="0">
- <property name="associatedClock" value="system" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="csi_system_reset" direction="input" role="reset" width="1" />
- </interface>
- <interface name="write" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port name="coe_write_export" direction="output" role="export" width="1" />
- </interface>
- <interface name="writedata" kind="conduit" start="0">
- <property name="associatedClock" value="" />
- <property name="associatedReset" value="" />
- <property name="prSafe" value="false" />
- <port
- name="coe_writedata_export"
- direction="output"
- role="export"
- width="32" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_rom_system_info"
- version="1.0"
- name="qsys_arts_unb2b_sc3_rom_system_info">
- <parameter name="AUTO_SYSTEM_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684356" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_SYSTEM_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/synth/qsys_arts_unb2b_sc3_rom_system_info.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/synth/qsys_arts_unb2b_sc3_rom_system_info.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_rom_system_info">"Generating: qsys_arts_unb2b_sc3_rom_system_info"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_rom_system_info">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
- <entity kind="avs_common_mm" version="1.0" name="avs_common_mm">
- <parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm_hw.tcl" />
- <file
- path="/home/donker/svn/UniBoard_FP7/UniBoard/trunk/Firmware/modules/common/src/vhdl/avs_common_mm.vhd" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_rom_system_info"
- as="qsys_arts_unb2b_sc3_rom_system_info" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_rom_system_info">"Generating: avs_common_mm"</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_bb.v
deleted file mode 100644
index ad099ff03add90fd27f14c53e91040a8da0e8ab3..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_bb.v
+++ /dev/null
@@ -1,32 +0,0 @@
-
-module qsys_arts_unb2b_sc3_rom_system_info (
- coe_address_export,
- coe_clk_export,
- avs_mem_address,
- avs_mem_write,
- avs_mem_writedata,
- avs_mem_read,
- avs_mem_readdata,
- coe_read_export,
- coe_readdata_export,
- coe_reset_export,
- csi_system_clk,
- csi_system_reset,
- coe_write_export,
- coe_writedata_export);
-
- output [4:0] coe_address_export;
- output coe_clk_export;
- input [4:0] avs_mem_address;
- input avs_mem_write;
- input [31:0] avs_mem_writedata;
- input avs_mem_read;
- output [31:0] avs_mem_readdata;
- output coe_read_export;
- input [31:0] coe_readdata_export;
- output coe_reset_export;
- input csi_system_clk;
- input csi_system_reset;
- output coe_write_export;
- output [31:0] coe_writedata_export;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_generation.rpt
deleted file mode 100644
index d08a354e2eb8afd0d72fe0e808c8fba6845ca115..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_generation.rpt
+++ /dev/null
@@ -1,25 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_rom_system_info: "Transforming system: qsys_arts_unb2b_sc3_rom_system_info"
-Info: qsys_arts_unb2b_sc3_rom_system_info: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_rom_system_info: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_rom_system_info: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_rom_system_info: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_rom_system_info: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_rom_system_info: Running transform interconnect_transform_chooser took 0.008s
-Info: qsys_arts_unb2b_sc3_rom_system_info: "Naming system components in system: qsys_arts_unb2b_sc3_rom_system_info"
-Info: qsys_arts_unb2b_sc3_rom_system_info: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_rom_system_info: "Generating: qsys_arts_unb2b_sc3_rom_system_info"
-Info: qsys_arts_unb2b_sc3_rom_system_info: "Generating: avs_common_mm"
-Info: qsys_arts_unb2b_sc3_rom_system_info: Done "qsys_arts_unb2b_sc3_rom_system_info" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_rom_system_info. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_inst.v
deleted file mode 100644
index ed4a8a46a2c92a76ef4a886bf5912f8daf9f40f8..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_inst.v
+++ /dev/null
@@ -1,17 +0,0 @@
- qsys_arts_unb2b_sc3_rom_system_info u0 (
- .coe_address_export (_connected_to_coe_address_export_), // address.export
- .coe_clk_export (_connected_to_coe_clk_export_), // clk.export
- .avs_mem_address (_connected_to_avs_mem_address_), // mem.address
- .avs_mem_write (_connected_to_avs_mem_write_), // .write
- .avs_mem_writedata (_connected_to_avs_mem_writedata_), // .writedata
- .avs_mem_read (_connected_to_avs_mem_read_), // .read
- .avs_mem_readdata (_connected_to_avs_mem_readdata_), // .readdata
- .coe_read_export (_connected_to_coe_read_export_), // read.export
- .coe_readdata_export (_connected_to_coe_readdata_export_), // readdata.export
- .coe_reset_export (_connected_to_coe_reset_export_), // reset.export
- .csi_system_clk (_connected_to_csi_system_clk_), // system.clk
- .csi_system_reset (_connected_to_csi_system_reset_), // system_reset.reset
- .coe_write_export (_connected_to_coe_write_export_), // write.export
- .coe_writedata_export (_connected_to_coe_writedata_export_) // writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_inst.vhd
deleted file mode 100644
index e7f1319328e9170440e78f7a88bbd0809425e70e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/qsys_arts_unb2b_sc3_rom_system_info_inst.vhd
+++ /dev/null
@@ -1,37 +0,0 @@
- component qsys_arts_unb2b_sc3_rom_system_info is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_arts_unb2b_sc3_rom_system_info;
-
- u0 : component qsys_arts_unb2b_sc3_rom_system_info
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/synth/qsys_arts_unb2b_sc3_rom_system_info.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/synth/qsys_arts_unb2b_sc3_rom_system_info.vhd
deleted file mode 100644
index 4b97467d8ebb451e9c0198fe46e6387491adfd40..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info/synth/qsys_arts_unb2b_sc3_rom_system_info.vhd
+++ /dev/null
@@ -1,79 +0,0 @@
--- qsys_arts_unb2b_sc3_rom_system_info.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library avs_common_mm_10;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_rom_system_info is
- port (
- coe_address_export : out std_logic_vector(4 downto 0); -- address.export
- coe_clk_export : out std_logic; -- clk.export
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => '0'); -- mem.address
- avs_mem_write : in std_logic := '0'; -- .write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- avs_mem_read : in std_logic := '0'; -- .read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- .readdata
- coe_read_export : out std_logic; -- read.export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => '0'); -- readdata.export
- coe_reset_export : out std_logic; -- reset.export
- csi_system_clk : in std_logic := '0'; -- system.clk
- csi_system_reset : in std_logic := '0'; -- system_reset.reset
- coe_write_export : out std_logic; -- write.export
- coe_writedata_export : out std_logic_vector(31 downto 0) -- writedata.export
- );
-end entity qsys_arts_unb2b_sc3_rom_system_info;
-
-architecture rtl of qsys_arts_unb2b_sc3_rom_system_info is
- component avs_common_mm_cmp is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- avs_mem_address : in std_logic_vector(4 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(31 downto 0); -- readdata
- coe_reset_export : out std_logic; -- export
- coe_clk_export : out std_logic; -- export
- coe_address_export : out std_logic_vector(4 downto 0); -- export
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
- );
- end component avs_common_mm_cmp;
-
- for qsys_arts_unb2b_sc3_rom_system_info : avs_common_mm_cmp
- use entity avs_common_mm_10.avs_common_mm;
-begin
-
- qsys_arts_unb2b_sc3_rom_system_info : component avs_common_mm_cmp
- generic map (
- g_adr_w => 5,
- g_dat_w => 32
- )
- port map (
- csi_system_clk => csi_system_clk, -- system.clk
- csi_system_reset => csi_system_reset, -- system_reset.reset
- avs_mem_address => avs_mem_address, -- mem.address
- avs_mem_write => avs_mem_write, -- .write
- avs_mem_writedata => avs_mem_writedata, -- .writedata
- avs_mem_read => avs_mem_read, -- .read
- avs_mem_readdata => avs_mem_readdata, -- .readdata
- coe_reset_export => coe_reset_export, -- reset.export
- coe_clk_export => coe_clk_export, -- clk.export
- coe_address_export => coe_address_export, -- address.export
- coe_write_export => coe_write_export, -- write.export
- coe_writedata_export => coe_writedata_export, -- writedata.export
- coe_read_export => coe_read_export, -- read.export
- coe_readdata_export => coe_readdata_export -- readdata.export
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_rom_system_info
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0.ip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0.ip
index cb18df710a292af650d75e73a047e4130c930db8..626db118de861d773937b6d8d9a528c59d5faf18 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0.ip
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0.ip
@@ -526,7 +526,7 @@
<spirit:parameter>
<spirit:name>alwaysRun</spirit:name>
<spirit:displayName>No Start/Stop control bits</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="alwaysRun">false</spirit:value>
+ <spirit:value spirit:format="bool" spirit:id="alwaysRun">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>counterSize</spirit:name>
@@ -536,7 +536,7 @@
<spirit:parameter>
<spirit:name>fixedPeriod</spirit:name>
<spirit:displayName>Fixed period</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="fixedPeriod">false</spirit:value>
+ <spirit:value spirit:format="bool" spirit:id="fixedPeriod">true</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>period</spirit:name>
@@ -556,7 +556,7 @@
<spirit:parameter>
<spirit:name>snapshot</spirit:name>
<spirit:displayName>Readable snapshot</spirit:displayName>
- <spirit:value spirit:format="bool" spirit:id="snapshot">true</spirit:value>
+ <spirit:value spirit:format="bool" spirit:id="snapshot">false</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>timeoutPulseOutput</spirit:name>
@@ -576,7 +576,7 @@
<spirit:parameter>
<spirit:name>timerPreset</spirit:name>
<spirit:displayName>Presets</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="timerPreset">FULL_FEATURED</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="timerPreset">SIMPLE_PERIODIC_INTERRUPT</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>periodUnitsString</spirit:name>
@@ -614,7 +614,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.ALWAYS_RUN</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ALWAYS_RUN">0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.ALWAYS_RUN">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.COUNTER_SIZE</spirit:name>
@@ -622,7 +622,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.FIXED_PERIOD</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FIXED_PERIOD">0</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.FIXED_PERIOD">1</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.FREQ</spirit:name>
@@ -650,7 +650,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.SNAPSHOT</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SNAPSHOT">1</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.SNAPSHOT">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.TICKS_PER_SEC</spirit:name>
@@ -660,22 +660,6 @@
<spirit:name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</spirit:name>
<spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT">0</spirit:value>
</spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.dts.compatible</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.compatible">altr,timer-1.0</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.dts.group</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.group">timer</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.dts.name</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.name">timer</spirit:value>
- </spirit:parameter>
- <spirit:parameter>
- <spirit:name>embeddedsw.dts.params.clock-frequency</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.dts.params.clock-frequency">125000000</spirit:value>
- </spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.dts.vendor</spirit:name>
<spirit:value spirit:format="string" spirit:id="embeddedsw.dts.vendor">altr</spirit:value>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/altera_avalon_timer_170/synth/qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/altera_avalon_timer_170/synth/qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy.v
deleted file mode 100644
index a06af334791e99a486a401e67583a4cc946c7f46..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/altera_avalon_timer_170/synth/qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy.v
+++ /dev/null
@@ -1,211 +0,0 @@
-//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
-//use of Altera Corporation's design tools, logic functions and other
-//software and tools, and its AMPP partner logic functions, and any
-//output files any of the foregoing (including device programming or
-//simulation files), and any associated documentation or information are
-//expressly subject to the terms and conditions of the Altera Program
-//License Subscription Agreement or other applicable license agreement,
-//including, without limitation, that your use is for the sole purpose
-//of programming logic devices manufactured by Altera and sold by Altera
-//or its authorized distributors. Please refer to the applicable
-//agreement for further details.
-
-// synthesis translate_off
-`timescale 1ns / 1ps
-// synthesis translate_on
-
-// turn off superfluous verilog processor warnings
-// altera message_level Level1
-// altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
-
-module qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy (
- // inputs:
- address,
- chipselect,
- clk,
- reset_n,
- write_n,
- writedata,
-
- // outputs:
- irq,
- readdata
- )
-;
-
- output irq;
- output [ 15: 0] readdata;
- input [ 2: 0] address;
- input chipselect;
- input clk;
- input reset_n;
- input write_n;
- input [ 15: 0] writedata;
-
-
-wire clk_en;
-wire control_continuous;
-wire control_interrupt_enable;
-reg [ 3: 0] control_register;
-wire control_wr_strobe;
-reg counter_is_running;
-wire counter_is_zero;
-wire [ 31: 0] counter_load_value;
-reg [ 31: 0] counter_snapshot;
-reg delayed_unxcounter_is_zeroxx0;
-wire do_start_counter;
-wire do_stop_counter;
-reg force_reload;
-reg [ 31: 0] internal_counter;
-wire irq;
-reg [ 15: 0] period_h_register;
-wire period_h_wr_strobe;
-reg [ 15: 0] period_l_register;
-wire period_l_wr_strobe;
-wire [ 15: 0] read_mux_out;
-reg [ 15: 0] readdata;
-wire snap_h_wr_strobe;
-wire snap_l_wr_strobe;
-wire [ 31: 0] snap_read_value;
-wire snap_strobe;
-wire start_strobe;
-wire status_wr_strobe;
-wire stop_strobe;
-wire timeout_event;
-reg timeout_occurred;
- assign clk_en = 1;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- internal_counter <= 32'h1E847;
- else if (counter_is_running || force_reload)
- if (counter_is_zero || force_reload)
- internal_counter <= counter_load_value;
- else
- internal_counter <= internal_counter - 1;
- end
-
-
- assign counter_is_zero = internal_counter == 0;
- assign counter_load_value = {period_h_register,
- period_l_register};
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- force_reload <= 0;
- else if (clk_en)
- force_reload <= period_h_wr_strobe || period_l_wr_strobe;
- end
-
-
- assign do_start_counter = start_strobe;
- assign do_stop_counter = (stop_strobe ) ||
- (force_reload ) ||
- (counter_is_zero && ~control_continuous );
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- counter_is_running <= 1'b0;
- else if (clk_en)
- if (do_start_counter)
- counter_is_running <= -1;
- else if (do_stop_counter)
- counter_is_running <= 0;
- end
-
-
- //delayed_unxcounter_is_zeroxx0, which is an e_register
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- delayed_unxcounter_is_zeroxx0 <= 0;
- else if (clk_en)
- delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
- end
-
-
- assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- timeout_occurred <= 0;
- else if (clk_en)
- if (status_wr_strobe)
- timeout_occurred <= 0;
- else if (timeout_event)
- timeout_occurred <= -1;
- end
-
-
- assign irq = timeout_occurred && control_interrupt_enable;
- //s1, which is an e_avalon_slave
- assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
- ({16 {(address == 3)}} & period_h_register) |
- ({16 {(address == 4)}} & snap_read_value[15 : 0]) |
- ({16 {(address == 5)}} & snap_read_value[31 : 16]) |
- ({16 {(address == 1)}} & control_register) |
- ({16 {(address == 0)}} & {counter_is_running,
- timeout_occurred});
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- readdata <= 0;
- else if (clk_en)
- readdata <= read_mux_out;
- end
-
-
- assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
- assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- period_l_register <= 59463;
- else if (period_l_wr_strobe)
- period_l_register <= writedata;
- end
-
-
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- period_h_register <= 1;
- else if (period_h_wr_strobe)
- period_h_register <= writedata;
- end
-
-
- assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
- assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
- assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- counter_snapshot <= 0;
- else if (snap_strobe)
- counter_snapshot <= internal_counter;
- end
-
-
- assign snap_read_value = counter_snapshot;
- assign control_wr_strobe = chipselect && ~write_n && (address == 1);
- always @(posedge clk or negedge reset_n)
- begin
- if (reset_n == 0)
- control_register <= 0;
- else if (control_wr_strobe)
- control_register <= writedata[3 : 0];
- end
-
-
- assign stop_strobe = writedata[3] && control_wr_strobe;
- assign start_strobe = writedata[2] && control_wr_strobe;
- assign control_continuous = control_register[1];
- assign control_interrupt_enable = control_register[0];
- assign status_wr_strobe = chipselect && ~write_n && (address == 0);
-
-endmodule
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.bsf b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.bsf
deleted file mode 100644
index 468c5c21626b872669482140d17b3861b4bac88a..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.bsf
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-*/
-(header "symbol" (version "1.1"))
-(symbol
- (rect 0 0 272 248)
- (text "qsys_arts_unb2b_sc3_timer_0" (rect 45 -1 172 11)(font "Arial" (font_size 10)))
- (text "inst" (rect 8 232 20 244)(font "Arial" ))
- (port
- (pt 0 72)
- (input)
- (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8)))
- (text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8)))
- (line (pt 0 72)(pt 96 72)(line_width 1))
- )
- (port
- (pt 0 112)
- (input)
- (text "reset_n" (rect 0 0 30 12)(font "Arial" (font_size 8)))
- (text "reset_n" (rect 4 101 46 112)(font "Arial" (font_size 8)))
- (line (pt 0 112)(pt 96 112)(line_width 1))
- )
- (port
- (pt 0 152)
- (input)
- (text "address[2..0]" (rect 0 0 51 12)(font "Arial" (font_size 8)))
- (text "address[2..0]" (rect 4 141 82 152)(font "Arial" (font_size 8)))
- (line (pt 0 152)(pt 96 152)(line_width 3))
- )
- (port
- (pt 0 168)
- (input)
- (text "writedata[15..0]" (rect 0 0 57 12)(font "Arial" (font_size 8)))
- (text "writedata[15..0]" (rect 4 157 100 168)(font "Arial" (font_size 8)))
- (line (pt 0 168)(pt 96 168)(line_width 3))
- )
- (port
- (pt 0 200)
- (input)
- (text "chipselect" (rect 0 0 37 12)(font "Arial" (font_size 8)))
- (text "chipselect" (rect 4 189 64 200)(font "Arial" (font_size 8)))
- (line (pt 0 200)(pt 96 200)(line_width 1))
- )
- (port
- (pt 0 216)
- (input)
- (text "write_n" (rect 0 0 28 12)(font "Arial" (font_size 8)))
- (text "write_n" (rect 4 205 46 216)(font "Arial" (font_size 8)))
- (line (pt 0 216)(pt 96 216)(line_width 1))
- )
- (port
- (pt 272 72)
- (output)
- (text "irq" (rect 0 0 9 12)(font "Arial" (font_size 8)))
- (text "irq" (rect 258 61 276 72)(font "Arial" (font_size 8)))
- (line (pt 272 72)(pt 176 72)(line_width 1))
- )
- (port
- (pt 0 184)
- (output)
- (text "readdata[15..0]" (rect 0 0 57 12)(font "Arial" (font_size 8)))
- (text "readdata[15..0]" (rect 4 173 94 184)(font "Arial" (font_size 8)))
- (line (pt 0 184)(pt 96 184)(line_width 3))
- )
- (drawing
- (text "clk" (rect 81 43 180 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "clk" (rect 101 67 220 144)(font "Arial" (color 0 0 0)))
- (text "irq" (rect 177 43 372 99)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "irq" (rect 162 67 342 144)(font "Arial" (color 0 0 0)))
- (text "reset" (rect 67 83 164 179)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "reset_n" (rect 101 107 244 224)(font "Arial" (color 0 0 0)))
- (text "s1" (rect 85 123 182 259)(font "Arial" (color 128 0 0)(font_size 9)))
- (text "address" (rect 101 147 244 304)(font "Arial" (color 0 0 0)))
- (text "writedata" (rect 101 163 256 336)(font "Arial" (color 0 0 0)))
- (text "readdata" (rect 101 179 250 368)(font "Arial" (color 0 0 0)))
- (text "chipselect" (rect 101 195 262 400)(font "Arial" (color 0 0 0)))
- (text "write_n" (rect 101 211 244 432)(font "Arial" (color 0 0 0)))
- (text " qsys_arts_unb2b_sc3_timer_0 " (rect 134 232 442 474)(font "Arial" ))
- (line (pt 96 32)(pt 176 32)(line_width 1))
- (line (pt 176 32)(pt 176 232)(line_width 1))
- (line (pt 96 232)(pt 176 232)(line_width 1))
- (line (pt 96 32)(pt 96 232)(line_width 1))
- (line (pt 97 52)(pt 97 76)(line_width 1))
- (line (pt 98 52)(pt 98 76)(line_width 1))
- (line (pt 175 52)(pt 175 76)(line_width 1))
- (line (pt 174 52)(pt 174 76)(line_width 1))
- (line (pt 97 92)(pt 97 116)(line_width 1))
- (line (pt 98 92)(pt 98 116)(line_width 1))
- (line (pt 97 132)(pt 97 220)(line_width 1))
- (line (pt 98 132)(pt 98 220)(line_width 1))
- (line (pt 0 0)(pt 272 0)(line_width 1))
- (line (pt 272 0)(pt 272 248)(line_width 1))
- (line (pt 0 248)(pt 272 248)(line_width 1))
- (line (pt 0 0)(pt 0 248)(line_width 1))
- )
-)
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.cmp b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.cmp
deleted file mode 100644
index b7b19b3928abf189ff5a37e3bc125f2022fde2aa..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.cmp
+++ /dev/null
@@ -1,13 +0,0 @@
- component qsys_arts_unb2b_sc3_timer_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
- );
- end component qsys_arts_unb2b_sc3_timer_0;
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.html b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.html
deleted file mode 100644
index c27b83f524459c4015606d97c97d0e91dac29a77..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.html
+++ /dev/null
@@ -1,264 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
-
-<html xmlns="http://www.w3.org/1999/xhtml">
- <head>
- <title>datasheet for qsys_arts_unb2b_sc3_timer_0</title>
- <style type="text/css">
-body { font-family:arial ;}
-a { text-decoration:underline ; color:#003000 ;}
-a:hover { text-decoration:underline ; color:0030f0 ;}
-td { padding : 5px ;}
-table.topTitle { width:100% ;}
-table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
-table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
-table.blueBar { width : 100% ; border-spacing : 0px ;}
-table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
-table.blueBar td.l { text-align : left ;}
-table.blueBar td.r { text-align : right ;}
-table.items { width:100% ; border-collapse:collapse ;}
-table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
-table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
-div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ; font-size:12px ;}
-body { font-family:arial ;}
-table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
-table.x td { border:1px solid #bbb ;}
-td.tableTitle { font-weight:bold ; text-align:center ;}
-table.grid { border-collapse:collapse ;}
-table.grid td { border:1px solid #bbb ;}
-table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
-table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
-table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
-table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
-table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
-table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
-table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
-table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
-table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
-table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
-table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
-table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
-table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
-table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
-table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
-table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
-table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
-.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
-.flowbox { display:inline-block ;}
-.parametersbox table { font-size:10px ;}
-td.parametername { font-style:italic ;}
-td.parametervalue { font-weight:bold ;}
-div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
- </head>
- <body>
- <table class="topTitle">
- <tr>
- <td class="l">qsys_arts_unb2b_sc3_timer_0</td>
- <td class="r">
- <br/>
- <br/>
- </td>
- </tr>
- </table>
- <table class="blueBar">
- <tr>
- <td class="l">2018.05.30.14:42:00</td>
- <td class="r">Datasheet</td>
- </tr>
- </table>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Overview</div>
- <div class="greydiv">
- <div style="display:inline-block ; text-align:left">
- <table class="connectionboxes">
- <tr style="height:6px">
- <td></td>
- </tr>
- </table>
- </div><span style="display:inline-block ; width:28px"> </span>
- <div style="display:inline-block ; text-align:left"><span>
- <br/>All Components
- <br/>  
- <a href="#module_qsys_arts_unb2b_sc3_timer_0"><b>qsys_arts_unb2b_sc3_timer_0</b>
- </a> altera_avalon_timer 17.0</span>
- </div>
- </div>
- <div style="width:100% ; height:10px"> </div>
- <div class="label">Memory Map</div>
- <table class="mmap">
- <tr>
- <td class="empty" rowspan="2"></td>
- </tr>
- <tr>
- <td class="slavemodule"> 
- <a href="#module_qsys_arts_unb2b_sc3_timer_0"><b>qsys_arts_unb2b_sc3_timer_0</b>
- </a>
- </td>
- </tr>
- <tr>
- <td class="slaveb">s1 </td>
- </tr>
- </table>
- <a name="module_qsys_arts_unb2b_sc3_timer_0"> </a>
- <div>
- <hr/>
- <h2>qsys_arts_unb2b_sc3_timer_0</h2>altera_avalon_timer v17.0
- <br/>
- <br/>
- <br/>
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Parameters</h2>
- <table>
- <tr>
- <td class="parametername">alwaysRun</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">counterSize</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">fixedPeriod</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">period</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">periodUnits</td>
- <td class="parametervalue">MSEC</td>
- </tr>
- <tr>
- <td class="parametername">resetOutput</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">snapshot</td>
- <td class="parametervalue">true</td>
- </tr>
- <tr>
- <td class="parametername">timeoutPulseOutput</td>
- <td class="parametervalue">false</td>
- </tr>
- <tr>
- <td class="parametername">systemFrequency</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">watchdogPulse</td>
- <td class="parametervalue">2</td>
- </tr>
- <tr>
- <td class="parametername">timerPreset</td>
- <td class="parametervalue">FULL_FEATURED</td>
- </tr>
- <tr>
- <td class="parametername">periodUnitsString</td>
- <td class="parametervalue">ms</td>
- </tr>
- <tr>
- <td class="parametername">valueInSecond</td>
- <td class="parametervalue">0.001</td>
- </tr>
- <tr>
- <td class="parametername">loadValue</td>
- <td class="parametervalue">124999</td>
- </tr>
- <tr>
- <td class="parametername">mult</td>
- <td class="parametervalue">0.001</td>
- </tr>
- <tr>
- <td class="parametername">ticksPerSec</td>
- <td class="parametervalue">1000.0</td>
- </tr>
- <tr>
- <td class="parametername">slave_address_width</td>
- <td class="parametervalue">3</td>
- </tr>
- <tr>
- <td class="parametername">deviceFamily</td>
- <td class="parametervalue">UNKNOWN</td>
- </tr>
- <tr>
- <td class="parametername">generateLegacySim</td>
- <td class="parametervalue">false</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>  
- <table class="flowbox">
- <tr>
- <td class="parametersbox">
- <h2>Software Assignments</h2>
- <table>
- <tr>
- <td class="parametername">ALWAYS_RUN</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">COUNTER_SIZE</td>
- <td class="parametervalue">32</td>
- </tr>
- <tr>
- <td class="parametername">FIXED_PERIOD</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">FREQ</td>
- <td class="parametervalue">125000000</td>
- </tr>
- <tr>
- <td class="parametername">LOAD_VALUE</td>
- <td class="parametervalue">124999</td>
- </tr>
- <tr>
- <td class="parametername">MULT</td>
- <td class="parametervalue">0.001</td>
- </tr>
- <tr>
- <td class="parametername">PERIOD</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">PERIOD_UNITS</td>
- <td class="parametervalue">ms</td>
- </tr>
- <tr>
- <td class="parametername">RESET_OUTPUT</td>
- <td class="parametervalue">0</td>
- </tr>
- <tr>
- <td class="parametername">SNAPSHOT</td>
- <td class="parametervalue">1</td>
- </tr>
- <tr>
- <td class="parametername">TICKS_PER_SEC</td>
- <td class="parametervalue">1000</td>
- </tr>
- <tr>
- <td class="parametername">TIMEOUT_PULSE_OUTPUT</td>
- <td class="parametervalue">0</td>
- </tr>
- </table>
- </td>
- </tr>
- </table>
- </div>
- <table class="blueBar">
- <tr>
- <td class="l">generation took 0.00 seconds</td>
- <td class="r">rendering took 0.01 seconds</td>
- </tr>
- </table>
- </body>
-</html>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.qgsynthc b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.qgsynthc
deleted file mode 100644
index df188a9b1ef32a26f3b4aca7c0249e45067578b0..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.qgsynthc
+++ /dev/null
@@ -1,109 +0,0 @@
-<?xml version="1.0" ?>
-<node xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xs="http://www.w3.org/2001/XMLSchema" xmlns:altera="http://www.altera.com/XMLSchema/Qsys/SystemTree">
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_timer_0</instanceKey>
- <instanceData xsi:type="data">
- <parameters></parameters>
- <interconnectAssignments>
- <interconnectAssignment>
- <name>qsys_mm.clockCrossingAdapter</name>
- <value>HANDSHAKE</value>
- </interconnectAssignment>
- <interconnectAssignment>
- <name>qsys_mm.maxAdditionalLatency</name>
- <value>0</value>
- </interconnectAssignment>
- </interconnectAssignments>
- <className>qsys_arts_unb2b_sc3_timer_0</className>
- <version>1.0</version>
- <name>qsys_arts_unb2b_sc3_timer_0</name>
- <uniqueName>qsys_arts_unb2b_sc3_timer_0</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- </instanceData>
- <children>
- <node>
- <instanceKey xsi:type="xs:string">qsys_arts_unb2b_sc3_timer_0</instanceKey>
- <instanceData xsi:type="data">
- <parameters>
- <parameter>
- <name>alwaysRun</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>counterSize</name>
- <value>32</value>
- </parameter>
- <parameter>
- <name>fixedPeriod</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>loadValue</name>
- <value>124999</value>
- </parameter>
- <parameter>
- <name>mult</name>
- <value>0.001</value>
- </parameter>
- <parameter>
- <name>period</name>
- <value>1</value>
- </parameter>
- <parameter>
- <name>periodUnits</name>
- <value>MSEC</value>
- </parameter>
- <parameter>
- <name>periodUnitsString</name>
- <value>ms</value>
- </parameter>
- <parameter>
- <name>resetOutput</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>slave_address_width</name>
- <value>3</value>
- </parameter>
- <parameter>
- <name>snapshot</name>
- <value>true</value>
- </parameter>
- <parameter>
- <name>systemFrequency</name>
- <value>125000000</value>
- </parameter>
- <parameter>
- <name>ticksPerSec</name>
- <value>1000.0</value>
- </parameter>
- <parameter>
- <name>timeoutPulseOutput</name>
- <value>false</value>
- </parameter>
- <parameter>
- <name>timerPreset</name>
- <value>FULL_FEATURED</value>
- </parameter>
- <parameter>
- <name>valueInSecond</name>
- <value>0.001</value>
- </parameter>
- <parameter>
- <name>watchdogPulse</name>
- <value>2</value>
- </parameter>
- </parameters>
- <interconnectAssignments></interconnectAssignments>
- <className>altera_avalon_timer</className>
- <version>17.0</version>
- <name>qsys_arts_unb2b_sc3_timer_0</name>
- <uniqueName>qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy</uniqueName>
- <nonce>0</nonce>
- <incidentConnections></incidentConnections>
- <path>qsys_arts_unb2b_sc3_timer_0.qsys_arts_unb2b_sc3_timer_0</path>
- </instanceData>
- <children></children>
- </node>
- </children>
-</node>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.qip b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.qip
deleted file mode 100644
index 3ae4e09107af321ec1b1b517f700d5a66d01932e..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.qip
+++ /dev/null
@@ -1,57 +0,0 @@
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_TOOL_NAME "QsysPrimePro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_TOOL_VERSION "17.0.2"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_TOOL_ENV "QsysPrimePro"
-set_global_assignment -library "qsys_arts_unb2b_sc3_timer_0" -name SOPCINFO_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_timer_0.sopcinfo"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name SLD_INFO "QSYS_NAME qsys_arts_unb2b_sc3_timer_0 HAS_SOPCINFO 1 GENERATION_ID 1527684117"
-set_global_assignment -library "qsys_arts_unb2b_sc3_timer_0" -name MISC_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_timer_0.cmp"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_timer_0" -name SLD_FILE [file join $::quartus(qip_path) "qsys_arts_unb2b_sc3_timer_0.regmap"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_TARGETED_DEVICE_FAMILY "Arria 10"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_GENERATED_DEVICE_FAMILY "{Arria 10}"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_QSYS_MODE "STANDALONE"
-set_global_assignment -name SYNTHESIS_ONLY_QIP ON
-set_global_assignment -library "qsys_arts_unb2b_sc3_timer_0" -name MISC_FILE [file join $::quartus(qip_path) "../qsys_arts_unb2b_sc3_timer_0.ip"]
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM190aW1lcl8wX2FsdGVyYV9hdmFsb25fdGltZXJfMTcwX2p3bGF1dXk="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_DISPLAY_NAME "SW50ZXJ2YWwgVGltZXI="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_VERSION "MTcuMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "YWx3YXlzUnVu::ZmFsc2U=::Tm8gU3RhcnQvU3RvcCBjb250cm9sIGJpdHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "Y291bnRlclNpemU=::MzI=::Q291bnRlciBTaXpl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "Zml4ZWRQZXJpb2Q=::ZmFsc2U=::Rml4ZWQgcGVyaW9k"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "cGVyaW9k::MQ==::UGVyaW9k"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "cGVyaW9kVW5pdHM=::TVNFQw==::VW5pdHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "cmVzZXRPdXRwdXQ=::ZmFsc2U=::U3lzdGVtIHJlc2V0IG9uIHRpbWVvdXQgKFdhdGNoZG9nKQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "c25hcHNob3Q=::dHJ1ZQ==::UmVhZGFibGUgc25hcHNob3Q="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "dGltZW91dFB1bHNlT3V0cHV0::ZmFsc2U=::VGltZW91dCBwdWxzZSAoMSBjbG9jayB3aWRlKQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "c3lzdGVtRnJlcXVlbmN5::MTI1MDAwMDAw::c3lzdGVtRnJlcXVlbmN5"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "d2F0Y2hkb2dQdWxzZQ==::Mg==::V2F0Y2hkb2cgVGltZXIgUHVsc2UgTGVuZ3Ro"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "dGltZXJQcmVzZXQ=::RlVMTF9GRUFUVVJFRA==::UHJlc2V0cw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "cGVyaW9kVW5pdHNTdHJpbmc=::bXM=::cGVyaW9kVW5pdHNTdHJpbmc="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "dmFsdWVJblNlY29uZA==::MC4wMDE=::dmFsdWVJblNlY29uZA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "bG9hZFZhbHVl::MTI0OTk5::bG9hZFZhbHVl"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "bXVsdA==::MC4wMDE=::bXVsdA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "dGlja3NQZXJTZWM=::MTAwMC4w::dGlja3NQZXJTZWM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_PARAMETER "c2xhdmVfYWRkcmVzc193aWR0aA==::Mw==::c2xhdmVfYWRkcmVzc193aWR0aA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_GROUP "UHJvY2Vzc29ycyBhbmQgUGVyaXBoZXJhbHMvUGVyaXBoZXJhbHM="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL3NmbzE0MDA3ODc5NTI5MzIvaWdhMTQwMTM5ODY0NDk1Mw=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_COMPONENT_DOCUMENTATION_LINK "aHR0cHM6Ly9kb2N1bWVudGF0aW9uLmFsdGVyYS5jb20vIy9saW5rL2hjbzE0MjE2OTgwNDIwODcvaGNvMTQyMTY5NzY4OTMwMA=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_NAME "cXN5c19hcnRzX3VuYjJiX3NjM190aW1lcl8w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_DISPLAY_NAME "c3lzdGVt"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_REPORT_HIERARCHY "On"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_VERSION "MS4w"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTUyNzY4NDExNw==::QXV0byBHRU5FUkFUSU9OX0lE"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::QXJyaWEgMTA=::QXV0byBERVZJQ0VfRkFNSUxZ"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::MTBBWDExNVUyRjQ1RTFTRw==::QXV0byBERVZJQ0U="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::MQ==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4="
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0" -library "qsys_arts_unb2b_sc3_timer_0" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4="
-
-set_global_assignment -library "altera_avalon_timer_170" -name VERILOG_FILE [file join $::quartus(qip_path) "altera_avalon_timer_170/synth/qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy.v"]
-set_global_assignment -library "qsys_arts_unb2b_sc3_timer_0" -name VHDL_FILE [file join $::quartus(qip_path) "synth/qsys_arts_unb2b_sc3_timer_0.vhd"]
-
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_TOOL_NAME "altera_avalon_timer"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_TOOL_VERSION "17.0"
-set_global_assignment -entity "qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy" -library "altera_avalon_timer_170" -name IP_TOOL_ENV "QsysPrimePro"
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.regmap b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.regmap
deleted file mode 100644
index 6037b4c45a65905fd7558c563655e9449a037959..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.regmap
+++ /dev/null
@@ -1,350 +0,0 @@
-<?xml version="1.0"?>
-<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
-<name>qsys_arts_unb2b_sc3_timer_0</name>
-<peripherals>
-<peripheral>
- <name>qsys_arts_unb2b_sc3_timer_0_s1_altera_avalon_timer</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>16</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>status</name>
- <displayName>Status</displayName>
- <description>The status register has two defined bits. TO (timeout), RUN</description>
- <addressOffset>0x0</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- <fields>
- <field><name>TO</name>
- <description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <readAction>clear</readAction>
- </field>
- <field><name>RUN</name>
- <description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
- a write operation to the status register.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>Reserved</name>
- <description>Reserved</description>
- <bitOffset>2</bitOffset>
- <bitWidth>14</bitWidth>
- <access>read-write</access>
- <parameters>
- <parameter>
- <name>Reserved</name>
- <value>true</value>
- </parameter>
- </parameters>
- </field>
- </fields>
- </register>
- <register>
- <name>control</name>
- <description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
- <addressOffset>0x1</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <reset>
- <value>0x0</value>
- </reset>
- <field>
- <name>ITO</name>
- <description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CONT</name>
- <description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>START</name>
- <description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>STOP</name>
- <description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>Reserved</name>
- <description>Reserved</description>
- <bitOffset>4</bitOffset>
- <bitWidth>12</bitWidth>
- <access>read-write</access>
- <parameters>
- <parameter>
- <name>Reserved</name>
- <value>true</value>
- </parameter>
- </parameters>
- </field>
- </register>
- <register>
- <name>${period_name_0}</name>
- <description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
- <addressOffset>0x2</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_name_0_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${period_name_1}</name>
- <description></description>
- <addressOffset>0x3</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_name_1_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${period_snap_0}</name>
- <description></description>
- <addressOffset>0x4</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_snap_0_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${period_snap_1}</name>
- <description></description>
- <addressOffset>0x5</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_snap_1_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_0}</name>
- <description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
- <addressOffset>0x6</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_1}</name>
- <description></description>
- <addressOffset>0x7</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_2}</name>
- <description></description>
- <addressOffset>0x8</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_3}</name>
- <description></description>
- <addressOffset>0x9</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>qsys_arts_unb2b_sc3_timer_0_qsys_arts_unb2b_sc3_timer_0_s1_altera_avalon_timer</name><baseAddress>0x00000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>16</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>status</name>
- <displayName>Status</displayName>
- <description>The status register has two defined bits. TO (timeout), RUN</description>
- <addressOffset>0x0</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- <fields>
- <field><name>TO</name>
- <description>The TO (timeout) bit is set to 1 when the internal counter reaches zero. Once set by a timeout event, the TO bit stays set until explicitly cleared by a master peripheral. Write zero to the status register to clear the TO bit.</description>
- <bitOffset>0x0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- <readAction>clear</readAction>
- </field>
- <field><name>RUN</name>
- <description>The RUN bit reads as 1 when the internal counter is running; otherwise this bit reads as 0. The RUN bit is not changed by
- a write operation to the status register.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>Reserved</name>
- <description>Reserved</description>
- <bitOffset>2</bitOffset>
- <bitWidth>14</bitWidth>
- <access>read-write</access>
- <parameters>
- <parameter>
- <name>Reserved</name>
- <value>true</value>
- </parameter>
- </parameters>
- </field>
- </fields>
- </register>
- <register>
- <name>control</name>
- <description>The control register has four defined bits. ITO (Timeout Interrupt), CONT (continue), START, STOP</description>
- <addressOffset>0x1</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <reset>
- <value>0x0</value>
- </reset>
- <field>
- <name>ITO</name>
- <description>If the ITO bit is 1, the interval timer core generates an IRQ when the status register's TO bit is 1. When the ITO bit is 0, the timer does not generate IRQs.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CONT</name>
- <description>The CONT (continuous) bit determines how the internal counter behaves when it reaches zero. If the CONT bit is 1, the counter runs continuously until it is stopped by the STOP bit. If CONT is 0, the counter stops after it reaches zero. When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the CONT bit.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>START</name>
- <description>Writing a 1 to the START bit starts the internal counter running (counting down). The START bit is an event bit that enables the counter when a write operation is performed. If the timer is stopped, writing a 1 to the START bit causes the timer to restart counting from the number currently stored in its counter. If the timer is already running, writing a 1 to START has no effect. Writing 0 to the START bit has no effect.</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>STOP</name>
- <description>Writing a 1 to the STOP bit stops the internal counter. The STOP bit is an event bit that causes the counter to stop when a write operation is performed. If the timer is already stopped, writing a 1 to STOP has no effect. Writing a 0 to the stop bit has no effect. If the timer hardware is configured with Start/Stop control bits off, writing the STOP bit has no effect.</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>Reserved</name>
- <description>Reserved</description>
- <bitOffset>4</bitOffset>
- <bitWidth>12</bitWidth>
- <access>read-write</access>
- <parameters>
- <parameter>
- <name>Reserved</name>
- <value>true</value>
- </parameter>
- </parameters>
- </field>
- </register>
- <register>
- <name>${period_name_0}</name>
- <description>The period_n registers together store the timeout period value when a write operation to one of the period_n register or the internal counter reaches 0. The timer's actual period is one cycle greater than the value stored in the period_n registers because the counter assumes the value zero for one clock cycle. Writing to one of the period_n registers stops the internal counter, except when the hardware is configured with Start/Stop control bits off. If Start/Stop control bits is off, writing either register does not stop the counter. When the hardware is configured with Writeable period disabled, writing to one of the period_n registers causes the counter to reset to the fixed Timeout Period specified at system generation time.</description>
- <addressOffset>0x2</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_name_0_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${period_name_1}</name>
- <description></description>
- <addressOffset>0x3</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_name_1_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${period_snap_0}</name>
- <description></description>
- <addressOffset>0x4</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_snap_0_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${period_snap_1}</name>
- <description></description>
- <addressOffset>0x5</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>${period_snap_1_reset_value}</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_0}</name>
- <description>A master peripheral may request a coherent snapshot of the current internal counter by performing a write operation (write-data ignored) to one of the snap_n registers. When a write occurs, the value of the counter is copied to snap_n registers. The snapshot occurs whether or not the counter is running. Requesting a snapshot does not change the internal counter's operation.</description>
- <addressOffset>0x6</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_1}</name>
- <description></description>
- <addressOffset>0x7</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_2}</name>
- <description></description>
- <addressOffset>0x8</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- <register>
- <name>${snap_3}</name>
- <description></description>
- <addressOffset>0x9</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <resetMask>0xffff</resetMask>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
\ No newline at end of file
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.sopcinfo b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.sopcinfo
deleted file mode 100644
index 339cdb017f5b97be3750dc428fe7d6f0774ac3ba..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.sopcinfo
+++ /dev/null
@@ -1,958 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<EnsembleReport
- name="qsys_arts_unb2b_sc3_timer_0"
- kind="qsys_arts_unb2b_sc3_timer_0"
- version="1.0"
- fabric="QSYS">
- <!-- Format version 17.0.2 297 (Future versions may contain additional information.) -->
- <!-- 2018.05.30.14:41:57 -->
- <!-- A collection of modules and connections -->
- <parameter name="AUTO_GENERATION_ID">
- <type>java.lang.Integer</type>
- <value>1527684117</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>GENERATION_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_UNIQUE_ID">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>UNIQUE_ID</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_FAMILY">
- <type>java.lang.String</type>
- <value>ARRIA10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE">
- <type>java.lang.String</type>
- <value>10AX115U2F45E1SG</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_DEVICE_SPEEDGRADE">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
- </parameter>
- <parameter name="AUTO_CLK_CLOCK_RATE">
- <type>java.lang.Long</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_CLOCK_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="AUTO_CLK_RESET_DOMAIN">
- <type>java.lang.Integer</type>
- <value>-1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>RESET_DOMAIN</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>Arria 10</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <module
- name="qsys_arts_unb2b_sc3_timer_0"
- kind="altera_avalon_timer"
- version="17.0"
- path="qsys_arts_unb2b_sc3_timer_0">
- <!-- Describes a single module. Module parameters are
-the requested settings for a module instance. -->
- <assignment>
- <name>embeddedsw.CMacro.ALWAYS_RUN</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.COUNTER_SIZE</name>
- <value>32</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.FIXED_PERIOD</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.FREQ</name>
- <value>125000000</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.LOAD_VALUE</name>
- <value>124999</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.MULT</name>
- <value>0.001</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.PERIOD</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.PERIOD_UNITS</name>
- <value>ms</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.RESET_OUTPUT</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.SNAPSHOT</name>
- <value>1</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.TICKS_PER_SEC</name>
- <value>1000</value>
- </assignment>
- <assignment>
- <name>embeddedsw.CMacro.TIMEOUT_PULSE_OUTPUT</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.compatible</name>
- <value>altr,timer-1.0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.group</name>
- <value>timer</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.name</name>
- <value>timer</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.params.clock-frequency</name>
- <value>125000000</value>
- </assignment>
- <assignment>
- <name>embeddedsw.dts.vendor</name>
- <value>altr</value>
- </assignment>
- <parameter name="alwaysRun">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="counterSize">
- <type>int</type>
- <value>32</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="fixedPeriod">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="period">
- <type>java.lang.String</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="periodUnits">
- <type>java.lang.String</type>
- <value>MSEC</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="resetOutput">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="snapshot">
- <type>boolean</type>
- <value>true</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timeoutPulseOutput">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="systemFrequency">
- <type>long</type>
- <value>125000000</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- <sysinfo_type>CLOCK_RATE</sysinfo_type>
- <sysinfo_arg>clk</sysinfo_arg>
- </parameter>
- <parameter name="watchdogPulse">
- <type>int</type>
- <value>2</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timerPreset">
- <type>java.lang.String</type>
- <value>FULL_FEATURED</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="periodUnitsString">
- <type>java.lang.String</type>
- <value>ms</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="valueInSecond">
- <type>double</type>
- <value>0.001</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="loadValue">
- <type>java.lang.String</type>
- <value>124999</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="mult">
- <type>double</type>
- <value>0.001</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ticksPerSec">
- <type>double</type>
- <value>1000.0</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="slave_address_width">
- <type>int</type>
- <value>3</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <interface name="clk" kind="clock_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="externallyDriven">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="ptfSchematicName">
- <type>java.lang.String</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRateKnown">
- <type>java.lang.Boolean</type>
- <value>true</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="clockRate">
- <type>java.lang.Long</type>
- <value>125000000</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <type>clock</type>
- <isStart>false</isStart>
- <port>
- <name>clk</name>
- <direction>Input</direction>
- <width>1</width>
- <role>clk</role>
- </port>
- </interface>
- <interface name="reset" kind="reset_sink" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="synchronousEdges">
- <type>com.altera.sopcmodel.reset.Reset$Edges</type>
- <value>DEASSERT</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>reset</type>
- <isStart>false</isStart>
- <port>
- <name>reset_n</name>
- <direction>Input</direction>
- <width>1</width>
- <role>reset_n</role>
- </port>
- </interface>
- <interface name="s1" kind="avalon_slave" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <assignment>
- <name>embeddedsw.configuration.isFlash</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isMemoryDevice</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isNonVolatileStorage</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isPrintableDevice</name>
- <value>0</value>
- </assignment>
- <assignment>
- <name>embeddedsw.configuration.isTimerDevice</name>
- <value>1</value>
- </assignment>
- <parameter name="addressAlignment">
- <type>com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment</type>
- <value>NATIVE</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressGroup">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressSpan">
- <type>java.math.BigInteger</type>
- <value>8</value>
- <derived>true</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="addressUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="alwaysBurstMaxBurst">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bitsPerSymbol">
- <type>int</type>
- <value>8</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedAddressOffset">
- <type>java.math.BigInteger</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToMaster">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstOnBurstBoundariesOnly">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="burstcountUnits">
- <type>com.altera.sopcmodel.avalon.EAddrBurstUnits</type>
- <value>WORDS</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="constantBurstBehavior">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="explicitAddressSpan">
- <type>java.math.BigInteger</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="holdTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="interleaveBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isBigEndian">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isFlash">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isMemoryDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="isNonVolatileStorage">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="linewrapBursts">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingReadTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="maximumPendingWriteTransactions">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumReadLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumResponseLatency">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="minimumUninterruptedRunLength">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="prSafe">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="printableDevice">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitStates">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="readWaitTime">
- <type>int</type>
- <value>1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerIncomingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="registerOutgoingSignals">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="setupTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="timingUnits">
- <type>com.altera.sopcmodel.avalon.TimingUnits</type>
- <value>Cycles</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="transparentBridge">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="waitrequestAllowance">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>false</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="wellBehavedWaitrequest">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeLatency">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitStates">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="writeWaitTime">
- <type>int</type>
- <value>0</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>avalon</type>
- <isStart>false</isStart>
- <port>
- <name>address</name>
- <direction>Input</direction>
- <width>3</width>
- <role>address</role>
- </port>
- <port>
- <name>writedata</name>
- <direction>Input</direction>
- <width>16</width>
- <role>writedata</role>
- </port>
- <port>
- <name>readdata</name>
- <direction>Output</direction>
- <width>16</width>
- <role>readdata</role>
- </port>
- <port>
- <name>chipselect</name>
- <direction>Input</direction>
- <width>1</width>
- <role>chipselect</role>
- </port>
- <port>
- <name>write_n</name>
- <direction>Input</direction>
- <width>1</width>
- <role>write_n</role>
- </port>
- </interface>
- <interface name="irq" kind="interrupt_sender" version="17.0">
- <!-- The connection points exposed by a module instance for the
-particular module parameters. Connection points and their
-parameters are a RESULT of the module parameters. -->
- <parameter name="associatedAddressablePoint">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value>qsys_arts_unb2b_sc3_timer_0.s1</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedClock">
- <type>java.lang.String</type>
- <value>clk</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="associatedReset">
- <type>java.lang.String</type>
- <value>reset</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgedReceiverOffset">
- <type>java.lang.Integer</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="bridgesToReceiver">
- <type>com.altera.entityinterfaces.IConnectionPoint</type>
- <value></value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="irqScheme">
- <type>com.altera.sopcmodel.interrupt.InterruptConnectionPoint$EIrqScheme</type>
- <value>NONE</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>false</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="deviceFamily">
- <type>java.lang.String</type>
- <value>UNKNOWN</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <parameter name="generateLegacySim">
- <type>boolean</type>
- <value>false</value>
- <derived>false</derived>
- <enabled>true</enabled>
- <visible>true</visible>
- <valid>true</valid>
- </parameter>
- <type>interrupt</type>
- <isStart>false</isStart>
- <port>
- <name>irq</name>
- <direction>Output</direction>
- <width>1</width>
- <role>irq</role>
- </port>
- </interface>
- </module>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>altera_avalon_timer</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IModule</subtype>
- <displayName>Interval Timer</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>clock_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Clock Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>reset_sink</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Reset Input</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>avalon_slave</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Avalon Memory Mapped Slave</displayName>
- <version>17.0</version>
- </plugin>
- <plugin>
- <instanceCount>1</instanceCount>
- <name>interrupt_sender</name>
- <type>com.altera.entityinterfaces.IElementClass</type>
- <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
- <displayName>Interrupt Sender</displayName>
- <version>17.0</version>
- </plugin>
- <reportVersion>17.0.2 297</reportVersion>
- <uniqueIdentifier></uniqueIdentifier>
-</EnsembleReport>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.xml b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.xml
deleted file mode 100644
index 7aa4f6130bd694bb721dec292c37613a653a9e27..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0.xml
+++ /dev/null
@@ -1,209 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<deploy
- date="2018.05.30.14:42:00"
- outputDirectory="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/">
- <perimeter>
- <parameter
- name="AUTO_GENERATION_ID"
- type="Integer"
- defaultValue="0"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_UNIQUE_ID"
- type="String"
- defaultValue=""
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_FAMILY"
- type="String"
- defaultValue="Arria 10"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE"
- type="String"
- defaultValue="10AX115U2F45E1SG"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_DEVICE_SPEEDGRADE"
- type="String"
- defaultValue="1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_CLOCK_RATE"
- type="Long"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_CLOCK_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <parameter
- name="AUTO_CLK_RESET_DOMAIN"
- type="Integer"
- defaultValue="-1"
- onHdl="0"
- affectsHdl="1" />
- <interface name="clk" kind="clock" start="0">
- <property name="clockRate" value="0" />
- <property name="externallyDriven" value="false" />
- <property name="ptfSchematicName" value="" />
- <port name="clk" direction="input" role="clk" width="1" />
- </interface>
- <interface name="irq" kind="interrupt" start="0">
- <property
- name="associatedAddressablePoint"
- value="qsys_arts_unb2b_sc3_timer_0.s1" />
- <property name="associatedClock" value="clk" />
- <property name="associatedReset" value="reset" />
- <property name="bridgedReceiverOffset" value="0" />
- <property name="bridgesToReceiver" value="" />
- <property name="irqScheme" value="NONE" />
- <port name="irq" direction="output" role="irq" width="1" />
- </interface>
- <interface name="reset" kind="reset" start="0">
- <property name="associatedClock" value="clk" />
- <property name="synchronousEdges" value="DEASSERT" />
- <port name="reset_n" direction="input" role="reset_n" width="1" />
- </interface>
- <interface name="s1" kind="avalon" start="0">
- <property name="addressAlignment" value="NATIVE" />
- <property name="addressGroup" value="0" />
- <property name="addressSpan" value="8" />
- <property name="addressUnits" value="WORDS" />
- <property name="alwaysBurstMaxBurst" value="false" />
- <property name="associatedClock" value="clk" />
- <property name="associatedReset" value="reset" />
- <property name="bitsPerSymbol" value="8" />
- <property name="bridgedAddressOffset" value="0" />
- <property name="bridgesToMaster" value="" />
- <property name="burstOnBurstBoundariesOnly" value="false" />
- <property name="burstcountUnits" value="WORDS" />
- <property name="constantBurstBehavior" value="false" />
- <property name="explicitAddressSpan" value="0" />
- <property name="holdTime" value="0" />
- <property name="interleaveBursts" value="false" />
- <property name="isBigEndian" value="false" />
- <property name="isFlash" value="false" />
- <property name="isMemoryDevice" value="false" />
- <property name="isNonVolatileStorage" value="false" />
- <property name="linewrapBursts" value="false" />
- <property name="maximumPendingReadTransactions" value="0" />
- <property name="maximumPendingWriteTransactions" value="0" />
- <property name="minimumReadLatency" value="1" />
- <property name="minimumResponseLatency" value="1" />
- <property name="minimumUninterruptedRunLength" value="1" />
- <property name="prSafe" value="false" />
- <property name="printableDevice" value="false" />
- <property name="readLatency" value="0" />
- <property name="readWaitStates" value="1" />
- <property name="readWaitTime" value="1" />
- <property name="registerIncomingSignals" value="false" />
- <property name="registerOutgoingSignals" value="false" />
- <property name="setupTime" value="0" />
- <property name="timingUnits" value="Cycles" />
- <property name="transparentBridge" value="false" />
- <property name="waitrequestAllowance" value="0" />
- <property name="wellBehavedWaitrequest" value="false" />
- <property name="writeLatency" value="0" />
- <property name="writeWaitStates" value="0" />
- <property name="writeWaitTime" value="0" />
- <port name="address" direction="input" role="address" width="3" />
- <port name="writedata" direction="input" role="writedata" width="16" />
- <port name="readdata" direction="output" role="readdata" width="16" />
- <port name="chipselect" direction="input" role="chipselect" width="1" />
- <port name="write_n" direction="input" role="write_n" width="1" />
- </interface>
- </perimeter>
- <entity
- kind="qsys_arts_unb2b_sc3_timer_0"
- version="1.0"
- name="qsys_arts_unb2b_sc3_timer_0">
- <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
- <parameter name="AUTO_GENERATION_ID" value="1527684117" />
- <parameter name="AUTO_DEVICE" value="10AX115U2F45E1SG" />
- <parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
- <parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
- <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
- <parameter name="AUTO_UNIQUE_ID" value="" />
- <parameter name="AUTO_DEVICE_SPEEDGRADE" value="1" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/synth/qsys_arts_unb2b_sc3_timer_0.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/synth/qsys_arts_unb2b_sc3_timer_0.vhd"
- attributes="CONTAINS_INLINE_CONFIGURATION" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0.ip" />
- </sourceFiles>
- <childSourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
- </childSourceFiles>
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_timer_0">"Generating: qsys_arts_unb2b_sc3_timer_0"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_timer_0">"Generating: qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_timer_0">Starting RTL generation for module 'qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy'</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_timer_0"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64//perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64//perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy --dir=/tmp/alt7681_6931282645914172388.dir/0008_qsys_arts_unb2b_sc3_timer_0_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0008_qsys_arts_unb2b_sc3_timer_0_gen//qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy_component_configuration.pl --do_build_sim=0 ]</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_timer_0">Done RTL generation for module 'qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy'</message>
- </messages>
- </entity>
- <entity
- kind="altera_avalon_timer"
- version="17.0"
- name="qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy">
- <parameter name="loadValue" value="124999" />
- <parameter name="timeoutPulseOutput" value="false" />
- <parameter name="period" value="1" />
- <parameter name="periodUnitsString" value="ms" />
- <parameter name="mult" value="0.001" />
- <parameter name="ticksPerSec" value="1000.0" />
- <parameter name="systemFrequency" value="125000000" />
- <parameter name="alwaysRun" value="false" />
- <parameter name="valueInSecond" value="0.001" />
- <parameter name="fixedPeriod" value="false" />
- <parameter name="counterSize" value="32" />
- <parameter name="periodUnits" value="MSEC" />
- <parameter name="watchdogPulse" value="2" />
- <parameter name="slave_address_width" value="3" />
- <parameter name="resetOutput" value="false" />
- <parameter name="snapshot" value="true" />
- <parameter name="timerPreset" value="FULL_FEATURED" />
- <generatedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/altera_avalon_timer_170/synth/qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy.v"
- attributes="" />
- </generatedFiles>
- <childGeneratedFiles>
- <file
- path="/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/altera_avalon_timer_170/synth/qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy.v"
- attributes="" />
- </childGeneratedFiles>
- <sourceFiles>
- <file
- path="/home/software/Altera/17.0/ip/altera/sopc_builder_ip/altera_avalon_timer/altera_avalon_timer_hw.tcl" />
- </sourceFiles>
- <childSourceFiles/>
- <instantiator
- instantiator="qsys_arts_unb2b_sc3_timer_0"
- as="qsys_arts_unb2b_sc3_timer_0" />
- <messages>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_timer_0">"Generating: qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy"</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_timer_0">Starting RTL generation for module 'qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy'</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_timer_0"> Generation command is [exec /home/software/Altera/17.0/quartus/linux64//perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64//perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy --dir=/tmp/alt7681_6931282645914172388.dir/0008_qsys_arts_unb2b_sc3_timer_0_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0008_qsys_arts_unb2b_sc3_timer_0_gen//qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy_component_configuration.pl --do_build_sim=0 ]</message>
- <message level="Info" culprit="qsys_arts_unb2b_sc3_timer_0">Done RTL generation for module 'qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy'</message>
- </messages>
- </entity>
-</deploy>
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_bb.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_bb.v
deleted file mode 100644
index 48cd77b2d2aa0251369bee125c2dfdfd91c6298c..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_bb.v
+++ /dev/null
@@ -1,20 +0,0 @@
-
-module qsys_arts_unb2b_sc3_timer_0 (
- clk,
- irq,
- reset_n,
- address,
- writedata,
- readdata,
- chipselect,
- write_n);
-
- input clk;
- output irq;
- input reset_n;
- input [2:0] address;
- input [15:0] writedata;
- output [15:0] readdata;
- input chipselect;
- input write_n;
-endmodule
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_generation.rpt b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_generation.rpt
deleted file mode 100644
index 7b2c6d939005e2c0e39ca62fa0cb8646db2b43ac..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_generation.rpt
+++ /dev/null
@@ -1,28 +0,0 @@
-Info: Generated by version: 17.0.2 build 297
-Info: Starting: Create block symbol file (.bsf)
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0.ip --block-symbol-file --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys-generate succeeded.
-Info: Finished: Create block symbol file (.bsf)
-Info:
-Info: Starting: Create HDL design files for synthesis
-Info: qsys-generate /home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0.ip --synthesis=VHDL --output-directory=/home/donker/svn/UniBoard_FP7/RadioHDL/trunk/build/unb2b/quartus/arts_unb2b_sc3/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0 --family="Arria 10" --part=10AX115U2F45E1SG
-Info: qsys_arts_unb2b_sc3_timer_0: "Transforming system: qsys_arts_unb2b_sc3_timer_0"
-Info: qsys_arts_unb2b_sc3_timer_0: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_timer_0: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_timer_0: Running transform generation_view_transform
-Info: qsys_arts_unb2b_sc3_timer_0: Running transform generation_view_transform took 0.000s
-Info: qsys_arts_unb2b_sc3_timer_0: Running transform interconnect_transform_chooser
-Info: qsys_arts_unb2b_sc3_timer_0: Running transform interconnect_transform_chooser took 0.008s
-Info: qsys_arts_unb2b_sc3_timer_0: "Naming system components in system: qsys_arts_unb2b_sc3_timer_0"
-Info: qsys_arts_unb2b_sc3_timer_0: "Processing generation queue"
-Info: qsys_arts_unb2b_sc3_timer_0: "Generating: qsys_arts_unb2b_sc3_timer_0"
-Info: qsys_arts_unb2b_sc3_timer_0: "Generating: qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy"
-Info: qsys_arts_unb2b_sc3_timer_0: Starting RTL generation for module 'qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy'
-Info: qsys_arts_unb2b_sc3_timer_0: Generation command is [exec /home/software/Altera/17.0/quartus/linux64//perl/bin/perl -I /home/software/Altera/17.0/quartus/linux64//perl/lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin/europa -I /home/software/Altera/17.0/quartus/sopc_builder/bin/perl_lib -I /home/software/Altera/17.0/quartus/sopc_builder/bin -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer -- /home/software/Altera/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_timer/generate_rtl.pl --name=qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy --dir=/tmp/alt7681_6931282645914172388.dir/0008_qsys_arts_unb2b_sc3_timer_0_gen/ --quartus_dir=/home/software/Altera/17.0/quartus --verilog --config=/tmp/alt7681_6931282645914172388.dir/0008_qsys_arts_unb2b_sc3_timer_0_gen//qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy_component_configuration.pl --do_build_sim=0 ]
-Info: qsys_arts_unb2b_sc3_timer_0: Done RTL generation for module 'qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy'
-Info: qsys_arts_unb2b_sc3_timer_0: Done "qsys_arts_unb2b_sc3_timer_0" with 2 modules, 2 files
-Info: qsys-generate succeeded.
-Info: Finished: Create HDL design files for synthesis
-Info: Starting: Generate IP Core documentation.
-Info: No documentation filesets were found for components in qsys_arts_unb2b_sc3_timer_0. No files generated.
-Info: Finished: Generate IP Core documentation.
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_inst.v b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_inst.v
deleted file mode 100644
index 577878425e15e7a1d844256c400b5b645acd6abf..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_inst.v
+++ /dev/null
@@ -1,11 +0,0 @@
- qsys_arts_unb2b_sc3_timer_0 u0 (
- .clk (_connected_to_clk_), // clk.clk
- .irq (_connected_to_irq_), // irq.irq
- .reset_n (_connected_to_reset_n_), // reset.reset_n
- .address (_connected_to_address_), // s1.address
- .writedata (_connected_to_writedata_), // .writedata
- .readdata (_connected_to_readdata_), // .readdata
- .chipselect (_connected_to_chipselect_), // .chipselect
- .write_n (_connected_to_write_n_) // .write_n
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_inst.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_inst.vhd
deleted file mode 100644
index fb1c5ffdef0a0c70028c2051b3db7bab44e5e974..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/qsys_arts_unb2b_sc3_timer_0_inst.vhd
+++ /dev/null
@@ -1,25 +0,0 @@
- component qsys_arts_unb2b_sc3_timer_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
- );
- end component qsys_arts_unb2b_sc3_timer_0;
-
- u0 : component qsys_arts_unb2b_sc3_timer_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- writedata => CONNECTED_TO_writedata, -- .writedata
- readdata => CONNECTED_TO_readdata, -- .readdata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write_n => CONNECTED_TO_write_n -- .write_n
- );
-
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/synth/qsys_arts_unb2b_sc3_timer_0.vhd b/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/synth/qsys_arts_unb2b_sc3_timer_0.vhd
deleted file mode 100644
index 87ec00dab3f7517888e584c4ded7423a26cf0853..0000000000000000000000000000000000000000
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0/synth/qsys_arts_unb2b_sc3_timer_0.vhd
+++ /dev/null
@@ -1,53 +0,0 @@
--- qsys_arts_unb2b_sc3_timer_0.vhd
-
--- Generated using ACDS version 17.0.2 297
-
-library IEEE;
-library altera_avalon_timer_170;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity qsys_arts_unb2b_sc3_timer_0 is
- port (
- clk : in std_logic := '0'; -- clk.clk
- irq : out std_logic; -- irq.irq
- reset_n : in std_logic := '0'; -- reset.reset_n
- address : in std_logic_vector(2 downto 0) := (others => '0'); -- s1.address
- writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
- readdata : out std_logic_vector(15 downto 0); -- .readdata
- chipselect : in std_logic := '0'; -- .chipselect
- write_n : in std_logic := '0' -- .write_n
- );
-end entity qsys_arts_unb2b_sc3_timer_0;
-
-architecture rtl of qsys_arts_unb2b_sc3_timer_0 is
- component qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy_cmp is
- port (
- clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X'; -- write_n
- irq : out std_logic -- irq
- );
- end component qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy_cmp;
-
- for qsys_arts_unb2b_sc3_timer_0 : qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy_cmp
- use entity altera_avalon_timer_170.qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy;
-begin
-
- qsys_arts_unb2b_sc3_timer_0 : component qsys_arts_unb2b_sc3_timer_0_altera_avalon_timer_170_jwlauuy_cmp
- port map (
- clk => clk, -- clk.clk
- reset_n => reset_n, -- reset.reset_n
- address => address, -- s1.address
- writedata => writedata, -- .writedata
- readdata => readdata, -- .readdata
- chipselect => chipselect, -- .chipselect
- write_n => write_n, -- .write_n
- irq => irq -- irq.irq
- );
-
-end architecture rtl; -- of qsys_arts_unb2b_sc3_timer_0
diff --git a/applications/arts/designs/arts_unb2b_sc3/quartus/qsys_arts_unb2b_sc3.qsys b/applications/arts/designs/arts_unb2b_sc3/quartus/qsys_arts_unb2b_sc3.qsys
index 2d28e2a567b5f11d6cae44800662f6a1ca5d3038..e8ee5392eae2fc2ac5d6c6992068fd324f3e71d8 100644
--- a/applications/arts/designs/arts_unb2b_sc3/quartus/qsys_arts_unb2b_sc3.qsys
+++ b/applications/arts/designs/arts_unb2b_sc3/quartus/qsys_arts_unb2b_sc3.qsys
@@ -10,9 +10,6 @@
tool="QsysPro" />
<parameter name="bonusData"><![CDATA[bonusData
{
- element $system
- {
- }
element avs_eth_0
{
datum _sortIndex
@@ -2808,30 +2805,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_avs_eth_2</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_avs_eth_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_avs_eth_2</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_2</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_avs_eth_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_avs_eth_2</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_2</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_avs_eth_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_avs_eth_2</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_2</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_avs_eth_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_2.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -4349,30 +4346,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_avs_eth_3</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_avs_eth_1</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_avs_eth_3</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_3</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_avs_eth_1</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_1</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_avs_eth_3</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_3</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_avs_eth_1</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_1</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_avs_eth_3</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_3</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_avs_eth_1</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_avs_eth_1</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_3.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_avs_eth_1.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -4585,30 +4582,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_clk_1</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_clk_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_clk_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_clk_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_clk_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_clk_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_clk_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_clk_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_clk_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_clk_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_clk_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_clk_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_clk_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_clk_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_clk_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -5866,30 +5863,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_cpu_1</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_cpu_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_cpu_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_cpu_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_cpu_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_cpu_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_cpu_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_cpu_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_cpu_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_cpu_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_cpu_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_cpu_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_cpu_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_cpu_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -6622,30 +6619,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_jtag_uart_1</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_jtag_uart_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_jtag_uart_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_jtag_uart_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_jtag_uart_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_jtag_uart_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_jtag_uart_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_jtag_uart_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_jtag_uart_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_jtag_uart_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_jtag_uart_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_jtag_uart_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_jtag_uart_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_jtag_uart_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_jtag_uart_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -7068,30 +7065,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_onchip_memory2_1</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_onchip_memory2_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_onchip_memory2_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_onchip_memory2_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_onchip_memory2_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_onchip_memory2_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_onchip_memory2_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_onchip_memory2_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_onchip_memory2_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_onchip_memory2_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_onchip_memory2_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_onchip_memory2_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_onchip_memory2_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_onchip_memory2_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_onchip_memory2_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -7780,30 +7777,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_pio_pps_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_pio_pps</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_pio_pps_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_pio_pps_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_pio_pps</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_pio_pps</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_pio_pps_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_pio_pps_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_pio_pps</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_pio_pps_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_pio_pps_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_pio_pps</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_pio_pps</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_pps.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -8395,30 +8392,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_pio_system_info_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_pio_system_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_pio_system_info_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_pio_system_info_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_pio_system_info</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_pio_system_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_pio_system_info_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_pio_system_info_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_pio_system_info</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_pio_system_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_pio_system_info_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_pio_system_info_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_pio_system_info</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_pio_system_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_system_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -8945,30 +8942,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_pio_wdi_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_pio_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_pio_wdi_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_pio_wdi_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_pio_wdi</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_pio_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_pio_wdi_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_pio_wdi_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_pio_wdi</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_pio_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_pio_wdi_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_pio_wdi_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_pio_wdi</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_pio_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_pio_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -9637,30 +9634,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -10252,30 +10249,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_dpmm_data_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_data_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_data_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_data_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_data_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_data_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_data_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -10867,30 +10864,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_epcs_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_epcs_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_epcs_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_epcs_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_epcs_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_epcs_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_epcs_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -11482,30 +11479,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_eth10g_qsfp_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -12097,30 +12094,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -12712,30 +12709,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -13982,30 +13979,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -14597,30 +14594,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_mmdp_data_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_data_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_data_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_data_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_data_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_data_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_data_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -15212,30 +15209,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_remu_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_remu_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_remu_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_remu_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_remu_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_remu_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_remu_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -15867,30 +15864,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_tr_10GbE_qsfp_ring.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -16482,30 +16479,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_unb_pmbus_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_unb_pmbus</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_unb_pmbus_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_pmbus_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_unb_pmbus_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_pmbus_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_unb_pmbus_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_pmbus_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_pmbus</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_pmbus_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_pmbus.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -17097,30 +17094,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_unb_sens_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_unb_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_unb_sens_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_sens_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_unb_sens_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_sens_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_unb_sens_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_sens_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_unb_sens</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_unb_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_unb_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -17712,30 +17709,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_reg_wdi_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_reg_wdi</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_wdi_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_wdi_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_wdi</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_wdi_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_wdi_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_reg_wdi_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_reg_wdi_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_reg_wdi</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_reg_wdi</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_reg_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -18327,30 +18324,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_rom_system_info_0</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_rom_system_info</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_rom_system_info_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_rom_system_info_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_rom_system_info</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_rom_system_info_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_rom_system_info_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_rom_system_info_0</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_rom_system_info_0</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_rom_system_info</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_rom_system_info</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info_0.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_rom_system_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -18997,30 +18994,30 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_arts_unb2b_sc3_timer_1</hdlLibraryName>
+ <hdlLibraryName>qsys_arts_unb2b_sc3_timer_0</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_timer_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_timer_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_timer_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_timer_0</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_timer_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_timer_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_timer_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_timer_0</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_arts_unb2b_sc3_timer_1</fileSetName>
- <fileSetFixedName>qsys_arts_unb2b_sc3_timer_1</fileSetFixedName>
+ <fileSetName>qsys_arts_unb2b_sc3_timer_0</fileSetName>
+ <fileSetFixedName>qsys_arts_unb2b_sc3_timer_0</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_1.ip</parameter>
+ <parameter name="logicalView">ip/qsys_arts_unb2b_sc3/qsys_arts_unb2b_sc3_timer_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
diff --git a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd
index 6b5c996bdac5c12415a499d1a04cbbfc8304f0e5..ec9178ba5f3638652556631663d00a1038614852 100644
--- a/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd
+++ b/applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3.vhd
@@ -117,22 +117,22 @@ ENTITY arts_unb2b_sc3 IS
PMBUS_ALERT : IN STD_LOGIC := '0';
-- front transceivers
- QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Input
- QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
- QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
-
- QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
- QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
- QSFP_RST : INOUT STD_LOGIC;
+ --QSFP_0_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0); -- Input
+ --QSFP_0_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_1_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_1_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_2_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_2_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_3_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_3_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_4_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_4_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_5_RX : IN STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+ --QSFP_5_TX : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.bus_w-1 downto 0);
+
+ --QSFP_SDA : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ --QSFP_SCL : INOUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp.i2c_w-1 downto 0);
+ --QSFP_RST : INOUT STD_LOGIC;
-- Leds
QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2_board_tr_qsfp_nof_leds-1 DOWNTO 0)