From bcac19a541b3b1a67a57a4f5e7fcffaccc3ad577 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Mon, 9 Mar 2015 13:48:29 +0000
Subject: [PATCH] Added generic for loopback enable -set nof_streams to 1 -
changed fofo-size definition
---
.../src/vhdl/compaan_unb1_dp_offload.vhd | 32 ++++++++++---------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/compaan_unb1_dp_offload.vhd b/applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/compaan_unb1_dp_offload.vhd
index 4b3e61dc67..e0f70ec12f 100644
--- a/applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/compaan_unb1_dp_offload.vhd
+++ b/applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/compaan_unb1_dp_offload.vhd
@@ -43,12 +43,13 @@ USE common_lib.common_field_pkg.ALL;
ENTITY compaan_unb1_dp_offload IS
GENERIC (
- g_sim : BOOLEAN := FALSE; -- set by ModelSim
- g_sim_unb_nr : NATURAL := 0; -- set by ModelSim
- g_sim_node_nr : NATURAL := 0; -- set by ModelSim
- g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
+ g_use_loopback : BOOLEAN := TRUE;
+ g_sim : BOOLEAN := FALSE; -- set by ModelSim
+ g_sim_unb_nr : NATURAL := 0; -- set by ModelSim
+ g_sim_node_nr : NATURAL := 0; -- set by ModelSim
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
);
PORT (
-- GENERAL
@@ -57,7 +58,7 @@ ENTITY compaan_unb1_dp_offload IS
WDI : OUT STD_LOGIC;
INTA : INOUT STD_LOGIC;
INTB : INOUT STD_LOGIC;
-
+
-- Others
VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
@@ -83,8 +84,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS
-- Revision controlled constants
CONSTANT c_use_1GbE : BOOLEAN := TRUE;
- CONSTANT c_dp_loopback : BOOLEAN := sel_a_b(g_sim_node_nr=0, TRUE, FALSE);
- CONSTANT c_nof_streams : NATURAL := 3;
+ CONSTANT c_nof_streams : NATURAL := 1;
CONSTANT c_data_w : NATURAL := c_tech_tse_data_w;
@@ -134,6 +134,8 @@ ARCHITECTURE str OF compaan_unb1_dp_offload IS
( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ) );
CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111011111100"&"0001"&"101111111";
+
+ CONSTANT c_fifo_size : NATURAL := 2*c_bg_block_size;
CONSTANT c_use_jumbo_frames : BOOLEAN := TRUE;
CONSTANT c_def_1GbE_block_size : NATURAL := 0; -- 0 first so we have time to set RX demux reg in dest. node
@@ -339,7 +341,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Connect BG and DB to dp_offload
-----------------------------------------------------------------------------
- no_loopback : IF c_dp_loopback=FALSE GENERATE
+ no_loopback : IF g_use_loopback=FALSE GENERATE
-- BG --> Tx
dp_offload_tx_snk_in_arr <= block_gen_src_out_arr;
block_gen_src_in_arr <= dp_offload_tx_snk_out_arr;
@@ -352,7 +354,7 @@ BEGIN
-----------------------------------------------------------------------------
-- DP loopback dp_offload_rx to dp_offload_tx
-----------------------------------------------------------------------------
- gen_loopback : IF c_dp_loopback=TRUE GENERATE
+ gen_loopback : IF g_use_loopback=TRUE GENERATE
-- Rx --> Tx
-- dp_offload_tx_snk_in_arr <= dp_offload_rx_src_out_arr;
-- dp_offload_rx_src_in_arr <= dp_offload_tx_snk_out_arr;
@@ -380,7 +382,7 @@ BEGIN
-- Loop FIFO in
g_fifo_in : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP (
- g_data_w => 576, -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w => 32, -- Should be 2 times the c_complex_w if g_use_complex = TRUE
g_bsn_w => 1,
g_empty_w => 1,
g_channel_w => 1,
@@ -392,7 +394,7 @@ BEGIN
g_use_sync => FALSE,
g_use_ctrl => TRUE, -- sop & eop
g_use_complex => FALSE, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_bg_blocks_per_sync, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size => c_fifo_size, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
g_fifo_af_margin => 4, -- >=4, Nof words below max (full) at which fifo is considered almost full
g_fifo_rl => 0
)
@@ -414,7 +416,7 @@ BEGIN
-- Loop FIFO out
g_fifo_out : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP (
- g_data_w => 576, -- Should be 2 times the c_complex_w if g_use_complex = TRUE
+ g_data_w => 32, -- Should be 2 times the c_complex_w if g_use_complex = TRUE
g_bsn_w => 1,
g_empty_w => 1,
g_channel_w => 1,
@@ -426,7 +428,7 @@ BEGIN
g_use_sync => FALSE,
g_use_ctrl => TRUE, -- sop & eop
g_use_complex => FALSE, -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
- g_fifo_size => c_bg_blocks_per_sync, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
+ g_fifo_size => c_fifo_size, -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
g_fifo_af_margin => 4, -- >=4, Nof words below max (full) at which fifo is considered almost full
g_fifo_rl => 0
)
--
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