diff --git a/boards/uniboard1/designs/unb1_test/hdllib.cfg b/boards/uniboard1/designs/unb1_test/hdllib.cfg
index ac5e99e2e7a5f2ee50da96ed0c16bb94831a1fe4..cf4a8b596957479fb517e7c48a221bc39ac2201c 100644
--- a/boards/uniboard1/designs/unb1_test/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/hdllib.cfg
@@ -9,7 +9,7 @@ synth_files =
src/vhdl/qsys_unb1_test_pkg.vhd
src/vhdl/unb1_test_pkg.vhd
src/vhdl/mmm_unb1_test.vhd
- src/vhdl/bgdb_stream_test.vhd
+ src/vhdl/udp_stream_test.vhd
src/vhdl/unb1_test.vhd
test_bench_files =
diff --git a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
index c4d316d4769302aa1cd6ae9055d1702fd9064470..164e1fba6255f5af1f082ecda753a29a91fe748c 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
+++ b/boards/uniboard1/designs/unb1_test/quartus/qsys_unb1_test.qsys
@@ -65,71 +65,71 @@
type = "String";
}
}
- element reg_bsn_monitor_10GbE.mem
+ element reg_diag_bg_10GbE.mem
{
datum baseAddress
{
- value = "12800";
+ value = "12768";
type = "long";
}
}
- element reg_dp_offload_tx_10GbE.mem
+ element ram_ss_ss_wide.mem
{
datum baseAddress
{
- value = "12480";
+ value = "393216";
type = "long";
}
}
- element reg_io_ddr.mem
+ element reg_tr_10GbE.mem
{
datum baseAddress
{
- value = "12672";
+ value = "262144";
type = "long";
}
}
- element reg_mmdp_ctrl.mem
+ element reg_dpmm_ctrl.mem
{
datum baseAddress
{
- value = "12704";
+ value = "12816";
type = "long";
}
}
- element ram_diag_data_buffer_1GbE.mem
+ element reg_dpmm_data.mem
{
datum baseAddress
{
- value = "65536";
+ value = "12824";
type = "long";
}
}
- element reg_epcs.mem
+ element reg_dp_offload_tx_1GbE.mem
{
datum baseAddress
{
- value = "12608";
+ value = "12856";
type = "long";
}
}
- element reg_diag_bg_1GbE.mem
+ element reg_dp_offload_rx_10GbE_hdr_dat.mem
{
datum baseAddress
{
- value = "12640";
+ value = "13312";
type = "long";
}
}
- element reg_diag_data_buffer_1GbE.mem
+ element reg_mmdp_ctrl.mem
{
datum baseAddress
{
- value = "128";
+ value = "12832";
type = "long";
}
}
- element pio_system_info.mem
+ element rom_system_info.mem
{
datum _lockedAddress
{
@@ -138,127 +138,137 @@
}
datum baseAddress
{
- value = "0";
+ value = "4096";
type = "long";
}
}
- element ram_ss_ss_wide.mem
+ element reg_dp_offload_tx_10GbE.mem
{
datum baseAddress
{
- value = "393216";
+ value = "12736";
type = "long";
}
}
- element reg_unb_sens.mem
+ element pio_system_info.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "12544";
+ value = "0";
type = "long";
}
}
- element reg_tr_10GbE.mem
+ element ram_diag_data_buffer_10GbE.mem
{
datum baseAddress
{
- value = "262144";
+ value = "458752";
type = "long";
}
}
- element reg_bsn_monitor_1GbE.mem
+ element ram_diag_bg_10GbE.mem
{
datum baseAddress
{
- value = "512";
+ value = "16384";
type = "long";
}
}
- element reg_dpmm_ctrl.mem
+ element reg_dp_offload_tx_10GbE_hdr_dat.mem
{
datum baseAddress
{
- value = "12688";
+ value = "1024";
type = "long";
}
}
- element reg_tr_xaui.mem
+ element reg_mmdp_data.mem
{
datum baseAddress
{
- value = "16384";
+ value = "12840";
type = "long";
}
}
- element reg_dp_offload_tx_1GbE.mem
+ element ram_diag_data_buffer_1GbE.mem
{
datum baseAddress
{
- value = "12416";
+ value = "65536";
type = "long";
}
}
- element reg_diag_bg_10GbE.mem
+ element reg_bsn_monitor_1GbE.mem
{
datum baseAddress
{
- value = "256";
+ value = "12544";
type = "long";
}
}
- element reg_dp_offload_rx_1GbE_hdr_dat.mem
+ element reg_unb_sens.mem
{
datum baseAddress
{
- value = "1024";
+ value = "12608";
type = "long";
}
}
- element reg_dp_offload_tx_1GbE_hdr_dat.mem
+ element pio_pps.mem
{
datum baseAddress
{
- value = "13312";
+ value = "12848";
type = "long";
}
}
- element reg_mmdp_data.mem
+ element reg_bsn_monitor_10GbE.mem
{
datum baseAddress
{
- value = "12712";
+ value = "768";
type = "long";
}
}
- element ram_diag_data_buffer_10GbE.mem
+ element reg_remu.mem
{
datum baseAddress
{
- value = "458752";
+ value = "12640";
type = "long";
}
}
- element pio_pps.mem
+ element reg_wdi.mem
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "12720";
+ value = "12288";
type = "long";
}
}
- element reg_dpmm_data.mem
+ element reg_dp_offload_rx_1GbE_hdr_dat.mem
{
datum baseAddress
{
- value = "12696";
+ value = "256";
type = "long";
}
}
- element reg_remu.mem
+ element reg_epcs.mem
{
datum baseAddress
{
- value = "12576";
+ value = "12672";
type = "long";
}
}
@@ -266,23 +276,23 @@
{
datum baseAddress
{
- value = "384";
+ value = "12416";
type = "long";
}
}
- element reg_dp_offload_rx_10GbE_hdr_dat.mem
+ element reg_tr_xaui.mem
{
datum baseAddress
{
- value = "29696";
+ value = "32768";
type = "long";
}
}
- element reg_dp_offload_tx_10GbE_hdr_dat.mem
+ element reg_dp_offload_tx_1GbE_hdr_dat.mem
{
datum baseAddress
{
- value = "28672";
+ value = "512";
type = "long";
}
}
@@ -290,41 +300,31 @@
{
datum baseAddress
{
- value = "32768";
+ value = "45056";
type = "long";
}
}
- element reg_wdi.mem
+ element reg_diag_data_buffer_1GbE.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "12288";
+ value = "128";
type = "long";
}
}
- element ram_diag_bg_10GbE.mem
+ element reg_io_ddr.mem
{
datum baseAddress
{
- value = "524288";
+ value = "12800";
type = "long";
}
}
- element rom_system_info.mem
+ element reg_diag_bg_1GbE.mem
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "4096";
+ value = "12704";
type = "long";
}
}
@@ -332,7 +332,7 @@
{
datum baseAddress
{
- value = "24576";
+ value = "40960";
type = "long";
}
}
@@ -626,16 +626,11 @@
type = "int";
}
}
- element onchip_memory2_0.s1
+ element pio_wdi.s1
{
- datum _lockedAddress
- {
- value = "1";
- type = "boolean";
- }
datum baseAddress
{
- value = "131072";
+ value = "12304";
type = "long";
}
}
@@ -647,11 +642,16 @@
type = "long";
}
}
- element pio_wdi.s1
+ element onchip_memory2_0.s1
{
+ datum _lockedAddress
+ {
+ value = "1";
+ type = "boolean";
+ }
datum baseAddress
{
- value = "12304";
+ value = "131072";
type = "long";
}
}
@@ -678,7 +678,7 @@
<parameter name="projectName" value="" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
- <parameter name="timeStamp" value="1429698630991" />
+ <parameter name="timeStamp" value="1429783651439" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface
@@ -2496,7 +2496,7 @@ q]]></parameter>
<parameter name="dcache_numTCDM" value="0" />
<parameter name="dcache_lineSize" value="32" />
<parameter name="instAddrWidth" value="18" />
- <parameter name="dataAddrWidth" value="20" />
+ <parameter name="dataAddrWidth" value="19" />
<parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
<parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
@@ -2506,7 +2506,7 @@ q]]></parameter>
<parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
<parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
<parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /></address-map>]]></parameter>
- <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_1GbE.mem' start='0x80' end='0x100' /><slave name='reg_diag_bg_10GbE.mem' start='0x100' end='0x180' /><slave name='reg_diag_data_buffer_10GbE.mem' start='0x180' end='0x200' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x200' end='0x400' /><slave name='reg_dp_offload_rx_1GbE_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_dp_offload_tx_1GbE.mem' start='0x3080' end='0x30C0' /><slave name='reg_dp_offload_tx_10GbE.mem' start='0x30C0' end='0x3100' /><slave name='reg_unb_sens.mem' start='0x3100' end='0x3120' /><slave name='reg_remu.mem' start='0x3120' end='0x3140' /><slave name='reg_epcs.mem' start='0x3140' end='0x3160' /><slave name='reg_diag_bg_1GbE.mem' start='0x3160' end='0x3180' /><slave name='reg_io_ddr.mem' start='0x3180' end='0x3190' /><slave name='reg_dpmm_ctrl.mem' start='0x3190' end='0x3198' /><slave name='reg_dpmm_data.mem' start='0x3198' end='0x31A0' /><slave name='reg_mmdp_ctrl.mem' start='0x31A0' end='0x31A8' /><slave name='reg_mmdp_data.mem' start='0x31A8' end='0x31B0' /><slave name='pio_pps.mem' start='0x31B0' end='0x31B8' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x3200' end='0x3400' /><slave name='reg_dp_offload_tx_1GbE_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='reg_tr_xaui.mem' start='0x4000' end='0x6000' /><slave name='avs_eth_0.mms_ram' start='0x6000' end='0x7000' /><slave name='reg_dp_offload_tx_10GbE_hdr_dat.mem' start='0x7000' end='0x7400' /><slave name='reg_dp_offload_rx_10GbE_hdr_dat.mem' start='0x7400' end='0x7800' /><slave name='ram_diag_bg_1GbE.mem' start='0x8000' end='0x10000' /><slave name='ram_diag_data_buffer_1GbE.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /><slave name='ram_diag_data_buffer_10GbE.mem' start='0x70000' end='0x80000' /><slave name='ram_diag_bg_10GbE.mem' start='0x80000' end='0x88000' /></address-map>]]></parameter>
+ <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' /><slave name='reg_diag_data_buffer_1GbE.mem' start='0x80' end='0x100' /><slave name='reg_dp_offload_rx_1GbE_hdr_dat.mem' start='0x100' end='0x200' /><slave name='reg_dp_offload_tx_1GbE_hdr_dat.mem' start='0x200' end='0x300' /><slave name='reg_bsn_monitor_10GbE.mem' start='0x300' end='0x400' /><slave name='reg_dp_offload_tx_10GbE_hdr_dat.mem' start='0x400' end='0x800' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3008' end='0x3010' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' /><slave name='timer_0.s1' start='0x3020' end='0x3040' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' /><slave name='reg_diag_data_buffer_10GbE.mem' start='0x3080' end='0x3100' /><slave name='reg_bsn_monitor_1GbE.mem' start='0x3100' end='0x3140' /><slave name='reg_unb_sens.mem' start='0x3140' end='0x3160' /><slave name='reg_remu.mem' start='0x3160' end='0x3180' /><slave name='reg_epcs.mem' start='0x3180' end='0x31A0' /><slave name='reg_diag_bg_1GbE.mem' start='0x31A0' end='0x31C0' /><slave name='reg_dp_offload_tx_10GbE.mem' start='0x31C0' end='0x31E0' /><slave name='reg_diag_bg_10GbE.mem' start='0x31E0' end='0x3200' /><slave name='reg_io_ddr.mem' start='0x3200' end='0x3210' /><slave name='reg_dpmm_ctrl.mem' start='0x3210' end='0x3218' /><slave name='reg_dpmm_data.mem' start='0x3218' end='0x3220' /><slave name='reg_mmdp_ctrl.mem' start='0x3220' end='0x3228' /><slave name='reg_mmdp_data.mem' start='0x3228' end='0x3230' /><slave name='pio_pps.mem' start='0x3230' end='0x3238' /><slave name='reg_dp_offload_tx_1GbE.mem' start='0x3238' end='0x3240' /><slave name='reg_dp_offload_rx_10GbE_hdr_dat.mem' start='0x3400' end='0x3800' /><slave name='cpu_0.jtag_debug_module' start='0x3800' end='0x4000' /><slave name='ram_diag_bg_10GbE.mem' start='0x4000' end='0x8000' /><slave name='reg_tr_xaui.mem' start='0x8000' end='0xA000' /><slave name='avs_eth_0.mms_ram' start='0xA000' end='0xB000' /><slave name='ram_diag_bg_1GbE.mem' start='0xB000' end='0xC000' /><slave name='ram_diag_data_buffer_1GbE.mem' start='0x10000' end='0x20000' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' /><slave name='reg_tr_10GbE.mem' start='0x40000' end='0x60000' /><slave name='ram_ss_ss_wide.mem' start='0x60000' end='0x70000' /><slave name='ram_diag_data_buffer_10GbE.mem' start='0x70000' end='0x80000' /></address-map>]]></parameter>
<parameter name="clockFrequency" value="125000000" />
<parameter name="deviceFamilyName" value="Stratix IV" />
<parameter name="internalIrqMaskSystemInfo" value="7" />
@@ -2526,7 +2526,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="reg_bsn_monitor_1GbE">
- <parameter name="g_adr_w" value="7" />
+ <parameter name="g_adr_w" value="4" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -2535,7 +2535,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="reg_dp_offload_tx_1GbE">
- <parameter name="g_adr_w" value="4" />
+ <parameter name="g_adr_w" value="1" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -2544,7 +2544,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="reg_dp_offload_tx_1GbE_hdr_dat">
- <parameter name="g_adr_w" value="8" />
+ <parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -2553,7 +2553,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="reg_dp_offload_rx_1GbE_hdr_dat">
- <parameter name="g_adr_w" value="8" />
+ <parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -2589,7 +2589,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="ram_diag_bg_1GbE">
- <parameter name="g_adr_w" value="13" />
+ <parameter name="g_adr_w" value="10" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -2608,7 +2608,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="reg_bsn_monitor_10GbE">
- <parameter name="g_adr_w" value="7" />
+ <parameter name="g_adr_w" value="6" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -2617,7 +2617,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="reg_diag_bg_10GbE">
- <parameter name="g_adr_w" value="5" />
+ <parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -2626,7 +2626,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="ram_diag_bg_10GbE">
- <parameter name="g_adr_w" value="13" />
+ <parameter name="g_adr_w" value="12" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -2635,7 +2635,7 @@ q]]></parameter>
version="1.0"
enabled="1"
name="reg_dp_offload_tx_10GbE">
- <parameter name="g_adr_w" value="4" />
+ <parameter name="g_adr_w" value="3" />
<parameter name="g_dat_w" value="32" />
<parameter name="AUTO_SYSTEM_CLOCK_RATE" value="125000000" />
</module>
@@ -2747,7 +2747,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_unb_sens.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3100" />
+ <parameter name="baseAddress" value="0x3140" />
</connection>
<connection
kind="avalon"
@@ -2779,7 +2779,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_remu.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3120" />
+ <parameter name="baseAddress" value="0x3160" />
</connection>
<connection
kind="avalon"
@@ -2787,7 +2787,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3190" />
+ <parameter name="baseAddress" value="0x3210" />
</connection>
<connection
kind="avalon"
@@ -2795,7 +2795,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dpmm_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3198" />
+ <parameter name="baseAddress" value="0x3218" />
</connection>
<connection
kind="avalon"
@@ -2803,7 +2803,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_ctrl.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31a0" />
+ <parameter name="baseAddress" value="0x3220" />
</connection>
<connection
kind="avalon"
@@ -2811,7 +2811,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_mmdp_data.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31a8" />
+ <parameter name="baseAddress" value="0x3228" />
</connection>
<connection
kind="avalon"
@@ -2819,7 +2819,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_epcs.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3140" />
+ <parameter name="baseAddress" value="0x3180" />
</connection>
<connection
kind="avalon"
@@ -2827,7 +2827,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="pio_pps.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x31b0" />
+ <parameter name="baseAddress" value="0x3230" />
</connection>
<connection
kind="avalon"
@@ -2859,7 +2859,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="avs_eth_0.mms_ram">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x6000" />
+ <parameter name="baseAddress" value="0xa000" />
</connection>
<connection
kind="interrupt"
@@ -2874,7 +2874,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_tr_xaui.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x4000" />
+ <parameter name="baseAddress" value="0x8000" />
</connection>
<connection
kind="reset"
@@ -3077,7 +3077,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_bsn_monitor_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0200" />
+ <parameter name="baseAddress" value="0x3100" />
</connection>
<connection
kind="reset"
@@ -3100,7 +3100,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_rx_1GbE_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0400" />
+ <parameter name="baseAddress" value="0x0100" />
</connection>
<connection
kind="reset"
@@ -3128,7 +3128,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_tx_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3080" />
+ <parameter name="baseAddress" value="0x3238" />
</connection>
<connection
kind="avalon"
@@ -3136,7 +3136,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_tx_1GbE_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3400" />
+ <parameter name="baseAddress" value="0x0200" />
</connection>
<connection
kind="avalon"
@@ -3180,7 +3180,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_bg_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3160" />
+ <parameter name="baseAddress" value="0x31a0" />
</connection>
<connection
kind="avalon"
@@ -3188,7 +3188,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="ram_diag_bg_1GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x8000" />
+ <parameter name="baseAddress" value="0xb000" />
</connection>
<connection
kind="reset"
@@ -3349,7 +3349,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_io_ddr.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3180" />
+ <parameter name="baseAddress" value="0x3200" />
</connection>
<connection
kind="reset"
@@ -3442,7 +3442,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_bsn_monitor_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x3200" />
+ <parameter name="baseAddress" value="0x0300" />
</connection>
<connection
kind="clock"
@@ -3455,7 +3455,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_tx_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x30c0" />
+ <parameter name="baseAddress" value="0x31c0" />
</connection>
<connection
kind="clock"
@@ -3468,7 +3468,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_tx_10GbE_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x7000" />
+ <parameter name="baseAddress" value="0x0400" />
</connection>
<connection
kind="clock"
@@ -3481,7 +3481,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_dp_offload_rx_10GbE_hdr_dat.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x7400" />
+ <parameter name="baseAddress" value="0x3400" />
</connection>
<connection
kind="clock"
@@ -3494,7 +3494,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_bg_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0100" />
+ <parameter name="baseAddress" value="0x31e0" />
</connection>
<connection
kind="clock"
@@ -3507,7 +3507,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="ram_diag_bg_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x00080000" />
+ <parameter name="baseAddress" value="0x4000" />
</connection>
<connection
kind="clock"
@@ -3520,7 +3520,7 @@ q]]></parameter>
start="cpu_0.data_master"
end="reg_diag_data_buffer_10GbE.mem">
<parameter name="arbitrationPriority" value="1" />
- <parameter name="baseAddress" value="0x0180" />
+ <parameter name="baseAddress" value="0x3080" />
</connection>
<connection
kind="clock"
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index 5cd0b73e783ef0aebaec880e66cdab364823255d..1f4a64f379d8e22cca0794802a4088ede898ccd2 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -44,7 +44,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/generated/ip_stratixiv_ddr3_uphy_4g_800_master.qip
#$RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/generated/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg
index ed3020b2e6096f980bf582326ebef4dc7cb06504..ee129e4191f9afec0cfc674782c3c72b11356f44 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/hdllib.cfg
@@ -34,5 +34,5 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/quartus/unb1_test_lpbk/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_lpbk/qsys_unb1_test/synthesis/qsys_unb1_test.qip
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg
index 51c734ad037e693445e197bb84626a4b1605a527..719d6deaf2a34089ad1aa9da9164d93c9f9c8f4b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_qsys/hdllib.cfg
@@ -33,5 +33,5 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $HDL_BUILD_DIR/quartus/unb1_test_qsys/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_qsys/qsys_unb1_test/synthesis/qsys_unb1_test.qip
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 06a5ede9de8fe19e6e44742270a500c7a37b1ef6..8af77608bfc83973da24637f95217e7431f84c87 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -257,26 +257,27 @@ BEGIN
----------------------------------------------------------------------------
gen_mm_file_io : IF g_sim = TRUE GENERATE
+ eth1g_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso);
u_mm_file_rom_unb_system_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "ROM_SYSTEM_INFO")
- PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso );
+ PORT MAP(mm_rst, mm_clk, rom_unb_system_info_mosi, rom_unb_system_info_miso);
u_mm_file_reg_wdi : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_WDI")
- PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso );
+ PORT MAP(mm_rst, mm_clk, reg_wdi_mosi, reg_wdi_miso);
u_mm_file_reg_unb_sens : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_UNB_SENS")
- PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso );
+ PORT MAP(mm_rst, mm_clk, reg_unb_sens_mosi, reg_unb_sens_miso);
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
- PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso);
- u_mm_file_reg_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GbE")
+ u_mm_file_reg_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_1GBE")
PORT MAP(mm_rst, mm_clk, reg_diag_bg_1GbE_mosi, reg_diag_bg_1GbE_miso);
- u_mm_file_ram_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GbE")
+ u_mm_file_ram_diag_bg_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG_1GBE")
PORT MAP(mm_rst, mm_clk, ram_diag_bg_1GbE_mosi, ram_diag_bg_1GbE_miso);
u_mm_file_reg_diag_bg_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_BG_10GBE")
@@ -301,16 +302,16 @@ BEGIN
u_mm_file_reg_dp_offload_rx_1GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_1GBE_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_1GbE_hdr_dat_mosi, reg_dp_offload_rx_1GbE_hdr_dat_miso);
u_mm_file_reg_dp_offload_rx_10GbE_hdr_dat : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_OFFLOAD_RX_10GBE_HDR_DAT")
- PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso );
+ PORT MAP(mm_rst, mm_clk, reg_dp_offload_rx_10GbE_hdr_dat_mosi, reg_dp_offload_rx_10GbE_hdr_dat_miso);
u_mm_file_reg_bsn_monitor_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_1GBE")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_1GbE_mosi, reg_bsn_monitor_1GbE_miso);
u_mm_file_reg_bsn_monitor_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_10GBE")
- PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso );
+ PORT MAP(mm_rst, mm_clk, reg_bsn_monitor_10GbE_mosi, reg_bsn_monitor_10GbE_miso);
u_mm_file_ram_diag_data_buffer_1GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_DATA_BUFFER_1GBE")
PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_1GbE_mosi, ram_diag_data_buf_1GbE_miso);
@@ -330,13 +331,13 @@ BEGIN
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
- PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
+ PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso);
u_mm_file_reg_tr_10GbE : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_10GBE")--, c_mm_clk_period, FALSE, 0)
- PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso );
+ PORT MAP(mm_rst, mm_clk, reg_tr_10GbE_mosi, reg_tr_10GbE_miso);
u_mm_file_reg_tr_xaui : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI")--, c_mm_clk_period, FALSE, 0)
- PORT MAP(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso );
+ PORT MAP(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index 1ccb9bc75c78d57f0d987f6dde547c3d6d0b98c0..1d4b5f70765ccd29bbcd80102d6b651d45e91c5b 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -27,10 +27,8 @@ PACKAGE qsys_unb1_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-----------------------------------------------------------------------------
-
- COMPONENT qsys_unb1_test is
- PORT (
-
+ component qsys_unb1_test is
+ port (
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
coe_readdata_export_to_the_reg_mmdp_ctrl : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
@@ -150,7 +148,7 @@ PACKAGE qsys_unb1_test_pkg IS
reg_bsn_monitor_1gbe_read_export : out std_logic; -- export
reg_bsn_monitor_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_1gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_1gbe_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_monitor_1gbe_clk_export : out std_logic; -- export
reg_bsn_monitor_1gbe_reset_export : out std_logic; -- export
ram_ss_ss_wide_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
@@ -178,14 +176,14 @@ PACKAGE qsys_unb1_test_pkg IS
ram_diag_bg_10gbe_read_export : out std_logic; -- export
ram_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_bg_10gbe_write_export : out std_logic; -- export
- ram_diag_bg_10gbe_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_diag_bg_10gbe_address_export : out std_logic_vector(11 downto 0); -- export
ram_diag_bg_10gbe_clk_export : out std_logic; -- export
ram_diag_bg_10gbe_reset_export : out std_logic; -- export
reg_diag_bg_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_diag_bg_10gbe_read_export : out std_logic; -- export
reg_diag_bg_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_diag_bg_10gbe_write_export : out std_logic; -- export
- reg_diag_bg_10gbe_address_export : out std_logic_vector(4 downto 0); -- export
+ reg_diag_bg_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
reg_diag_bg_10gbe_clk_export : out std_logic; -- export
reg_diag_bg_10gbe_reset_export : out std_logic; -- export
reg_dp_offload_rx_10gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
@@ -206,33 +204,33 @@ PACKAGE qsys_unb1_test_pkg IS
reg_dp_offload_tx_10gbe_read_export : out std_logic; -- export
reg_dp_offload_tx_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_10gbe_write_export : out std_logic; -- export
- reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_offload_tx_10gbe_address_export : out std_logic_vector(2 downto 0); -- export
reg_dp_offload_tx_10gbe_clk_export : out std_logic; -- export
reg_dp_offload_tx_10gbe_reset_export : out std_logic; -- export
reg_bsn_monitor_10gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_bsn_monitor_10gbe_read_export : out std_logic; -- export
reg_bsn_monitor_10gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_monitor_10gbe_write_export : out std_logic; -- export
- reg_bsn_monitor_10gbe_address_export : out std_logic_vector(6 downto 0); -- export
+ reg_bsn_monitor_10gbe_address_export : out std_logic_vector(5 downto 0); -- export
reg_bsn_monitor_10gbe_clk_export : out std_logic; -- export
reg_bsn_monitor_10gbe_reset_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_reset_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(3 downto 0); -- export
+ reg_dp_offload_tx_1gbe_address_export : out std_logic_vector(0 downto 0); -- export
reg_dp_offload_tx_1gbe_write_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_1gbe_read_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_tx_1gbe_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_tx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
reg_dp_offload_tx_1gbe_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_tx_1gbe_hdr_dat_read_export : out std_logic; -- export
reg_dp_offload_tx_1gbe_hdr_dat_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_offload_rx_1gbe_hdr_dat_reset_export : out std_logic; -- export
reg_dp_offload_rx_1gbe_hdr_dat_clk_export : out std_logic; -- export
- reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(7 downto 0); -- export
+ reg_dp_offload_rx_1gbe_hdr_dat_address_export : out std_logic_vector(5 downto 0); -- export
reg_dp_offload_rx_1gbe_hdr_dat_write_export : out std_logic; -- export
reg_dp_offload_rx_1gbe_hdr_dat_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_offload_rx_1gbe_hdr_dat_read_export : out std_logic; -- export
@@ -246,7 +244,7 @@ PACKAGE qsys_unb1_test_pkg IS
reg_diag_bg_1gbe_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
ram_diag_bg_1gbe_reset_export : out std_logic; -- export
ram_diag_bg_1gbe_clk_export : out std_logic; -- export
- ram_diag_bg_1gbe_address_export : out std_logic_vector(12 downto 0); -- export
+ ram_diag_bg_1gbe_address_export : out std_logic_vector(9 downto 0); -- export
ram_diag_bg_1gbe_write_export : out std_logic; -- export
ram_diag_bg_1gbe_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_diag_bg_1gbe_read_export : out std_logic; -- export
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/bgdb_stream_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream_test.vhd
similarity index 97%
rename from boards/uniboard1/designs/unb1_test/src/vhdl/bgdb_stream_test.vhd
rename to boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream_test.vhd
index e50ac621d8b7e94d3fba457d38f38aa74219716b..b7cb00e69cf028fe27e304972e87a72f21d3e6f7 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/bgdb_stream_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream_test.vhd
@@ -34,7 +34,7 @@ USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE work.unb1_test_pkg.ALL;
-ENTITY bgdb_stream_test IS
+ENTITY udp_stream_test IS
GENERIC (
g_sim : BOOLEAN := FALSE;
g_nof_streams : NATURAL;
@@ -92,11 +92,11 @@ ENTITY bgdb_stream_test IS
ram_diag_data_buf_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_diag_data_buf_miso : OUT t_mem_miso
);
-END bgdb_stream_test;
+END udp_stream_test;
-ARCHITECTURE str OF bgdb_stream_test IS
+ARCHITECTURE str OF udp_stream_test IS
-- Block generator
CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 0b726ee21dcb8546b014b6b845d0268acfbf3047..11eb46779437efc36f20e09544889d39a1453113 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -125,8 +125,11 @@ ARCHITECTURE str OF unb1_test IS
CONSTANT c_use_front : BOOLEAN := TRUE; -- connect SI_FN_[0..2]
CONSTANT c_use_back : BOOLEAN := FALSE; -- however SI_FN_[0..2] do connect to copper connectors of single board unb
- -- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
- CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(g_sim, 0, 1),
+ -- Revision controlled constants
+ CONSTANT c_use_1GbE : BOOLEAN := g_design_name = "unb1_test_1GbE" OR g_design_name = "unb1_test_10GbE";
+ CONSTANT c_use_10GbE : BOOLEAN := g_design_name = "unb1_test_10GbE";
+
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (sel_a_b(c_use_1GbE, 1, 0),
sel_a_b(c_use_front, 1, 0),
0,
sel_a_b(c_use_back, 1, 0),
@@ -134,9 +137,6 @@ ARCHITECTURE str OF unb1_test IS
sel_a_b(g_use_MB_II,1, 0),
0, 1);
- -- Revision controlled constants
- CONSTANT c_use_1GbE : BOOLEAN := g_design_name = "unb1_test_1GbE" OR g_design_name = "unb1_test_10GbE";
- CONSTANT c_use_10GbE : BOOLEAN := g_design_name = "unb1_test_10GbE";
CONSTANT c_nof_streams_10GbE : NATURAL := sel_a_b(c_use_10GbE,3,0);
CONSTANT c_nof_streams_1GbE : NATURAL := sel_a_b(c_use_1GbE,1,0);
CONSTANT c_nof_streams_ddr : NATURAL := sel_a_b(g_use_MB_I,sel_a_b(g_use_MB_II,2,1),0);
@@ -593,7 +593,7 @@ BEGIN
);
- u_bgdb_stream_test_1GbE : ENTITY work.bgdb_stream_test
+ u_udp_stream_test_1GbE : ENTITY work.udp_stream_test
GENERIC MAP (
g_sim => g_sim,
g_nof_streams => c_nof_streams_1GbE,
@@ -646,7 +646,7 @@ BEGIN
);
- u_bgdb_stream_test_10GbE : ENTITY work.bgdb_stream_test
+ u_udp_stream_test_10GbE : ENTITY work.udp_stream_test
GENERIC MAP (
g_sim => g_sim,
g_nof_streams => c_nof_streams_10GbE,