diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 4b88f228595ecc68035b9fa574b36064ebe8b91e..37b58b49b76f0b9a8cdf48339be448a2de30a941 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -86,8 +86,6 @@ BEGIN
   last_mm_address <= g_step_size * (g_nof_data - 1) + g_data_size + start_address - 1;
   mm_address      <= start_address + r.word_index + r.step_index;
   
-  mm_mosi.address <= TO_MEM_ADDRESS(mm_address);
-
   -- Take care of g_mm_rd_latency for out_sosi.sop and out_sosi.eop
   r_sop_p <= r.sop WHEN rising_edge(clk);
   r_eop_p <= r.eop WHEN rising_edge(clk);
@@ -120,7 +118,9 @@ BEGIN
     v := r;
     v.sop := '0';
     v.eop := '0';
-    mm_mosi.rd <= '0';
+    mm_mosi <= c_mem_mosi_rst;  -- use default 0 to avoid Warning: (vsim-8684) No drivers exist on out port .wr, .wrdata
+    mm_mosi.address <= TO_MEM_ADDRESS(mm_address);  -- only use mosi.rd and mosi.address
+
     IF r.busy = '0' AND start_pulse = '1' THEN
       -- initiate next block
       v.busy := '1';
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 2520c398666f8fa545c8e61c4cb38b375f29aee6..711ca1a86d7e7a56bc4f28d6a303859ecb9999ee 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -65,10 +65,15 @@ ARCHITECTURE rtl OF dp_block_to_mm IS
   SIGNAL address : NATURAL := 0;
 
 BEGIN
-  address         <= start_address + r.word_index + r.step_index;
-  mm_mosi.address <= TO_MEM_ADDRESS(address);
-  mm_mosi.wrdata  <= RESIZE_MEM_DATA(in_sosi.data);
-  mm_mosi.wr      <= d.wr;
+  address <= start_address + r.word_index + r.step_index;
+
+  p_mm_mosi : PROCESS(address, in_sosi, d)
+  BEGIN
+    mm_mosi <= c_mem_mosi_rst;  -- default to avoid ** Warning: (vsim-8684) No drivers exist on out port mm_mosi.rd
+    mm_mosi.address <= TO_MEM_ADDRESS(address);
+    mm_mosi.wrdata  <= RESIZE_MEM_DATA(in_sosi.data);
+    mm_mosi.wr      <= d.wr;
+  END PROCESS;
   
   p_reg : PROCESS(rst, clk)
   BEGIN
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index 7898f94d3415f65df10ac943340699cb361cff52..d139f3759ed1daaac47c051f7902127421137580 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -76,13 +76,12 @@ ARCHITECTURE tb OF tb_dp_block_from_mm IS
   SIGNAL block_done        : STD_LOGIC;
 
   SIGNAL rd_mosi           : t_mem_mosi;
-  SIGNAL rd_miso           : t_mem_miso;
+  SIGNAL rd_miso           : t_mem_miso := c_mem_miso_rst;
   
   SIGNAL blk_sosi          : t_dp_sosi;
   SIGNAL blk_siso          : t_dp_siso := c_dp_siso_rdy;
 
-  SIGNAL wr_mosi           : t_mem_mosi;
-  SIGNAL wr_miso           : t_mem_miso;
+  SIGNAL wr_mosi           : t_mem_mosi := c_mem_mosi_rst;
 
   -- needed for init and verify
   SIGNAL ram_wr_en         : STD_LOGIC := '0';