diff --git a/libraries/base/diag/hdllib.cfg b/libraries/base/diag/hdllib.cfg
index c232fd5208b9d528884776a09f680a64a51ca2e5..067b38ffa11b7f123c04fe718d19fe7e11918e3c 100644
--- a/libraries/base/diag/hdllib.cfg
+++ b/libraries/base/diag/hdllib.cfg
@@ -33,7 +33,7 @@ test_bench_files =
$UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_diag_wg.vhd
$UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_diag_wg_wideband.vhd
$UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_diag_tx_seq.vhd
- $UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_diag_rx_seq.vhd
+ tb/vhdl/tb_diag_rx_seq.vhd
tb/vhdl/tb_diag_tx_frm.vhd
$UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_diag_frm_generator.vhd
$UNB/Firmware/modules/Lofar/diag/tb/vhdl/tb_diag_frm_monitor.vhd
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..424f5df52bb65098e156e725c0388a85efc82acb
--- /dev/null
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -0,0 +1,267 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2009
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+
+-- Purpose: test bench for diag_rx_seq control
+-- Usage:
+-- > as 5
+-- > run -all
+-- . default should run OK i.e. no mismatches reported
+-- . force errors by briefly using different tx sequence at the end of the
+--- stimuli process, these mismatches are reported
+
+ENTITY tb_diag_rx_seq IS
+END tb_diag_rx_seq;
+
+ARCHITECTURE tb OF tb_diag_rx_seq IS
+
+ CONSTANT c_period : TIME := 100 ns;
+ CONSTANT c_nof_cycles : NATURAL := 100;
+
+ CONSTANT c_dat_w : NATURAL := 12; -- = 12, for RCU test data
+ --CONSTANT c_dat_w : NATURAL := 16; -- = 16, for TBBI test data
+
+ CONSTANT c_diag_res_w : NATURAL := c_dat_w + 1;
+
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL clk : STD_LOGIC := '1';
+ SIGNAL rst : STD_LOGIC;
+
+ -- Tx test data
+ SIGNAL tx_diag_en : STD_LOGIC;
+ SIGNAL tx_diag_sel : STD_LOGIC;
+ SIGNAL tx_diag_req : STD_LOGIC;
+ SIGNAL seq_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
+ SIGNAL seq_val : STD_LOGIC;
+
+ -- Rx test data
+ SIGNAL rx_diag_en : STD_LOGIC;
+ SIGNAL rx_diag_sel : STD_LOGIC;
+ SIGNAL diag_res : STD_LOGIC_VECTOR(c_diag_res_w-1 DOWNTO 0);
+ SIGNAL diag_res_val : STD_LOGIC;
+
+BEGIN
+
+ rst <= '1', '0' AFTER c_period/10;
+ clk <= NOT clk OR tb_end AFTER c_period/2;
+
+ stimuli: PROCESS
+ -- run 100 us
+ BEGIN
+ tx_diag_en <= '0';
+ rx_diag_en <= '0';
+ tx_diag_sel <= '0';
+ rx_diag_sel <= '0';
+ tx_diag_req <= '1';
+
+ -- COUNTER
+ WAIT FOR c_period;
+ tx_diag_sel <= '1';
+ rx_diag_sel <= '1';
+ WAIT FOR c_period;
+ tx_diag_en <= '1';
+ WAIT FOR 10*c_period;
+ rx_diag_en <= '1'; -- restart diag_res
+ WAIT FOR c_nof_cycles*c_period;
+ tx_diag_req <= '0'; -- inactive request cycle
+ WAIT FOR c_period;
+ tx_diag_req <= '1';
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR 10*c_period;
+ rx_diag_en <= '1'; -- restart diag_res
+ WAIT FOR c_nof_cycles*c_period;
+ tx_diag_req <= '0'; -- inactive request cycles
+ WAIT FOR 1*c_period;
+ tx_diag_req <= '1';
+ WAIT FOR 2*c_period;
+ tx_diag_req <= '0'; -- inactive request cycles
+ WAIT FOR 3*c_period;
+ tx_diag_req <= '1';
+ WAIT FOR 4*c_period;
+ tx_diag_req <= '0'; -- inactive request cycles
+ WAIT FOR 5*c_period;
+ tx_diag_req <= '1';
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+
+ -- PRSG
+ WAIT FOR c_period;
+ tx_diag_sel <= '0';
+ rx_diag_sel <= '0';
+ WAIT FOR c_period;
+ tx_diag_en <= '1';
+ WAIT FOR 10*c_period;
+ rx_diag_en <= '1'; -- restart diag_res
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+
+ -- COUNTER
+ tx_diag_en <= '0'; -- stop tx
+ WAIT FOR c_period;
+ tx_diag_sel <= '1';
+ rx_diag_sel <= '1';
+ WAIT FOR 10*c_period; -- wait until no more valid data arrives from tx
+ rx_diag_en <= '1'; -- restart diag_res before tx is on
+ WAIT FOR 10*c_period;
+ tx_diag_en <= '1'; -- restart tx
+ WAIT FOR c_nof_cycles*c_period;
+ tx_diag_req <= '0'; -- inactive request cycle
+ WAIT FOR c_period;
+ tx_diag_req <= '1';
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+
+ -- COUNTER
+ tx_diag_en <= '0'; -- stop tx
+ tx_diag_req <= '0'; -- inactive tx request
+ WAIT FOR c_period;
+ tx_diag_sel <= '1';
+ rx_diag_sel <= '1';
+ WAIT FOR 10*c_period; -- wait until no more valid data arrives from tx
+ rx_diag_en <= '1'; -- restart diag_res before tx is on
+ WAIT FOR 10*c_period;
+ tx_diag_en <= '1'; -- restart tx
+ tx_diag_req <= '0'; -- inactive request cycle
+ WAIT FOR c_period;
+ tx_diag_req <= '1';
+ WAIT FOR c_period;
+ tx_diag_req <= '0'; -- inactive request cycles
+ WAIT FOR 4*c_period;
+ tx_diag_req <= '1';
+ WAIT FOR c_period;
+ tx_diag_req <= '0'; -- inactive request cycles
+ WAIT FOR 4*c_period;
+ tx_diag_req <= '1';
+ WAIT FOR c_period;
+ tx_diag_req <= '0'; -- inactive request cycles
+ WAIT FOR 4*c_period;
+ tx_diag_req <= '1';
+ WAIT FOR c_period;
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+
+ -- PRSG
+ WAIT FOR c_period;
+ tx_diag_sel <= '0';
+ rx_diag_sel <= '0';
+ WAIT FOR c_period;
+ tx_diag_en <= '1';
+ WAIT FOR 10*c_period;
+ rx_diag_en <= '1'; -- restart diag_res
+ WAIT FOR c_nof_cycles*c_period;
+ WAIT FOR c_period;
+ tx_diag_en <= '0'; -- stop tx
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+
+ -- PRSG
+ WAIT FOR c_period;
+ tx_diag_sel <= '0';
+ rx_diag_sel <= '0';
+ tx_diag_en <= '1';
+ WAIT FOR 10*c_period;
+ rx_diag_en <= '1'; -- restart diag_res
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR 1*c_period;
+ rx_diag_en <= '1'; -- fast restart diag_res
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR 10*c_period;
+ rx_diag_en <= '1'; -- slow restart diag_res
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+ WAIT FOR 10*c_period;
+ rx_diag_en <= '1'; -- slow restart diag_res
+ WAIT FOR c_nof_cycles*c_period;
+ tx_diag_en <= '0'; -- stop tx
+ WAIT FOR c_nof_cycles*c_period;
+ rx_diag_en <= '0'; -- stop diag_res
+
+ -- COUNTER
+ WAIT FOR c_period;
+ tx_diag_sel <= '1';
+ rx_diag_sel <= '1';
+ WAIT FOR c_period;
+ tx_diag_en <= '1';
+ WAIT FOR 10*c_period;
+ rx_diag_en <= '1'; -- restart diag_res
+ WAIT FOR c_nof_cycles*c_period;
+ --tx_diag_sel <= '0'; -- uncomment this line to force errors by using a different tx sequence
+ WAIT FOR 5*c_period; -- for multiple cycles to show that all bits get in error state
+ tx_diag_sel <= '1';
+ WAIT FOR c_nof_cycles*c_period; -- some more cylces to show that the diag_res error state is preserved
+ tx_diag_en <= '0'; -- stop tx
+ rx_diag_en <= '0'; -- stop diag_res
+
+ WAIT FOR c_nof_cycles*c_period;
+ tb_end <= '1';
+ WAIT FOR c_nof_cycles*c_period;
+ WAIT;
+ END PROCESS;
+
+ u_diag_tx_seq : ENTITY work.diag_tx_seq
+ GENERIC MAP (
+ g_dat_w => c_dat_w
+ )
+ PORT MAP (
+ clk => clk,
+ rst => rst,
+ diag_en => tx_diag_en,
+ diag_sel => tx_diag_sel,
+ diag_req => tx_diag_req,
+ out_dat => seq_dat,
+ out_val => seq_val
+ );
+
+ u_diag_rx_seq : ENTITY work.diag_rx_seq
+ GENERIC MAP (
+ g_dat_w => c_dat_w,
+ g_diag_res_w => c_diag_res_w
+ )
+ PORT MAP (
+ clk => clk,
+ rst => rst,
+ in_dat => seq_dat,
+ in_val => seq_val,
+ diag_en => rx_diag_en,
+ diag_sel => rx_diag_sel,
+ diag_res => diag_res,
+ diag_res_val => diag_res_val
+ );
+
+ p_report : PROCESS (clk)
+ BEGIN
+ IF rising_edge(clk) THEN
+ IF diag_res_val='1' THEN
+ ASSERT UNSIGNED(diag_res)=0 REPORT "DIAG sequence mismatch occured.";
+ END IF;
+ END IF;
+ END PROCESS;
+
+END tb;
+