diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index dc9b8b805a4c6f04e9da0b69b7b019340f280c6d..4703e1799ee43a64a566f6b0394ad2ee42622311 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -137,7 +137,7 @@ peripherals:
address_offset: 0x0
number_of_fields: 1
radix: unsigned
- #radix_width: g_gain_w
+ #user_width: g_gain_w # EK TODO check
radix_resolution: 0 - g_lsb_w
- - field_name: unused
field_description: "Not used."
@@ -161,12 +161,12 @@ peripherals:
range (h downto 0) where the first header field (eth_destination_mac) is at index h.
. the RO fields are filled in by the logic, when the packet header is transmitted, however
the read value does not still represents the MM write value, not the transmitted value.
- . dp_bsn with radix_width = 64 is stored as:
+ . dp_bsn with user_width = 64 is stored as:
word byte
addr addr bits
0 0x0 [31:0] = dp_bsn[31:0]
1 0x4 [31:0] = dp_bsn[63:32]
- . eth_dst_mac with radix_width = 48 is stored as:
+ . eth_dst_mac with user_width = 48 is stored as:
word byte
addr addr bits
21 0x84 [31:0] = eth_dst_mac[31:0]
@@ -175,8 +175,8 @@ peripherals:
mm_port_type: REG
fields:
# eth field group
- - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
- - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
+ - - { field_name: eth_destination_mac, width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
- - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
@@ -212,13 +212,13 @@ peripherals:
- { field_name: beamlet_width, width: 3, bit_offset: 5, access_mode: RW, address_offset: 0x24 }
- { field_name: gn_index, width: 5, bit_offset: 0, access_mode: RW, address_offset: 0x24 }
- - - { field_name: reserved, width: 32, access_mode: RW, address_offset: 0x1C, radix_width: 40 }
+ - - { field_name: reserved, width: 32, user_width: 40, access_mode: RW, address_offset: 0x1C }
- - { field_name: beamlet_scale, width: 16, access_mode: RW, address_offset: 0x18 }
- - { field_name: beamlet_index, width: 16, access_mode: RW, address_offset: 0x14 }
- - { field_name: nof_blocks_per_packet, width: 8, access_mode: RW, address_offset: 0x10 }
- - { field_name: nof_beamlets_per_block, width: 16, access_mode: RW, address_offset: 0xC }
- - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+ - - { field_name: BSN, width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_sst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -239,8 +239,9 @@ peripherals:
mm_port_type: REG
fields:
# eth field group
- - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
- - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
+ - - { field_name: word_align, width: 16, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: eth_destination_mac, width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
- - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
@@ -288,7 +289,7 @@ peripherals:
- - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
- - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
- - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+ - - { field_name: BSN, width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_bst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -309,8 +310,9 @@ peripherals:
mm_port_type: REG
fields:
# eth field group
- - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
- - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
+ - - { field_name: word_align, width: 16, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: eth_destination_mac, width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
- - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
@@ -358,7 +360,7 @@ peripherals:
- - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
- - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
- - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+ - - { field_name: BSN, width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
- peripheral_name: sdp_statistics_offload_hdr_dat_xst # pi_dp_offload_tx_hdr_dat_lofar2_sdp_statistics_offload.py
@@ -380,8 +382,9 @@ peripherals:
mm_port_type: REG
fields:
# eth field group
- - - { field_name: eth_destination_mac, width: 32, access_mode: RW, address_offset: 0x84, radix_width: 48 }
- - - { field_name: eth_source_mac, width: 32, access_mode: RO, address_offset: 0x7C, radix_width: 48 }
+ - - { field_name: word_align, width: 16, access_mode: RW, address_offset: 0x8C }
+ - - { field_name: eth_destination_mac, width: 32, user_width: 48, access_mode: RW, address_offset: 0x84 }
+ - - { field_name: eth_source_mac, width: 32, user_width: 48, access_mode: RO, address_offset: 0x7C }
- - { field_name: eth_type, width: 16, access_mode: RO, address_offset: 0x78 }
# ip field group
- - { field_name: ip_version, width: 4, access_mode: RW, address_offset: 0x74 }
@@ -431,5 +434,5 @@ peripherals:
- - { field_name: nof_bytes_per_statistic, width: 8, access_mode: RW, address_offset: 0x10 }
- - { field_name: nof_statistics_per_packet, width: 16, access_mode: RW, address_offset: 0xC }
- - { field_name: block_period, width: 16, access_mode: RW, address_offset: 0x8 }
- - - { field_name: BSN, width: 32, access_mode: RW, address_offset: 0x0, radix_width: 64 }
+ - - { field_name: BSN, width: 32, user_width: 64, access_mode: RW, address_offset: 0x0 }
diff --git a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
index 254ac5e1c7e182c50a91e78df03f08789fb39790..1446b091aecfe4be79ec88229d6da1a960ed82e2 100644
--- a/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
+++ b/boards/uniboard2b/libraries/unb2b_board/unb2b_board.peripheral.yaml
@@ -106,11 +106,11 @@ peripherals:
address_offset: 0x4
- - field_name: design_name
field_description: "FPGA FW design name string."
+ user_width: 8
access_mode: RO
address_offset: 0x8
number_of_fields: 13
radix: char
- radix_width: 8
- - field_name: stamp_date
field_description: "FPGA FW compile date string."
access_mode: RO
@@ -129,11 +129,11 @@ peripherals:
radix: hexadecimal
- - field_name: design_note
field_description: "FPGA FW design note string."
+ user_width: 8
access_mode: RO
address_offset: 0x50
number_of_fields: 13
radix: char
- radix_width: 8
- peripheral_name: wdi # pi_wdi.py
peripheral_description: ""
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 2d2b0570c3c965e81927fb4b479bb79817c3d709..2b8a2d2c526b0493f40e9c2debbe8270d88a4ca2 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -139,9 +139,9 @@ peripherals:
# address_offset: 0xC
- - field_name: bsn
field_description: "Initial BSN"
+ user_width: 64
access_mode: RW
address_offset: 0x8
- radix_width: 64
- peripheral_name: dp_bsn_source_v2 # pi_dp_bsn_source_v2.py
@@ -185,9 +185,9 @@ peripherals:
# address_offset: 0xC
- - field_name: bsn_init
field_description: "Initial BSN"
+ user_width: 64
access_mode: RW
address_offset: 0x8
- radix_width: 64
- - field_name: bsn_time_offset
field_description: "The BSN block time offset in number of clock cycles, with respect to the PPS."
width: g_bsn_time_offset_w
@@ -213,9 +213,9 @@ peripherals:
# address_offset: 0x4
- - field_name: scheduled_bsn
field_description: "Write scheduled BSN. First access lo, then hi."
+ user_width: 64
access_mode: RW
address_offset: 0x0
- radix_width: 64
- peripheral_name: dp_bsn_monitor # pi_dp_bsn_monitor.py
@@ -258,9 +258,9 @@ peripherals:
# address_offset: 0x8
- - field_name: bsn_at_sync
field_description: "Data stream BSN at sync."
+ user_width: 64
access_mode: RO
address_offset: 0x4
- radix_width: 64
- - field_name: nof_sop
field_description: "Number data blocks (sop = start of packet) during last sync interval."
access_mode: RO
@@ -283,9 +283,9 @@ peripherals:
# address_offset: 0x1C
- - field_name: bsn_first
field_description: "First data stream BSN ever."
+ user_width: 64
access_mode: RO
address_offset: 0x18
- radix_width: 64
- - field_name: bsn_first_cycle_cnt
field_description: "Arrival latency of first data stream BSN ever, relative to local sync."
access_mode: RO
@@ -332,9 +332,9 @@ peripherals:
# address_offset: 0x8
- - field_name: bsn_at_sync
field_description: "Data stream BSN at sync."
+ user_width: 64
access_mode: RO
address_offset: 0x4
- radix_width: 64
- - field_name: nof_sop
field_description: "Number data blocks (sop = start of packet) during last sync interval."
access_mode: RO
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
index c7c9f0c1f8718215ec467035485555bc0c4dac51..9b44ee5f6e297b4fc638aafd0f0f19809669d498 100644
--- a/libraries/dsp/st/st.peripheral.yaml
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -64,9 +64,9 @@ peripherals:
- - field_name: power
field_description: ""
width: 32
+ user_width: g_stat_data_w
address_offset: 0x0
number_of_fields: g_nof_stat * g_stat_data_sz
- radix_width: g_stat_data_w
- peripheral_name: st_bst_for_sdp # pi_st_bst.py
@@ -94,6 +94,6 @@ peripherals:
- - field_name: power
field_description: ""
width: 32
+ user_width: g_stat_data_w
address_offset: 0x0
number_of_fields: g_nof_stat * g_stat_data_sz
- radix_width: g_stat_data_w
diff --git a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
index c70b59c3b9abca3930868c04f33f630373978632..704335142b480d22362f0fec75559eede8bdea8e 100644
--- a/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
+++ b/libraries/io/nw_10GbE/nw_10GbE.peripheral.yaml
@@ -31,120 +31,120 @@ peripherals:
mm_port_description: "MAC registers"
number_of_mm_ports: g_nof_macs
fields:
- - - {field_name: rx_transfer_control, width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
- - - {field_name: rx_transfer_status, width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
- - - {field_name: rx_padcrc_control, width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
- - - {field_name: rx_crccheck_control, width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
- - - {field_name: rx_pktovrflow_error, width: 32, access_mode: RO, address_offset: 0x0300, radix_width: 36 } # = 0x00C0
- - - {field_name: rx_pktovrflow_etherStatsDropEvents, width: 32, access_mode: RO, address_offset: 0x0308, radix_width: 36 } # = 0x00C2
- - - {field_name: rx_lane_decoder_preamble_control, width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
- - - {field_name: rx_preamble_inserter_control, width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
- - - {field_name: rx_frame_control, width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
- - - {field_name: rx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
- - - {field_name: rx_frame_addr0, width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
- - - {field_name: rx_frame_addr1, width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
- - - {field_name: rx_frame_spaddr0_0, width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
- - - {field_name: rx_frame_spaddr0_1, width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
- - - {field_name: rx_frame_spaddr1_0, width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
- - - {field_name: rx_frame_spaddr1_1, width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
- - - {field_name: rx_frame_spaddr2_0, width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
- - - {field_name: rx_frame_spaddr2_1, width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
- - - {field_name: rx_frame_spaddr3_0, width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
- - - {field_name: rx_frame_spaddr3_1, width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
- - - {field_name: rx_pfc_control, width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
- - - {field_name: tx_transfer_control, width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
- - - {field_name: tx_transfer_status, width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
- - - {field_name: tx_padins_control, width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
- - - {field_name: tx_crcins_control, width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
- - - {field_name: tx_pktunderflow_error, width: 32, access_mode: RO, address_offset: 0x4300, radix_width: 36 } # = 0x10C0
- - - {field_name: tx_preamble_control, width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
- - - {field_name: tx_pauseframe_control, width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
- - - {field_name: tx_pauseframe_quanta, width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
- - - {field_name: tx_pauseframe_enable, width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
+ - - {field_name: rx_transfer_control, width: 1, access_mode: RW, address_offset: 0x0000 } # = 0x0000
+ - - {field_name: rx_transfer_status, width: 1, access_mode: RO, address_offset: 0x0004 } # = 0x0001
+ - - {field_name: rx_padcrc_control, width: 2, access_mode: RW, address_offset: 0x0100 } # = 0x0040
+ - - {field_name: rx_crccheck_control, width: 2, access_mode: RW, address_offset: 0x0200 } # = 0x0080
+ - - {field_name: rx_pktovrflow_error, width: 32, user_width: 36, access_mode: RO, address_offset: 0x0300 } # = 0x00C0
+ - - {field_name: rx_pktovrflow_etherStatsDropEvents, width: 32, user_width: 36, access_mode: RO, address_offset: 0x0308 } # = 0x00C2
+ - - {field_name: rx_lane_decoder_preamble_control, width: 1, access_mode: RW, address_offset: 0x0400 } # = 0x0100
+ - - {field_name: rx_preamble_inserter_control, width: 1, access_mode: RW, address_offset: 0x0500 } # = 0x0140
+ - - {field_name: rx_frame_control, width: 20, access_mode: RW, address_offset: 0x2000 } # = 0x0800
+ - - {field_name: rx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x2004 } # = 0x0801
+ - - {field_name: rx_frame_addr0, width: 16, access_mode: RW, address_offset: 0x2008 } # = 0x0802
+ - - {field_name: rx_frame_addr1, width: 16, access_mode: RW, address_offset: 0x200c } # = 0x0803
+ - - {field_name: rx_frame_spaddr0_0, width: 16, access_mode: RW, address_offset: 0x2010 } # = 0x0804
+ - - {field_name: rx_frame_spaddr0_1, width: 16, access_mode: RW, address_offset: 0x2014 } # = 0x0805
+ - - {field_name: rx_frame_spaddr1_0, width: 16, access_mode: RW, address_offset: 0x2018 } # = 0x0806
+ - - {field_name: rx_frame_spaddr1_1, width: 16, access_mode: RW, address_offset: 0x201c } # = 0x0807
+ - - {field_name: rx_frame_spaddr2_0, width: 16, access_mode: RW, address_offset: 0x2020 } # = 0x0808
+ - - {field_name: rx_frame_spaddr2_1, width: 16, access_mode: RW, address_offset: 0x2024 } # = 0x0809
+ - - {field_name: rx_frame_spaddr3_0, width: 16, access_mode: RW, address_offset: 0x2028 } # = 0x080A
+ - - {field_name: rx_frame_spaddr3_1, width: 16, access_mode: RW, address_offset: 0x202c } # = 0x080B
+ - - {field_name: rx_pfc_control, width: 17, access_mode: RW, address_offset: 0x2060 } # = 0x0818
+ - - {field_name: tx_transfer_control, width: 1, access_mode: RW, address_offset: 0x4000 } # = 0x1000
+ - - {field_name: tx_transfer_status, width: 1, access_mode: RO, address_offset: 0x4004 } # = 0x1001
+ - - {field_name: tx_padins_control, width: 1, access_mode: RW, address_offset: 0x4100 } # = 0x1040
+ - - {field_name: tx_crcins_control, width: 2, access_mode: RW, address_offset: 0x4200 } # = 0x1080
+ - - {field_name: tx_pktunderflow_error, width: 32, user_width: 36, access_mode: RO, address_offset: 0x4300 } # = 0x10C0
+ - - {field_name: tx_preamble_control, width: 1, access_mode: RW, address_offset: 0x4400 } # = 0x1100
+ - - {field_name: tx_pauseframe_control, width: 2, access_mode: RW, address_offset: 0x4500 } # = 0x1140
+ - - {field_name: tx_pauseframe_quanta, width: 16, access_mode: RW, address_offset: 0x4504 } # = 0x1141
+ - - {field_name: tx_pauseframe_enable, width: 1, access_mode: RW, address_offset: 0x4508 } # = 0x1142
# Altera is unclear about the width of the quanta registers. Assuming 32 bits, where bits 16:31 are reserved:
- - - {field_name: pfc_pause_quanta_0, width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
- - - {field_name: pfc_pause_quanta_1, width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
- - - {field_name: pfc_pause_quanta_2, width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
- - - {field_name: pfc_pause_quanta_3, width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
- - - {field_name: pfc_pause_quanta_4, width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
- - - {field_name: pfc_pause_quanta_5, width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
- - - {field_name: pfc_pause_quanta_6, width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
- - - {field_name: pfc_pause_quanta_7, width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
- - - {field_name: pfc_holdoff_quanta_0, width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
- - - {field_name: pfc_holdoff_quanta_1, width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
- - - {field_name: pfc_holdoff_quanta_2, width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
- - - {field_name: pfc_holdoff_quanta_3, width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
- - - {field_name: pfc_holdoff_quanta_4, width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
- - - {field_name: pfc_holdoff_quanta_5, width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
- - - {field_name: pfc_holdoff_quanta_6, width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
- - - {field_name: pfc_holdoff_quanta_7, width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
- - - {field_name: tx_pfc_priority_enable, width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
- - - {field_name: tx_addrins_control, width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
- - - {field_name: tx_addrins_macaddr0, width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
- - - {field_name: tx_addrins_macaddr1, width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
- - - {field_name: tx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
- - - {field_name: rx_stats_clr, width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
- - - {field_name: tx_stats_clr, width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
- - - {field_name: rx_stats_framesOK, width: 32, access_mode: RO, address_offset: 0x3008, radix_width: 36 } # = 0x0C02
- - - {field_name: tx_stats_framesOK, width: 32, access_mode: RO, address_offset: 0x7008, radix_width: 36 } # = 0x1C02
- - - {field_name: rx_stats_framesErr, width: 32, access_mode: RO, address_offset: 0x3010, radix_width: 36 } # = 0x0C04
- - - {field_name: tx_stats_framesErr, width: 32, access_mode: RO, address_offset: 0x7010, radix_width: 36 } # = 0x1C04
- - - {field_name: rx_stats_framesCRCErr, width: 32, access_mode: RO, address_offset: 0x3018, radix_width: 36 } # = 0x0C06
- - - {field_name: tx_stats_framesCRCErr, width: 32, access_mode: RO, address_offset: 0x7018, radix_width: 36 } # = 0x1C06
- - - {field_name: rx_stats_octetsOK, width: 32, access_mode: RO, address_offset: 0x3020, radix_width: 36 } # = 0x0C08
- - - {field_name: tx_stats_octetsOK, width: 32, access_mode: RO, address_offset: 0x7020, radix_width: 36 } # = 0x1C08
- - - {field_name: rx_stats_pauseMACCtrl_Frames, width: 32, access_mode: RO, address_offset: 0x3028, radix_width: 36 } # = 0x0C0A
- - - {field_name: tx_stats_pauseMACCtrl_Frames, width: 32, access_mode: RO, address_offset: 0x7028, radix_width: 36 } # = 0x1C0A
- - - {field_name: rx_stats_ifErrors, width: 32, access_mode: RO, address_offset: 0x3030, radix_width: 36 } # = 0x0C0C
- - - {field_name: tx_stats_ifErrors, width: 32, access_mode: RO, address_offset: 0x7030, radix_width: 36 } # = 0x1C0C
- - - {field_name: rx_stats_unicast_FramesOK, width: 32, access_mode: RO, address_offset: 0x3038, radix_width: 36 } # = 0x0C0E
- - - {field_name: tx_stats_unicast_FramesOK, width: 32, access_mode: RO, address_offset: 0x7038, radix_width: 36 } # = 0x1C0E
- - - {field_name: rx_stats_unicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3040, radix_width: 36 } # = 0x0C10
- - - {field_name: tx_stats_unicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7040, radix_width: 36 } # = 0x1C10
- - - {field_name: rx_stats_multicastFramesOK, width: 32, access_mode: RO, address_offset: 0x3048, radix_width: 36 } # = 0x0C12
- - - {field_name: tx_stats_multicastFramesOK, width: 32, access_mode: RO, address_offset: 0x7048, radix_width: 36 } # = 0x1C12
- - - {field_name: rx_stats_multicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3050, radix_width: 36 } # = 0x0C14
- - - {field_name: tx_stats_multicast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7050, radix_width: 36 } # = 0x1C14
- - - {field_name: rx_stats_broadcastFramesOK, width: 32, access_mode: RO, address_offset: 0x3058, radix_width: 36 } # = 0x0C16
- - - {field_name: tx_stats_broadcastFramesOK, width: 32, access_mode: RO, address_offset: 0x7058, radix_width: 36 } # = 0x1C16
- - - {field_name: rx_stats_broadcast_FramesErr, width: 32, access_mode: RO, address_offset: 0x3060, radix_width: 36 } # = 0x0C18
- - - {field_name: tx_stats_broadcast_FramesErr, width: 32, access_mode: RO, address_offset: 0x7060, radix_width: 36 } # = 0x1C18
- - - {field_name: rx_stats_etherStatsOctets, width: 32, access_mode: RO, address_offset: 0x3068, radix_width: 36 } # = 0x0C1A
- - - {field_name: tx_stats_etherStatsOctets, width: 32, access_mode: RO, address_offset: 0x7068, radix_width: 36 } # = 0x1C1A
- - - {field_name: rx_stats_etherStatsPkts, width: 32, access_mode: RO, address_offset: 0x3070, radix_width: 36 } # = 0x0C1C
- - - {field_name: tx_stats_etherStatsPkts, width: 32, access_mode: RO, address_offset: 0x7070, radix_width: 36 } # = 0x1C1C
- - - {field_name: rx_stats_etherStats_UndersizePkts, width: 32, access_mode: RO, address_offset: 0x3078, radix_width: 36 } # = 0x0C1E
- - - {field_name: tx_stats_etherStats_UndersizePkts, width: 32, access_mode: RO, address_offset: 0x7078, radix_width: 36 } # = 0x1C1E
- - - {field_name: rx_stats_etherStats_OversizePkts, width: 32, access_mode: RO, address_offset: 0x3080, radix_width: 36 } # = 0x0C20
- - - {field_name: tx_stats_etherStats_OversizePkts, width: 32, access_mode: RO, address_offset: 0x7080, radix_width: 36 } # = 0x1C20
- - - {field_name: rx_stats_etherStats_Pkts64Octets, width: 32, access_mode: RO, address_offset: 0x3088, radix_width: 36 } # = 0x0C22
- - - {field_name: tx_stats_etherStats_Pkts64Octets, width: 32, access_mode: RO, address_offset: 0x7088, radix_width: 36 } # = 0x1C22
- - - {field_name: rx_stats_etherStats_Pkts65to127Octets, width: 32, access_mode: RO, address_offset: 0x3090, radix_width: 36 } # = 0x0C24
- - - {field_name: tx_stats_etherStats_Pkts65to127Octets, width: 32, access_mode: RO, address_offset: 0x7090, radix_width: 36 } # = 0x1C24
- - - {field_name: rx_stats_etherStats_Pkts128to255Octets, width: 32, access_mode: RO, address_offset: 0x3098, radix_width: 36 } # = 0x0C26
- - - {field_name: tx_stats_etherStats_Pkts128to255Octets, width: 32, access_mode: RO, address_offset: 0x7098, radix_width: 36 } # = 0x1C26
- - - {field_name: rx_stats_etherStats_Pkts256to511Octets, width: 32, access_mode: RO, address_offset: 0x30a0, radix_width: 36 } # = 0x0C28
- - - {field_name: tx_stats_etherStats_Pkts256to511Octets, width: 32, access_mode: RO, address_offset: 0x70a0, radix_width: 36 } # = 0x1C28
- - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, width: 32, access_mode: RO, address_offset: 0x30a8, radix_width: 36 } # = 0x0C2A
- - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, width: 32, access_mode: RO, address_offset: 0x70a8, radix_width: 36 } # = 0x1C2A
- - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, width: 32, access_mode: RO, address_offset: 0x30b0, radix_width: 36 } # = 0x0C2C
- - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, width: 32, access_mode: RO, address_offset: 0x70b0, radix_width: 36 } # = 0x1C2C
- - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, width: 32, access_mode: RO, address_offset: 0x30b8, radix_width: 36 } # = 0x0C2E
- - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, width: 32, access_mode: RO, address_offset: 0x70b8, radix_width: 36 } # = 0x1C2E
- - - {field_name: rx_stats_etherStats_Fragments, width: 32, access_mode: RO, address_offset: 0x30c0, radix_width: 36 } # = 0x0C30
- - - {field_name: tx_stats_etherStats_Fragments, width: 32, access_mode: RO, address_offset: 0x70c0, radix_width: 36 } # = 0x1C30
- - - {field_name: rx_stats_etherStats_Jabbers, width: 32, access_mode: RO, address_offset: 0x30c8, radix_width: 36 } # = 0x0C32
- - - {field_name: tx_stats_etherStats_Jabbers, width: 32, access_mode: RO, address_offset: 0x70c8, radix_width: 36 } # = 0x1C32
- - - {field_name: rx_stats_etherStatsCRCErr, width: 32, access_mode: RO, address_offset: 0x30d0, radix_width: 36 } # = 0x0C34
- - - {field_name: tx_stats_etherStatsCRCErr, width: 32, access_mode: RO, address_offset: 0x70d0, radix_width: 36 } # = 0x1C34
- - - {field_name: rx_stats_unicastMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x30d8, radix_width: 36 } # = 0x0C36
- - - {field_name: tx_stats_unicastMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x70d8, radix_width: 36 } # = 0x1C36
- - - {field_name: rx_stats_multicastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x30e0, radix_width: 36 } # = 0x0C38
- - - {field_name: tx_stats_multicastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x70e0, radix_width: 36 } # = 0x1C38
- - - {field_name: rx_stats_broadcastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x30e8, radix_width: 36 } # = 0x0C3A
- - - {field_name: tx_stats_broadcastMAC_CtrlFrames, width: 32, access_mode: RO, address_offset: 0x70e8, radix_width: 36 } # = 0x1C3A
- - - {field_name: rx_stats_PFCMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x30f0, radix_width: 36 } # = 0x0C3C
- - - {field_name: tx_stats_PFCMACCtrlFrames, width: 32, access_mode: RO, address_offset: 0x70f0, radix_width: 36 } # = 0x1C3C
+ - - {field_name: pfc_pause_quanta_0, width: 32, access_mode: RW, address_offset: 0x4600 } # = 0x1180
+ - - {field_name: pfc_pause_quanta_1, width: 32, access_mode: RW, address_offset: 0x4604 } # = 0x1181
+ - - {field_name: pfc_pause_quanta_2, width: 32, access_mode: RW, address_offset: 0x4608 } # = 0x1182
+ - - {field_name: pfc_pause_quanta_3, width: 32, access_mode: RW, address_offset: 0x460c } # = 0x1183
+ - - {field_name: pfc_pause_quanta_4, width: 32, access_mode: RW, address_offset: 0x4610 } # = 0x1184
+ - - {field_name: pfc_pause_quanta_5, width: 32, access_mode: RW, address_offset: 0x4614 } # = 0x1185
+ - - {field_name: pfc_pause_quanta_6, width: 32, access_mode: RW, address_offset: 0x4618 } # = 0x1186
+ - - {field_name: pfc_pause_quanta_7, width: 32, access_mode: RW, address_offset: 0x461c } # = 0x1187
+ - - {field_name: pfc_holdoff_quanta_0, width: 32, access_mode: RW, address_offset: 0x4640 } # = 0x1190
+ - - {field_name: pfc_holdoff_quanta_1, width: 32, access_mode: RW, address_offset: 0x4644 } # = 0x1191
+ - - {field_name: pfc_holdoff_quanta_2, width: 32, access_mode: RW, address_offset: 0x4648 } # = 0x1192
+ - - {field_name: pfc_holdoff_quanta_3, width: 32, access_mode: RW, address_offset: 0x464c } # = 0x1193
+ - - {field_name: pfc_holdoff_quanta_4, width: 32, access_mode: RW, address_offset: 0x4650 } # = 0x1194
+ - - {field_name: pfc_holdoff_quanta_5, width: 32, access_mode: RW, address_offset: 0x4654 } # = 0x1195
+ - - {field_name: pfc_holdoff_quanta_6, width: 32, access_mode: RW, address_offset: 0x4658 } # = 0x1196
+ - - {field_name: pfc_holdoff_quanta_7, width: 32, access_mode: RW, address_offset: 0x465c } # = 0x1197
+ - - {field_name: tx_pfc_priority_enable, width: 8, access_mode: RW, address_offset: 0x4680 } # = 0x11A0
+ - - {field_name: tx_addrins_control, width: 1, access_mode: RW, address_offset: 0x4800 } # = 0x1200
+ - - {field_name: tx_addrins_macaddr0, width: 32, access_mode: RW, address_offset: 0x4804 } # = 0x1201
+ - - {field_name: tx_addrins_macaddr1, width: 16, access_mode: RW, address_offset: 0x4808 } # = 0x1202
+ - - {field_name: tx_frame_maxlength, width: 16, access_mode: RW, address_offset: 0x6004 } # = 0x1801
+ - - {field_name: rx_stats_clr, width: 1, access_mode: RW, address_offset: 0x3000 } # = 0x0C00
+ - - {field_name: tx_stats_clr, width: 1, access_mode: RW, address_offset: 0x7000 } # = 0x1C00
+ - - {field_name: rx_stats_framesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3008 } # = 0x0C02
+ - - {field_name: tx_stats_framesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7008 } # = 0x1C02
+ - - {field_name: rx_stats_framesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3010 } # = 0x0C04
+ - - {field_name: tx_stats_framesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7010 } # = 0x1C04
+ - - {field_name: rx_stats_framesCRCErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3018 } # = 0x0C06
+ - - {field_name: tx_stats_framesCRCErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7018 } # = 0x1C06
+ - - {field_name: rx_stats_octetsOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3020 } # = 0x0C08
+ - - {field_name: tx_stats_octetsOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7020 } # = 0x1C08
+ - - {field_name: rx_stats_pauseMACCtrl_Frames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3028 } # = 0x0C0A
+ - - {field_name: tx_stats_pauseMACCtrl_Frames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7028 } # = 0x1C0A
+ - - {field_name: rx_stats_ifErrors, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3030 } # = 0x0C0C
+ - - {field_name: tx_stats_ifErrors, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7030 } # = 0x1C0C
+ - - {field_name: rx_stats_unicast_FramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3038 } # = 0x0C0E
+ - - {field_name: tx_stats_unicast_FramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7038 } # = 0x1C0E
+ - - {field_name: rx_stats_unicast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3040 } # = 0x0C10
+ - - {field_name: tx_stats_unicast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7040 } # = 0x1C10
+ - - {field_name: rx_stats_multicastFramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3048 } # = 0x0C12
+ - - {field_name: tx_stats_multicastFramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7048 } # = 0x1C12
+ - - {field_name: rx_stats_multicast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3050 } # = 0x0C14
+ - - {field_name: tx_stats_multicast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7050 } # = 0x1C14
+ - - {field_name: rx_stats_broadcastFramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3058 } # = 0x0C16
+ - - {field_name: tx_stats_broadcastFramesOK, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7058 } # = 0x1C16
+ - - {field_name: rx_stats_broadcast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3060 } # = 0x0C18
+ - - {field_name: tx_stats_broadcast_FramesErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7060 } # = 0x1C18
+ - - {field_name: rx_stats_etherStatsOctets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3068 } # = 0x0C1A
+ - - {field_name: tx_stats_etherStatsOctets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7068 } # = 0x1C1A
+ - - {field_name: rx_stats_etherStatsPkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3070 } # = 0x0C1C
+ - - {field_name: tx_stats_etherStatsPkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7070 } # = 0x1C1C
+ - - {field_name: rx_stats_etherStats_UndersizePkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3078 } # = 0x0C1E
+ - - {field_name: tx_stats_etherStats_UndersizePkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7078 } # = 0x1C1E
+ - - {field_name: rx_stats_etherStats_OversizePkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3080 } # = 0x0C20
+ - - {field_name: tx_stats_etherStats_OversizePkts, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7080 } # = 0x1C20
+ - - {field_name: rx_stats_etherStats_Pkts64Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3088 } # = 0x0C22
+ - - {field_name: tx_stats_etherStats_Pkts64Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7088 } # = 0x1C22
+ - - {field_name: rx_stats_etherStats_Pkts65to127Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3090 } # = 0x0C24
+ - - {field_name: tx_stats_etherStats_Pkts65to127Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7090 } # = 0x1C24
+ - - {field_name: rx_stats_etherStats_Pkts128to255Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x3098 } # = 0x0C26
+ - - {field_name: tx_stats_etherStats_Pkts128to255Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x7098 } # = 0x1C26
+ - - {field_name: rx_stats_etherStats_Pkts256to511Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a0 } # = 0x0C28
+ - - {field_name: tx_stats_etherStats_Pkts256to511Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a0 } # = 0x1C28
+ - - {field_name: rx_stats_etherStats_Pkts512to1023Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30a8 } # = 0x0C2A
+ - - {field_name: tx_stats_etherStats_Pkts512to1023Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70a8 } # = 0x1C2A
+ - - {field_name: rx_stats_etherStat_Pkts1024to1518Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b0 } # = 0x0C2C
+ - - {field_name: tx_stats_etherStat_Pkts1024to1518Octets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b0 } # = 0x1C2C
+ - - {field_name: rx_stats_etherStats_Pkts1519toXOctets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30b8 } # = 0x0C2E
+ - - {field_name: tx_stats_etherStats_Pkts1519toXOctets, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70b8 } # = 0x1C2E
+ - - {field_name: rx_stats_etherStats_Fragments, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c0 } # = 0x0C30
+ - - {field_name: tx_stats_etherStats_Fragments, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c0 } # = 0x1C30
+ - - {field_name: rx_stats_etherStats_Jabbers, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30c8 } # = 0x0C32
+ - - {field_name: tx_stats_etherStats_Jabbers, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70c8 } # = 0x1C32
+ - - {field_name: rx_stats_etherStatsCRCErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d0 } # = 0x0C34
+ - - {field_name: tx_stats_etherStatsCRCErr, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d0 } # = 0x1C34
+ - - {field_name: rx_stats_unicastMACCtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30d8 } # = 0x0C36
+ - - {field_name: tx_stats_unicastMACCtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70d8 } # = 0x1C36
+ - - {field_name: rx_stats_multicastMAC_CtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e0 } # = 0x0C38
+ - - {field_name: tx_stats_multicastMAC_CtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e0 } # = 0x1C38
+ - - {field_name: rx_stats_broadcastMAC_CtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30e8 } # = 0x0C3A
+ - - {field_name: tx_stats_broadcastMAC_CtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70e8 } # = 0x1C3A
+ - - {field_name: rx_stats_PFCMACCtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x30f0 } # = 0x0C3C
+ - - {field_name: tx_stats_PFCMACCtrlFrames, width: 32, user_width: 36, access_mode: RO, address_offset: 0x70f0 } # = 0x1C3C
- peripheral_name: nw_10GbE_eth10g # pi_nw_10GbE_eth10g.py / pi_10GbE.py