From bb7588beeeab72fe31f1dfbeaba9eeb8a02808c5 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Thu, 6 Jul 2023 09:49:57 +0200
Subject: [PATCH] replaced if statement with generate statement
---
.../eth/src/vhdl/eth_ip_header_checksum.vhd | 66 ++++++++++++-------
1 file changed, 42 insertions(+), 24 deletions(-)
diff --git a/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd b/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
index bdd74448aa..5f5067f952 100644
--- a/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
@@ -74,6 +74,7 @@ architecture rtl of eth_ip_header_checksum is
constant c_hdr_nof_words : natural := ceil_div(c_hdr_len, g_data_w);
constant c_crc_word_span : natural := 1 + c_hdr_crc_word_hi - c_hdr_crc_word_lo;
+ constant c_crc_in_one_word : boolean := c_crc_word_span = 1;
signal checksum : std_logic_vector(c_network_ip_header_checksum_w - 1 downto 0) := (others => '0');
signal count : std_logic_vector(31 downto 0);
@@ -92,34 +93,51 @@ begin
---------------------------------------------------
-- process to insert checksum in outgoing stream --
---------------------------------------------------
- p_insert_crc : process(dp_pipeline_src_out, checksum, count, reg_done)
- variable v_count : natural := 0;
- variable v_hi : natural := 0;
- variable v_lo : natural := 0;
- begin
- v_count := TO_UINT(count);
- src_out <= dp_pipeline_src_out;
- nxt_reg_done <= reg_done;
- if reg_done = '0' and dp_pipeline_src_out.valid = '1' then
- if v_count = c_hdr_crc_word_hi and v_count = c_hdr_crc_word_lo then -- checksum is in 1 word.
+ gen_insert_crc_one : if c_crc_in_one_word generate -- checksum is in 1 word.
+ p_insert_crc_one : process(dp_pipeline_src_out, checksum, count, reg_done)
+ variable v_count : natural := 0;
+ begin
+ v_count := TO_UINT(count);
+ src_out <= dp_pipeline_src_out;
+ nxt_reg_done <= reg_done;
+ if reg_done = '0' and dp_pipeline_src_out.valid = '1' and v_count = c_hdr_crc_word_hi then
src_out.data(c_crc_hi_bit_in_word downto c_crc_lo_bit_in_word) <= checksum;
nxt_reg_done <= '1';
- elsif v_count = c_hdr_crc_word_hi then
- src_out.data(c_crc_hi_bit_in_word downto 0) <= checksum(c_network_ip_header_checksum_w - 1 downto c_network_ip_header_checksum_w - c_crc_hi_bit_in_word - 1);
- elsif v_count = c_hdr_crc_word_lo then
- src_out.data(g_data_w - 1 downto c_crc_lo_bit_in_word) <= checksum(g_data_w - c_crc_lo_bit_in_word - 1 downto 0);
- nxt_reg_done <= '1';
- elsif v_count < c_hdr_crc_word_hi and v_count > c_hdr_crc_word_lo then
- v_hi := c_network_ip_header_checksum_w - 1 - c_crc_hi_bit_in_word - 1 - g_data_w * (c_hdr_crc_word_hi - v_count - 1);
- v_lo := v_hi + 1 - g_data_w;
- src_out.data(g_data_w - 1 downto 0) <= checksum(v_hi downto v_lo);
end if;
- end if;
- if reg_done = '1' and dp_pipeline_src_out.eop = '1' then
- nxt_reg_done <= '0';
- end if;
- end process;
+ if reg_done = '1' and dp_pipeline_src_out.eop = '1' then
+ nxt_reg_done <= '0';
+ end if;
+ end process;
+ end generate;
+
+ gen_insert_crc_multi : if not c_crc_in_one_word generate
+ p_insert_crc_multi : process(dp_pipeline_src_out, checksum, count, reg_done)
+ variable v_count : natural := 0;
+ variable v_hi : natural := 0;
+ variable v_lo : natural := 0;
+ begin
+ v_count := TO_UINT(count);
+ src_out <= dp_pipeline_src_out;
+ nxt_reg_done <= reg_done;
+ if reg_done = '0' and dp_pipeline_src_out.valid = '1' then
+ if v_count = c_hdr_crc_word_hi then
+ src_out.data(c_crc_hi_bit_in_word downto 0) <= checksum(c_network_ip_header_checksum_w - 1 downto c_network_ip_header_checksum_w - c_crc_hi_bit_in_word - 1);
+ elsif v_count = c_hdr_crc_word_lo then
+ src_out.data(g_data_w - 1 downto c_crc_lo_bit_in_word) <= checksum(g_data_w - c_crc_lo_bit_in_word - 1 downto 0);
+ nxt_reg_done <= '1';
+ elsif v_count < c_hdr_crc_word_hi and v_count > c_hdr_crc_word_lo then
+ v_hi := c_network_ip_header_checksum_w - 1 - c_crc_hi_bit_in_word - 1 - g_data_w * (c_hdr_crc_word_hi - v_count - 1);
+ v_lo := v_hi + 1 - g_data_w;
+ src_out.data(g_data_w - 1 downto 0) <= checksum(v_hi downto v_lo);
+ end if;
+ end if;
+
+ if reg_done = '1' and dp_pipeline_src_out.eop = '1' then
+ nxt_reg_done <= '0';
+ end if;
+ end process;
+ end generate;
------------------------------------------------------------------------------------------
-- using common_counter to keep track of the word alignment during checksum calculation --
--
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