diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
index 7035896dd0df611db885190793f5dca175091e37..629006f70e379209faff73fc323875805973f7e9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
@@ -203,27 +203,27 @@ peripherals:
mm_port_names:
- REG_STAT_HDR_DAT_SST
-# #############################################################################
-# # Xsub = Subband Correlator (from node_sdp_correlator.vhd)
-# #############################################################################
-#
-# - peripheral_name: dp/dp_bsn_scheduler
-# peripheral_group: xsub
-# mm_port_names:
-# - REG_BSN_SCHEDULER_XSUB
-#
-# - peripheral_name: dp/dp_sync_insert_v2
-# mm_port_names:
-# - REG_DP_SYNC_INSERT_V2
-#
-# - peripheral_name: st/st_xst
-# mm_port_names:
-# - RAM_ST_XSQ
-#
-# - peripheral_name: sdp/sdp_crosslets_subband_select
-# mm_port_names:
-# - REG_CROSSLETS_INFO
-#
+ #############################################################################
+ # Xsub = Subband Correlator (from node_sdp_correlator.vhd)
+ #############################################################################
+
+ - peripheral_name: dp/dp_bsn_scheduler
+ peripheral_group: xsub
+ mm_port_names:
+ - REG_BSN_SCHEDULER_XSUB
+
+ - peripheral_name: dp/dp_sync_insert_v2
+ mm_port_names:
+ - REG_DP_SYNC_INSERT_V2
+
+ - peripheral_name: st/st_xst_for_sdp
+ mm_port_names:
+ - RAM_ST_XSQ
+
+ - peripheral_name: sdp/sdp_crosslets_subband_select
+ mm_port_names:
+ - REG_CROSSLETS_INFO
+
#############################################################################
# BF = Beamformer (from node_sdp_beamformer.vhd)
#############################################################################
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
index a041aae6d83c1972821b3e27f333568006a8c93e..82c0df011c95f6503ba618f2fbe419b37c5765ab 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station.sdc
@@ -97,8 +97,8 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
-# false paths added for the jesd test design
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|link_clk}]
-set_false_path -from [get_clocks {*core_pll|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*core_pll|frame_clk}]
-set_false_path -from [get_clocks {*core_pll|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+# false paths added for the jesd interface as these clocks are independent.
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
+set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
+set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
diff --git a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
index 67eef47dc7e3f47dbb1558b2b6cfac89b0c9593f..84a1502e5dff2560c39693d948b943367d2febba 100644
--- a/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
+++ b/applications/lofar2/libraries/sdp/sdp.peripheral.yaml
@@ -6,7 +6,7 @@ hdl_library_name: sdp
hdl_library_description: "Station Digital Processor (SDP) for LOFAR2.0"
peripherals:
- - peripheral_name: sdp_info # pi_sdp_info.py ?
+ - peripheral_name: sdp_info # pi_sdp_info.py
peripheral_description: "SDP info."
mm_ports:
# MM port for sdp_info.vhd
@@ -31,6 +31,23 @@ peripherals:
- - { field_name: block_period, mm_width: 16, access_mode: RO, address_offset: 0x4 }
- - { field_name: beamlet_scale, mm_width: 16, access_mode: RW, address_offset: 0x0 }
+
+ - peripheral_name: sdp_crosslets_subband_select # pi_sdp_crosslets_info.py
+ peripheral_description: "SDP crosslets info."
+ mm_ports:
+ # MM port for sdp_info.vhd
+ - mm_port_name: REG_CROSSLETS_INFO
+ mm_port_type: REG
+ mm_port_description: |
+ "The SDP crosslets info contains the step size and 15 offsets, that are used to select a new
+ crosslet subband for every integration interval"
+ fields:
+ - - { field_name: step, access_mode: RW, address_offset: 0x3C }
+ - - field_name: offset
+ number_of_fields: 15
+ address_offset: 0x0
+
+
- peripheral_name: sdp_subband_equalizer # pi_sdp_subband_equalizer.py
peripheral_description: "SDP Subband equalizer coefficients."
parameters:
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index ab3d08b91f394964b07440c87d29a487bbe350b4..ae271ee613332fceee60cd871908b4d6690bd0a9 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
--- Authors : J Hargreaves, L Hiemstra
+-- Authors : J Hargreaves, L Hiemstra, R van der Walle
-- Purpose:
-- AIT - ADC (Jesd) receiver, input, timing and associated diagnostic blocks
-- Description:
@@ -124,7 +124,6 @@ ARCHITECTURE str OF node_sdp_adc_input_and_timing IS
SIGNAL rx_rst : STD_LOGIC;
SIGNAL rx_sysref : STD_LOGIC;
- SIGNAL arst : STD_LOGIC;
SIGNAL rx_bsn_source_restart : STD_LOGIC;
-- Sosis and sosi arrays
@@ -213,7 +212,7 @@ BEGIN
GENERIC MAP (
g_nof_streams => c_sdp_S_pn,
g_nof_words => c_sdp_V_sample_delay,
- g_data_w => c_sdp_W_adc_jesd,
+ g_data_w => c_sdp_W_adc,
g_use_sync_in => TRUE
)
PORT MAP (
@@ -393,7 +392,7 @@ BEGIN
GENERIC MAP (
g_cross_clock_domain => TRUE,
g_nof_streams => c_sdp_S_pn,
- g_symbol_w => c_sdp_W_adc_jesd,
+ g_symbol_w => c_sdp_W_adc,
g_nof_symbols_per_data => 1, -- Wideband factor is 1
g_nof_accumulations => g_bsn_nof_clk_per_sync
)
@@ -423,7 +422,7 @@ BEGIN
GENERIC MAP (
g_technology => g_technology,
g_nof_streams => c_sdp_S_pn,
- g_data_w => c_sdp_W_adc_jesd,
+ g_data_w => c_sdp_W_adc,
g_buf_nof_data => g_buf_nof_data,
g_buf_use_sync => TRUE -- when TRUE start filling the buffer at the in_sync, else after the last word was read
)
@@ -447,47 +446,31 @@ BEGIN
-- Output Stage
-- . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
-----------------------------------------------------------------------------
-
- gen_dp_fifo_dc : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
- u_dp_fifo_dc : ENTITY dp_lib.dp_fifo_dc
- GENERIC MAP (
- g_data_w => c_sdp_W_adc_jesd,
- g_bsn_w => c_bs_bsn_w,
- g_use_empty => FALSE, --TRUE,
- g_use_ctrl => TRUE,
- g_use_sync => TRUE,
- g_use_bsn => TRUE,
- g_fifo_size => c_dp_fifo_dc_size
- )
- PORT MAP (
- wr_rst => rx_rst,
- wr_clk => rx_clk,
- rd_rst => dp_rst,
- rd_clk => dp_clk,
- snk_in => st_sosi_arr(I),
- src_out => out_sosi_arr(I)
- );
- END GENERATE;
-
- -- use common dc fifo for restart signal
- u_common_fifo_dc_restart : ENTITY common_lib.common_fifo_dc
- GENERIC MAP (
- g_dat_w => 1,
- g_nof_words => c_dp_fifo_dc_size
- )
- PORT MAP (
- rst => arst,
- wr_clk => rx_clk,
- wr_dat(0) => rx_bsn_source_restart,
- wr_req => bs_sosi.valid,
- rd_clk => dp_clk,
- rd_dat(0) => dp_bsn_source_restart,
- rd_req => '1'
- );
-
- arst <= rx_rst OR dp_rst;
+ u_dp_fifo_dc_arr : ENTITY dp_lib.dp_fifo_dc_arr
+ GENERIC MAP (
+ g_nof_streams => c_sdp_S_pn,
+ g_data_w => c_sdp_W_adc,
+ g_bsn_w => c_bs_bsn_w,
+ g_use_empty => FALSE,
+ g_use_ctrl => TRUE,
+ g_use_sync => TRUE,
+ g_use_bsn => TRUE,
+ g_use_aux => TRUE,
+ g_fifo_size => c_dp_fifo_dc_size
+ )
+ PORT MAP (
+ wr_rst => rx_rst,
+ wr_clk => rx_clk,
+ rd_rst => dp_rst,
+ rd_clk => dp_clk,
+ snk_in_arr => st_sosi_arr,
+ src_out_arr => out_sosi_arr,
+ in_aux(0) => rx_bsn_source_restart,
+ out_aux(0) => dp_bsn_source_restart
+ );
- -----------------------------------------------------------------------------
+
+-----------------------------------------------------------------------------
-- JESD Control register
-----------------------------------------------------------------------------
u_mm_jesd_ctrl_reg : ENTITY common_lib.common_reg_r_w
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index 69356104b26cf09270a30ac75a2be71193b51ce8..a30bf342f7766974952a2bc51bdb9824b95d587d 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -181,7 +181,8 @@ BEGIN
g_use_prefilter => TRUE,
g_stats_ena => FALSE,
g_use_bg => FALSE,
- g_coefs_file_prefix => c_coefs_file_prefix
+ g_coefs_file_prefix => c_coefs_file_prefix,
+ g_restart_on_valid => FALSE
)
PORT MAP (
dp_rst => dp_rst,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 5400b70e891a44d1835da0be6150ebb100f02824..6186496de7639b08c7c70444aa041e917c994603 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -167,6 +167,7 @@ BEGIN
BEGIN
v := r;
v.col_select_mosi := c_mem_mosi_rst;
+ v_offsets := r.offsets;
-- start/restart
IF start_trigger = '1' THEN
diff --git a/libraries/base/dp/dp.peripheral.yaml b/libraries/base/dp/dp.peripheral.yaml
index 7a8008c0e8addecda2dee9e1579f39f0fd09c9d6..5bf3166f9730c7bc147e51888724bd6e83228739 100644
--- a/libraries/base/dp/dp.peripheral.yaml
+++ b/libraries/base/dp/dp.peripheral.yaml
@@ -326,3 +326,18 @@ peripherals:
address_offset: 0x0
mm_width: 1
access_mode: RW
+
+
+ - peripheral_name: dp_sync_insert_v2 # pi_dp_sync_insert_v2.py
+ peripheral_description: "Every nof_blk_per_sync block a sync pulse is created at the output."
+ mm_ports:
+ # MM port for dp_sync_insert_v2.vhd
+ - mm_port_name: REG_DP_SYNC_INSERT_V2
+ mm_port_type: REG
+ mm_port_description: ""
+ fields:
+ - - field_name: nof_blk_per_sync
+ field_description: |
+ "The block counter resets if a sync arrives at the input or when nof_blk_per_sync is reached."
+ address_offset: 0x0
+ access_mode: RW
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
index 0327d6162cd04d63f778800b4d4b2b04422743c3..7ba4f77b717a704897571900528cc7eba1ad8d99 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
@@ -62,17 +62,17 @@ ARCHITECTURE rtl OF st_xsq_mm_to_dp IS
crosslets_index : NATURAL;
in_a_index : NATURAL;
in_b_index : NATURAL;
+ mm_mosi : t_mem_mosi;
END RECORD;
- CONSTANT c_reg_rst : t_reg := (c_dp_sosi_rst, c_dp_sosi_rst, '0', 0, 0, 0);
+ CONSTANT c_reg_rst : t_reg := (c_dp_sosi_rst, c_dp_sosi_rst, '0', 0, 0, 0, c_mem_mosi_rst);
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
- SIGNAL mm_mosi : t_mem_mosi := c_mem_mosi_rst;
BEGIN
- mm_mosi_arr <= (OTHERS => mm_mosi); -- all mosi are identical.
+ mm_mosi_arr <= (OTHERS => nxt_r.mm_mosi); -- all mosi are identical.
u_sosi : PROCESS(r, mm_miso_arr)
BEGIN
@@ -98,7 +98,7 @@ BEGIN
BEGIN
v := r;
v.out_sosi_ctrl := c_dp_sosi_rst;
- mm_mosi.rd <= '0';
+ v.mm_mosi.rd := '0';
-- initiate next block and capture in_sosi strobe
IF r.busy = '0' AND in_sosi.sop = '1' THEN
@@ -106,8 +106,8 @@ BEGIN
v.in_sosi_strobe := in_sosi;
ELSIF r.busy = '1' THEN
-- continue with block
- mm_mosi.rd <= '1';
- mm_mosi.address <= TO_MEM_ADDRESS(r.crosslets_index * g_nof_signal_inputs + r.in_b_index); -- streams iterate over in_b_index
+ v.mm_mosi.rd := '1';
+ v.mm_mosi.address := TO_MEM_ADDRESS(r.crosslets_index * g_nof_signal_inputs + r.in_b_index); -- streams iterate over in_b_index
-- Indices counters to select data order
IF r.in_b_index < g_nof_signal_inputs - 1 THEN
diff --git a/libraries/dsp/st/src/vhdl/st_xst.vhd b/libraries/dsp/st/src/vhdl/st_xst.vhd
index 6a03cbdc49a6395e090e4222ad068707e7ecdf5b..1a0e75770b67e3cbe3710b95062940c087bf3a82 100644
--- a/libraries/dsp/st/src/vhdl/st_xst.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xst.vhd
@@ -69,9 +69,12 @@ ARCHITECTURE str OF st_xst IS
busy : STD_LOGIC;
in_a_index : NATURAL;
in_b_index : NATURAL;
+ x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ in_a_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
END RECORD;
- CONSTANT c_reg_rst : t_reg := ('0', 0, 0);
+ CONSTANT c_reg_rst : t_reg := ('0', 0, 0, (OTHERS=>(OTHERS => '0')), (OTHERS=>(OTHERS => '0')), (OTHERS => c_dp_sosi_rst) );
SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg;
@@ -80,8 +83,6 @@ ARCHITECTURE str OF st_xst IS
SIGNAL in_b_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
SIGNAL x_sosi_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
- SIGNAL reg_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
- SIGNAL reg_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
BEGIN
-- MM -> DP
@@ -103,20 +104,7 @@ BEGIN
-- in_b_sosi_arr = x_sosi_arr
in_b_sosi_arr <= x_sosi_arr;
-
- -- Capture x_sosi_arr(0) data
- reg_x_sosi_0_re(nxt_r.in_b_index) <= x_sosi_arr(0).re;
- reg_x_sosi_0_im(nxt_r.in_b_index) <= x_sosi_arr(0).im;
-
- -- reorder x_sosi_arr(0) data to follow in_a_index instead of in_b_index. All sosi in in_a_sosi_arr are identical.
- p_in_a : PROCESS(x_sosi_arr, reg_x_sosi_0_re, reg_x_sosi_0_im, nxt_r.in_a_index)
- BEGIN
- FOR I IN 0 TO g_nof_streams-1 LOOP
- in_a_sosi_arr(I) <= x_sosi_arr(0);
- in_a_sosi_arr(I).re <= reg_x_sosi_0_re(nxt_r.in_a_index);
- in_a_sosi_arr(I).im <= reg_x_sosi_0_im(nxt_r.in_a_index);
- END LOOP;
- END PROCESS;
+ in_a_sosi_arr <= nxt_r.in_a_sosi_arr;
-- Register process
p_reg : PROCESS(dp_rst, dp_clk)
@@ -128,11 +116,19 @@ BEGIN
END IF;
END PROCESS;
- -- Combinatorial process to create in_a_index and in_b_index for reoredering x_sosi_arr(0) data.
+ -- Combinatorial process to create in_a_index and in_b_index and reoredering x_sosi_arr(0) data.
p_comb : PROCESS(r, x_sosi_arr)
VARIABLE v : t_reg;
+ VARIABLE v_in_a_index : NATURAL;
+ VARIABLE v_in_b_index : NATURAL;
+ VARIABLE v_x_sosi_0_re : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
+ VARIABLE v_x_sosi_0_im : t_slv_64_arr(g_nof_signal_inputs-1 DOWNTO 0);
BEGIN
v := r;
+ v_in_a_index := r.in_a_index;
+ v_in_b_index := r.in_b_index;
+ v_x_sosi_0_re := r.x_sosi_0_re;
+ v_x_sosi_0_im := r.x_sosi_0_im;
-- initiate next block
IF r.busy = '0' AND x_sosi_arr(0).sop = '1' THEN
v.busy := '1';
@@ -140,22 +136,39 @@ BEGIN
ELSIF r.busy = '1' THEN
-- Indices counters to select data order
IF r.in_b_index < g_nof_signal_inputs - 1 THEN
- v.in_b_index := r.in_b_index + 1;
+ v_in_b_index := r.in_b_index + 1;
ELSE
- v.in_b_index := 0;
+ v_in_b_index := 0;
IF r.in_a_index < g_nof_signal_inputs - 1 THEN
- v.in_a_index := r.in_a_index + 1;
+ v_in_a_index := r.in_a_index + 1;
ELSE
- v.in_a_index := 0;
+ v_in_a_index := 0;
END IF;
END IF;
END IF;
-- End of block
IF x_sosi_arr(0).eop = '1' THEN
v.busy := '0';
- v.in_a_index := 0;
- v.in_b_index := 0;
+ v_in_a_index := 0;
+ v_in_b_index := 0;
END IF;
+
+ -- Capture x_sosi_arr(0) data
+ v_x_sosi_0_re(v_in_b_index) := x_sosi_arr(0).re;
+ v_x_sosi_0_im(v_in_b_index) := x_sosi_arr(0).im;
+
+ -- reorder x_sosi_arr(0) data to follow in_a_index instead of in_b_index. All sosi in in_a_sosi_arr are identical.
+ FOR I IN 0 TO g_nof_streams-1 LOOP
+ v.in_a_sosi_arr(I) := x_sosi_arr(0);
+ v.in_a_sosi_arr(I).re := v_x_sosi_0_re(v_in_a_index);
+ v.in_a_sosi_arr(I).im := v_x_sosi_0_im(v_in_a_index);
+ END LOOP;
+
+ v.in_a_index := v_in_a_index;
+ v.in_b_index := v_in_b_index;
+ v.x_sosi_0_re := v_x_sosi_0_re;
+ v.x_sosi_0_im := v_x_sosi_0_im;
+
nxt_r <= v;
END PROCESS;
diff --git a/libraries/dsp/st/st.peripheral.yaml b/libraries/dsp/st/st.peripheral.yaml
index 13bbf592e2000dc1d0336ff519d3f8050e8cdef1..6bf0a7aac2d6e7aeefd67cbce394af06fb7a9b6e 100644
--- a/libraries/dsp/st/st.peripheral.yaml
+++ b/libraries/dsp/st/st.peripheral.yaml
@@ -101,3 +101,36 @@ peripherals:
mm_width: 32
user_width: g_stat_data_w
radix: uint64
+
+
+ - peripheral_name: st_xst_for_sdp # pi_st_xst.py
+ peripheral_description: |
+ "Calculate Crosslets Statistics during a sync interval for the crosslets statistics (XST) in LOFAR2.0 SDP"
+ parameters:
+ # Parameters of pi_st_xst.py, fixed in node_sdp_correlator.vhd / sdp_pkg.vhd
+ - { name: g_nof_streams, value: 9 } # P_sq
+ # Parameters of st_xst.vhd, fixed in node_sdp_correlator.vhd / sdp_pkg.vhd
+ - { name: g_nof_crosslets, value: 1 } # N_crosslets
+ - { name: g_nof_signal_inputs, value: 12 } # S_pn = 12
+ - { name: g_in_data_w, value: 16 } # W_crosslet = 16
+ - { name: g_stat_data_w, value: 64 } # W_statistic = 64
+ - { name: g_stat_data_sz, value: 2 } # W_statistic_sz = 2
+ mm_ports:
+ # MM port for st_sst.vhd
+ - mm_port_name: RAM_ST_XSQ
+ mm_port_type: RAM
+ mm_port_description: |
+ "The crosslets statistics per PN are stored in 1 block of
+ g_nof_crosslets * g_nof_signal_inputs**2 * c_nof_complex * g_stat_data_sz = 1 * 12 * 12 * 2 * 2 = 576 values as:
+
+ (cint64)XST[] = (cint64)XST[crosslets][in A][in B][complex][word]"
+
+ number_of_mm_ports: 1
+ fields:
+ - - field_name: power
+ field_description: ""
+ number_of_fields: 576
+ address_offset: 0x0
+ mm_width: 32
+ user_width: g_stat_data_w
+ radix: cint64_ir
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index 5188d93bd2cc1cc01f51cedbd5974a3e48a9eb5e..e63d1860dc244929c83b99be41d886fefff7c7cf 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -365,7 +365,8 @@ entity wpfb_unit_dev is
g_use_prefilter : boolean := TRUE;
g_stats_ena : boolean := TRUE; -- Enables the statistics unit
g_use_bg : boolean := FALSE;
- g_coefs_file_prefix : string := "data/coefs_wide" -- File prefix for the coefficients files.
+ g_coefs_file_prefix : string := "data/coefs_wide"; -- File prefix for the coefficients files.
+ g_restart_on_valid : boolean := TRUE
);
port (
dp_rst : in std_logic := '0';
@@ -383,7 +384,7 @@ entity wpfb_unit_dev is
in_sosi_arr : in t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
fil_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
out_sosi_arr : out t_dp_sosi_arr(g_wpfb.nof_wb_streams*g_wpfb.wb_factor-1 downto 0);
- dp_bsn_source_restart : in std_logic
+ dp_bsn_source_restart : in std_logic := '0'
);
end entity wpfb_unit_dev;
@@ -466,7 +467,11 @@ begin
begin
v := r;
v.in_sosi_arr := in_sosi_arr;
- v.bsn_source_restart := dp_bsn_source_restart;
+ IF g_restart_on_valid THEN
+ v.bsn_source_restart := (NOT r.in_sosi_arr(0).valid) AND in_sosi_arr(0).valid;
+ ELSE
+ v.bsn_source_restart := dp_bsn_source_restart;
+ END IF;
rin <= v;
end process comb;
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
index 61eb02d33154f9d5913df6b2ca23e7f768f61a5b..f789359e1d3410443b43e3e84fa048ff4c21290c 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
@@ -330,8 +330,7 @@ BEGIN
ram_bg_data_mosi => ram_diag_bg_pfb_mosi,
ram_bg_data_miso => ram_diag_bg_pfb_miso,
in_sosi_arr => bg_sosi_arr,
- out_sosi_arr => out_sosi_arr,
- dp_bsn_source_restart => bg_sosi_arr(0).sync
+ out_sosi_arr => out_sosi_arr
);
time_map : process is
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index bf8e6cb17e5dfd61f20376510f7a5174c379d400..d385e8f7cfe41cbcfee9ae6e1713c7d263d71383 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -486,8 +486,7 @@ begin
ram_bg_data_miso => open,
in_sosi_arr => in_sosi_arr,
fil_sosi_arr => fil_sosi_arr,
- out_sosi_arr => out_sosi_arr,
- dp_bsn_source_restart => in_sosi_arr(0).sync
+ out_sosi_arr => out_sosi_arr
);
p_fil_sosi_arr : process(fil_sosi_arr)