From baf6c23f25e9f1e0354ae0494e285499e3b6318c Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 23 Jan 2015 09:04:56 +0000
Subject: [PATCH] Added u_wr_burst_size_1.
---
libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index 02eaac579d..c60fdc3265 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -73,13 +73,14 @@ BEGIN
u_ext_memory_model : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, FALSE, 5 ns, 5 ns, 5 ns, 1, 1000, 1, 2, 3, 1, "VAL") PORT MAP (tb_end_vec(3));
u_mixed_width : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 8, 1000, 1, 3, 2, 1, "VAL") PORT MAP (tb_end_vec(4));
- u_wr_burst_size_0 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, FALSE, 5 ns, 5 ns, 5 ns, 4, 5, 1, 6, 5, 1, "VAL") PORT MAP (tb_end_vec(5));
+ u_wr_burst_size_0 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, FALSE, 5 ns, 5 ns, 5 ns, 4, 2,10, 3, 3, 2, "VAL") PORT MAP (tb_end_vec(5));
+ u_wr_burst_size_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, TRUE, FALSE, 5 ns, 5 ns, 5 ns, 4, 1,10, 1, 1, 2, "VAL") PORT MAP (tb_end_vec(6));
- u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 20 ns, 5 ns, 1, 1000, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(6));
- u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 1 ns, 5 ns, 1, 1000, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(7));
+ u_cross_dvr_to_faster_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 20 ns, 5 ns, 1, 1000, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(7));
+ u_cross_dvr_to_slower_ctlr : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 1 ns, 5 ns, 1, 1000, 1, 1, 4, 1, "VAL") PORT MAP (tb_end_vec(8));
- u_sequencer_1_16 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 4, 64, 9, 1,16, 1, "VAL") PORT MAP (tb_end_vec(8));
- u_sequencer_16_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 4, 64, 9,16, 1, 1, "VAL") PORT MAP (tb_end_vec(9));
+ u_sequencer_1_16 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 4, 64,10, 1,16, 1, "VAL") PORT MAP (tb_end_vec(9));
+ u_sequencer_16_1 : ENTITY work.tb_io_ddr GENERIC MAP (c_technology, c_tech_ddr3, c_tech_ddr4, FALSE, FALSE, FALSE, 5 ns, 5 ns, 5 ns, 4, 64,10,16, 1, 1, "VAL") PORT MAP (tb_end_vec(10));
END GENERATE;
-- Distinghuis between tests for DDR3 and DDR4, because the Quartus 14.1 ip_arria10 DDR4 model simulates about 40x slower than the Quartus 11.1 ip_stratixiv DDR3 uniphy model.
--
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