From ba32b0869f9199a7cebdfbcff1d707d4b09d2534 Mon Sep 17 00:00:00 2001
From: Jonathan Hargreaves <hargreaves@jive.eu>
Date: Tue, 24 Mar 2020 12:19:50 +0100
Subject: [PATCH] Multichannel simulation of lofar2_unb2b_adc
---
.../designs/lofar2_unb2b_adc/hdllib.cfg | 1 +
.../src/vhdl/lofar2_unb2b_adc.vhd | 6 +-
.../vhdl/tb_lofar2_unb2b_adc_multichannel.vhd | 404 ++++++++++++++++++
.../altera_iopll_180/compile_ip.tcl | 4 +-
.../altera_xcvr_native_a10_180/compile_ip.tcl | 10 +
.../ip_arria10_e1sg/jesd204b/hdllib.cfg | 8 +-
.../jesd204b/ip_arria10_e1sg_jesd204b.vhd | 70 +--
7 files changed, 437 insertions(+), 66 deletions(-)
create mode 100644 applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
index 68048b09ca..0d94bd7415 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/hdllib.cfg
@@ -12,6 +12,7 @@ synth_files =
test_bench_files =
tb/vhdl/tb_lofar2_unb2b_adc.vhd
+ tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
[modelsim_project_file]
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index c76f0c9a93..e91c02ce92 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -121,7 +121,7 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
SIGNAL xo_rst : STD_LOGIC;
SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC := '0';
SIGNAL st_rst : STD_LOGIC;
SIGNAL st_clk : STD_LOGIC;
@@ -192,8 +192,8 @@ ARCHITECTURE str OF lofar2_unb2b_adc IS
SIGNAL reg_remu_miso : t_mem_miso;
-- JESD
- SIGNAL jesd204b_mosi : t_mem_mosi;
- SIGNAL jesd204b_miso : t_mem_miso;
+ SIGNAL jesd204b_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL jesd204b_miso : t_mem_miso := c_mem_miso_rst;
-- WG
SIGNAL reg_wg_mosi_arr : t_mem_mosi_arr(c_nof_streams_input-1 DOWNTO 0);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
new file mode 100644
index 0000000000..bad655f343
--- /dev/null
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -0,0 +1,404 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2018
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Jonathan Hargreaves
+-- Purpose: Tb to show that lofar2_unb2b_adc can simulate
+-- Description:
+-- Must use c_sim = TRUE to speed up simulation
+-- This is a compile-only test bench
+-- Usage:
+-- Load sim # check that design can load in vsim
+-- > as 10 # check that the hierarchy for g_design_name is complete
+-- > run -a # check that design can simulate some us without error
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, ip_arria10_e1sg_jesd204b_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
+
+ENTITY tb_lofar2_unb2b_adc_multichannel IS
+END tb_lofar2_unb2b_adc_multichannel;
+
+ARCHITECTURE tb OF tb_lofar2_unb2b_adc_multichannel IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+ CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
+ CONSTANT c_node_nr : NATURAL := 0; -- Back node 3
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+ CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 0);
+
+ CONSTANT c_eth_clk_period : TIME := 8 ns; -- 125 MHz XO on UniBoard
+ CONSTANT c_ext_clk_period : TIME := 5 ns;
+ CONSTANT c_jesd204b_sampclk_period : TIME := 5 ns;
+ CONSTANT c_pps_period : NATURAL := 1000;
+ CONSTANT c_bondingclk_period : TIME := 10 ns;
+ CONSTANT c_sysref_period : NATURAL := 20000; -- number of sample clocks between sysref pulses
+
+ -- Transport delays
+ TYPE t_time_arr IS ARRAY (11 DOWNTO 0) OF TIME;
+ CONSTANT c_nof_jesd204b_tx : NATURAL := 3; -- number of jesd204b input sources to instantiate
+ CONSTANT c_delay_data_arr : t_time_arr := (800 ps,
+ 900 ps,
+ 950 ps,
+ 800 ps,
+ 900 ps,
+ 950 ps,
+ 800 ps,
+ 900 ps,
+ 950 ps,
+ 800 ps,
+ 900 ps,
+ 950 ps) ; -- transport delays tx to rx data
+ CONSTANT c_delay_sysreftoadc_arr : t_time_arr := (1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps,
+ 1000 ps) ; -- transport delays clock source to adc(tx)
+ CONSTANT c_delay_sysreftofpga : TIME := 1000 ps;
+
+
+
+ -- clocks and resets for the jesd204b tx
+ SIGNAL txlink_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL dev_sync_n : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL txphy_clk : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL mm_rst : STD_LOGIC;
+ SIGNAL avs_rst_n : STD_LOGIC;
+ SIGNAL txlink_rst_n : STD_LOGIC;
+ SIGNAL tx_analogreset : STD_LOGIC_VECTOR(0 downto 0);
+ SIGNAL tx_digitalreset : STD_LOGIC_VECTOR(0 downto 0);
+ SIGNAL tx_bonding_clocks : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
+ SIGNAL bonding_clock_0 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_1 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_2 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_3 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_4 : STD_LOGIC := '0';
+ SIGNAL bonding_clock_5 : STD_LOGIC := '0';
+ SIGNAL pll_locked : STD_LOGIC_VECTOR(0 downto 0);
+
+ CONSTANT c_mm_clk_period : TIME := 20 ns;
+ SIGNAL mm_clk : STD_LOGIC := '0';
+
+ -- Tb
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL sim_done : STD_LOGIC := '0';
+
+ -- DUT
+ SIGNAL ext_clk : STD_LOGIC := '0';
+ SIGNAL pps : STD_LOGIC := '0';
+ SIGNAL pps_rst : STD_LOGIC := '0';
+
+ SIGNAL WDI : STD_LOGIC;
+ SIGNAL INTA : STD_LOGIC;
+ SIGNAL INTB : STD_LOGIC;
+
+ SIGNAL eth_clk : STD_LOGIC := '0';
+ SIGNAL eth_txp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+ SIGNAL eth_rxp : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+ SIGNAL sens_scl : STD_LOGIC;
+ SIGNAL sens_sda : STD_LOGIC;
+ SIGNAL pmbus_scl : STD_LOGIC;
+ SIGNAL pmbus_sda : STD_LOGIC;
+
+ -- serial transceivers
+ SIGNAL serial_tx : STD_LOGIC_VECTOR(c_nof_jesd204b_tx-1 downto 0);
+ SIGNAL bck_rx : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0) := (others => '0');
+
+ -- jesd204b syncronization signals and delayed copies
+ SIGNAL jesd204b_sysref : STD_LOGIC;
+ SIGNAL jesd204b_sampclk : STD_LOGIC := '0';
+
+ SIGNAL jesd204b_sampclk_fpga : STD_LOGIC := '1';
+ SIGNAL jesd204b_sampclk_adc : STD_LOGIC_VECTOR(11 DOWNTO 0);
+ SIGNAL jesd204b_sysref_fpga : STD_LOGIC;
+ SIGNAL jesd204b_sysref_adc : STD_LOGIC_VECTOR(11 DOWNTO 0);
+ SIGNAL jesd204b_sysref_adc_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
+ SIGNAL jesd204b_sysref_adc_2 : STD_LOGIC_VECTOR(11 DOWNTO 0);
+ SIGNAL jesd204b_sync_adc : STD_LOGIC_VECTOR(11 DOWNTO 0);
+ SIGNAL jesd204b_sync_fpga : STD_LOGIC_VECTOR(11 DOWNTO 0);
+
+ -- Test bench data
+ SIGNAL jesd204b_tx_link_data_arr : t_slv_32_arr(11 DOWNTO 0);
+ SIGNAL jesd204b_tx_link_valid : STD_LOGIC_VECTOR(11 DOWNTO 0);
+ SIGNAL jesd204b_tx_link_ready : STD_LOGIC_VECTOR(11 DOWNTO 0);
+ SIGNAL jesd204b_tx_frame_ready : STD_LOGIC_VECTOR(11 DOWNTO 0);
+
+BEGIN
+
+
+ ----------------------------------------------------------------------------
+ -- System setup
+ ----------------------------------------------------------------------------
+ ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2; -- External clock (200 MHz)
+ eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (125 MHz)
+
+ INTA <= 'H'; -- pull up
+ INTB <= 'H'; -- pull up
+
+ sens_scl <= 'H'; -- pull up
+ sens_sda <= 'H'; -- pull up
+ pmbus_scl <= 'H'; -- pull up
+ pmbus_sda <= 'H'; -- pull up
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+ --jesd204b_sysref <= pps;
+
+ ------------------------------------------------------------------------------
+ -- DUT
+ ------------------------------------------------------------------------------
+ u_lofar_unb2b_adc : ENTITY work.lofar2_unb2b_adc
+ GENERIC MAP (
+ g_design_name => "lofar2_unb2b_adc_one_node",
+ g_design_note => "Lofar2 adc with one node",
+ g_sim => c_sim,
+ g_sim_unb_nr => c_unb_nr,
+ g_sim_node_nr => c_node_nr
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => ext_clk,
+ PPS => pps,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => c_version,
+ ID => c_id,
+ TESTIO => open,
+
+ -- I2C Interface to Sensors
+ SENS_SC => sens_scl,
+ SENS_SD => sens_sda,
+
+ PMBUS_SC => pmbus_scl,
+ PMBUS_SD => pmbus_sda,
+ PMBUS_ALERT => open,
+
+ -- 1GbE Control Interface
+ ETH_CLK => eth_clk,
+ ETH_SGIN => eth_rxp,
+ ETH_SGOUT => eth_txp,
+
+ -- LEDs
+ QSFP_LED => open,
+
+ -- back transceivers
+ BCK_RX => bck_rx,
+ BCK_REF_CLK => jesd204b_sampclk_fpga,
+
+ -- jesd204b syncronization signals
+ JESD204B_SYSREF => jesd204b_sysref_fpga,
+ JESD204B_SYNC => jesd204b_sync_fpga
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Transport
+ -----------------------------------------------------------------------------
+
+ gen_transport : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
+ bck_rx(i) <= transport serial_tx(i) after c_delay_data_arr(i);
+ jesd204b_sampclk_adc(i) <= transport jesd204b_sampclk after c_delay_sysreftoadc_arr(i);
+ jesd204b_sysref_adc(i) <= transport jesd204b_sysref after c_delay_sysreftoadc_arr(i);
+-- txlink_clk(i) <= jesd204b_sampclk_div2 after c_delay_sysreftoadc_arr(i);
+ jesd204b_sync_adc(i) <= transport jesd204b_sync_fpga(i) after c_delay_data_arr(i);
+ END GENERATE;
+
+ jesd204b_sampclk_fpga <= transport jesd204b_sampclk after c_delay_sysreftofpga;
+ jesd204b_sysref_fpga <= transport jesd204b_sysref after c_delay_sysreftofpga;
+
+ -----------------------------------------------------------------------------
+ -- Use a jesd204b instance in TX-ONLY modeTransmit Only.
+ -----------------------------------------------------------------------------
+
+ gen_jesd204b_tx : FOR i IN 0 TO c_nof_jesd204b_tx-1 GENERATE
+ u_ip_arria10_e1sg_jesd204b_tx : ip_arria10_e1sg_jesd204b_tx
+ PORT MAP
+ (
+ csr_cf => OPEN,
+ csr_cs => OPEN,
+ csr_f => OPEN,
+ csr_hd => OPEN,
+ csr_k => OPEN,
+ csr_l => OPEN,
+ csr_lane_powerdown => open, --out
+ csr_m => OPEN,
+ csr_n => OPEN,
+ csr_np => OPEN,
+ csr_tx_testmode => OPEN,
+ csr_tx_testpattern_a => OPEN,
+ csr_tx_testpattern_b => OPEN,
+ csr_tx_testpattern_c => OPEN,
+ csr_tx_testpattern_d => OPEN,
+ csr_s => OPEN,
+ dev_sync_n => dev_sync_n(i), --out
+ jesd204_tx_avs_chipselect => '0', --jesd204b_mosi_arr(i).chipselect,
+ jesd204_tx_avs_address => (others => '0'),
+ jesd204_tx_avs_read => '0',
+ jesd204_tx_avs_readdata => open,
+ jesd204_tx_avs_waitrequest => open,
+ jesd204_tx_avs_write => '0',
+ jesd204_tx_avs_writedata => (others => '0'),
+ jesd204_tx_avs_clk => mm_clk,
+ jesd204_tx_avs_rst_n => avs_rst_n,
+ jesd204_tx_dlb_data => open, -- debug/loopback testing
+ jesd204_tx_dlb_kchar_data => open, -- debug/loopback testing
+ jesd204_tx_frame_ready => jesd204b_tx_frame_ready(i),
+ jesd204_tx_frame_error => '0',
+ jesd204_tx_int => OPEN, -- Connected to status IO in example design
+ jesd204_tx_link_data => jesd204b_tx_link_data_arr(i), --in
+ jesd204_tx_link_valid => jesd204b_tx_link_valid(i), --in
+ jesd204_tx_link_ready => jesd204b_tx_link_ready(i), --out
+ mdev_sync_n => dev_sync_n(i), --in
+ pll_locked => pll_locked, --in
+ sync_n => jesd204b_sync_adc(i), --in
+ tx_analogreset => tx_analogreset,
+ tx_bonding_clocks => tx_bonding_clocks,--: in std_logic_vector(5 downto 0) := (others => 'X'); -- clk
+ tx_cal_busy => open,
+ tx_digitalreset => tx_digitalreset,
+ tx_serial_data => serial_tx(i downto i),
+ txlink_clk => txlink_clk(i),
+ txlink_rst_n_reset_n => txlink_rst_n,
+ txphy_clk => txphy_clk(i downto i),
+ somf => OPEN,
+ sysref => jesd204b_sysref_adc(i)
+ );
+
+ -- Generate test pattern at each ADC
+
+ proc_data : PROCESS (jesd204b_sampclk_adc(i), mm_rst)
+ VARIABLE data : INTEGER := 0;
+ BEGIN
+ IF mm_rst = '1' THEN
+ jesd204b_tx_link_data_arr(i) <= (others => '0');
+ jesd204b_tx_link_valid(i) <= '0';
+ txlink_clk(i) <= '0';
+ data := 0;
+ ELSE
+ IF rising_edge(jesd204b_sampclk_adc(i)) THEN
+ jesd204b_tx_link_valid(i) <= '1';
+ txlink_clk(i) <= not txlink_clk(i);
+ jesd204b_tx_link_data_arr(i) <= TO_SVEC(data, 32);
+ jesd204b_sysref_adc_1(i) <= jesd204b_sysref_adc(i);
+ jesd204b_sysref_adc_2(i) <= jesd204b_sysref_adc_1(i);
+ IF (jesd204b_sysref_adc_1(i) = '1') THEN
+ data := 1000;
+ ELSIF (jesd204b_sysref_adc_2(i) = '1') THEN
+ data := -1000;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- Stimulii
+ -----------------------------------------------------------------------------
+
+ -- Clocks and resets
+ mm_clk <= not mm_clk after c_mm_clk_period/2;
+ mm_rst <= '1', '0' after 800 ns;
+ avs_rst_n <= '0', '1' after 23500 ns;
+ tx_analogreset(0) <= '1', '0' after 18500 ns;
+ tx_digitalreset(0) <= '1', '0' after 23000 ns;
+ txlink_rst_n <= '0', '1' after 25500 ns;
+ pll_locked(0) <= '0', '1' after 1000 ns;
+
+ bonding_clock_5 <= not bonding_clock_5 after 250 ps;
+ bonding_clock_4 <= not bonding_clock_4 after 250 ps;
+ bonding_clock_3 <= not bonding_clock_3 after 500 ps;
+ bonding_clock_2 <= not bonding_clock_2 after 500 ps;
+ bonding_clock_0 <= not bonding_clock_0 after 2500 ps;
+
+ bonding_clock_1_process : process
+ begin
+ bonding_clock_1 <= '0';
+ wait for 4000 ps;
+ bonding_clock_1 <= '1';
+ wait for 1000 ps;
+ end process;
+
+ tx_bonding_clocks(5) <= transport bonding_clock_5 after 4890 ps;
+ tx_bonding_clocks(4) <= transport bonding_clock_4 after 4640 ps;
+ tx_bonding_clocks(3) <= transport bonding_clock_3 after 4920 ps;
+ tx_bonding_clocks(2) <= transport bonding_clock_2 after 4930 ps;
+ tx_bonding_clocks(1) <= transport bonding_clock_1 after 7490 ps;
+ tx_bonding_clocks(0) <= transport bonding_clock_0 after 4000 ps;
+
+ -- Sample Clock
+ jesd204b_sampclk <= NOT jesd204b_sampclk AFTER c_jesd204b_sampclk_period/2; -- JESD sample clock (200MHz)
+
+ -- clock source process
+
+ proc_sysref : PROCESS (jesd204b_sampclk, mm_rst)
+ VARIABLE count : NATURAL := 0;
+ BEGIN
+ IF mm_rst = '1' THEN
+ jesd204b_sysref <= '0';
+ count := 0;
+ ELSE
+ IF rising_edge(jesd204b_sampclk) THEN
+ IF (count = c_sysref_period-1) THEN
+ count := 0;
+ ELSE
+ count := count + 1;
+ END IF;
+
+ IF count > c_sysref_period-40 THEN
+ jesd204b_sysref <= '1';
+ ELSE
+ jesd204b_sysref <= '0';
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
+
+
+
+ ------------------------------------------------------------------------------
+ -- Simulation end
+ ------------------------------------------------------------------------------
+ --sim_done <= '0', '1' AFTER 1 us;
+ sim_done <= '0';
+
+ proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
+END tb;
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
index c55c9c297a..aed590371d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
@@ -38,4 +38,6 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_qkytlfy.vo" -work altera_iopll_180
-
+
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll/sim"
+ vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_altera_iopll_180_4sgpama.vo" -work altera_iopll_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
index 5c4256f75c..9020d9e373 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
@@ -96,3 +96,13 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+
+# jesd204b rx
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_rx_altera_xcvr_native_a10_180_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+
+# jesd204b tx
+set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_xcvr_native_a10_180_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
index 490c785689..f02a98b552 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
@@ -1,14 +1,18 @@
hdl_lib_name = ip_arria10_e1sg_jesd204b
hdl_library_clause_name = ip_arria10_e1sg_jesd204b_lib
hdl_lib_uses_synth = technology tech_pll common dp
-hdl_lib_uses_sim =
+hdl_lib_uses_sim = ip_arria10_e1sg_altera_jesd204_180 ip_arria10_e1sg_altera_xcvr_reset_control_180
hdl_lib_technology = ip_arria10_e1sg
synth_files =
+ ip_arria10_e1sg_jesd204b_component_pkg.vhd
ip_arria10_e1sg_jesd204b.vhd
test_bench_files =
+modelsim_compile_ip_files =
+ $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
+
[modelsim_project_file]
[quartus_project_file]
@@ -17,6 +21,7 @@ quartus_qip_files =
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll/ip_arria10_e1sg_jesd204b_rx_core_pll.qip
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip
$RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip
+ $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx/ip_arria10_e1sg_jesd204b_rx.qip
[generate_ip_libs]
qsys-generate_ip_files =
@@ -24,5 +29,6 @@ qsys-generate_ip_files =
ip_arria10_e1sg_jesd204b_rx_core_pll.ip
ip_arria10_e1sg_jesd204b_rx_reset_seq.ip
ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.ip
+ ip_arria10_e1sg_jesd204b_tx.ip
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index fa5d74a806..cc028549d1 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -34,6 +34,7 @@ USE technology_lib.technology_pkg.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
+USE ip_arria10_e1sg_jesd204b_lib.ip_arria10_e1sg_jesd204b_component_pkg.ALL;
ENTITY ip_arria10_e1sg_jesd204b IS
GENERIC (
@@ -71,8 +72,8 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
-- JESD204 control status registers
SIGNAL jesd204b_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
SIGNAL jesd204b_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL reset_seq_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
+ SIGNAL reset_seq_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
-- Clocks
SIGNAL rxframe_clk : STD_LOGIC;
@@ -89,7 +90,7 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
SIGNAL xcvr_rst_ctrl_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rx_xcvr_ready_in_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL pll_reset_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL xcvr_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rx_avs_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rxlink_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
SIGNAL rxframe_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
@@ -220,63 +221,6 @@ ARCHITECTURE str OF ip_arria10_e1sg_jesd204b IS
end component ip_arria10_e1sg_jesd204b_rx_core_pll;
component ip_arria10_e1sg_jesd204b_rx_reset_seq is
- generic (
- NUM_OUTPUTS : integer := 3;
- ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
- ENABLE_ASSERTION_SEQUENCE : integer := 0;
- ENABLE_DEASSERTION_SEQUENCE : integer := 0;
- MIN_ASRT_TIME : integer := 0;
- ASRT_DELAY0 : integer := 0;
- DSRT_DELAY0 : integer := 0;
- ASRT_REMAP0 : integer := 0;
- DSRT_REMAP0 : integer := 0;
- DSRT_QUALCNT_0 : integer := 0;
- ASRT_DELAY1 : integer := 0;
- DSRT_DELAY1 : integer := 0;
- ASRT_REMAP1 : integer := 1;
- DSRT_REMAP1 : integer := 1;
- DSRT_QUALCNT_1 : integer := 0;
- ASRT_DELAY2 : integer := 0;
- DSRT_DELAY2 : integer := 0;
- ASRT_REMAP2 : integer := 2;
- DSRT_REMAP2 : integer := 2;
- DSRT_QUALCNT_2 : integer := 0;
- ASRT_DELAY3 : integer := 0;
- DSRT_DELAY3 : integer := 0;
- ASRT_REMAP3 : integer := 3;
- DSRT_REMAP3 : integer := 3;
- DSRT_QUALCNT_3 : integer := 0;
- ASRT_DELAY4 : integer := 0;
- DSRT_DELAY4 : integer := 0;
- ASRT_REMAP4 : integer := 4;
- DSRT_REMAP4 : integer := 4;
- DSRT_QUALCNT_4 : integer := 0;
- ASRT_DELAY5 : integer := 0;
- DSRT_DELAY5 : integer := 0;
- ASRT_REMAP5 : integer := 5;
- DSRT_REMAP5 : integer := 5;
- DSRT_QUALCNT_5 : integer := 0;
- ASRT_DELAY6 : integer := 0;
- DSRT_DELAY6 : integer := 0;
- ASRT_REMAP6 : integer := 6;
- DSRT_REMAP6 : integer := 6;
- DSRT_QUALCNT_6 : integer := 0;
- ASRT_DELAY7 : integer := 0;
- DSRT_DELAY7 : integer := 0;
- ASRT_REMAP7 : integer := 7;
- DSRT_REMAP7 : integer := 7;
- DSRT_QUALCNT_7 : integer := 0;
- ASRT_DELAY8 : integer := 0;
- DSRT_DELAY8 : integer := 0;
- ASRT_REMAP8 : integer := 8;
- DSRT_REMAP8 : integer := 8;
- DSRT_QUALCNT_8 : integer := 0;
- ASRT_DELAY9 : integer := 0;
- DSRT_DELAY9 : integer := 0;
- ASRT_REMAP9 : integer := 9;
- DSRT_REMAP9 : integer := 9;
- DSRT_QUALCNT_9 : integer := 0
- );
port (
av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
av_readdata : out std_logic_vector(31 downto 0); -- readdata
@@ -454,7 +398,8 @@ BEGIN
reset_out7 => rxframe_rst_arr(i)
);
- rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i);
+ --rx_xcvr_ready_in_arr(i) <= rx_csr_lane_powerdown_arr(i) OR xcvr_rst_ctrl_rx_ready_arr(i);
+ rx_xcvr_ready_in_arr(i) <= '1' when rx_csr_lane_powerdown_arr(i)='1' OR xcvr_rst_ctrl_rx_ready_arr(i)='1' else '0';
-- Invert thr active-low resets
rx_avs_rst_n_arr(i) <= not rx_avs_rst_arr(i);
@@ -542,5 +487,8 @@ BEGIN
miso_arr => jesd204b_miso_arr
);
+
END str;
+
+
--
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