From b932cc3d2acf7eaa022ce614c81d89154e2408b9 Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Thu, 8 Jun 2017 09:34:16 +0000
Subject: [PATCH] -Fixed compile error in rsp_terminal_frame_dec; . updated
generics of dp_deinterleave. -Added the RSP test benches to the regression
test.
---
.../aartfaac/libraries/rsp_serdes/hdllib.cfg | 2 ++
.../aartfaac/libraries/rsp_terminal/hdllib.cfg | 2 ++
.../src/vhdl/rsp_terminal_frame_dec.vhd | 13 +++++++------
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg b/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg
index 8cd3e8966e..bb4b9bff67 100644
--- a/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg
+++ b/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg
@@ -10,6 +10,8 @@ synth_files =
test_bench_files =
$SVN/RadioHDL/trunk/applications/aartfaac/libraries/rsp_serdes/tb/vhdl/tb_rsp_serdes.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_rsp_serdes.vhd
[modelsim_project_file]
diff --git a/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg b/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg
index 406dd1472f..56b224f138 100644
--- a/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg
+++ b/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg
@@ -18,6 +18,8 @@ test_bench_files =
$SVN/RadioHDL/trunk/applications/aartfaac/libraries/rsp_terminal/tb/vhdl/tb_rsp_terminal.vhd
$SVN/RadioHDL/trunk/applications/aartfaac/libraries/rsp_terminal/tb/vhdl/tb_tb_rsp_terminal.vhd
+regression_test_vhdl =
+ tb/vhdl/tb_tb_rsp_terminal.vhd
[modelsim_project_file]
modelsim_copy_files =
diff --git a/applications/aartfaac/libraries/rsp_terminal/src/vhdl/rsp_terminal_frame_dec.vhd b/applications/aartfaac/libraries/rsp_terminal/src/vhdl/rsp_terminal_frame_dec.vhd
index 1e489c6acb..be9e791ac3 100644
--- a/applications/aartfaac/libraries/rsp_terminal/src/vhdl/rsp_terminal_frame_dec.vhd
+++ b/applications/aartfaac/libraries/rsp_terminal/src/vhdl/rsp_terminal_frame_dec.vhd
@@ -162,12 +162,13 @@ BEGIN
-- De-interleave the alternating Re, Im complex from the data
u_dp_deinterleave : ENTITY dp_lib.dp_deinterleave
GENERIC MAP (
- g_dat_w => g_usr_dat_w,
- g_nof_out => c_nof_complex, -- = 2
- g_block_size => 1,
- g_use_ctrl => TRUE,
- g_use_complex => FALSE,
- g_align_out => TRUE
+ g_dat_w => g_usr_dat_w,
+ g_nof_out => c_nof_complex, -- = 2
+ g_block_size_int => 1,
+ g_block_size_output => g_usr_block_size,
+ g_use_ctrl => TRUE,
+ g_use_complex => FALSE,
+ g_align_out => TRUE
)
PORT MAP (
rst => dp_rst,
--
GitLab