diff --git a/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg b/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg index 8cd3e8966ee07ec9a4747e8af52c881de724a547..bb4b9bff6785cfc4524a5154fb6a028f8fedf46a 100644 --- a/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg +++ b/applications/aartfaac/libraries/rsp_serdes/hdllib.cfg @@ -10,6 +10,8 @@ synth_files = test_bench_files = $SVN/RadioHDL/trunk/applications/aartfaac/libraries/rsp_serdes/tb/vhdl/tb_rsp_serdes.vhd +regression_test_vhdl = + tb/vhdl/tb_rsp_serdes.vhd [modelsim_project_file] diff --git a/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg b/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg index 406dd1472fa30c2a73ec25b18dda28da8072cade..56b224f1388550cda8607b490293fdef31dddc17 100644 --- a/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg +++ b/applications/aartfaac/libraries/rsp_terminal/hdllib.cfg @@ -18,6 +18,8 @@ test_bench_files = $SVN/RadioHDL/trunk/applications/aartfaac/libraries/rsp_terminal/tb/vhdl/tb_rsp_terminal.vhd $SVN/RadioHDL/trunk/applications/aartfaac/libraries/rsp_terminal/tb/vhdl/tb_tb_rsp_terminal.vhd +regression_test_vhdl = + tb/vhdl/tb_tb_rsp_terminal.vhd [modelsim_project_file] modelsim_copy_files = diff --git a/applications/aartfaac/libraries/rsp_terminal/src/vhdl/rsp_terminal_frame_dec.vhd b/applications/aartfaac/libraries/rsp_terminal/src/vhdl/rsp_terminal_frame_dec.vhd index 1e489c6acb6d72130990585ccb341c8ea0a2a62b..be9e791ac379a4f15d5f6752603d13ed32871303 100644 --- a/applications/aartfaac/libraries/rsp_terminal/src/vhdl/rsp_terminal_frame_dec.vhd +++ b/applications/aartfaac/libraries/rsp_terminal/src/vhdl/rsp_terminal_frame_dec.vhd @@ -162,12 +162,13 @@ BEGIN -- De-interleave the alternating Re, Im complex from the data u_dp_deinterleave : ENTITY dp_lib.dp_deinterleave GENERIC MAP ( - g_dat_w => g_usr_dat_w, - g_nof_out => c_nof_complex, -- = 2 - g_block_size => 1, - g_use_ctrl => TRUE, - g_use_complex => FALSE, - g_align_out => TRUE + g_dat_w => g_usr_dat_w, + g_nof_out => c_nof_complex, -- = 2 + g_block_size_int => 1, + g_block_size_output => g_usr_block_size, + g_use_ctrl => TRUE, + g_use_complex => FALSE, + g_align_out => TRUE ) PORT MAP ( rst => dp_rst,