diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index d5eb95c53e926a6f7869e38d3a9cab1ed7b510a4..24d3d4a0fa856f4ddc48a4d1bb8568daa7237ab9 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -58,6 +58,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_minimal/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip b/boards/uniboard2b/designs/unb2b_minimal/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
index 01d65f303738b4166764cf39e74c05950c2ee899..722101ac42b4f5f557f3a34753274d39d464ac8f 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
+++ b/boards/uniboard2b/designs/unb2b_minimal/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
@@ -2073,7 +2073,7 @@
<spirit:parameter>
<spirit:name>breakAbsoluteAddr</spirit:name>
<spirit:displayName>Break vector</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="breakAbsoluteAddr">14368</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="breakAbsoluteAddr">20512</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>mmu_TLBMissExcAbsAddr</spirit:name>
@@ -2208,7 +2208,7 @@
<spirit:parameter>
<spirit:name>instSlaveMapParam</spirit:name>
<spirit:displayName>instSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>faSlaveMapParam</spirit:name>
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -2344,7 +2344,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.BREAK_ADDR</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BREAK_ADDR">0x00003820</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BREAK_ADDR">0x00005020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -3527,7 +3527,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/boards/uniboard2b/designs/unb2b_minimal/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip b/boards/uniboard2b/designs/unb2b_minimal/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
new file mode 100644
index 0000000000000000000000000000000000000000..e97d294126b031d53805ac04c46d7b8209202435
--- /dev/null
+++ b/boards/uniboard2b/designs/unb2b_minimal/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_unb2b_minimal_ram_scrap</spirit:library>
+ <spirit:name>qsys_unb2b_minimal_ram_scrap</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">2048</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm_readlatency2</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>8</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>8</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_unb2b_minimal_ram_scrap</spirit:library>
+ <spirit:name>avs_common_mm_readlatency2</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">9</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">50000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>2048</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>2</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>11</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>50000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2b_minimal_ram_scrap.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2b_minimal_ram_scrap.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2b_minimal_ram_scrap.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2b_minimal_ram_scrap.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2b_minimal_ram_scrap.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2b_minimal_ram_scrap.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2b_minimal_ram_scrap.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2b_minimal_ram_scrap.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2b_minimal_ram_scrap.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2b_minimal_ram_scrap.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/boards/uniboard2b/designs/unb2b_minimal/quartus/qsys_unb2b_minimal.qsys b/boards/uniboard2b/designs/unb2b_minimal/quartus/qsys_unb2b_minimal.qsys
index e8920f505d1278fd05b19c240249b539eb43f466..6273fb3ef2b6823de386978aef79d9c09fa12be3 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/quartus/qsys_unb2b_minimal.qsys
+++ b/boards/uniboard2b/designs/unb2b_minimal/quartus/qsys_unb2b_minimal.qsys
@@ -62,7 +62,7 @@
{
datum baseAddress
{
- value = "14336";
+ value = "20480";
type = "String";
}
}
@@ -169,6 +169,22 @@
type = "String";
}
}
+ element ram_scrap
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ }
+ element ram_scrap.mem
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "String";
+ }
+ }
element reg_dpmm_ctrl
{
datum _sortIndex
@@ -644,6 +660,41 @@
internal="pio_wdi.external_connection"
type="conduit"
dir="end" />
+ <interface
+ name="ram_scrap_address"
+ internal="ram_scrap.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_clk"
+ internal="ram_scrap.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_read"
+ internal="ram_scrap.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_readdata"
+ internal="ram_scrap.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_reset"
+ internal="ram_scrap.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_write"
+ internal="ram_scrap.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_writedata"
+ internal="ram_scrap.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dpmm_ctrl_address"
internal="reg_dpmm_ctrl.address"
@@ -4016,7 +4067,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -4054,7 +4105,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -4116,7 +4167,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.BREAK_ADDR</key>
- <value>0x00003820</value>
+ <value>0x00005020</value>
</entry>
<entry>
<key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
@@ -7271,7 +7322,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="ram_scrap"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -7287,7 +7338,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -7351,7 +7402,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -7420,7 +7471,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -7523,7 +7574,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -7802,9 +7853,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
+ <className>avs_common_mm_readlatency2</className>
<version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <displayName>avs_common_mm_readlatency2</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -7826,11 +7877,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>11</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -7857,37 +7908,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_ram_scrap</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_ram_scrap</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -8473,37 +8524,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -8519,7 +8570,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -8583,7 +8634,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -8652,7 +8703,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -9058,11 +9109,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -9089,37 +9140,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -9705,37 +9756,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -9751,7 +9802,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9815,7 +9866,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9884,7 +9935,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -10290,11 +10341,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -10321,37 +10372,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -10367,7 +10418,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -10431,7 +10482,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -10500,7 +10551,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -10906,11 +10957,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -10937,37 +10988,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -11553,37 +11604,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -11599,7 +11650,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11663,7 +11714,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11732,7 +11783,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12138,11 +12189,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12169,37 +12220,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_pmbus"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12215,7 +12266,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12279,7 +12330,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12348,7 +12399,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12754,11 +12805,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12785,37 +12836,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_unb_pmbus</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_unb2b_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_sens"
+ name="reg_unb_pmbus"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13401,10 +13452,626 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2b_minimal_reg_unb_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_unb_pmbus</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2b_minimal_reg_unb_sens</fileSetName>
+ <fileSetName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_unb2b_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_unb_sens"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>50000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_unb2b_minimal_reg_unb_sens</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_unb2b_minimal_reg_unb_sens</fileSetName>
<fileSetFixedName>qsys_unb2b_minimal_reg_unb_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
@@ -13424,7 +14091,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -14040,7 +14707,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -14656,7 +15323,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
@@ -15327,7 +15994,7 @@
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip</parameter>
+ <parameter name="logicalView">../../../../../build/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap>
<entry>
@@ -15398,7 +16065,7 @@
version="18.0"
start="cpu_0.data_master"
end="cpu_0.debug_mem_slave">
- <parameter name="baseAddress" value="0x3800" />
+ <parameter name="baseAddress" value="0x5000" />
</connection>
<connection
kind="avalon"
@@ -15498,6 +16165,13 @@
end="reg_fpga_voltage_sens.mem">
<parameter name="baseAddress" value="0x00c0" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="ram_scrap.mem">
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
<connection
kind="avalon"
version="18.0"
@@ -15545,7 +16219,7 @@
version="18.0"
start="cpu_0.instruction_master"
end="cpu_0.debug_mem_slave">
- <parameter name="baseAddress" value="0x3800" />
+ <parameter name="baseAddress" value="0x5000" />
</connection>
<connection
kind="avalon"
@@ -15618,6 +16292,7 @@
version="18.0"
start="clk_0.clk"
end="reg_fpga_voltage_sens.system" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="ram_scrap.system" />
<connection
kind="interrupt"
version="18.0"
@@ -15729,6 +16404,11 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_fpga_voltage_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="ram_scrap.system_reset" />
<connection
kind="reset"
version="18.0"
@@ -15829,6 +16509,11 @@
version="18.0"
start="cpu_0.debug_reset_request"
end="reg_fpga_voltage_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="cpu_0.debug_reset_request"
+ end="ram_scrap.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..87c0b0f7ef2fcca0f763c79bcc2638e713407e21
--- /dev/null
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg
@@ -0,0 +1,67 @@
+hdl_lib_name = unb2b_minimal_125m
+hdl_library_clause_name = unb2b_minimal_125m_lib
+hdl_lib_uses_synth = common mm technology unb2b_minimal
+hdl_lib_uses_sim =
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip =
+
+synth_files =
+ unb2b_minimal_125m.vhd
+
+test_bench_files =
+
+
+[modelsim_project_file]
+modelsim_copy_files =
+
+
+[quartus_project_file]
+synth_top_level_entity =
+
+quartus_copy_files =
+ ../../quartus .
+
+quartus_qsf_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+
+quartus_sdc_pre_files =
+ quartus/unb2b_test_10GbE.sdc
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
+
+quartus_sdc_files =
+ $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+
+quartus_tcl_files =
+ ../../quartus/unb2b_minimal_pins.tcl
+
+quartus_vhdl_files =
+
+quartus_qip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal_125m/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+
+quartus_ip_files =
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
+
+nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
+
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0e4de21d22dbe759991389097aed876dfbc47c5d
--- /dev/null
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
@@ -0,0 +1,122 @@
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, unb2b_minimal_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+
+ENTITY unb2b_minimal_125m IS
+ GENERIC (
+ g_design_name : STRING := "unb2b_minimal_125m";
+ g_design_note : STRING := "UNUSED";
+ g_technology : NATURAL := c_tech_arria10_e1sg;
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := ""; -- revision id -- set by QSF
+ g_factory_image : BOOLEAN := TRUE;
+ g_protect_addr_range: BOOLEAN := FALSE
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2b_minimal_125m;
+
+
+ARCHITECTURE str OF unb2b_minimal_125m IS
+
+BEGIN
+ u_revision : ENTITY unb2b_minimal_lib.unb2b_minimal
+ GENERIC MAP (
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_technology => g_technology,
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ PORT MAP (
+ -- GENERAL
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+
+ -- Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+
+ -- I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+
+ -- 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT,
+
+ -- pmbus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ QSFP_LED => QSFP_LED
+ );
+END str;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index 9c99f381a3f76fc1e91acafddabb8b3b63e9fede..8d0ad7874fc06c8663f29ef4a5daab1a35227616 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -97,7 +97,11 @@ ENTITY mmm_unb2b_minimal IS
-- Remote Update
reg_remu_mosi : OUT t_mem_mosi;
- reg_remu_miso : IN t_mem_miso
+ reg_remu_miso : IN t_mem_miso;
+
+ -- Scrap RAM
+ ram_scrap_mosi : OUT t_mem_mosi;
+ ram_scrap_miso : IN t_mem_miso
);
END mmm_unb2b_minimal;
@@ -139,6 +143,9 @@ BEGIN
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
@@ -296,7 +303,15 @@ BEGIN
reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_address_export => ram_scrap_mosi.address(8 DOWNTO 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
index ec0a3501b6ee47db52ed92c0ef7888268d15c72f..14655178f412dac63871f472d83e26abe8e25597 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
@@ -65,6 +65,13 @@ PACKAGE qsys_unb2b_minimal_pkg IS
pio_system_info_write_export : out std_logic; -- export
pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_wdi_external_connection_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
reg_dpmm_ctrl_clk_export : out std_logic; -- export
reg_dpmm_ctrl_read_export : out std_logic; -- export
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
index f35aaa30f30e30d959d0286b895bc1943364df0d..bd5005bfe3983d9ca9962771c61455d836b51ff4 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
@@ -1,380 +1,393 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2015
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE unb2b_board_lib.unb2b_board_pkg.ALL;
-
-ENTITY unb2b_minimal IS
- GENERIC (
- g_design_name : STRING := "unb2b_minimal";
- g_design_note : STRING := "UNUSED";
- g_technology : NATURAL := c_tech_arria10_e1sg;
- g_sim : BOOLEAN := FALSE; --Overridden by TB
- g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0;
- g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : STRING := ""; -- revision id -- set by QSF
- g_factory_image : BOOLEAN := TRUE;
- g_protect_addr_range: BOOLEAN := FALSE
- );
- PORT (
- -- GENERAL
- CLK : IN STD_LOGIC; -- System Clock
- PPS : IN STD_LOGIC; -- System Sync
- WDI : OUT STD_LOGIC; -- Watchdog Clear
- INTA : INOUT STD_LOGIC; -- FPGA interconnect line
- INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-
- -- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
-
- -- I2C Interface to Sensors
- SENS_SC : INOUT STD_LOGIC;
- SENS_SD : INOUT STD_LOGIC;
-
- PMBUS_SC : INOUT STD_LOGIC;
- PMBUS_SD : INOUT STD_LOGIC;
- PMBUS_ALERT : IN STD_LOGIC := '0';
-
- -- 1GbE Control Interface
- ETH_CLK : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
-
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
- );
-END unb2b_minimal;
-
-
-ARCHITECTURE str OF unb2b_minimal IS
-
- -- Firmware version x.y
- CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2b_board_mm_clk_freq_50M;
-
- -- System
- SIGNAL cs_sim : STD_LOGIC;
- SIGNAL xo_ethclk : STD_LOGIC;
- SIGNAL xo_rst : STD_LOGIC;
- SIGNAL xo_rst_n : STD_LOGIC;
- SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_rst : STD_LOGIC;
-
- SIGNAL st_rst : STD_LOGIC;
- SIGNAL st_clk : STD_LOGIC;
-
- -- PIOs
- SIGNAL pout_wdi : STD_LOGIC;
-
- -- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi;
- SIGNAL reg_wdi_miso : t_mem_miso;
-
- -- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi;
- SIGNAL reg_ppsh_miso : t_mem_miso;
-
- -- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
- SIGNAL rom_unb_system_info_miso : t_mem_miso;
-
- -- UniBoard I2C sens
- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
- SIGNAL reg_unb_sens_miso : t_mem_miso;
-
- -- pm bus
- SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
- SIGNAL reg_unb_pmbus_miso : t_mem_miso;
-
- -- FPGA sensors
- SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
- SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
- SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
- SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
-
- -- eth1g
- SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso;
-
- -- EPCS read
- SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_data_miso : t_mem_miso;
- SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
-
- -- EPCS write
- SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_data_miso : t_mem_miso;
- SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
-
- -- EPCS status/control
- SIGNAL reg_epcs_mosi : t_mem_mosi;
- SIGNAL reg_epcs_miso : t_mem_miso;
-
- -- Remote Update
- SIGNAL reg_remu_mosi : t_mem_mosi;
- SIGNAL reg_remu_miso : t_mem_miso;
-
- -- QSFP leds
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-
-BEGIN
-
- -----------------------------------------------------------------------------
- -- General control function
- -----------------------------------------------------------------------------
- u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
- GENERIC MAP (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
- g_aux => c_unb2b_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- PORT MAP (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
-
- -----------------------------------------------------------------------------
- -- MM master
- -----------------------------------------------------------------------------
- u_mmm : ENTITY work.mmm_unb2b_minimal
- GENERIC MAP (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- PORT MAP(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
-
- u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
- GENERIC MAP (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- PORT MAP (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
-
- u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
- GENERIC MAP (
- g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
- )
- PORT MAP (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
-
-END str;
-
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+
+ENTITY unb2b_minimal IS
+ GENERIC (
+ g_design_name : STRING := "unb2b_minimal";
+ g_design_note : STRING := "UNUSED";
+ g_technology : NATURAL := c_tech_arria10_e1sg;
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := ""; -- revision id -- set by QSF
+ g_factory_image : BOOLEAN := TRUE;
+ g_protect_addr_range: BOOLEAN := FALSE
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2b_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2b_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 DOWNTO 0);
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2b_minimal;
+
+
+ARCHITECTURE str OF unb2b_minimal IS
+
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb2b_board_fw_version := (1, 1);
+ CONSTANT c_use_125m : BOOLEAN := g_design_name="unb2b_minimal_125m";
+ CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(c_use_125m, c_unb2b_board_mm_clk_freq_125M, c_unb2b_board_mm_clk_freq_50M);
+
+ -- System
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_ethclk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL st_rst : STD_LOGIC;
+ SIGNAL st_clk : STD_LOGIC;
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+
+ -- PPSH
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- pm bus
+ SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
+ SIGNAL reg_unb_pmbus_miso : t_mem_miso;
+
+ -- FPGA sensors
+ SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
+ SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ -- EPCS read
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+
+ -- EPCS write
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+
+ -- EPCS status/control
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
+
+ -- Remote Update
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
+
+ -- Scrap RAM
+ SIGNAL ram_scrap_mosi : t_mem_mosi;
+ SIGNAL ram_scrap_miso : t_mem_miso;
+
+ -- QSFP leds
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2b_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb2b_board_lib.ctrl_unb2b_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2b_board_eth_clk_freq_125M,
+ g_aux => c_unb2b_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ PORT MAP (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_mmm : ENTITY work.mmm_unb2b_minimal
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
+
+ u_front_led : ENTITY unb2b_board_lib.unb2b_board_qsfp_leds
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2b_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
+
+ u_front_io : ENTITY unb2b_board_lib.unb2b_board_front_io
+ GENERIC MAP (
+ g_nof_qsfp_bus => c_unb2b_board_tr_qsfp.nof_bus
+ )
+ PORT MAP (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
+
+END str;
+
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index d268fcb494f3c4c02f8538e52a8f0f78f70a9c75..9b8ac84e51df559864bc43d0da20041717b134d2 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -213,6 +213,11 @@ ENTITY ctrl_unb2b_board IS
udp_rx_sosi_arr : OUT t_dp_sosi_arr(g_udp_offload_nof_streams-1 DOWNTO 0);
udp_rx_siso_arr : IN t_dp_siso_arr(g_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+ -- Scrap RAM
+ ram_scrap_mosi : IN t_mem_mosi;
+ ram_scrap_miso : OUT t_mem_miso;
+
+
--
-- >>> Ctrl FPGA pins
--
@@ -256,7 +261,8 @@ ARCHITECTURE str OF ctrl_unb2b_board IS
CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(g_sim=FALSE,g_mm_clk_freq,c_unb2b_board_mm_clk_freq_10M);
-
+ CONSTANT c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2**9, 'X');
+
-- Clock and reset
SIGNAL i_ext_clk200 : STD_LOGIC;
SIGNAL ext_pps : STD_LOGIC;
@@ -816,4 +822,20 @@ BEGIN
);
END GENERATE;
+ u_ram_scrap : ENTITY common_lib.common_ram_r_w
+ GENERIC MAP (
+ g_ram => c_ram_scrap
+ )
+ PORT MAP (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ wr_en => ram_scrap_mosi.wr,
+ wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w-1 DOWNTO 0),
+ wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w-1 DOWNTO 0),
+ rd_en => ram_scrap_mosi.rd,
+ rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w-1 DOWNTO 0),
+ rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w-1 DOWNTO 0),
+ rd_val => ram_scrap_miso.rdval
+ );
+
END str;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
index b41f722c594cb055c2f8b2ac85db2eb965fcb60f..7a89f256525af55ffc87653edb10125bd4cffbe5 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
@@ -58,6 +58,7 @@ quartus_ip_files =
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
$RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
+ $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_ram_scrap.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip
index 4e21d21150344b6e7ed0b700bb14822d13c23b0b..3f20b37b3bbbe2f7d5fc59fab99efde13ac4de36 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs_eth_0.ip
@@ -2113,7 +2113,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip
index 6cdc373cdaa730fbab629577b3fc5f2ea1845d1b..1eb1516e83a3f178d88b218974eb5333a22cb65a 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_cpu_0.ip
@@ -2073,7 +2073,7 @@
<spirit:parameter>
<spirit:name>breakAbsoluteAddr</spirit:name>
<spirit:displayName>Break vector</spirit:displayName>
- <spirit:value spirit:format="long" spirit:id="breakAbsoluteAddr">14368</spirit:value>
+ <spirit:value spirit:format="long" spirit:id="breakAbsoluteAddr">20512</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>mmu_TLBMissExcAbsAddr</spirit:name>
@@ -2208,7 +2208,7 @@
<spirit:parameter>
<spirit:name>instSlaveMapParam</spirit:name>
<spirit:displayName>instSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="instSlaveMapParam"><![CDATA[<address-map><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>faSlaveMapParam</spirit:name>
@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
+ <spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
@@ -2313,7 +2313,7 @@
<spirit:parameter>
<spirit:name>AUTO_DEVICE</spirit:name>
<spirit:displayName>Auto DEVICE</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="AUTO_DEVICE">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AUTO_DEVICE_SPEEDGRADE</spirit:name>
@@ -2344,7 +2344,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.BREAK_ADDR</spirit:name>
- <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BREAK_ADDR">0x00003820</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.CMacro.BREAK_ADDR">0x00005020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</spirit:name>
@@ -2541,7 +2541,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -3527,7 +3527,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
index 7b5f0fe25e180cffc329e31057bff1308a56a399..7f9871e0c9f201e051e550b94f4ef75e94c7e13d 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
@@ -678,7 +678,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
index 84857f4e72747ba2792d3cbffb86e9f836e05059..45e20821f046a8939545f1726b265d8cc53b8415 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
@@ -794,7 +794,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
index 7bef01f2909e9582a692e86d1c1eb031bdc99ec3..3e7b0ab130a7ffd46e16ba19f304a76d72a3073a 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
@@ -691,7 +691,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_ram_scrap.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_ram_scrap.ip
new file mode 100644
index 0000000000000000000000000000000000000000..bf3a3df773ee01260e81d5c37739b9faea02612a
--- /dev/null
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_ram_scrap.ip
@@ -0,0 +1,1447 @@
+<?xml version="1.0" ?>
+<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_unb2c_minimal_ram_scrap</spirit:library>
+ <spirit:name>qsys_unb2c_minimal_ram_scrap</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>address</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_address_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>clk</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_clk_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>mem</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="avalon" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>address</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_address</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>write</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_write</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>writedata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>read</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_read</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>readdata</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>addressAlignment</spirit:name>
+ <spirit:displayName>Slave addressing</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressAlignment">DYNAMIC</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressGroup</spirit:name>
+ <spirit:displayName>Address group</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="addressGroup">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressSpan</spirit:name>
+ <spirit:displayName>Address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressSpan">2048</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>addressUnits</spirit:name>
+ <spirit:displayName>Address units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="addressUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>alwaysBurstMaxBurst</spirit:name>
+ <spirit:displayName>Always burst maximum burst</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="alwaysBurstMaxBurst">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>Associated reset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset">system_reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bitsPerSymbol</spirit:name>
+ <spirit:displayName>Bits per symbol</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="bitsPerSymbol">8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgedAddressOffset</spirit:name>
+ <spirit:displayName>Bridged Address Offset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgedAddressOffset">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bridgesToMaster</spirit:name>
+ <spirit:displayName>Bridges to master</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bridgesToMaster"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstOnBurstBoundariesOnly</spirit:name>
+ <spirit:displayName>Burst on burst boundaries only</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="burstOnBurstBoundariesOnly">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>burstcountUnits</spirit:name>
+ <spirit:displayName>Burstcount units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="burstcountUnits">WORDS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>constantBurstBehavior</spirit:name>
+ <spirit:displayName>Constant burst behavior</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="constantBurstBehavior">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>explicitAddressSpan</spirit:name>
+ <spirit:displayName>Explicit address span</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="explicitAddressSpan">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>holdTime</spirit:name>
+ <spirit:displayName>Hold</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="holdTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>interleaveBursts</spirit:name>
+ <spirit:displayName>Interleave bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="interleaveBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isBigEndian</spirit:name>
+ <spirit:displayName>Big endian</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isBigEndian">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isFlash</spirit:name>
+ <spirit:displayName>Flash memory</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isFlash">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isMemoryDevice</spirit:name>
+ <spirit:displayName>Memory device</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isMemoryDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>isNonVolatileStorage</spirit:name>
+ <spirit:displayName>Non-volatile storage</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="isNonVolatileStorage">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>linewrapBursts</spirit:name>
+ <spirit:displayName>Linewrap bursts</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="linewrapBursts">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingReadTransactions</spirit:name>
+ <spirit:displayName>Maximum pending read transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingReadTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>maximumPendingWriteTransactions</spirit:name>
+ <spirit:displayName>Maximum pending write transactions</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="maximumPendingWriteTransactions">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumReadLatency</spirit:name>
+ <spirit:displayName>minimumReadLatency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumReadLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumResponseLatency</spirit:name>
+ <spirit:displayName>Minimum response latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumResponseLatency">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>minimumUninterruptedRunLength</spirit:name>
+ <spirit:displayName>Minimum uninterrupted run length</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="minimumUninterruptedRunLength">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>printableDevice</spirit:name>
+ <spirit:displayName>Can receive stdout/stderr</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="printableDevice">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readLatency</spirit:name>
+ <spirit:displayName>Read latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readLatency">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitStates</spirit:name>
+ <spirit:displayName>Read wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>readWaitTime</spirit:name>
+ <spirit:displayName>Read wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="readWaitTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerIncomingSignals</spirit:name>
+ <spirit:displayName>Register incoming signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerIncomingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>registerOutgoingSignals</spirit:name>
+ <spirit:displayName>Register outgoing signals</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="registerOutgoingSignals">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>setupTime</spirit:name>
+ <spirit:displayName>Setup</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="setupTime">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>timingUnits</spirit:name>
+ <spirit:displayName>Timing units</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="timingUnits">Cycles</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>transparentBridge</spirit:name>
+ <spirit:displayName>Transparent bridge</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="transparentBridge">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>waitrequestAllowance</spirit:name>
+ <spirit:displayName>Waitrequest allowance</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="waitrequestAllowance">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>wellBehavedWaitrequest</spirit:name>
+ <spirit:displayName>Well-behaved waitrequest</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="wellBehavedWaitrequest">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeLatency</spirit:name>
+ <spirit:displayName>Write latency</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeLatency">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitStates</spirit:name>
+ <spirit:displayName>Write wait states</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitStates">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>writeWaitTime</spirit:name>
+ <spirit:displayName>Write wait</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="writeWaitTime">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <altera:altera_assignments>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isFlash</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isFlash">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isMemoryDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isMemoryDevice">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isNonVolatileStorage</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isNonVolatileStorage">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>embeddedsw.configuration.isPrintableDevice</spirit:name>
+ <spirit:value spirit:format="string" spirit:id="embeddedsw.configuration.isPrintableDevice">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_assignments>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>read</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_read_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>readdata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_readdata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_reset_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="clock" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>clk</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_clk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>clockRate</spirit:name>
+ <spirit:displayName>Clock rate</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="clockRate">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>externallyDriven</spirit:name>
+ <spirit:displayName>Externally driven</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="externallyDriven">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ptfSchematicName</spirit:name>
+ <spirit:displayName>PTF schematic name</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="ptfSchematicName"></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>system_reset</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="reset" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>reset</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>csi_system_reset</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>Associated clock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock">system</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>synchronousEdges</spirit:name>
+ <spirit:displayName>Synchronous edges</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="synchronousEdges">DEASSERT</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>write</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_write_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>writedata</spirit:name>
+ <spirit:busType spirit:vendor="altera" spirit:library="altera" spirit:name="conduit" spirit:version="18.0"></spirit:busType>
+ <spirit:slave></spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>export</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>coe_writedata_export</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>associatedClock</spirit:name>
+ <spirit:displayName>associatedClock</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedClock"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>associatedReset</spirit:name>
+ <spirit:displayName>associatedReset</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="associatedReset"></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>prSafe</spirit:name>
+ <spirit:displayName>Partial Reconfiguration Safe</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="prSafe">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>QUARTUS_SYNTH</spirit:name>
+ <spirit:envIdentifier>:quartus.altera.com:</spirit:envIdentifier>
+ <spirit:modelName>avs_common_mm_readlatency2</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>QUARTUS_SYNTH</spirit:localName>
+ </spirit:fileSetRef>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>csi_system_clk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>csi_system_reset</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_address</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>8</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_write</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_writedata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_read</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>avs_mem_readdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_reset_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_clk_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_address_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>8</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_write_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_writedata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_read_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>coe_readdata_export</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left>0</spirit:left>
+ <spirit:right>31</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
+ <spirit:viewNameRef>QUARTUS_SYNTH</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <altera:entity_info>
+ <spirit:vendor>ASTRON</spirit:vendor>
+ <spirit:library>qsys_unb2c_minimal_ram_scrap</spirit:library>
+ <spirit:name>avs_common_mm_readlatency2</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ </altera:entity_info>
+ <altera:altera_module_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>g_adr_w</spirit:name>
+ <spirit:displayName>g_adr_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_adr_w">9</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>g_dat_w</spirit:name>
+ <spirit:displayName>g_dat_w</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="g_dat_w">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_SYSTEM_CLOCK_RATE</spirit:name>
+ <spirit:displayName>Auto CLOCK_RATE</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="AUTO_SYSTEM_CLOCK_RATE">50000000</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_module_parameters>
+ <altera:altera_system_parameters>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>device</spirit:name>
+ <spirit:displayName>Device</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceFamily</spirit:name>
+ <spirit:displayName>Device family</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceFamily">Arria 10</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>deviceSpeedGrade</spirit:name>
+ <spirit:displayName>Device Speed Grade</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="deviceSpeedGrade">2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>generationId</spirit:name>
+ <spirit:displayName>Generation Id</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:id="generationId">0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>bonusData</spirit:name>
+ <spirit:displayName>bonusData</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="bonusData">bonusData
+{
+}
+</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>hideFromIPCatalog</spirit:name>
+ <spirit:displayName>Hide from IP Catalog</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:id="hideFromIPCatalog">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>lockedInterfaceDefinition</spirit:name>
+ <spirit:displayName>lockedInterfaceDefinition</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="lockedInterfaceDefinition"><![CDATA[<boundaryDefinition>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>9</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>2048</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>2</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+</boundaryDefinition>]]></spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>systemInfos</spirit:name>
+ <spirit:displayName>systemInfos</spirit:displayName>
+ <spirit:value spirit:format="string" spirit:id="systemInfos"><![CDATA[<systemInfosDefinition>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>11</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>50000000</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+</systemInfosDefinition>]]></spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </altera:altera_system_parameters>
+ <altera:altera_interface_boundary>
+ <altera:interface_mapping altera:name="address" altera:internal="qsys_unb2c_minimal_ram_scrap.address" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="clk" altera:internal="qsys_unb2c_minimal_ram_scrap.clk" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="mem" altera:internal="qsys_unb2c_minimal_ram_scrap.mem" altera:type="avalon" altera:dir="end">
+ <altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
+ <altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="read" altera:internal="qsys_unb2c_minimal_ram_scrap.read" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="readdata" altera:internal="qsys_unb2c_minimal_ram_scrap.readdata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="reset" altera:internal="qsys_unb2c_minimal_ram_scrap.reset" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system" altera:internal="qsys_unb2c_minimal_ram_scrap.system" altera:type="clock" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="system_reset" altera:internal="qsys_unb2c_minimal_ram_scrap.system_reset" altera:type="reset" altera:dir="end">
+ <altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="write" altera:internal="qsys_unb2c_minimal_ram_scrap.write" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ <altera:interface_mapping altera:name="writedata" altera:internal="qsys_unb2c_minimal_ram_scrap.writedata" altera:type="conduit" altera:dir="end">
+ <altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
+ </altera:interface_mapping>
+ </altera:altera_interface_boundary>
+ <altera:altera_has_warnings>false</altera:altera_has_warnings>
+ <altera:altera_has_errors>false</altera:altera_has_errors>
+ </spirit:vendorExtensions>
+</spirit:component>
\ No newline at end of file
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
index 1ce9235df0f966a26131283cc479be308f0fde1d..e519cd9c003587aa76fa040a3596cd1d6f3431b3 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
@@ -794,7 +794,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
index d25ad0dfcf9db1cfe8e01f51745d03182cefc212..d61250f80215202891a4f5dfaeb0027dd062e595 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
@@ -794,7 +794,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
index 5ff9582c696c73fe1c313fca47a7ee484084a28f..62bd6346021221db619ba002881c443391cc91f5 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
@@ -802,7 +802,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
index 2f137cbdc8ff4a64471b99d574b31c55bc717f66..dc6d4c0da61b20e55bee63385f2cc023b285a1aa 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
@@ -802,7 +802,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
index 13be9f9e1b9c30aa4150386217871bf5f9557db5..f6b87d546e4bd730ec360f27920d8a73029771ea 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
@@ -802,7 +802,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
index c8e5e7d8620a257bd7bd000542d53fd2e8d876f2..247daac67b63bc6bda9f8aba37b05a192096bcdc 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
@@ -794,7 +794,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
index 27d16daf69f9842e918cec585fc15b125ad34f93..a9d33f0384ae5506aea57a8d18ccf08cf5b5dc21 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
@@ -794,7 +794,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
index 75fba884ad24df93e8bb3e1aef57ca766a03a3ff..994fac78aedd895ed1983b07e9af9b61d373ade1 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
@@ -802,7 +802,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip
index 52408b5274f7634641143bd193d968402498bf92..3a04d4ea8afb830878da924543f5ae6f6c424bea 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip
@@ -802,7 +802,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip
index 37075b4aed7c127b923b712e3ea5123bd702fe16..2c42c301e8ccc0ece8ddd1e105965694375ca691 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_sens.ip
@@ -802,7 +802,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
index 82e6d5db98b4ac4b1d8c1c248b38d2b3555327a7..dc6e7f617c33564934dcc829aad2618a87a9772f 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
@@ -671,7 +671,7 @@
<spirit:parameter>
<spirit:name>device</spirit:name>
<spirit:displayName>Device</spirit:displayName>
- <spirit:value spirit:format="string" spirit:id="device">10AX115U2F45E1SG</spirit:value>
+ <spirit:value spirit:format="string" spirit:id="device">10AX115U3F45E2SG</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>deviceFamily</spirit:name>
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/qsys_unb2c_minimal.qsys b/boards/uniboard2c/designs/unb2c_minimal/quartus/qsys_unb2c_minimal.qsys
index 03821d22fc67052cef87c38780187fe7028f6709..770f83dfc0dcad2365acb7fd1877032b0017138d 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/qsys_unb2c_minimal.qsys
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/qsys_unb2c_minimal.qsys
@@ -62,7 +62,7 @@
{
datum baseAddress
{
- value = "14336";
+ value = "20480";
type = "String";
}
}
@@ -169,6 +169,22 @@
type = "String";
}
}
+ element ram_scrap
+ {
+ datum _sortIndex
+ {
+ value = "21";
+ type = "int";
+ }
+ }
+ element ram_scrap.mem
+ {
+ datum baseAddress
+ {
+ value = "14336";
+ type = "String";
+ }
+ }
element reg_dpmm_ctrl
{
datum _sortIndex
@@ -435,9 +451,9 @@
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
- <parameter name="device" value="10AX115U2F45E1SG" />
+ <parameter name="device" value="10AX115U3F45E2SG" />
<parameter name="deviceFamily" value="Arria 10" />
- <parameter name="deviceSpeedGrade" value="1" />
+ <parameter name="deviceSpeedGrade" value="2" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
@@ -644,6 +660,41 @@
internal="pio_wdi.external_connection"
type="conduit"
dir="end" />
+ <interface
+ name="ram_scrap_address"
+ internal="ram_scrap.address"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_clk"
+ internal="ram_scrap.clk"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_read"
+ internal="ram_scrap.read"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_readdata"
+ internal="ram_scrap.readdata"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_reset"
+ internal="ram_scrap.reset"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_write"
+ internal="ram_scrap.write"
+ type="conduit"
+ dir="end" />
+ <interface
+ name="ram_scrap_writedata"
+ internal="ram_scrap.writedata"
+ type="conduit"
+ dir="end" />
<interface
name="reg_dpmm_ctrl_address"
internal="reg_dpmm_ctrl.address"
@@ -4016,7 +4067,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0x80' end='0xC0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xC0' end='0x100' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x200' end='0x300' datawidth='32' /><slave name='timer_0.s1' start='0x300' end='0x320' datawidth='16' /><slave name='reg_fpga_temp_sens.mem' start='0x320' end='0x340' datawidth='32' /><slave name='reg_epcs.mem' start='0x340' end='0x360' datawidth='32' /><slave name='reg_remu.mem' start='0x360' end='0x380' datawidth='32' /><slave name='pio_wdi.s1' start='0x380' end='0x390' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0x390' end='0x398' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0x398' end='0x3A0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0x3A0' end='0x3A8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0x3A8' end='0x3B0' datawidth='32' /><slave name='pio_pps.mem' start='0x3B0' end='0x3B8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0x3B8' end='0x3C0' datawidth='32' /><slave name='rom_system_info.mem' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='ram_scrap.mem' start='0x3800' end='0x4000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x4000' end='0x5000' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -4054,7 +4105,7 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='cpu_0.debug_mem_slave' start='0x5000' end='0x5800' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
@@ -4116,7 +4167,7 @@
</entry>
<entry>
<key>embeddedsw.CMacro.BREAK_ADDR</key>
- <value>0x00003820</value>
+ <value>0x00005020</value>
</entry>
<entry>
<key>embeddedsw.CMacro.CPU_ARCH_NIOS2_R1</key>
@@ -7271,7 +7322,7 @@
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_ctrl"
+ name="ram_scrap"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -7287,7 +7338,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -7351,7 +7402,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>9</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -7420,7 +7471,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>2048</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -7523,7 +7574,7 @@
</entry>
<entry>
<key>readLatency</key>
- <value>1</value>
+ <value>2</value>
</entry>
<entry>
<key>readWaitStates</key>
@@ -7802,9 +7853,9 @@
</interfaces>
</boundary>
<originalModuleInfo>
- <className>avs_common_mm</className>
+ <className>avs_common_mm_readlatency2</className>
<version>1.0</version>
- <displayName>avs_common_mm</displayName>
+ <displayName>avs_common_mm_readlatency2</displayName>
</originalModuleInfo>
<systemInfoParameterDescriptors>
<descriptors>
@@ -7826,11 +7877,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x800' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>11</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -7857,37 +7908,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_dpmm_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_ram_scrap</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_ram_scrap</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_ram_scrap</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_ram_scrap</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_ram_scrap.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_dpmm_data"
+ name="reg_dpmm_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -8473,37 +8524,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_dpmm_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_dpmm_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_epcs"
+ name="reg_dpmm_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -8519,7 +8570,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -8583,7 +8634,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -8652,7 +8703,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -9058,11 +9109,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -9089,37 +9140,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_epcs</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_dpmm_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_epcs</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_dpmm_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_dpmm_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_temp_sens"
+ name="reg_epcs"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -9705,37 +9756,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_fpga_temp_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_epcs</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_epcs</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_epcs</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_epcs</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_fpga_voltage_sens"
+ name="reg_fpga_temp_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -9751,7 +9802,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9815,7 +9866,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>4</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -9884,7 +9935,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>64</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -10290,11 +10341,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>6</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -10321,37 +10372,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_fpga_voltage_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_fpga_temp_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_temp_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_ctrl"
+ name="reg_fpga_voltage_sens"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -10367,7 +10418,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -10431,7 +10482,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>1</width>
+ <width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -10500,7 +10551,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>8</value>
+ <value>64</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -10906,11 +10957,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x40' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>3</value>
+ <value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -10937,37 +10988,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_mmdp_ctrl</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_fpga_voltage_sens</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_fpga_voltage_sens</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_mmdp_data"
+ name="reg_mmdp_ctrl"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -11553,37 +11604,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_mmdp_data</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_mmdp_ctrl</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_data</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_ctrl</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_remu"
+ name="reg_mmdp_data"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -11599,7 +11650,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11663,7 +11714,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>3</width>
+ <width>1</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -11732,7 +11783,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>32</value>
+ <value>8</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12138,11 +12189,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x8' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>5</value>
+ <value>3</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12169,37 +12220,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_remu</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_mmdp_data</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_data</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_remu</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_mmdp_data</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_mmdp_data</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_pmbus"
+ name="reg_remu"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -12215,7 +12266,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12279,7 +12330,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
- <width>6</width>
+ <width>3</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
@@ -12348,7 +12399,7 @@
</entry>
<entry>
<key>addressSpan</key>
- <value>256</value>
+ <value>32</value>
</entry>
<entry>
<key>addressUnits</key>
@@ -12754,11 +12805,11 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
- <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ <value><address-map><slave name='mem' start='0x0' end='0x20' datawidth='32' /></address-map></value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
- <value>8</value>
+ <value>5</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
@@ -12785,37 +12836,37 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_unb_pmbus</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_remu</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_remu</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VERILOG</fileSetKind>
<fileSetFiles/>
</fileSet>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetName>
- <fileSetFixedName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetName>qsys_unb2c_minimal_reg_remu</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_remu</fileSetFixedName>
<fileSetKind>SIM_VHDL</fileSetKind>
<fileSetFiles/>
</fileSet>
</fileSets>
</generationInfoDefinition>]]></parameter>
<parameter name="hlsFile" value="" />
- <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip</parameter>
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip</parameter>
<parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
<assignmentValueMap/>
</assignmentDefinition>]]></parameter>
<parameter name="svInterfaceDefinition" value="" />
</module>
<module
- name="reg_unb_sens"
+ name="reg_unb_pmbus"
kind="altera_generic_component"
version="1.0"
enabled="1">
@@ -13401,10 +13452,626 @@
</systemInfos>
</componentDefinition>]]></parameter>
<parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
- <hdlLibraryName>qsys_unb2c_minimal_reg_unb_sens</hdlLibraryName>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_unb_pmbus</hdlLibraryName>
<fileSets>
<fileSet>
- <fileSetName>qsys_unb2c_minimal_reg_unb_sens</fileSetName>
+ <fileSetName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>QUARTUS_SYNTH</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>SIM_VERILOG</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ <fileSet>
+ <fileSetName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetName>
+ <fileSetFixedName>qsys_unb2c_minimal_reg_unb_pmbus</fileSetFixedName>
+ <fileSetKind>SIM_VHDL</fileSetKind>
+ <fileSetFiles/>
+ </fileSet>
+ </fileSets>
+</generationInfoDefinition>]]></parameter>
+ <parameter name="hlsFile" value="" />
+ <parameter name="logicalView">ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_unb_pmbus.ip</parameter>
+ <parameter name="moduleAssignmentDefinition"><![CDATA[<assignmentDefinition>
+ <assignmentValueMap/>
+</assignmentDefinition>]]></parameter>
+ <parameter name="svInterfaceDefinition" value="" />
+ </module>
+ <module
+ name="reg_unb_sens"
+ kind="altera_generic_component"
+ version="1.0"
+ enabled="1">
+ <parameter name="componentDefinition"><![CDATA[<componentDefinition>
+ <boundary>
+ <interfaces>
+ <interface>
+ <name>address</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_address_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>clk</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_clk_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>mem</name>
+ <type>avalon</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>avs_mem_address</name>
+ <role>address</role>
+ <direction>Input</direction>
+ <width>6</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_write</name>
+ <role>write</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_writedata</name>
+ <role>writedata</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_read</name>
+ <role>read</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ <port>
+ <name>avs_mem_readdata</name>
+ <role>readdata</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap>
+ <entry>
+ <key>embeddedsw.configuration.isFlash</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isMemoryDevice</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isNonVolatileStorage</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>embeddedsw.configuration.isPrintableDevice</key>
+ <value>0</value>
+ </entry>
+ </assignmentValueMap>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>addressAlignment</key>
+ <value>DYNAMIC</value>
+ </entry>
+ <entry>
+ <key>addressGroup</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>addressSpan</key>
+ <value>256</value>
+ </entry>
+ <entry>
+ <key>addressUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>alwaysBurstMaxBurst</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ <value>system_reset</value>
+ </entry>
+ <entry>
+ <key>bitsPerSymbol</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>bridgedAddressOffset</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>bridgesToMaster</key>
+ </entry>
+ <entry>
+ <key>burstOnBurstBoundariesOnly</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>burstcountUnits</key>
+ <value>WORDS</value>
+ </entry>
+ <entry>
+ <key>constantBurstBehavior</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>explicitAddressSpan</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>holdTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>interleaveBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isBigEndian</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isFlash</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isMemoryDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>isNonVolatileStorage</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>linewrapBursts</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>maximumPendingReadTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>maximumPendingWriteTransactions</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>minimumReadLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumResponseLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>minimumUninterruptedRunLength</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>printableDevice</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>readLatency</key>
+ <value>1</value>
+ </entry>
+ <entry>
+ <key>readWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>readWaitTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>registerIncomingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>registerOutgoingSignals</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>setupTime</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>timingUnits</key>
+ <value>Cycles</value>
+ </entry>
+ <entry>
+ <key>transparentBridge</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>waitrequestAllowance</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>wellBehavedWaitrequest</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>writeLatency</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitStates</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>writeWaitTime</key>
+ <value>0</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>read</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_read_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>readdata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_readdata_export</name>
+ <role>export</role>
+ <direction>Input</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>reset</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_reset_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system</name>
+ <type>clock</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_clk</name>
+ <role>clk</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>clockRate</key>
+ <value>0</value>
+ </entry>
+ <entry>
+ <key>externallyDriven</key>
+ <value>false</value>
+ </entry>
+ <entry>
+ <key>ptfSchematicName</key>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>system_reset</name>
+ <type>reset</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>csi_system_reset</name>
+ <role>reset</role>
+ <direction>Input</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ <value>system</value>
+ </entry>
+ <entry>
+ <key>synchronousEdges</key>
+ <value>DEASSERT</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>write</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_write_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>1</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ <interface>
+ <name>writedata</name>
+ <type>conduit</type>
+ <isStart>false</isStart>
+ <ports>
+ <port>
+ <name>coe_writedata_export</name>
+ <role>export</role>
+ <direction>Output</direction>
+ <width>32</width>
+ <lowerBound>0</lowerBound>
+ <vhdlType>STD_LOGIC_VECTOR</vhdlType>
+ </port>
+ </ports>
+ <assignments>
+ <assignmentValueMap/>
+ </assignments>
+ <parameters>
+ <parameterValueMap>
+ <entry>
+ <key>associatedClock</key>
+ </entry>
+ <entry>
+ <key>associatedReset</key>
+ </entry>
+ <entry>
+ <key>prSafe</key>
+ <value>false</value>
+ </entry>
+ </parameterValueMap>
+ </parameters>
+ </interface>
+ </interfaces>
+ </boundary>
+ <originalModuleInfo>
+ <className>avs_common_mm</className>
+ <version>1.0</version>
+ <displayName>avs_common_mm</displayName>
+ </originalModuleInfo>
+ <systemInfoParameterDescriptors>
+ <descriptors>
+ <descriptor>
+ <parameterDefaultValue>-1</parameterDefaultValue>
+ <parameterName>AUTO_SYSTEM_CLOCK_RATE</parameterName>
+ <parameterType>java.lang.Long</parameterType>
+ <systemInfoArgs>system</systemInfoArgs>
+ <systemInfotype>CLOCK_RATE</systemInfotype>
+ </descriptor>
+ </descriptors>
+ </systemInfoParameterDescriptors>
+ <systemInfos>
+ <connPtSystemInfos>
+ <entry>
+ <key>mem</key>
+ <value>
+ <connectionPointName>mem</connectionPointName>
+ <suppliedSystemInfos>
+ <entry>
+ <key>ADDRESS_MAP</key>
+ <value><address-map><slave name='mem' start='0x0' end='0x100' datawidth='32' /></address-map></value>
+ </entry>
+ <entry>
+ <key>ADDRESS_WIDTH</key>
+ <value>8</value>
+ </entry>
+ <entry>
+ <key>MAX_SLAVE_DATA_WIDTH</key>
+ <value>32</value>
+ </entry>
+ </suppliedSystemInfos>
+ <consumedSystemInfos/>
+ </value>
+ </entry>
+ <entry>
+ <key>system</key>
+ <value>
+ <connectionPointName>system</connectionPointName>
+ <suppliedSystemInfos/>
+ <consumedSystemInfos>
+ <entry>
+ <key>CLOCK_RATE</key>
+ <value>50000000</value>
+ </entry>
+ </consumedSystemInfos>
+ </value>
+ </entry>
+ </connPtSystemInfos>
+ </systemInfos>
+</componentDefinition>]]></parameter>
+ <parameter name="generationInfoDefinition"><![CDATA[<generationInfoDefinition>
+ <hdlLibraryName>qsys_unb2c_minimal_reg_unb_sens</hdlLibraryName>
+ <fileSets>
+ <fileSet>
+ <fileSetName>qsys_unb2c_minimal_reg_unb_sens</fileSetName>
<fileSetFixedName>qsys_unb2c_minimal_reg_unb_sens</fileSetFixedName>
<fileSetKind>QUARTUS_SYNTH</fileSetKind>
<fileSetFiles/>
@@ -15398,7 +16065,7 @@
version="18.0"
start="cpu_0.data_master"
end="cpu_0.debug_mem_slave">
- <parameter name="baseAddress" value="0x3800" />
+ <parameter name="baseAddress" value="0x5000" />
</connection>
<connection
kind="avalon"
@@ -15498,6 +16165,13 @@
end="reg_fpga_voltage_sens.mem">
<parameter name="baseAddress" value="0x00c0" />
</connection>
+ <connection
+ kind="avalon"
+ version="18.0"
+ start="cpu_0.data_master"
+ end="ram_scrap.mem">
+ <parameter name="baseAddress" value="0x3800" />
+ </connection>
<connection
kind="avalon"
version="18.0"
@@ -15545,7 +16219,7 @@
version="18.0"
start="cpu_0.instruction_master"
end="cpu_0.debug_mem_slave">
- <parameter name="baseAddress" value="0x3800" />
+ <parameter name="baseAddress" value="0x5000" />
</connection>
<connection
kind="avalon"
@@ -15618,6 +16292,7 @@
version="18.0"
start="clk_0.clk"
end="reg_fpga_voltage_sens.system" />
+ <connection kind="clock" version="18.0" start="clk_0.clk" end="ram_scrap.system" />
<connection
kind="interrupt"
version="18.0"
@@ -15729,6 +16404,11 @@
version="18.0"
start="clk_0.clk_reset"
end="reg_fpga_voltage_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="clk_0.clk_reset"
+ end="ram_scrap.system_reset" />
<connection
kind="reset"
version="18.0"
@@ -15829,6 +16509,11 @@
version="18.0"
start="cpu_0.debug_reset_request"
end="reg_fpga_voltage_sens.system_reset" />
+ <connection
+ kind="reset"
+ version="18.0"
+ start="cpu_0.debug_reset_request"
+ end="ram_scrap.system_reset" />
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
index 4f3f7b17ee743180825b03b5f5ef177e4f654b5a..6be32e1f9ef6be5d3518bd53a1f6ca0d6d091c18 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
@@ -97,7 +97,11 @@ ENTITY mmm_unb2c_minimal IS
-- Remote Update
reg_remu_mosi : OUT t_mem_mosi;
- reg_remu_miso : IN t_mem_miso
+ reg_remu_miso : IN t_mem_miso;
+
+ -- Scrap RAM
+ ram_scrap_mosi : OUT t_mem_mosi;
+ ram_scrap_miso : IN t_mem_miso
);
END mmm_unb2c_minimal;
@@ -139,6 +143,9 @@ BEGIN
u_mm_file_reg_ppsh : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_PPS")
PORT MAP(mm_rst, mm_clk, reg_ppsh_mosi, reg_ppsh_miso );
+ u_mm_file_ram_scrap : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_SCRAP")
+ PORT MAP(mm_rst, mm_clk, ram_scrap_mosi, ram_scrap_miso );
+
-- Note: the eth1g RAM and TSE buses are only required by unb_osy on the NIOS as they provide the ethernet<->MM gateway.
u_mm_file_reg_eth : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
PORT MAP(mm_rst, mm_clk, eth1g_reg_mosi, eth1g_reg_miso );
@@ -296,7 +303,15 @@ BEGIN
reg_mmdp_ctrl_read_export => reg_mmdp_ctrl_mosi.rd,
reg_mmdp_ctrl_readdata_export => reg_mmdp_ctrl_miso.rddata(c_word_w-1 DOWNTO 0),
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
- reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0)
+ reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w-1 DOWNTO 0),
+
+ ram_scrap_reset_export => OPEN,
+ ram_scrap_clk_export => OPEN,
+ ram_scrap_address_export => ram_scrap_mosi.address(8 DOWNTO 0),
+ ram_scrap_write_export => ram_scrap_mosi.wr,
+ ram_scrap_writedata_export => ram_scrap_mosi.wrdata(c_word_w-1 DOWNTO 0),
+ ram_scrap_read_export => ram_scrap_mosi.rd,
+ ram_scrap_readdata_export => ram_scrap_miso.rddata(c_word_w-1 DOWNTO 0)
);
END GENERATE;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
index b0ab468d8e8d0dde3a0707da8ad94506c09a17a0..31437f17be8d76e5d617699d5275d62fbd4ed6f3 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
@@ -65,6 +65,13 @@ PACKAGE qsys_unb2c_minimal_pkg IS
pio_system_info_write_export : out std_logic; -- export
pio_system_info_writedata_export : out std_logic_vector(31 downto 0); -- export
pio_wdi_external_connection_export : out std_logic; -- export
+ ram_scrap_address_export : out std_logic_vector(8 downto 0); -- export
+ ram_scrap_clk_export : out std_logic; -- export
+ ram_scrap_read_export : out std_logic; -- export
+ ram_scrap_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ ram_scrap_reset_export : out std_logic; -- export
+ ram_scrap_write_export : out std_logic; -- export
+ ram_scrap_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dpmm_ctrl_address_export : out std_logic_vector(0 downto 0); -- export
reg_dpmm_ctrl_clk_export : out std_logic; -- export
reg_dpmm_ctrl_read_export : out std_logic; -- export
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
index bd2533c32eb6dd6340f021394e5a0de7fb034534..763519a089057846fc6ed1abe786b353d5c181da 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
@@ -1,380 +1,392 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2015
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
-LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE unb2c_board_lib.unb2c_board_pkg.ALL;
-
-ENTITY unb2c_minimal IS
- GENERIC (
- g_design_name : STRING := "unb2c_minimal";
- g_design_note : STRING := "UNUSED";
- g_technology : NATURAL := c_tech_arria10_e1sg;
- g_sim : BOOLEAN := FALSE; --Overridden by TB
- g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0;
- g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
- g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
- g_revision_id : STRING := ""; -- revision id -- set by QSF
- g_factory_image : BOOLEAN := TRUE;
- g_protect_addr_range: BOOLEAN := FALSE
- );
- PORT (
- -- GENERAL
- CLK : IN STD_LOGIC; -- System Clock
- PPS : IN STD_LOGIC; -- System Sync
- WDI : OUT STD_LOGIC; -- Watchdog Clear
- INTA : INOUT STD_LOGIC; -- FPGA interconnect line
- INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-
- -- Others
- VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
-
- -- I2C Interface to Sensors
- SENS_SC : INOUT STD_LOGIC;
- SENS_SD : INOUT STD_LOGIC;
-
- PMBUS_SC : INOUT STD_LOGIC;
- PMBUS_SD : INOUT STD_LOGIC;
- PMBUS_ALERT : IN STD_LOGIC := '0';
-
- -- 1GbE Control Interface
- ETH_CLK : IN STD_LOGIC;
- ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
- ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
-
- QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
- );
-END unb2c_minimal;
-
-
-ARCHITECTURE str OF unb2c_minimal IS
-
- -- Firmware version x.y
- CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 1);
- CONSTANT c_mm_clk_freq : NATURAL := c_unb2c_board_mm_clk_freq_50M;
-
- -- System
- SIGNAL cs_sim : STD_LOGIC;
- SIGNAL xo_ethclk : STD_LOGIC;
- SIGNAL xo_rst : STD_LOGIC;
- SIGNAL xo_rst_n : STD_LOGIC;
- SIGNAL mm_clk : STD_LOGIC;
- SIGNAL mm_rst : STD_LOGIC;
-
- SIGNAL st_rst : STD_LOGIC;
- SIGNAL st_clk : STD_LOGIC;
-
- -- PIOs
- SIGNAL pout_wdi : STD_LOGIC;
-
- -- WDI override
- SIGNAL reg_wdi_mosi : t_mem_mosi;
- SIGNAL reg_wdi_miso : t_mem_miso;
-
- -- PPSH
- SIGNAL reg_ppsh_mosi : t_mem_mosi;
- SIGNAL reg_ppsh_miso : t_mem_miso;
-
- -- UniBoard system info
- SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
- SIGNAL reg_unb_system_info_miso : t_mem_miso;
- SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
- SIGNAL rom_unb_system_info_miso : t_mem_miso;
-
- -- UniBoard I2C sens
- SIGNAL reg_unb_sens_mosi : t_mem_mosi;
- SIGNAL reg_unb_sens_miso : t_mem_miso;
-
- -- pm bus
- SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
- SIGNAL reg_unb_pmbus_miso : t_mem_miso;
-
- -- FPGA sensors
- SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
- SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
- SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
- SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
-
- -- eth1g
- SIGNAL eth1g_mm_rst : STD_LOGIC;
- SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
- SIGNAL eth1g_tse_miso : t_mem_miso;
- SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
- SIGNAL eth1g_reg_miso : t_mem_miso;
- SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
- SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
- SIGNAL eth1g_ram_miso : t_mem_miso;
-
- -- EPCS read
- SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_data_miso : t_mem_miso;
- SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
-
- -- EPCS write
- SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_data_miso : t_mem_miso;
- SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
- SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
-
- -- EPCS status/control
- SIGNAL reg_epcs_mosi : t_mem_mosi;
- SIGNAL reg_epcs_miso : t_mem_miso;
-
- -- Remote Update
- SIGNAL reg_remu_mosi : t_mem_mosi;
- SIGNAL reg_remu_miso : t_mem_miso;
-
- -- QSFP leds
- SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
- SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
-
-BEGIN
-
- -----------------------------------------------------------------------------
- -- General control function
- -----------------------------------------------------------------------------
- u_ctrl : ENTITY unb2c_board_lib.ctrl_unb2c_board
- GENERIC MAP (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_design_note => g_design_note,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_fw_version => c_fw_version,
- g_mm_clk_freq => c_mm_clk_freq,
- g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
- g_aux => c_unb2c_board_aux,
- g_factory_image => g_factory_image,
- g_protect_addr_range => g_protect_addr_range
- )
- PORT MAP (
- -- Clock an reset signals
- cs_sim => cs_sim,
- xo_ethclk => xo_ethclk,
- xo_rst => xo_rst,
- xo_rst_n => xo_rst_n,
-
- mm_clk => mm_clk,
- mm_rst => mm_rst,
-
- dp_rst => st_rst,
- dp_clk => st_clk,
- dp_pps => OPEN,
- dp_rst_in => st_rst,
- dp_clk_in => st_clk,
-
- -- Toggle WDI
- pout_wdi => pout_wdi,
-
- -- MM buses
- -- REMU
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- . Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- . System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- . UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- . FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- . PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- FPGA pins
- -- . General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
- -- . Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
- -- . I2C Interface to Sensors
- SENS_SC => SENS_SC,
- SENS_SD => SENS_SD,
- -- PM bus
- PMBUS_SC => PMBUS_SC,
- PMBUS_SD => PMBUS_SD,
- PMBUS_ALERT => PMBUS_ALERT,
-
- -- . 1GbE Control Interface
- ETH_clk => ETH_CLK,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
-
- -----------------------------------------------------------------------------
- -- MM master
- -----------------------------------------------------------------------------
- u_mmm : ENTITY work.mmm_unb2c_minimal
- GENERIC MAP (
- g_sim => g_sim,
- g_sim_unb_nr => g_sim_unb_nr,
- g_sim_node_nr => g_sim_node_nr
- )
- PORT MAP(
- mm_rst => mm_rst,
- mm_clk => mm_clk,
-
- -- PIOs
- pout_wdi => pout_wdi,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
- reg_unb_pmbus_miso => reg_unb_pmbus_miso,
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
- reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
- reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
- reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
-
- -- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
-
- -- eth1g
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- -- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- -- EPCS status/control
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
-
- -- Remote Update
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso
- );
-
- u_front_led : ENTITY unb2c_board_lib.unb2c_board_qsfp_leds
- GENERIC MAP (
- g_sim => g_sim,
- g_factory_image => g_factory_image,
- g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
- )
- PORT MAP (
- rst => mm_rst,
- clk => mm_clk,
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr
- );
-
- u_front_io : ENTITY unb2c_board_lib.unb2c_board_front_io
- GENERIC MAP (
- g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
- )
- PORT MAP (
- green_led_arr => qsfp_green_led_arr,
- red_led_arr => qsfp_red_led_arr,
- QSFP_LED => QSFP_LED
- );
-
-END str;
-
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, unb2c_board_lib, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE unb2c_board_lib.unb2c_board_pkg.ALL;
+
+ENTITY unb2c_minimal IS
+ GENERIC (
+ g_design_name : STRING := "unb2c_minimal";
+ g_design_note : STRING := "UNUSED";
+ g_technology : NATURAL := c_tech_arria10_e1sg;
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_revision_id : STRING := ""; -- revision id -- set by QSF
+ g_factory_image : BOOLEAN := TRUE;
+ g_protect_addr_range: BOOLEAN := FALSE
+ );
+ PORT (
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb2c_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb2c_board_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC;
+ SENS_SD : INOUT STD_LOGIC;
+
+ PMBUS_SC : INOUT STD_LOGIC;
+ PMBUS_SD : INOUT STD_LOGIC;
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC;
+ ETH_SGIN : IN STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+ ETH_SGOUT : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_eth-1 DOWNTO 0);
+
+ QSFP_LED : OUT STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp_nof_leds-1 DOWNTO 0)
+ );
+END unb2c_minimal;
+
+
+ARCHITECTURE str OF unb2c_minimal IS
+
+ -- Firmware version x.y
+ CONSTANT c_fw_version : t_unb2c_board_fw_version := (1, 1);
+ CONSTANT c_mm_clk_freq : NATURAL := c_unb2c_board_mm_clk_freq_50M;
+
+ -- System
+ SIGNAL cs_sim : STD_LOGIC;
+ SIGNAL xo_ethclk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
+ SIGNAL xo_rst_n : STD_LOGIC;
+ SIGNAL mm_clk : STD_LOGIC;
+ SIGNAL mm_rst : STD_LOGIC;
+
+ SIGNAL st_rst : STD_LOGIC;
+ SIGNAL st_clk : STD_LOGIC;
+
+ -- PIOs
+ SIGNAL pout_wdi : STD_LOGIC;
+
+ -- WDI override
+ SIGNAL reg_wdi_mosi : t_mem_mosi;
+ SIGNAL reg_wdi_miso : t_mem_miso;
+
+ -- PPSH
+ SIGNAL reg_ppsh_mosi : t_mem_mosi;
+ SIGNAL reg_ppsh_miso : t_mem_miso;
+
+ -- UniBoard system info
+ SIGNAL reg_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL reg_unb_system_info_miso : t_mem_miso;
+ SIGNAL rom_unb_system_info_mosi : t_mem_mosi;
+ SIGNAL rom_unb_system_info_miso : t_mem_miso;
+
+ -- UniBoard I2C sens
+ SIGNAL reg_unb_sens_mosi : t_mem_mosi;
+ SIGNAL reg_unb_sens_miso : t_mem_miso;
+
+ -- pm bus
+ SIGNAL reg_unb_pmbus_mosi : t_mem_mosi;
+ SIGNAL reg_unb_pmbus_miso : t_mem_miso;
+
+ -- FPGA sensors
+ SIGNAL reg_fpga_temp_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_temp_sens_miso : t_mem_miso;
+ SIGNAL reg_fpga_voltage_sens_mosi : t_mem_mosi;
+ SIGNAL reg_fpga_voltage_sens_miso : t_mem_miso;
+
+ -- eth1g
+ SIGNAL eth1g_mm_rst : STD_LOGIC;
+ SIGNAL eth1g_tse_mosi : t_mem_mosi; -- ETH TSE MAC registers
+ SIGNAL eth1g_tse_miso : t_mem_miso;
+ SIGNAL eth1g_reg_mosi : t_mem_mosi; -- ETH control and status registers
+ SIGNAL eth1g_reg_miso : t_mem_miso;
+ SIGNAL eth1g_reg_interrupt : STD_LOGIC; -- Interrupt
+ SIGNAL eth1g_ram_mosi : t_mem_mosi; -- ETH rx frame and tx frame memory
+ SIGNAL eth1g_ram_miso : t_mem_miso;
+
+ -- EPCS read
+ SIGNAL reg_dpmm_data_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_data_miso : t_mem_miso;
+ SIGNAL reg_dpmm_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_dpmm_ctrl_miso : t_mem_miso;
+
+ -- EPCS write
+ SIGNAL reg_mmdp_data_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_data_miso : t_mem_miso;
+ SIGNAL reg_mmdp_ctrl_mosi : t_mem_mosi;
+ SIGNAL reg_mmdp_ctrl_miso : t_mem_miso;
+
+ -- EPCS status/control
+ SIGNAL reg_epcs_mosi : t_mem_mosi;
+ SIGNAL reg_epcs_miso : t_mem_miso;
+
+ -- Remote Update
+ SIGNAL reg_remu_mosi : t_mem_mosi;
+ SIGNAL reg_remu_miso : t_mem_miso;
+
+ -- Scrap RAM
+ SIGNAL ram_scrap_mosi : t_mem_mosi;
+ SIGNAL ram_scrap_miso : t_mem_miso;
+
+ -- QSFP leds
+ SIGNAL qsfp_green_led_arr : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+ SIGNAL qsfp_red_led_arr : STD_LOGIC_VECTOR(c_unb2c_board_tr_qsfp.nof_bus-1 DOWNTO 0);
+
+BEGIN
+
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb2c_board_lib.ctrl_unb2c_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_mm_clk_freq,
+ g_eth_clk_freq => c_unb2c_board_eth_clk_freq_125M,
+ g_aux => c_unb2c_board_aux,
+ g_factory_image => g_factory_image,
+ g_protect_addr_range => g_protect_addr_range
+ )
+ PORT MAP (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_ethclk => xo_ethclk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ dp_rst => st_rst,
+ dp_clk => st_clk,
+ dp_pps => OPEN,
+ dp_rst_in => st_rst,
+ dp_clk_in => st_clk,
+
+ -- Toggle WDI
+ pout_wdi => pout_wdi,
+
+ -- MM buses
+ -- REMU
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- . FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- . PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- scrap ram
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ SENS_SC => SENS_SC,
+ SENS_SD => SENS_SD,
+ -- PM bus
+ PMBUS_SC => PMBUS_SC,
+ PMBUS_SD => PMBUS_SD,
+ PMBUS_ALERT => PMBUS_ALERT,
+
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_CLK,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM master
+ -----------------------------------------------------------------------------
+ u_mmm : ENTITY work.mmm_unb2c_minimal
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr
+ )
+ PORT MAP(
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- PIOs
+ pout_wdi => pout_wdi,
+
+ -- Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- system_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ reg_unb_pmbus_mosi => reg_unb_pmbus_mosi,
+ reg_unb_pmbus_miso => reg_unb_pmbus_miso,
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi => reg_fpga_temp_sens_mosi,
+ reg_fpga_temp_sens_miso => reg_fpga_temp_sens_miso,
+ reg_fpga_voltage_sens_mosi => reg_fpga_voltage_sens_mosi,
+ reg_fpga_voltage_sens_miso => reg_fpga_voltage_sens_miso,
+
+ -- PPSH
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
+
+ -- eth1g
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- EPCS read
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ -- EPCS write
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ -- EPCS status/control
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
+
+ -- Remote Update
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
+
+ -- Scrap RAM
+ ram_scrap_mosi => ram_scrap_mosi,
+ ram_scrap_miso => ram_scrap_miso
+ );
+
+ u_front_led : ENTITY unb2c_board_lib.unb2c_board_qsfp_leds
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_factory_image => g_factory_image,
+ g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
+ g_pulse_us => 1000 / (10**9 / c_mm_clk_freq) -- nof clk cycles to get us period
+ )
+ PORT MAP (
+ rst => mm_rst,
+ clk => mm_clk,
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr
+ );
+
+ u_front_io : ENTITY unb2c_board_lib.unb2c_board_front_io
+ GENERIC MAP (
+ g_nof_qsfp_bus => c_unb2c_board_tr_qsfp.nof_bus
+ )
+ PORT MAP (
+ green_led_arr => qsfp_green_led_arr,
+ red_led_arr => qsfp_red_led_arr,
+ QSFP_LED => QSFP_LED
+ );
+
+END str;
+
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index bd1308a5c1d67fa877075d643a751a80428a8b70..2920908aef0b8a38942376a042c137e83d96e8a3 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -1,819 +1,840 @@
--------------------------------------------------------------------------------
---
--- Copyright (C) 2012-2015
--- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
--- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, either version 3 of the License, or
--- (at your option) any later version.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
---
--------------------------------------------------------------------------------
-
--- Purpose: Provide general control infrastructure
--- Usage: In a design <design_name>.vhd that consists of:
--- . mmm_<design_name>.vhd with a Nios2 and the MM bus and the peripherals
--- . ctrl_unb2c_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
-
-LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
-USE IEEE.STD_LOGIC_1164.ALL;
-USE IEEE.NUMERIC_STD.ALL;
-USE common_lib.common_pkg.ALL;
-USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE work.unb2c_board_pkg.ALL;
-USE i2c_lib.i2c_pkg.ALL;
-USE technology_lib.technology_pkg.ALL;
-USE tech_tse_lib.tech_tse_pkg.ALL;
-USE eth_lib.eth_pkg.ALL;
-
-ENTITY ctrl_unb2c_board IS
- GENERIC (
- ----------------------------------------------------------------------------
- -- General
- ----------------------------------------------------------------------------
- g_technology : NATURAL := c_tech_arria10;
- g_sim : BOOLEAN := FALSE;
- g_design_name : STRING := "UNUSED";
- g_fw_version : t_unb2c_board_fw_version := (0, 0); -- firmware version x.y
- g_stamp_date : NATURAL := 0;
- g_stamp_time : NATURAL := 0;
- g_revision_id : STRING := ""; -- revision_id, commit hash (first 9 chars) or number
- g_design_note : STRING := "UNUSED";
- g_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
- g_mm_clk_freq : NATURAL := c_unb2c_board_mm_clk_freq_125M;
- g_eth_clk_freq : NATURAL := c_unb2c_board_eth_clk_freq_125M;
- g_tse_clk_buf : BOOLEAN := FALSE;
-
- ----------------------------------------------------------------------------
- -- External CLK
- ----------------------------------------------------------------------------
- g_dp_clk_freq : NATURAL := c_unb2c_board_ext_clk_freq_200M;
- g_dp_clk_use_pll : BOOLEAN := TRUE;
- -- PLL phase clk shift with respect to CLK
- -- STRING := "0" = 0
- -- STRING := "156" = 011.25
- -- STRING := "313" = 022.5
- -- STRING := "469" = 033.75
- -- STRING := "625" = 045
- -- STRING := "781" = 056.25
- -- STRING := "938" = 067.5
- -- STRING := "1094" = 078.75
- -- STRING := "1250" = 090
- -- STRING := "1406" = 1250+ 156 = 101.25
- -- STRING := "1563" = 1250+ 313 = 112.5
- -- STRING := "1719" = 1250+ 469 = 123.75
- -- STRING := "1875" = 1250+ 625 = 135
- -- STRING := "2031" = 1250+ 781 = 146.25
- -- STRING := "2188" = 1250+ 938 = 157.5
- -- STRING := "2344" = 1250+1094 = 168.75
- -- STRING := "2500" = 1250+1250 = 180
- -- STRING := "2656" = 2500+ 156 = 191.25
- -- STRING := "2813" = 2500+ 313 = 202.5
- -- STRING := "2969" = 2500+ 469 = 213.75
- -- STRING := "3125" = 2500+ 625 = 225
- -- STRING := "3281" = 2500+ 781 = 236.25
- -- STRING := "3438" = 2500+ 938 = 247.5
- -- STRING := "3594" = 2500+1094 = 258.75
- -- STRING := "3750" = 2500+1250 = 270
- -- STRING := "3906" = 3750+ 156 = 281.25
- -- STRING := "4063" = 3750+ 313 = 292.5
- -- STRING := "4219" = 3750+ 469 = 303.75
- -- STRING := "4375" = 3750+ 625 = 315
- -- STRING := "4531" = 3750+ 781 = 326.25
- -- STRING := "4688" = 3750+ 938 = 337.5
- -- STRING := "4844" = 3750+1094 = 348.75
- -- STRING := "5000" = 3750+1250 = 360
- g_dp_clk_phase : STRING := "0"; -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
-
- ----------------------------------------------------------------------------
- -- 1GbE UDP offload
- ----------------------------------------------------------------------------
- g_udp_offload : BOOLEAN := FALSE;
- g_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
-
- ----------------------------------------------------------------------------
- -- Auxiliary Interface
- ----------------------------------------------------------------------------
- g_fpga_temp_high : NATURAL := 85;
- g_app_led_red : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_red
- g_app_led_green : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_green
-
- g_aux : t_c_unb2c_board_aux := c_unb2c_board_aux;
- g_factory_image : BOOLEAN := FALSE;
- g_protect_addr_range: BOOLEAN := FALSE;
- g_protected_addr_lo : NATURAL := 0; -- Byte address
- g_protected_addr_hi : NATURAL := 41943039 -- Byte address, for UniBoard1 this is 640 sectors*256 pages*256 bytes -1 = 41943039
- );
- PORT (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- cs_sim : OUT STD_LOGIC;
-
- xo_ethclk : OUT STD_LOGIC; -- 125 MHz ETH_CLK
- xo_rst : OUT STD_LOGIC; -- reset in ETH_CLK domain released after few cycles
- xo_rst_n : OUT STD_LOGIC;
-
- ext_clk200 : OUT STD_LOGIC; -- 200 MHz CLK
- ext_rst200 : OUT STD_LOGIC; -- reset in CLK clock domain released after mm_rst
-
- mm_clk : OUT STD_LOGIC; -- MM clock from xo_ethclk PLL
- mm_rst : OUT STD_LOGIC; -- reset in MM clock domain released after xo_ethclk PLL locked
-
- dp_rst : OUT STD_LOGIC; -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
- dp_clk : OUT STD_LOGIC; -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
- dp_pps : OUT STD_LOGIC; -- PPS in dp_clk domain
- dp_rst_in : IN STD_LOGIC; -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
- dp_clk_in : IN STD_LOGIC; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
-
- mb_I_ref_rst : OUT STD_LOGIC; -- reset in MB_I_REF_CLK domain released after mm_rst
- mb_II_ref_rst : OUT STD_LOGIC; -- reset in MB_II_REF_CLK domain released after mm_rst
-
- this_chip_id : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_chip_w-1 DOWNTO 0); -- [1:0], so range 0-3 for PN
- this_bck_id : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_uniboard_w-1 DOWNTO 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
-
- app_led_red : IN STD_LOGIC := '0';
- app_led_green : IN STD_LOGIC := '1';
-
- -- PIOs
- pout_wdi : IN STD_LOGIC; -- Toggled by unb_osy; can be overriden by reg_wdi.
-
- -- Manual WDI override
- reg_wdi_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_wdi_miso : OUT t_mem_miso;
-
- -- REMU
- reg_remu_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_remu_miso : OUT t_mem_miso;
-
- -- EPCS read
- reg_dpmm_data_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dpmm_data_miso : OUT t_mem_miso;
- reg_dpmm_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dpmm_ctrl_miso : OUT t_mem_miso;
-
- -- EPCS write
- reg_mmdp_data_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_mmdp_data_miso : OUT t_mem_miso;
- reg_mmdp_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_mmdp_ctrl_miso : OUT t_mem_miso;
-
- -- EPCS status/control
- reg_epcs_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_epcs_miso : OUT t_mem_miso;
-
- -- MM buses to/from mms_unb2c_board_system_info
- reg_unb_system_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_unb_system_info_miso : OUT t_mem_miso;
-
- rom_unb_system_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- rom_unb_system_info_miso : OUT t_mem_miso;
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_unb_sens_miso : OUT t_mem_miso;
-
- reg_unb_pmbus_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_unb_pmbus_miso : OUT t_mem_miso;
-
- -- FPGA sensors
- reg_fpga_temp_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_fpga_temp_sens_miso : OUT t_mem_miso;
- reg_fpga_voltage_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_fpga_voltage_sens_miso : OUT t_mem_miso;
-
- -- PPSH
- reg_ppsh_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_ppsh_miso : OUT t_mem_miso;
-
- -- eth1g control&monitoring
- eth1g_mm_rst : IN STD_LOGIC;
- eth1g_tse_mosi : IN t_mem_mosi; -- ETH TSE MAC registers
- eth1g_tse_miso : OUT t_mem_miso;
- eth1g_reg_mosi : IN t_mem_mosi; -- ETH control and status registers
- eth1g_reg_miso : OUT t_mem_miso;
- eth1g_reg_interrupt : OUT STD_LOGIC; -- Interrupt
- eth1g_ram_mosi : IN t_mem_mosi; -- ETH rx frame and tx frame memory
- eth1g_ram_miso : OUT t_mem_miso;
-
- -- eth1g UDP streaming ports
- udp_tx_sosi_arr : IN t_dp_sosi_arr(g_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
- udp_tx_siso_arr : OUT t_dp_siso_arr(g_udp_offload_nof_streams-1 DOWNTO 0);
- udp_rx_sosi_arr : OUT t_dp_sosi_arr(g_udp_offload_nof_streams-1 DOWNTO 0);
- udp_rx_siso_arr : IN t_dp_siso_arr(g_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
-
- --
- -- >>> Ctrl FPGA pins
- --
- -- GENERAL
- CLK : IN STD_LOGIC; -- System Clock
- PPS : IN STD_LOGIC; -- System Sync
- WDI : OUT STD_LOGIC; -- Watchdog Clear
- INTA : INOUT STD_LOGIC; -- FPGA interconnect line
- INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-
- -- Others
- VERSION : IN STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(g_aux.testio_w-1 DOWNTO 0);
-
- -- I2C Interface to Sensors
- SENS_SC : INOUT STD_LOGIC := 'Z';
- SENS_SD : INOUT STD_LOGIC := 'Z';
-
- -- pmbus
- PMBUS_SC : INOUT STD_LOGIC := 'Z';
- PMBUS_SD : INOUT STD_LOGIC := 'Z';
- PMBUS_ALERT : IN STD_LOGIC := '0';
-
- -- DDR reference clock domains reset creation
- MB_I_REF_CLK : IN STD_LOGIC := '0'; -- 25 MHz
- MB_II_REF_CLK : IN STD_LOGIC := '0'; -- 25 MHz
-
- -- 1GbE Control Interface
- ETH_CLK : IN STD_LOGIC; -- 125 MHz
- ETH_SGIN : IN STD_LOGIC := '0';
- ETH_SGOUT : OUT STD_LOGIC
- );
-END ctrl_unb2c_board;
-
-
-ARCHITECTURE str OF ctrl_unb2c_board IS
-
- CONSTANT c_rom_version : NATURAL := 2; -- Only increment when something changes to the register map of rom_system_info.
-
- CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
- CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(g_sim=FALSE,g_mm_clk_freq,c_unb2c_board_mm_clk_freq_10M);
-
-
- -- Clock and reset
- SIGNAL i_ext_clk200 : STD_LOGIC;
- SIGNAL ext_pps : STD_LOGIC;
-
- SIGNAL common_areset_in_rst : STD_LOGIC;
-
- SIGNAL i_xo_ethclk : STD_LOGIC;
- SIGNAL i_xo_rst : STD_LOGIC;
- SIGNAL i_mm_rst : STD_LOGIC;
- SIGNAL i_mm_clk : STD_LOGIC;
- SIGNAL mm_locked : STD_LOGIC;
- SIGNAL mm_sim_clk : STD_LOGIC := '1';
- SIGNAL epcs_clk : STD_LOGIC := '1';
- SIGNAL clk125 : STD_LOGIC := '1';
- SIGNAL clk100 : STD_LOGIC := '1';
- SIGNAL clk50 : STD_LOGIC := '1';
-
- SIGNAL mm_wdi : STD_LOGIC;
- SIGNAL eth1g_st_clk : STD_LOGIC;
- SIGNAL eth1g_st_rst : STD_LOGIC;
-
- SIGNAL mm_pulse_ms : STD_LOGIC;
- SIGNAL mm_pulse_s : STD_LOGIC;
- SIGNAL mm_board_sens_start : STD_LOGIC;
-
- SIGNAL led_toggle : STD_LOGIC;
- SIGNAL led_toggle_red : STD_LOGIC;
- SIGNAL led_toggle_green : STD_LOGIC;
-
- -- eth1g
- SIGNAL i_tse_clk : STD_LOGIC;
- SIGNAL eth1g_led : t_tech_tse_led;
-
- -- Manual WDI override
- SIGNAL wdi_override : STD_LOGIC;
-
- -- Temperature alarm (temp > g_fpga_temp_high)
- SIGNAL temp_alarm : STD_LOGIC;
-
- -- UDP offload I/O
- SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
- SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
- SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
-
- attribute keep: boolean;
- attribute keep of led_toggle_red: signal is true;
- attribute keep of led_toggle_green: signal is true;
-
- attribute maxfan : integer;
- attribute maxfan of dp_rst : signal is 1024;
-
-BEGIN
-
- ext_clk200 <= i_ext_clk200;
- xo_ethclk <= i_xo_ethclk;
- xo_rst <= i_xo_rst;
- xo_rst_n <= NOT i_xo_rst;
- mm_clk <= i_mm_clk;
- mm_rst <= i_mm_rst;
-
- -- Default leave unused INOUT tri-state
- INTA <= 'Z';
- INTB <= 'Z';
-
- TESTIO <= (OTHERS=>'Z'); -- Leave unused INOUT tri-state
-
- ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
-
- -----------------------------------------------------------------------------
- -- ext_clk200 = CLK
- -----------------------------------------------------------------------------
- i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
-
- u_common_areset_ext : ENTITY common_lib.common_areset
- GENERIC MAP (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- PORT MAP (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_ext_clk200,
- out_rst => ext_rst200
- );
-
- -----------------------------------------------------------------------------
- -- xo_ethclk = ETH_CLK
- -----------------------------------------------------------------------------
-
- i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
-
- u_common_areset_xo : ENTITY common_lib.common_areset
- GENERIC MAP (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- PORT MAP (
- in_rst => '0', -- release reset after some clock cycles
- clk => i_xo_ethclk,
- out_rst => i_xo_rst
- );
-
-
- -----------------------------------------------------------------------------
- -- MB_I_REF_CLK --> mb_I_ref_rst
- -- MB_II_REF_CLK --> mb_II_ref_rst
- -----------------------------------------------------------------------------
-
- u_common_areset_mb_I : ENTITY common_lib.common_areset
- GENERIC MAP (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- PORT MAP (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_I_REF_CLK,
- out_rst => mb_I_ref_rst
- );
-
- u_common_areset_mb_II : ENTITY common_lib.common_areset
- GENERIC MAP (
- g_rst_level => '1', -- power up default will be inferred in FPGA
- g_delay_len => c_reset_len
- )
- PORT MAP (
- in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => MB_II_REF_CLK,
- out_rst => mb_II_ref_rst
- );
-
- -----------------------------------------------------------------------------
- -- dp_clk + dp_rst generation
- -- . dp_clk = i_ext_clk200 in sim or on HW when PLL is not desired
- -- . dp_rst always comes from common_areset
- -----------------------------------------------------------------------------
- no_pll: IF g_sim=TRUE OR (g_sim=FALSE AND g_dp_clk_use_pll=FALSE) GENERATE
- dp_clk <= i_ext_clk200;
- common_areset_in_rst <= i_mm_rst;
- END GENERATE;
-
- gen_pll: IF g_sim=FALSE AND g_dp_clk_use_pll=TRUE GENERATE
- u_unb2c_board_clk200_pll : ENTITY work.unb2c_board_clk200_pll
- GENERIC MAP (
- g_technology => g_technology,
- g_use_fpll => TRUE,
- g_clk200_phase_shift => g_dp_clk_phase
- )
- PORT MAP (
- arst => i_mm_rst,
- clk200 => i_ext_clk200,
- st_clk200 => dp_clk, -- = c0
- st_rst200 => common_areset_in_rst
- );
- END GENERATE;
-
- u_common_areset_dp_rst : ENTITY common_lib.common_areset
- GENERIC MAP (
- g_rst_level => '1',
- g_delay_len => c_reset_len
- )
- PORT MAP (
- in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
- clk => dp_clk_in,
- out_rst => dp_rst
- );
-
- -----------------------------------------------------------------------------
- -- mm_clk
- -- . use mm_sim_clk in sim
- -- . derived from ETH_CLK via PLL on hardware
- -----------------------------------------------------------------------------
-
- i_mm_clk <= mm_sim_clk WHEN g_sim = TRUE ELSE
- clk125 WHEN g_mm_clk_freq = c_unb2c_board_mm_clk_freq_125M ELSE
- clk100 WHEN g_mm_clk_freq = c_unb2c_board_mm_clk_freq_100M ELSE
- clk50 WHEN g_mm_clk_freq = c_unb2c_board_mm_clk_freq_50M ELSE
- clk50; -- default
-
- gen_mm_clk_sim: IF g_sim = TRUE GENERATE
- epcs_clk <= NOT epcs_clk AFTER 25 ns; -- 20 MHz, 50ns/2
- clk50 <= NOT clk50 AFTER 10 ns; -- 50 MHz, 20ns/2
- clk100 <= NOT clk100 AFTER 5 ns; -- 100 MHz, 10ns/2
- clk125 <= NOT clk125 AFTER 4 ns; -- 125 MHz, 8ns/2
- mm_sim_clk <= NOT mm_sim_clk AFTER 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
- mm_locked <= '0', '1' AFTER 70 ns;
- END GENERATE;
-
- gen_mm_clk_hardware: IF g_sim = FALSE GENERATE
- u_unb2c_board_clk125_pll : ENTITY work.unb2c_board_clk125_pll
- GENERIC MAP (
- g_use_fpll => TRUE,
- g_technology => g_technology
- )
- PORT MAP (
- arst => i_xo_rst,
- clk125 => i_xo_ethclk,
- c0_clk20 => epcs_clk,
- c1_clk50 => clk50,
- c2_clk100 => clk100,
- c3_clk125 => clk125,
- pll_locked => mm_locked
- );
- END GENERATE;
-
- u_unb2c_board_node_ctrl : ENTITY work.unb2c_board_node_ctrl
- GENERIC MAP (
- g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
- )
- PORT MAP (
- -- MM clock domain reset
- mm_clk => i_mm_clk,
- mm_locked => mm_locked,
- mm_rst => i_mm_rst,
- -- WDI extend
- mm_wdi_in => pout_wdi,
- mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
- -- Pulses
- mm_pulse_us => OPEN,
- mm_pulse_ms => mm_pulse_ms,
- mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
- );
-
- -----------------------------------------------------------------------------
- -- System info
- -----------------------------------------------------------------------------
- cs_sim <= is_true(g_sim);
-
- u_mms_unb2c_board_system_info : ENTITY work.mms_unb2c_board_system_info
- GENERIC MAP (
- g_sim => g_sim,
- g_technology => g_technology,
- g_design_name => g_design_name,
- g_fw_version => g_fw_version,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_revision_id => g_revision_id,
- g_design_note => g_design_note,
- g_rom_version => c_rom_version
- )
- PORT MAP (
- mm_clk => i_mm_clk,
- mm_rst => i_mm_rst,
-
- hw_version => VERSION,
- id => ID,
-
- reg_mosi => reg_unb_system_info_mosi,
- reg_miso => reg_unb_system_info_miso,
-
- rom_mosi => rom_unb_system_info_mosi,
- rom_miso => rom_unb_system_info_miso,
-
- chip_id => this_chip_id,
- bck_id => this_bck_id
- );
-
-
- -----------------------------------------------------------------------------
- -- Red LED control
- -----------------------------------------------------------------------------
-
- gen_app_led_red: IF g_app_led_red = TRUE GENERATE
- -- Let external app control the LED via the app_led_red input
- TESTIO(c_unb2c_board_testio_led_red) <= app_led_red;
- END GENERATE;
-
- no_app_led_red: IF g_app_led_red = FALSE GENERATE
- TESTIO(c_unb2c_board_testio_led_red) <= led_toggle_red;
- END GENERATE;
-
-
- -----------------------------------------------------------------------------
- -- Green LED control
- -----------------------------------------------------------------------------
-
- gen_app_led_green: IF g_app_led_green = TRUE GENERATE
- -- Let external app control the LED via the app_led_green input
- TESTIO(c_unb2c_board_testio_led_green) <= app_led_green;
- END GENERATE;
-
- no_app_led_green: IF g_app_led_green = FALSE GENERATE
- TESTIO(c_unb2c_board_testio_led_green) <= led_toggle_green;
- END GENERATE;
-
-
- ------------------------------------------------------------------------------
- -- Toggle red LED when unb2c_minimal is running, green LED for other designs.
- ------------------------------------------------------------------------------
- led_toggle_red <= sel_a_b(g_factory_image=TRUE, led_toggle, '0');
- led_toggle_green <= sel_a_b(g_factory_image=FALSE, led_toggle, '0');
-
- u_toggle : ENTITY common_lib.common_toggle
- PORT MAP (
- rst => i_mm_rst,
- clk => i_mm_clk,
- in_dat => mm_pulse_s,
- out_dat => led_toggle
- );
-
-
- ------------------------------------------------------------------------------
- -- WDI override
- ------------------------------------------------------------------------------
- -- Actively reset watchdog from software when used, else disable watchdog by leaving the WDI at tri-state level.
- -- A high temp_alarm will keep WDI asserted, causing the watch dog to reset the FPGA.
- -- A third option is to override the WDI manually using the output of a dedicated reg_wdi.
- WDI <= mm_wdi OR temp_alarm OR wdi_override;
-
- u_unb2c_board_wdi_reg : ENTITY work.unb2c_board_wdi_reg
- PORT MAP (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- sla_in => reg_wdi_mosi,
- sla_out => reg_wdi_miso,
-
- wdi_override => wdi_override
- );
-
-
- ------------------------------------------------------------------------------
- -- Remote upgrade
- ------------------------------------------------------------------------------
- -- Every design instantiates an mms_remu instance + MM status & control ports.
- -- So there is full control over the memory mapped registers to set start address of the flash
- -- and reconfigure from that address.
- u_mms_remu: ENTITY remu_lib.mms_remu
- GENERIC MAP (
- g_technology => g_technology
- )
- PORT MAP (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- epcs_clk => epcs_clk,
-
- remu_mosi => reg_remu_mosi,
- remu_miso => reg_remu_miso
- );
-
- -------------------------------------------------------------------------------
- ---- EPCS
- -------------------------------------------------------------------------------
- u_mms_epcs: ENTITY epcs_lib.mms_epcs
- GENERIC MAP (
- g_technology => g_technology,
- g_protect_addr_range => g_protect_addr_range,
- g_protected_addr_lo => g_protected_addr_lo,
- g_protected_addr_hi => g_protected_addr_hi
- )
- PORT MAP (
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- epcs_clk => epcs_clk,
-
- epcs_mosi => reg_epcs_mosi,
- epcs_miso => reg_epcs_miso,
-
- dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-
- dpmm_data_mosi => reg_dpmm_data_mosi,
- dpmm_data_miso => reg_dpmm_data_miso,
-
- mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
-
- mmdp_data_mosi => reg_mmdp_data_mosi,
- mmdp_data_miso => reg_mmdp_data_miso
- );
-
- ------------------------------------------------------------------------------
- -- PPS input
- ------------------------------------------------------------------------------
-
- u_mms_ppsh : ENTITY ppsh_lib.mms_ppsh
- GENERIC MAP (
- g_technology => g_technology,
- g_st_clk_freq => g_dp_clk_freq
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- st_rst => dp_rst_in,
- st_clk => dp_clk_in,
- pps_ext => ext_pps, -- with unknown but constant phase to st_clk
-
- -- Memory-mapped clock domain
- reg_mosi => reg_ppsh_mosi,
- reg_miso => reg_ppsh_miso,
-
- -- Streaming clock domain
- pps_sys => dp_pps
- );
-
-
- ------------------------------------------------------------------------------
- -- I2C control for UniBoard sensors
- ------------------------------------------------------------------------------
-
- mm_board_sens_start <= mm_pulse_s WHEN g_sim=FALSE ELSE mm_pulse_s; --mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
-
- u_mms_unb2c_board_sens : ENTITY work.mms_unb2c_board_sens
- GENERIC MAP (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_sens,
- g_sens_nof_result => 40,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_sens_mosi,
- reg_miso => reg_unb_sens_miso,
-
- -- i2c bus
- scl => SENS_SC,
- sda => SENS_SD
- );
-
- u_mms_unb2c_board_pmbus : ENTITY work.mms_unb2c_board_sens
- GENERIC MAP (
- g_sim => g_sim,
- g_i2c_peripheral => c_i2c_peripheral_pmbus,
- g_sens_nof_result => 42,
- g_clk_freq => g_mm_clk_freq,
- g_comma_w => 13
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
- mm_start => mm_board_sens_start,
-
- -- Memory-mapped clock domain
- reg_mosi => reg_unb_pmbus_mosi,
- reg_miso => reg_unb_pmbus_miso,
-
- -- i2c bus
- scl => PMBUS_SC,
- sda => PMBUS_SD
- );
-
- u_mms_unb2c_fpga_sens : ENTITY work.mms_unb2c_fpga_sens
- GENERIC MAP (
- g_sim => g_sim,
- g_technology => g_technology,
- g_temp_high => g_fpga_temp_high
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => i_mm_rst,
- mm_clk => i_mm_clk,
-
- --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
- mm_start => '1', -- this works
-
- -- Memory-mapped clock domain
- reg_temp_mosi => reg_fpga_temp_sens_mosi,
- reg_temp_miso => reg_fpga_temp_sens_miso,
- reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
- reg_voltage_miso => reg_fpga_voltage_sens_miso,
-
- -- Temperature alarm
- temp_alarm => temp_alarm
- );
-
-
- ------------------------------------------------------------------------------
- -- Ethernet 1GbE
- ------------------------------------------------------------------------------
-
- gen_tse_clk_buf: IF g_tse_clk_buf=TRUE GENERATE
- -- Separate clkbuf for the 1GbE tse_clk:
- u_tse_clk_buf : ENTITY tech_clkbuf_lib.tech_clkbuf
- GENERIC MAP (
- g_technology => g_technology,
- g_clock_net => "GLOBAL"
- )
- PORT MAP (
- inclk => i_xo_ethclk,
- outclk => i_tse_clk
- );
- END GENERATE;
-
- gen_tse_no_clk_buf: IF g_tse_clk_buf=FALSE GENERATE
- i_tse_clk <= i_xo_ethclk;
- END GENERATE;
-
-
- wire_udp_offload: FOR i IN 0 TO g_udp_offload_nof_streams-1 GENERATE
- eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
- udp_tx_siso_arr(i) <= eth1g_udp_tx_siso_arr(i);
-
- udp_rx_sosi_arr(i) <= eth1g_udp_rx_sosi_arr(i);
- eth1g_udp_rx_siso_arr(i) <= udp_rx_siso_arr(i);
- END GENERATE;
-
- -- In simulation use file IO for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
- no_eth1g : IF g_sim=TRUE AND g_udp_offload=FALSE GENERATE
- eth1g_reg_interrupt <= '0';
- eth1g_tse_miso <= c_mem_miso_rst;
- eth1g_reg_miso <= c_mem_miso_rst;
- eth1g_ram_miso <= c_mem_miso_rst;
- END GENERATE;
-
- --On hardware always generate 1GbE for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
- gen_eth: IF g_sim=FALSE OR g_udp_offload=TRUE GENERATE
-
- eth1g_st_clk <= dp_clk_in WHEN g_udp_offload=TRUE ELSE i_mm_clk;
- eth1g_st_rst <= dp_rst_in WHEN g_udp_offload=TRUE ELSE eth1g_mm_rst;
-
- u_eth : ENTITY eth_lib.eth
- GENERIC MAP (
- g_technology => g_technology,
- g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
- g_cross_clock_domain => g_udp_offload,
- g_frm_discard_en => TRUE
- )
- PORT MAP (
- -- Clocks and reset
- mm_rst => eth1g_mm_rst, -- use reset from QSYS
- mm_clk => i_mm_clk, -- use mm_clk direct
- eth_clk => i_tse_clk, -- 125 MHz clock
- st_rst => eth1g_st_rst,
- st_clk => eth1g_st_clk,
-
- -- UDP transmit interface
- udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
- -- UDP receive interface
- udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
- udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
-
- -- Memory Mapped Slaves
- tse_sla_in => eth1g_tse_mosi,
- tse_sla_out => eth1g_tse_miso,
- reg_sla_in => eth1g_reg_mosi,
- reg_sla_out => eth1g_reg_miso,
- reg_sla_interrupt => eth1g_reg_interrupt,
- ram_sla_in => eth1g_ram_mosi,
- ram_sla_out => eth1g_ram_miso,
-
- -- PHY interface
- eth_txp => ETH_SGOUT,
- eth_rxp => ETH_SGIN,
-
- -- LED interface
- tse_led => eth1g_led
- );
- END GENERATE;
-
-END str;
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012-2015
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: Provide general control infrastructure
+-- Usage: In a design <design_name>.vhd that consists of:
+-- . mmm_<design_name>.vhd with a Nios2 and the MM bus and the peripherals
+-- . ctrl_unb2c_board.vhd with e.g. 1GbE, PPS, I2C, Remu, EPCS
+
+LIBRARY IEEE, common_lib, dp_lib, ppsh_lib, i2c_lib, technology_lib, tech_tse_lib, eth_lib, remu_lib, epcs_lib, tech_pll_lib, tech_clkbuf_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.unb2c_board_pkg.ALL;
+USE i2c_lib.i2c_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+
+ENTITY ctrl_unb2c_board IS
+ GENERIC (
+ ----------------------------------------------------------------------------
+ -- General
+ ----------------------------------------------------------------------------
+ g_technology : NATURAL := c_tech_arria10;
+ g_sim : BOOLEAN := FALSE;
+ g_design_name : STRING := "UNUSED";
+ g_fw_version : t_unb2c_board_fw_version := (0, 0); -- firmware version x.y
+ g_stamp_date : NATURAL := 0;
+ g_stamp_time : NATURAL := 0;
+ g_revision_id : STRING := ""; -- revision_id, commit hash (first 9 chars) or number
+ g_design_note : STRING := "UNUSED";
+ g_base_ip : STD_LOGIC_VECTOR(16-1 DOWNTO 0) := X"0A63"; -- Base IP address used by unb_osy: 10.99.xx.yy
+ g_mm_clk_freq : NATURAL := c_unb2c_board_mm_clk_freq_125M;
+ g_eth_clk_freq : NATURAL := c_unb2c_board_eth_clk_freq_125M;
+ g_tse_clk_buf : BOOLEAN := FALSE;
+
+ ----------------------------------------------------------------------------
+ -- External CLK
+ ----------------------------------------------------------------------------
+ g_dp_clk_freq : NATURAL := c_unb2c_board_ext_clk_freq_200M;
+ g_dp_clk_use_pll : BOOLEAN := TRUE;
+ -- PLL phase clk shift with respect to CLK
+ -- STRING := "0" = 0
+ -- STRING := "156" = 011.25
+ -- STRING := "313" = 022.5
+ -- STRING := "469" = 033.75
+ -- STRING := "625" = 045
+ -- STRING := "781" = 056.25
+ -- STRING := "938" = 067.5
+ -- STRING := "1094" = 078.75
+ -- STRING := "1250" = 090
+ -- STRING := "1406" = 1250+ 156 = 101.25
+ -- STRING := "1563" = 1250+ 313 = 112.5
+ -- STRING := "1719" = 1250+ 469 = 123.75
+ -- STRING := "1875" = 1250+ 625 = 135
+ -- STRING := "2031" = 1250+ 781 = 146.25
+ -- STRING := "2188" = 1250+ 938 = 157.5
+ -- STRING := "2344" = 1250+1094 = 168.75
+ -- STRING := "2500" = 1250+1250 = 180
+ -- STRING := "2656" = 2500+ 156 = 191.25
+ -- STRING := "2813" = 2500+ 313 = 202.5
+ -- STRING := "2969" = 2500+ 469 = 213.75
+ -- STRING := "3125" = 2500+ 625 = 225
+ -- STRING := "3281" = 2500+ 781 = 236.25
+ -- STRING := "3438" = 2500+ 938 = 247.5
+ -- STRING := "3594" = 2500+1094 = 258.75
+ -- STRING := "3750" = 2500+1250 = 270
+ -- STRING := "3906" = 3750+ 156 = 281.25
+ -- STRING := "4063" = 3750+ 313 = 292.5
+ -- STRING := "4219" = 3750+ 469 = 303.75
+ -- STRING := "4375" = 3750+ 625 = 315
+ -- STRING := "4531" = 3750+ 781 = 326.25
+ -- STRING := "4688" = 3750+ 938 = 337.5
+ -- STRING := "4844" = 3750+1094 = 348.75
+ -- STRING := "5000" = 3750+1250 = 360
+ g_dp_clk_phase : STRING := "0"; -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
+
+ ----------------------------------------------------------------------------
+ -- 1GbE UDP offload
+ ----------------------------------------------------------------------------
+ g_udp_offload : BOOLEAN := FALSE;
+ g_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
+
+ ----------------------------------------------------------------------------
+ -- Auxiliary Interface
+ ----------------------------------------------------------------------------
+ g_fpga_temp_high : NATURAL := 85;
+ g_app_led_red : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_red
+ g_app_led_green : BOOLEAN := FALSE; -- when TRUE use external LED control via app_led_green
+
+ g_aux : t_c_unb2c_board_aux := c_unb2c_board_aux;
+ g_factory_image : BOOLEAN := FALSE;
+ g_protect_addr_range: BOOLEAN := FALSE;
+ g_protected_addr_lo : NATURAL := 0; -- Byte address
+ g_protected_addr_hi : NATURAL := 41943039 -- Byte address, for UniBoard1 this is 640 sectors*256 pages*256 bytes -1 = 41943039
+ );
+ PORT (
+ --
+ -- >>> SOPC system with conduit peripheral MM bus
+ --
+ -- System
+ cs_sim : OUT STD_LOGIC;
+
+ xo_ethclk : OUT STD_LOGIC; -- 125 MHz ETH_CLK
+ xo_rst : OUT STD_LOGIC; -- reset in ETH_CLK domain released after few cycles
+ xo_rst_n : OUT STD_LOGIC;
+
+ ext_clk200 : OUT STD_LOGIC; -- 200 MHz CLK
+ ext_rst200 : OUT STD_LOGIC; -- reset in CLK clock domain released after mm_rst
+
+ mm_clk : OUT STD_LOGIC; -- MM clock from xo_ethclk PLL
+ mm_rst : OUT STD_LOGIC; -- reset in MM clock domain released after xo_ethclk PLL locked
+
+ dp_rst : OUT STD_LOGIC; -- reset in DP clock domain released after mm_rst and after CLK PLL locked in case g_dp_clk_use_pll=TRUE
+ dp_clk : OUT STD_LOGIC; -- 200 MHz DP clock from CLK system clock direct or via CLK PLL dependent on g_dp_clk_use_pll
+ dp_pps : OUT STD_LOGIC; -- PPS in dp_clk domain
+ dp_rst_in : IN STD_LOGIC; -- externally wire OUT dp_rst to dp_rst_in to avoid delta cycle difference on dp_clk
+ dp_clk_in : IN STD_LOGIC; -- externally wire OUT dp_clk to dp_clk_in to avoid delta cycle difference on dp_clk
+
+ mb_I_ref_rst : OUT STD_LOGIC; -- reset in MB_I_REF_CLK domain released after mm_rst
+ mb_II_ref_rst : OUT STD_LOGIC; -- reset in MB_II_REF_CLK domain released after mm_rst
+
+ this_chip_id : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_chip_w-1 DOWNTO 0); -- [1:0], so range 0-3 for PN
+ this_bck_id : OUT STD_LOGIC_VECTOR(c_unb2c_board_nof_uniboard_w-1 DOWNTO 0); -- [1:0] used out of ID[7:2] to index boards 3..0 in subrack
+
+ app_led_red : IN STD_LOGIC := '0';
+ app_led_green : IN STD_LOGIC := '1';
+
+ -- PIOs
+ pout_wdi : IN STD_LOGIC; -- Toggled by unb_osy; can be overriden by reg_wdi.
+
+ -- Manual WDI override
+ reg_wdi_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_wdi_miso : OUT t_mem_miso;
+
+ -- REMU
+ reg_remu_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_remu_miso : OUT t_mem_miso;
+
+ -- EPCS read
+ reg_dpmm_data_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dpmm_data_miso : OUT t_mem_miso;
+ reg_dpmm_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dpmm_ctrl_miso : OUT t_mem_miso;
+
+ -- EPCS write
+ reg_mmdp_data_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_mmdp_data_miso : OUT t_mem_miso;
+ reg_mmdp_ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_mmdp_ctrl_miso : OUT t_mem_miso;
+
+ -- EPCS status/control
+ reg_epcs_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_epcs_miso : OUT t_mem_miso;
+
+ -- MM buses to/from mms_unb2c_board_system_info
+ reg_unb_system_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_unb_system_info_miso : OUT t_mem_miso;
+
+ rom_unb_system_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ rom_unb_system_info_miso : OUT t_mem_miso;
+
+ -- UniBoard I2C sensors
+ reg_unb_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_unb_sens_miso : OUT t_mem_miso;
+
+ reg_unb_pmbus_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_unb_pmbus_miso : OUT t_mem_miso;
+
+ -- FPGA sensors
+ reg_fpga_temp_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_fpga_temp_sens_miso : OUT t_mem_miso;
+ reg_fpga_voltage_sens_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_fpga_voltage_sens_miso : OUT t_mem_miso;
+
+ -- PPSH
+ reg_ppsh_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_ppsh_miso : OUT t_mem_miso;
+
+ -- eth1g control&monitoring
+ eth1g_mm_rst : IN STD_LOGIC;
+ eth1g_tse_mosi : IN t_mem_mosi; -- ETH TSE MAC registers
+ eth1g_tse_miso : OUT t_mem_miso;
+ eth1g_reg_mosi : IN t_mem_mosi; -- ETH control and status registers
+ eth1g_reg_miso : OUT t_mem_miso;
+ eth1g_reg_interrupt : OUT STD_LOGIC; -- Interrupt
+ eth1g_ram_mosi : IN t_mem_mosi; -- ETH rx frame and tx frame memory
+ eth1g_ram_miso : OUT t_mem_miso;
+
+ -- eth1g UDP streaming ports
+ udp_tx_sosi_arr : IN t_dp_sosi_arr(g_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ udp_tx_siso_arr : OUT t_dp_siso_arr(g_udp_offload_nof_streams-1 DOWNTO 0);
+ udp_rx_sosi_arr : OUT t_dp_sosi_arr(g_udp_offload_nof_streams-1 DOWNTO 0);
+ udp_rx_siso_arr : IN t_dp_siso_arr(g_udp_offload_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+
+ -- Scrap RAM
+ ram_scrap_mosi : IN t_mem_mosi;
+ ram_scrap_miso : OUT t_mem_miso;
+
+ --
+ -- >>> Ctrl FPGA pins
+ --
+ -- GENERAL
+ CLK : IN STD_LOGIC; -- System Clock
+ PPS : IN STD_LOGIC; -- System Sync
+ WDI : OUT STD_LOGIC; -- Watchdog Clear
+ INTA : INOUT STD_LOGIC; -- FPGA interconnect line
+ INTB : INOUT STD_LOGIC; -- FPGA interconnect line
+
+ -- Others
+ VERSION : IN STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(g_aux.testio_w-1 DOWNTO 0);
+
+ -- I2C Interface to Sensors
+ SENS_SC : INOUT STD_LOGIC := 'Z';
+ SENS_SD : INOUT STD_LOGIC := 'Z';
+
+ -- pmbus
+ PMBUS_SC : INOUT STD_LOGIC := 'Z';
+ PMBUS_SD : INOUT STD_LOGIC := 'Z';
+ PMBUS_ALERT : IN STD_LOGIC := '0';
+
+ -- DDR reference clock domains reset creation
+ MB_I_REF_CLK : IN STD_LOGIC := '0'; -- 25 MHz
+ MB_II_REF_CLK : IN STD_LOGIC := '0'; -- 25 MHz
+
+ -- 1GbE Control Interface
+ ETH_CLK : IN STD_LOGIC; -- 125 MHz
+ ETH_SGIN : IN STD_LOGIC := '0';
+ ETH_SGOUT : OUT STD_LOGIC
+ );
+END ctrl_unb2c_board;
+
+
+ARCHITECTURE str OF ctrl_unb2c_board IS
+
+ CONSTANT c_rom_version : NATURAL := 2; -- Only increment when something changes to the register map of rom_system_info.
+
+ CONSTANT c_reset_len : NATURAL := 4; -- >= c_meta_delay_len from common_pkg
+ CONSTANT c_mm_clk_freq : NATURAL := sel_a_b(g_sim=FALSE,g_mm_clk_freq,c_unb2c_board_mm_clk_freq_10M);
+
+ CONSTANT c_ram_scrap : t_c_mem := (c_mem_ram_rd_latency, 9, 32, 2**9, 'X');
+
+ -- Clock and reset
+ SIGNAL i_ext_clk200 : STD_LOGIC;
+ SIGNAL ext_pps : STD_LOGIC;
+
+ SIGNAL common_areset_in_rst : STD_LOGIC;
+
+ SIGNAL i_xo_ethclk : STD_LOGIC;
+ SIGNAL i_xo_rst : STD_LOGIC;
+ SIGNAL i_mm_rst : STD_LOGIC;
+ SIGNAL i_mm_clk : STD_LOGIC;
+ SIGNAL mm_locked : STD_LOGIC;
+ SIGNAL mm_sim_clk : STD_LOGIC := '1';
+ SIGNAL epcs_clk : STD_LOGIC := '1';
+ SIGNAL clk125 : STD_LOGIC := '1';
+ SIGNAL clk100 : STD_LOGIC := '1';
+ SIGNAL clk50 : STD_LOGIC := '1';
+
+ SIGNAL mm_wdi : STD_LOGIC;
+ SIGNAL eth1g_st_clk : STD_LOGIC;
+ SIGNAL eth1g_st_rst : STD_LOGIC;
+
+ SIGNAL mm_pulse_ms : STD_LOGIC;
+ SIGNAL mm_pulse_s : STD_LOGIC;
+ SIGNAL mm_board_sens_start : STD_LOGIC;
+
+ SIGNAL led_toggle : STD_LOGIC;
+ SIGNAL led_toggle_red : STD_LOGIC;
+ SIGNAL led_toggle_green : STD_LOGIC;
+
+ -- eth1g
+ SIGNAL i_tse_clk : STD_LOGIC;
+ SIGNAL eth1g_led : t_tech_tse_led;
+
+ -- Manual WDI override
+ SIGNAL wdi_override : STD_LOGIC;
+
+ -- Temperature alarm (temp > g_fpga_temp_high)
+ SIGNAL temp_alarm : STD_LOGIC;
+
+ -- UDP offload I/O
+ SIGNAL eth1g_udp_tx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
+ SIGNAL eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports-1 DOWNTO 0);
+ SIGNAL eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+
+ attribute keep: boolean;
+ attribute keep of led_toggle_red: signal is true;
+ attribute keep of led_toggle_green: signal is true;
+
+ attribute maxfan : integer;
+ attribute maxfan of dp_rst : signal is 1024;
+
+BEGIN
+
+ ext_clk200 <= i_ext_clk200;
+ xo_ethclk <= i_xo_ethclk;
+ xo_rst <= i_xo_rst;
+ xo_rst_n <= NOT i_xo_rst;
+ mm_clk <= i_mm_clk;
+ mm_rst <= i_mm_rst;
+
+ -- Default leave unused INOUT tri-state
+ INTA <= 'Z';
+ INTB <= 'Z';
+
+ TESTIO <= (OTHERS=>'Z'); -- Leave unused INOUT tri-state
+
+ ext_pps <= PPS; -- use more special name for PPS pin signal to ease searching for it in editor
+
+ -----------------------------------------------------------------------------
+ -- ext_clk200 = CLK
+ -----------------------------------------------------------------------------
+ i_ext_clk200 <= CLK; -- use more special name for CLK pin signal to ease searching for it in editor, the external 200 MHz CLK as ext_clk200
+
+ u_common_areset_ext : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_ext_clk200,
+ out_rst => ext_rst200
+ );
+
+ -----------------------------------------------------------------------------
+ -- xo_ethclk = ETH_CLK
+ -----------------------------------------------------------------------------
+
+ i_xo_ethclk <= ETH_CLK; -- use the ETH_CLK pin as xo_clk
+
+ u_common_areset_xo : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => '0', -- release reset after some clock cycles
+ clk => i_xo_ethclk,
+ out_rst => i_xo_rst
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- MB_I_REF_CLK --> mb_I_ref_rst
+ -- MB_II_REF_CLK --> mb_II_ref_rst
+ -----------------------------------------------------------------------------
+
+ u_common_areset_mb_I : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_I_REF_CLK,
+ out_rst => mb_I_ref_rst
+ );
+
+ u_common_areset_mb_II : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1', -- power up default will be inferred in FPGA
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => i_mm_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => MB_II_REF_CLK,
+ out_rst => mb_II_ref_rst
+ );
+
+ -----------------------------------------------------------------------------
+ -- dp_clk + dp_rst generation
+ -- . dp_clk = i_ext_clk200 in sim or on HW when PLL is not desired
+ -- . dp_rst always comes from common_areset
+ -----------------------------------------------------------------------------
+ no_pll: IF g_sim=TRUE OR (g_sim=FALSE AND g_dp_clk_use_pll=FALSE) GENERATE
+ dp_clk <= i_ext_clk200;
+ common_areset_in_rst <= i_mm_rst;
+ END GENERATE;
+
+ gen_pll: IF g_sim=FALSE AND g_dp_clk_use_pll=TRUE GENERATE
+ u_unb2c_board_clk200_pll : ENTITY work.unb2c_board_clk200_pll
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_use_fpll => TRUE,
+ g_clk200_phase_shift => g_dp_clk_phase
+ )
+ PORT MAP (
+ arst => i_mm_rst,
+ clk200 => i_ext_clk200,
+ st_clk200 => dp_clk, -- = c0
+ st_rst200 => common_areset_in_rst
+ );
+ END GENERATE;
+
+ u_common_areset_dp_rst : ENTITY common_lib.common_areset
+ GENERIC MAP (
+ g_rst_level => '1',
+ g_delay_len => c_reset_len
+ )
+ PORT MAP (
+ in_rst => common_areset_in_rst, -- release reset some clock cycles after i_mm_rst went low
+ clk => dp_clk_in,
+ out_rst => dp_rst
+ );
+
+ -----------------------------------------------------------------------------
+ -- mm_clk
+ -- . use mm_sim_clk in sim
+ -- . derived from ETH_CLK via PLL on hardware
+ -----------------------------------------------------------------------------
+
+ i_mm_clk <= mm_sim_clk WHEN g_sim = TRUE ELSE
+ clk125 WHEN g_mm_clk_freq = c_unb2c_board_mm_clk_freq_125M ELSE
+ clk100 WHEN g_mm_clk_freq = c_unb2c_board_mm_clk_freq_100M ELSE
+ clk50 WHEN g_mm_clk_freq = c_unb2c_board_mm_clk_freq_50M ELSE
+ clk50; -- default
+
+ gen_mm_clk_sim: IF g_sim = TRUE GENERATE
+ epcs_clk <= NOT epcs_clk AFTER 25 ns; -- 20 MHz, 50ns/2
+ clk50 <= NOT clk50 AFTER 10 ns; -- 50 MHz, 20ns/2
+ clk100 <= NOT clk100 AFTER 5 ns; -- 100 MHz, 10ns/2
+ clk125 <= NOT clk125 AFTER 4 ns; -- 125 MHz, 8ns/2
+ mm_sim_clk <= NOT mm_sim_clk AFTER 50 ns; -- 10 MHz, 100ns/2 --> FIXME: this mm_sim_clk should come from the MMM so that its speed can be adapted
+ mm_locked <= '0', '1' AFTER 70 ns;
+ END GENERATE;
+
+ gen_mm_clk_hardware: IF g_sim = FALSE GENERATE
+ u_unb2c_board_clk125_pll : ENTITY work.unb2c_board_clk125_pll
+ GENERIC MAP (
+ g_use_fpll => TRUE,
+ g_technology => g_technology
+ )
+ PORT MAP (
+ arst => i_xo_rst,
+ clk125 => i_xo_ethclk,
+ c0_clk20 => epcs_clk,
+ c1_clk50 => clk50,
+ c2_clk100 => clk100,
+ c3_clk125 => clk125,
+ pll_locked => mm_locked
+ );
+ END GENERATE;
+
+ u_unb2c_board_node_ctrl : ENTITY work.unb2c_board_node_ctrl
+ GENERIC MAP (
+ g_pulse_us => c_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
+ )
+ PORT MAP (
+ -- MM clock domain reset
+ mm_clk => i_mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => i_mm_rst,
+ -- WDI extend
+ mm_wdi_in => pout_wdi,
+ mm_wdi_out => mm_wdi, -- actively toggle the WDI via pout_wdi from software with toggle extend to allow software reload
+ -- Pulses
+ mm_pulse_us => OPEN,
+ mm_pulse_ms => mm_pulse_ms,
+ mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
+ );
+
+ -----------------------------------------------------------------------------
+ -- System info
+ -----------------------------------------------------------------------------
+ cs_sim <= is_true(g_sim);
+
+ u_mms_unb2c_board_system_info : ENTITY work.mms_unb2c_board_system_info
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_design_name => g_design_name,
+ g_fw_version => g_fw_version,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_revision_id => g_revision_id,
+ g_design_note => g_design_note,
+ g_rom_version => c_rom_version
+ )
+ PORT MAP (
+ mm_clk => i_mm_clk,
+ mm_rst => i_mm_rst,
+
+ hw_version => VERSION,
+ id => ID,
+
+ reg_mosi => reg_unb_system_info_mosi,
+ reg_miso => reg_unb_system_info_miso,
+
+ rom_mosi => rom_unb_system_info_mosi,
+ rom_miso => rom_unb_system_info_miso,
+
+ chip_id => this_chip_id,
+ bck_id => this_bck_id
+ );
+
+
+ -----------------------------------------------------------------------------
+ -- Red LED control
+ -----------------------------------------------------------------------------
+
+ gen_app_led_red: IF g_app_led_red = TRUE GENERATE
+ -- Let external app control the LED via the app_led_red input
+ TESTIO(c_unb2c_board_testio_led_red) <= app_led_red;
+ END GENERATE;
+
+ no_app_led_red: IF g_app_led_red = FALSE GENERATE
+ TESTIO(c_unb2c_board_testio_led_red) <= led_toggle_red;
+ END GENERATE;
+
+
+ -----------------------------------------------------------------------------
+ -- Green LED control
+ -----------------------------------------------------------------------------
+
+ gen_app_led_green: IF g_app_led_green = TRUE GENERATE
+ -- Let external app control the LED via the app_led_green input
+ TESTIO(c_unb2c_board_testio_led_green) <= app_led_green;
+ END GENERATE;
+
+ no_app_led_green: IF g_app_led_green = FALSE GENERATE
+ TESTIO(c_unb2c_board_testio_led_green) <= led_toggle_green;
+ END GENERATE;
+
+
+ ------------------------------------------------------------------------------
+ -- Toggle red LED when unb2c_minimal is running, green LED for other designs.
+ ------------------------------------------------------------------------------
+ led_toggle_red <= sel_a_b(g_factory_image=TRUE, led_toggle, '0');
+ led_toggle_green <= sel_a_b(g_factory_image=FALSE, led_toggle, '0');
+
+ u_toggle : ENTITY common_lib.common_toggle
+ PORT MAP (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ in_dat => mm_pulse_s,
+ out_dat => led_toggle
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- WDI override
+ ------------------------------------------------------------------------------
+ -- Actively reset watchdog from software when used, else disable watchdog by leaving the WDI at tri-state level.
+ -- A high temp_alarm will keep WDI asserted, causing the watch dog to reset the FPGA.
+ -- A third option is to override the WDI manually using the output of a dedicated reg_wdi.
+ WDI <= mm_wdi OR temp_alarm OR wdi_override;
+
+ u_unb2c_board_wdi_reg : ENTITY work.unb2c_board_wdi_reg
+ PORT MAP (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ sla_in => reg_wdi_mosi,
+ sla_out => reg_wdi_miso,
+
+ wdi_override => wdi_override
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- Remote upgrade
+ ------------------------------------------------------------------------------
+ -- Every design instantiates an mms_remu instance + MM status & control ports.
+ -- So there is full control over the memory mapped registers to set start address of the flash
+ -- and reconfigure from that address.
+ u_mms_remu: ENTITY remu_lib.mms_remu
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ epcs_clk => epcs_clk,
+
+ remu_mosi => reg_remu_mosi,
+ remu_miso => reg_remu_miso
+ );
+
+ -------------------------------------------------------------------------------
+ ---- EPCS
+ -------------------------------------------------------------------------------
+ u_mms_epcs: ENTITY epcs_lib.mms_epcs
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_protect_addr_range => g_protect_addr_range,
+ g_protected_addr_lo => g_protected_addr_lo,
+ g_protected_addr_hi => g_protected_addr_hi
+ )
+ PORT MAP (
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ epcs_clk => epcs_clk,
+
+ epcs_mosi => reg_epcs_mosi,
+ epcs_miso => reg_epcs_miso,
+
+ dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+
+ dpmm_data_mosi => reg_dpmm_data_mosi,
+ dpmm_data_miso => reg_dpmm_data_miso,
+
+ mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+
+ mmdp_data_mosi => reg_mmdp_data_mosi,
+ mmdp_data_miso => reg_mmdp_data_miso
+ );
+
+ ------------------------------------------------------------------------------
+ -- PPS input
+ ------------------------------------------------------------------------------
+
+ u_mms_ppsh : ENTITY ppsh_lib.mms_ppsh
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_st_clk_freq => g_dp_clk_freq
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ st_rst => dp_rst_in,
+ st_clk => dp_clk_in,
+ pps_ext => ext_pps, -- with unknown but constant phase to st_clk
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_ppsh_mosi,
+ reg_miso => reg_ppsh_miso,
+
+ -- Streaming clock domain
+ pps_sys => dp_pps
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- I2C control for UniBoard sensors
+ ------------------------------------------------------------------------------
+
+ mm_board_sens_start <= mm_pulse_s WHEN g_sim=FALSE ELSE mm_pulse_s; --mm_pulse_ms; ms pulse comes before the end of the I2C frame, this results in an overflow in simulation -- speed up in simulation
+
+ u_mms_unb2c_board_sens : ENTITY work.mms_unb2c_board_sens
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_sens,
+ g_sens_nof_result => 40,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_sens_mosi,
+ reg_miso => reg_unb_sens_miso,
+
+ -- i2c bus
+ scl => SENS_SC,
+ sda => SENS_SD
+ );
+
+ u_mms_unb2c_board_pmbus : ENTITY work.mms_unb2c_board_sens
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_i2c_peripheral => c_i2c_peripheral_pmbus,
+ g_sens_nof_result => 42,
+ g_clk_freq => g_mm_clk_freq,
+ g_comma_w => 13
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+ mm_start => mm_board_sens_start,
+
+ -- Memory-mapped clock domain
+ reg_mosi => reg_unb_pmbus_mosi,
+ reg_miso => reg_unb_pmbus_miso,
+
+ -- i2c bus
+ scl => PMBUS_SC,
+ sda => PMBUS_SD
+ );
+
+ u_mms_unb2c_fpga_sens : ENTITY work.mms_unb2c_fpga_sens
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_technology => g_technology,
+ g_temp_high => g_fpga_temp_high
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => i_mm_rst,
+ mm_clk => i_mm_clk,
+
+ --mm_start => mm_board_sens_start, -- this does not work, perhaps pulsewidth is too small
+ mm_start => '1', -- this works
+
+ -- Memory-mapped clock domain
+ reg_temp_mosi => reg_fpga_temp_sens_mosi,
+ reg_temp_miso => reg_fpga_temp_sens_miso,
+ reg_voltage_mosi => reg_fpga_voltage_sens_mosi,
+ reg_voltage_miso => reg_fpga_voltage_sens_miso,
+
+ -- Temperature alarm
+ temp_alarm => temp_alarm
+ );
+
+
+ ------------------------------------------------------------------------------
+ -- Ethernet 1GbE
+ ------------------------------------------------------------------------------
+
+ gen_tse_clk_buf: IF g_tse_clk_buf=TRUE GENERATE
+ -- Separate clkbuf for the 1GbE tse_clk:
+ u_tse_clk_buf : ENTITY tech_clkbuf_lib.tech_clkbuf
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_clock_net => "GLOBAL"
+ )
+ PORT MAP (
+ inclk => i_xo_ethclk,
+ outclk => i_tse_clk
+ );
+ END GENERATE;
+
+ gen_tse_no_clk_buf: IF g_tse_clk_buf=FALSE GENERATE
+ i_tse_clk <= i_xo_ethclk;
+ END GENERATE;
+
+
+ wire_udp_offload: FOR i IN 0 TO g_udp_offload_nof_streams-1 GENERATE
+ eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
+ udp_tx_siso_arr(i) <= eth1g_udp_tx_siso_arr(i);
+
+ udp_rx_sosi_arr(i) <= eth1g_udp_rx_sosi_arr(i);
+ eth1g_udp_rx_siso_arr(i) <= udp_rx_siso_arr(i);
+ END GENERATE;
+
+ -- In simulation use file IO for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
+ no_eth1g : IF g_sim=TRUE AND g_udp_offload=FALSE GENERATE
+ eth1g_reg_interrupt <= '0';
+ eth1g_tse_miso <= c_mem_miso_rst;
+ eth1g_reg_miso <= c_mem_miso_rst;
+ eth1g_ram_miso <= c_mem_miso_rst;
+ END GENERATE;
+
+ --On hardware always generate 1GbE for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
+ gen_eth: IF g_sim=FALSE OR g_udp_offload=TRUE GENERATE
+
+ eth1g_st_clk <= dp_clk_in WHEN g_udp_offload=TRUE ELSE i_mm_clk;
+ eth1g_st_rst <= dp_rst_in WHEN g_udp_offload=TRUE ELSE eth1g_mm_rst;
+
+ u_eth : ENTITY eth_lib.eth
+ GENERIC MAP (
+ g_technology => g_technology,
+ g_init_ip_address => g_base_ip & X"0000", -- Last two bytes set by board/FPGA ID.
+ g_cross_clock_domain => g_udp_offload,
+ g_frm_discard_en => TRUE
+ )
+ PORT MAP (
+ -- Clocks and reset
+ mm_rst => eth1g_mm_rst, -- use reset from QSYS
+ mm_clk => i_mm_clk, -- use mm_clk direct
+ eth_clk => i_tse_clk, -- 125 MHz clock
+ st_rst => eth1g_st_rst,
+ st_clk => eth1g_st_clk,
+
+ -- UDP transmit interface
+ udp_tx_snk_in_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_snk_out_arr => eth1g_udp_tx_siso_arr,
+ -- UDP receive interface
+ udp_rx_src_in_arr => eth1g_udp_rx_siso_arr,
+ udp_rx_src_out_arr => eth1g_udp_rx_sosi_arr,
+
+ -- Memory Mapped Slaves
+ tse_sla_in => eth1g_tse_mosi,
+ tse_sla_out => eth1g_tse_miso,
+ reg_sla_in => eth1g_reg_mosi,
+ reg_sla_out => eth1g_reg_miso,
+ reg_sla_interrupt => eth1g_reg_interrupt,
+ ram_sla_in => eth1g_ram_mosi,
+ ram_sla_out => eth1g_ram_miso,
+
+ -- PHY interface
+ eth_txp => ETH_SGOUT,
+ eth_rxp => ETH_SGIN,
+
+ -- LED interface
+ tse_led => eth1g_led
+ );
+ END GENERATE;
+
+ u_ram_scrap : ENTITY common_lib.common_ram_r_w
+ GENERIC MAP (
+ g_ram => c_ram_scrap
+ )
+ PORT MAP (
+ rst => i_mm_rst,
+ clk => i_mm_clk,
+ wr_en => ram_scrap_mosi.wr,
+ wr_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w-1 DOWNTO 0),
+ wr_dat => ram_scrap_mosi.wrdata(c_ram_scrap.dat_w-1 DOWNTO 0),
+ rd_en => ram_scrap_mosi.rd,
+ rd_adr => ram_scrap_mosi.address(c_ram_scrap.adr_w-1 DOWNTO 0),
+ rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w-1 DOWNTO 0),
+ rd_val => ram_scrap_miso.rdval
+ );
+
+END str;