From b789855a8ad7e72c111cb1d388ea02609b042656 Mon Sep 17 00:00:00 2001
From: JobvanWee <wee@astron.nl>
Date: Thu, 31 Mar 2022 13:28:54 +0200
Subject: [PATCH] Ready for Merge.
---
.../libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd | 15 ++++-----------
.../ddrctrl/tb/vhdl/tb_ddrctrl_input.vhd | 10 +++++-----
.../tb/vhdl/tb_ddrctrl_input_address_counter.vhd | 4 ++--
3 files changed, 11 insertions(+), 18 deletions(-)
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 6c13daed69..ebbc092b4d 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -37,7 +37,6 @@ ENTITY tb_ddrctrl IS
GENERIC (
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
- g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
g_nof_streams : POSITIVE := 12; -- number of input streams
g_data_w : NATURAL := 14; -- data with of input data vectors
g_sim_length : NATURAL := 16500; -- close to the amount of word that gets put into the memory
@@ -50,6 +49,7 @@ END tb_ddrctrl;
ARCHITECTURE tb OF tb_ddrctrl IS
-- constants for testbench
+ CONSTANT c_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
CONSTANT c_mm_clk_freq : NATURAL := 100; -- mm clock frequency in MHz
@@ -59,7 +59,7 @@ ARCHITECTURE tb OF tb_ddrctrl IS
-- Select DDR3 or DDR4 dependent on the technology and sim model
CONSTANT c_mem_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, g_tech_ddr3, g_tech_ddr4);
CONSTANT c_sim_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, c_tech_ddr3_sim_16k, c_tech_ddr4_sim_16k);
- CONSTANT c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_sim_model, c_sim_ddr, c_mem_ddr);
+ CONSTANT c_tech_ddr : t_c_tech_ddr := func_tech_sel_ddr(c_sim_model, c_sim_ddr, c_mem_ddr);
-- constants for readability
@@ -126,16 +126,9 @@ BEGIN
wr_not_rd <= '1';
WAIT FOR c_clk_period*1;
- make_data_0 : FOR J IN 1 TO 40-1 LOOP
- in_data_cnt <= in_data_cnt+1;
- fill_in_sosi_arr_rest_0 : FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
- END LOOP;
- WAIT FOR c_clk_period*1;
- END LOOP;
-- filling the input data vectors with the corresponding numbers
- make_data : FOR J IN 40 TO c_sim_length-1 LOOP
+ make_data : FOR J IN 0 TO c_sim_length-1 LOOP
in_data_cnt <= in_data_cnt+1;
fill_in_sosi_arr_rest : FOR I IN 0 TO g_nof_streams-1 LOOP
in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
@@ -158,7 +151,7 @@ BEGIN
u_ddrctrl : ENTITY work.ddrctrl
GENERIC MAP (
g_tech_ddr => c_tech_ddr,
- g_sim_model => g_sim_model,
+ g_sim_model => c_sim_model,
g_technology => g_technology,
g_nof_streams => g_nof_streams,
g_data_w => g_data_w
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input.vhd
index 86316cbb50..1df9277d93 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input.vhd
@@ -36,7 +36,6 @@ ENTITY tb_ddrctrl_input IS
GENERIC (
g_tech_ddr : t_c_tech_ddr := c_tech_ddr4_8g_1600m; -- type of memory
- g_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
g_nof_streams : POSITIVE := 12; -- number of input streams
g_data_w : NATURAL := 14; -- data with of input data vectors
g_sim_length : NATURAL := 52
@@ -47,6 +46,7 @@ END tb_ddrctrl_input;
ARCHITECTURE tb OF tb_ddrctrl_input IS
-- constants for testbench
+ CONSTANT c_sim_model : BOOLEAN := TRUE; -- determens if this is a simulation
CONSTANT c_clk_freq : NATURAL := 200; -- clock frequency in MHz
CONSTANT c_clk_period : TIME := (10**6 / c_clk_freq) * 1 ps; -- clock priod, 5 ns
@@ -58,12 +58,12 @@ ARCHITECTURE tb OF tb_ddrctrl_input IS
-- function for making total data vector
FUNCTION c_total_vector_init RETURN STD_LOGIC_VECTOR IS
- VARIABLE temp : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0);
+ VARIABLE v_total_vector : STD_LOGIC_VECTOR(c_in_data_w*g_sim_length-1 DOWNTO 0);
BEGIN
FOR I IN 0 TO g_sim_length*g_nof_streams-1 LOOP
- temp(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
+ v_total_vector(g_data_w*(I+1)-1 DOWNTO g_data_w*I) := TO_UVEC(I, g_data_w);
END LOOP;
- RETURN temp;
+ RETURN v_total_vector;
END FUNCTION c_total_vector_init;
-- constant for running the test
@@ -206,7 +206,7 @@ BEGIN
u_ddrctrl_input : ENTITY work.ddrctrl_input
GENERIC MAP (
g_tech_ddr => g_tech_ddr,
- g_sim_model => g_sim_model,
+ g_sim_model => c_sim_model,
g_nof_streams => g_nof_streams,
g_data_w => g_data_w
)
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_address_counter.vhd
index 9f54658dcb..843e6b0e8e 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl_input_address_counter.vhd
@@ -146,8 +146,8 @@ BEGIN
BEGIN
WAIT UNTIL rising_edge(clk);
IF rising_edge(clk) THEN
- ASSERT q_q_in_data(c_data_w-1 DOWNTO 0) = out_sosi.data(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_sosi.wrdata" SEVERITY ERROR;
- ASSERT q_q_in_data_enable = out_sosi.valid REPORT "in_sosi.valid does not match out_sosi.wr" SEVERITY ERROR;
+ ASSERT q_q_in_data(c_data_w-1 DOWNTO 0) = out_sosi.data(c_data_w-1 DOWNTO 0) REPORT "in_sosi.data does not match out_sosi.data" SEVERITY ERROR;
+ ASSERT q_q_in_data_enable = out_sosi.valid REPORT "in_sosi.valid does not match out_sosi.valid" SEVERITY ERROR;
ASSERT q_q_in_of = out_of REPORT "in_of does not match out_of" SEVERITY ERROR;
END IF;
END PROCESS;
--
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