From b661ed37516bb2f47722bd906b8b55714accd33f Mon Sep 17 00:00:00 2001 From: Pepping <pepping> Date: Tue, 26 Apr 2016 14:32:43 +0000 Subject: [PATCH] ROunded the number of regs of a single stream to a power of 2. --- libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd index dff5af7b83..5bc2d73e74 100644 --- a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd +++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd @@ -82,7 +82,7 @@ END dp_fifo_fill_reg; ARCHITECTURE str OF dp_fifo_fill_reg IS CONSTANT c_reg_max_used_words_offset : NATURAL := 2; - CONSTANT c_nof_regs_per_stream : NATURAL := 3; + CONSTANT c_nof_regs_per_stream : NATURAL := 4; -- Must always be a power of 2 in order to meet the python register definition. -- Define the actual size of the MM slave register CONSTANT c_mm_reg : t_c_mem := (latency => 1, -- GitLab