diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
index dff5af7b8365a63db60e354ca2b4a3830eadc932..5bc2d73e7464c969e62f95c4570c848b9ee9d319 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
@@ -82,7 +82,7 @@ END dp_fifo_fill_reg;
 ARCHITECTURE str OF dp_fifo_fill_reg IS
   
   CONSTANT c_reg_max_used_words_offset : NATURAL := 2; 
-  CONSTANT c_nof_regs_per_stream       : NATURAL := 3; 
+  CONSTANT c_nof_regs_per_stream       : NATURAL := 4; -- Must always be a power of 2 in order to meet the python register definition.  
   
   -- Define the actual size of the MM slave register
   CONSTANT c_mm_reg : t_c_mem := (latency  => 1,