From b5c656580bbce79482d208ef97aed1e34a1ff086 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Thu, 12 Feb 2015 09:11:40 +0000
Subject: [PATCH] Added sequence data valid counter.
---
libraries/base/diag/src/vhdl/diag_rx_seq.vhd | 21 +++++++++++++++++-
libraries/base/diag/src/vhdl/diag_tx_seq.vhd | 23 +++++++++++++++++++-
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
index 33d7217033..68c38ef3a6 100644
--- a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
@@ -52,6 +52,7 @@ ENTITY diag_rx_seq IS
GENERIC (
g_input_reg : BOOLEAN := FALSE; -- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
g_sel : STD_LOGIC := '1'; -- '0' = PRSG, '1' = COUNTER
+ g_cnt_w : NATURAL := c_word_w;
g_dat_w : NATURAL := 12;
g_diag_res_w : NATURAL := 16
);
@@ -67,7 +68,8 @@ ENTITY diag_rx_seq IS
diag_res_val : OUT STD_LOGIC;
-- ST input
- in_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
+ in_cnt : OUT STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0); -- count valid input test sequence data
+ in_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- input test sequence data
in_val : IN STD_LOGIC -- gaps are allowed, however diag_res requires at least 2 valid in_dat to report a valid result
);
END diag_rx_seq;
@@ -280,4 +282,21 @@ BEGIN
END IF;
END PROCESS;
+
+ ------------------------------------------------------------------------------
+ -- Count number of valid input data
+ ------------------------------------------------------------------------------
+ u_common_counter : ENTITY common_lib.common_counter
+ GENERIC MAP (
+ g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => g_cnt_w
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_en => in_val,
+ count => in_cnt
+ );
END rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
index cd084b0248..99ee6d584a 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
@@ -39,6 +39,7 @@ ENTITY diag_tx_seq IS
GENERIC (
g_sel : STD_LOGIC := '1'; -- '0' = PRSG, '1' = COUNTER
g_init : NATURAL := 0; -- init value for out_dat when diag_en = '0'
+ g_cnt_w : NATURAL := c_word_w;
g_dat_w : NATURAL -- >= 1, test data width
);
PORT (
@@ -51,7 +52,8 @@ ENTITY diag_tx_seq IS
diag_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := TO_UVEC(g_init, g_dat_w); -- init value for out_dat when diag_en = '0'
-- ST output
diag_req : IN STD_LOGIC := '1'; -- '1' = request output, '0' = halt output
- out_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- test sequence data
+ out_cnt : OUT STD_LOGIC_VECTOR(g_cnt_w-1 DOWNTO 0); -- count valid output test sequence data
+ out_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0); -- output test sequence data
out_val : OUT STD_LOGIC -- '1' when out_dat is valid
);
END diag_tx_seq;
@@ -61,6 +63,8 @@ ARCHITECTURE rtl OF diag_tx_seq IS
CONSTANT c_lfsr_nr : NATURAL := g_dat_w - c_common_lfsr_first;
+ SIGNAL diag_dis : STD_LOGIC;
+
SIGNAL prsg : STD_LOGIC_VECTOR(out_dat'RANGE);
SIGNAL nxt_prsg : STD_LOGIC_VECTOR(out_dat'RANGE);
SIGNAL cntr : STD_LOGIC_VECTOR(out_dat'RANGE);
@@ -71,6 +75,8 @@ ARCHITECTURE rtl OF diag_tx_seq IS
BEGIN
+ diag_dis <= NOT diag_en;
+
p_clk : PROCESS (rst, clk)
BEGIN
IF rst='1' THEN
@@ -100,4 +106,19 @@ BEGIN
nxt_out_dat <= prsg WHEN diag_sel='0' ELSE cntr;
nxt_out_val <= diag_en AND diag_req; -- 'en' for entire test on/off, 'req' for dynamic invalid gaps in the stream
+ -- Count number of valid output data
+ u_common_counter : ENTITY common_lib.common_counter
+ GENERIC MAP (
+ g_latency => 1, -- default 1 for registered count output, use 0 for immediate combinatorial count output
+ g_width => g_cnt_w
+ )
+ PORT MAP (
+ rst => rst,
+ clk => clk,
+ clken => clken,
+ cnt_clr => diag_dis, -- synchronous cnt_clr is only interpreted when clken is active
+ cnt_en => nxt_out_val,
+ count => out_cnt
+ );
+
END rtl;
--
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