diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 26386d044ae617180dd8bbedcd7e438e76997c25..99ca70f314661414c2819d92253333783c5b8a9e 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -37,6 +37,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
USE common_lib.tb_common_mem_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
@@ -52,7 +53,18 @@ ARCHITECTURE str of tb_io_ddr IS
CONSTANT c_tech_ddr : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
- CONSTANT c_data_w : NATURAL := 256; --32;
+-- CONSTANT c_ddr_addr_hi : t_tech_ddr_addr := ((OTHERS=>'0'),
+-- (OTHERS=>'0'),
+-- TO_UVEC( 3, c_tech_ddr_max.a_row_w),
+-- TO_UVEC(2**c_tech_ddr_4g.a_col_w-c_tech_ddr_4g.rsl, c_tech_ddr_max.a_col_w));
+ CONSTANT c_ddr_addr_hi : t_tech_ddr_addr := ((OTHERS=>'0'),
+ (OTHERS=>'0'),
+ TO_UVEC( 3, c_tech_ddr_max.a_row_w),
+ TO_UVEC(2**c_tech_ddr_4g.a_col_w-1, c_tech_ddr_max.a_col_w));
+
+ CONSTANT c_ctlr_data_w : NATURAL := func_tech_ddr_ctrl_data_w(c_tech_ddr);
+ CONSTANT c_dp_data_w : NATURAL := 32;
+ CONSTANT c_dp_factor : NATURAL := c_ctlr_data_w/c_dp_data_w;
SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
SIGNAL ctlr_ref_rst : STD_LOGIC;
@@ -73,9 +85,6 @@ ARCHITECTURE str of tb_io_ddr IS
SIGNAL wr_siso : t_dp_siso;
SIGNAL wr_sosi : t_dp_sosi;
- SIGNAL wr_siso_pre_fifo : t_dp_siso;
- SIGNAL wr_sosi_pre_fifo : t_dp_sosi;
-
SIGNAL rd_siso : t_dp_siso;
SIGNAL rd_sosi : t_dp_sosi;
@@ -86,7 +95,8 @@ ARCHITECTURE str of tb_io_ddr IS
SIGNAL snk_diag_res : STD_LOGIC;
SIGNAL snk_diag_res_val : STD_LOGIC;
SIGNAL snk_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
+ SIGNAL expected_cnt : NATURAL;
+
SIGNAL phy_in : t_tech_ddr_phy_in;
SIGNAL phy_io : t_tech_ddr_phy_io;
SIGNAL phy_ou : t_tech_ddr_phy_ou;
@@ -100,7 +110,7 @@ BEGIN
dp_rst <= '1', '0' AFTER 100 ns;
dvr_start_addr <= c_tech_ddr_addr_lo;
- dvr_end_addr <= c_tech_ddr_addr_hi_sim;
+ dvr_end_addr <= c_ddr_addr_hi;
p_stimuli : PROCESS
BEGIN
@@ -110,50 +120,49 @@ BEGIN
dvr_wr_not_rd <= '0';
snk_diag_en <= '0';
- WAIT UNTIL ctlr_init_done = '1';
- FOR i IN 0 TO 1 LOOP
- WAIT UNTIL rising_edge(dp_clk); -- Give the driver FSM a cycle to go into idle mode
- END LOOP;
+ proc_common_wait_until_high(dp_clk, ctlr_init_done);
+ proc_common_wait_some_cycles(dp_clk, 2); -- Give the driver FSM a cycle to go into idle mode
- -- START WRITE
+ -- START diagnostics source for write and sink for verify read
src_diag_en <= '1';
+ snk_diag_en <= '1';
+
+ -- START WRITE
dvr_wr_not_rd <= '1';
dvr_en <= '1';
-
- WAIT UNTIL rising_edge(dp_clk);
-
+ proc_common_wait_some_cycles(dp_clk, 1);
dvr_en <= '0';
-- WRITE DONE
- WAIT UNTIL dvr_done = '1';
-
- src_diag_en <= '0';
+ proc_common_wait_some_cycles(dp_clk, 10);
+ proc_common_wait_until_high(dp_clk, dvr_done);
-- START READ
- snk_diag_en <= '1';
dvr_wr_not_rd <= '0';
dvr_en <= '1';
-
- WAIT UNTIL rising_edge(dp_clk);
-
+ proc_common_wait_some_cycles(dp_clk, 1);
dvr_en <= '0';
-- READ DONE
- WAIT UNTIL dvr_done = '1';
+ proc_common_wait_some_cycles(dp_clk, 10);
+ proc_common_wait_until_high(dp_clk, dvr_done);
- WAIT FOR 2 us; -- 'Done' means all requests are posted. Wait for the last read data to arrive.
+ expected_cnt <= 1024*c_dp_factor;
+ proc_common_wait_some_cycles(dp_clk, 500*c_dp_factor); -- 'Done' means all requests are posted. Wait for the last read data to arrive.
- ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!" SEVERITY FAILURE;
- ASSERT snk_diag_res = '0' REPORT "[ERROR] NON-ZERO DIAG_RES!" SEVERITY FAILURE;
- ASSERT FALSE REPORT "[OK] Test passed." SEVERITY NOTE;
- tb_end <= '1';
+ ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!" SEVERITY FAILURE;
+ ASSERT snk_diag_res = '0' REPORT "[ERROR] NON-ZERO DIAG_RES!" SEVERITY FAILURE;
+ ASSERT UNSIGNED(snk_val_cnt) = expected_cnt REPORT "[ERROR] Unexpected number of read data!" SEVERITY FAILURE;
+
+ REPORT "[OK] Test passed." SEVERITY NOTE;
+ tb_end <= '1';
WAIT;
END PROCESS;
u_diagnostics: ENTITY diagnostics_lib.diagnostics
GENERIC MAP (
- g_dat_w => c_data_w,
+ g_dat_w => c_dp_data_w,
g_nof_streams => 1
)
PORT MAP (
@@ -179,8 +188,8 @@ BEGIN
GENERIC MAP(
g_technology => c_tech_select_default,
g_tech_ddr => c_tech_ddr,
- g_wr_data_w => c_data_w,
- g_rd_data_w => c_data_w
+ g_wr_data_w => c_dp_data_w,
+ g_rd_data_w => c_dp_data_w
)
PORT MAP (
ctlr_ref_clk => ctlr_ref_clk,