From b523d3ddf40ad13a38e93cab332e246bd8824214 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Wed, 18 Feb 2015 16:48:41 +0000
Subject: [PATCH] Updated names, libraries and prefixes to RadioHDL environment
---
.../src/vhdl/apertif_unb1_fn_beamformer.vhd | 747 +++++-------------
...apertif_unb1_fn_beamformer_udp_offload.vhd | 72 +-
...tif_unb1_fn_beamformer_udp_offload_pkg.vhd | 54 +-
.../vhdl/node_apertif_unb1_fn_beamformer.vhd | 36 +-
4 files changed, 292 insertions(+), 617 deletions(-)
diff --git a/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd b/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
index 5a77baba93..46ea2cac16 100644
--- a/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd
@@ -18,52 +18,37 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-------------------------------------------------------------------------------
-
-LIBRARY IEEE, common_lib, unb_common_lib, dp_lib, tse_lib, bf_lib, tr_xaui_lib, tr_10GbE_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, dp_lib, eth_lib, tech_tse_lib, bf_lib, tr_10GbE_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE unb_common_lib.unb_common_pkg.ALL;
-USE unb_common_lib.unb_peripherals_pkg.ALL;
+USE common_lib.common_field_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
-USE tse_lib.eth_layers_pkg.ALL;
-USE tse_lib.tse_pkg.ALL;
-USE tse_lib.eth_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE bf_lib.bf_pkg.ALL;
-USE tr_xaui_lib.tr_xaui_pkg.ALL;
-USE work.fn_beamformer_udp_offload_pkg.ALL;
-USE common_lib.common_field_pkg.ALL;
+USE work.apertif_unb1_fn_beamformer_udp_offload_pkg.ALL;
-ENTITY fn_beamformer IS
+
+ENTITY apertif_unb1_fn_beamformer IS
GENERIC (
- -- General
- g_bf : t_c_bf := c_bf;
- g_sim : BOOLEAN := FALSE;
- g_design_name : STRING := "fn_beamformer"; -- Set to "fn_beamformer_rev_multi_unb" by revision fn_beamformer_rev_multi
- -- Stamps are passed via QIP at compile start if $UNB_COMPILE_STAMPS is set
- g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD)
- g_stamp_time : NATURAL := 0; -- Time (HHMMSS)
- g_stamp_svn : NATURAL := 0; -- SVN revision
- -- Development note := "<---------max 32 chars--------->"
- g_design_note : STRING := "Apertif subband beamformer";
-
- g_fw_version : t_unb_fw_version := (3, 1); -- firmware version x.y
- g_use_bf : BOOLEAN := TRUE;
- -- Use PHY Interface
- -- TYPE t_c_unb_use_phy IS RECORD
- -- eth1g : NATURAL;
- -- tr_front: NATURAL;
- -- tr_mesh : NATURAL;
- -- tr_back : NATURAL;
- -- ddr3_I : NATURAL;
- -- ddr3_II : NATURAL;
- -- adc : NATURAL;
- -- wdi : NATURAL;
- -- END RECORD;
- g_use_phy : t_c_unb_use_phy := (1, 1, 1, 0, 0, 0, 0, 1);
- g_tr_mesh : t_c_unb_tr := c_unb_tr_mesh;
- g_aux : t_c_unb_aux := c_unb_aux
+ g_design_name : STRING := "fn_beamformer"; --"apertif_unb1_fn_beamformer";
+ g_design_note : STRING := "Apertif subband beamformer"; --"UNUSED";
+ g_sim : BOOLEAN := FALSE; --Overridden by TB
+ g_sim_unb_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0;
+ g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
+ g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
+ g_stamp_svn : NATURAL := 0; -- SVN revision -- set by QSF
+ g_bf : t_c_bf := c_bf;
+ g_use_bf : BOOLEAN := TRUE
);
PORT (
-- GENERAL
@@ -74,9 +59,9 @@ ENTITY fn_beamformer IS
INTB : INOUT STD_LOGIC; -- FPGA interconnect line
-- Others
- VERSION : IN STD_LOGIC_VECTOR(g_aux.version_w-1 DOWNTO 0);
- ID : IN STD_LOGIC_VECTOR(g_aux.id_w-1 DOWNTO 0);
- TESTIO : INOUT STD_LOGIC_VECTOR(g_aux.testio_w-1 DOWNTO 0);
+ VERSION : IN STD_LOGIC_VECTOR(c_unb1_board_aux.version_w-1 DOWNTO 0);
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+ TESTIO : INOUT STD_LOGIC_VECTOR(c_unb1_board_aux.testio_w-1 DOWNTO 0);
-- I2C Interface to Sensors
sens_sc : INOUT STD_LOGIC;
@@ -92,81 +77,45 @@ ENTITY fn_beamformer IS
SB_CLK : IN STD_LOGIC := '0'; -- TR clock FN-BN (tr_mesh)
-- Mesh Serial I/O
- FN_BN_0_TX : OUT STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0);
- FN_BN_0_RX : IN STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- FN_BN_1_TX : OUT STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0);
- FN_BN_1_RX : IN STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- FN_BN_2_TX : OUT STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0);
- FN_BN_2_RX : IN STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- FN_BN_3_TX : OUT STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0);
- FN_BN_3_RX : IN STD_LOGIC_VECTOR(g_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
+ FN_BN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0);
+ FN_BN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_tr_mesh.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-- Front Serial I/O
- SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0);
- SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb_ci.tr.bus_w-1 DOWNTO 0);
-
- SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
- SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0);
- SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_0_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_0_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_1_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_2_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_TX : OUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SI_FN_3_RX : IN STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+
+ SI_FN_0_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
+ SI_FN_1_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_2_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
+ SI_FN_3_CNTRL : INOUT STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SI_FN_RSTN : OUT STD_LOGIC := '1' -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
-- So we need to assign a '1' to it.
);
-END fn_beamformer;
-
-
-ARCHITECTURE str OF fn_beamformer IS
-
- CONSTANT c_bg_diag_wave_period : POSITIVE := 4;
-
- -- Actual MM address widths, the MM data width is fixed at the default c_word_w=32
- CONSTANT c_reg_diag_bg_addr_w : NATURAL := 3;
- CONSTANT c_ram_diag_bg_addr_w : NATURAL := ceil_log2(c_bg_diag_wave_period) + ceil_log2(g_bf.nof_subbands*g_bf.nof_signal_paths/g_bf.nof_input_streams)+ceil_log2(g_bf.nof_input_streams);
- CONSTANT c_ram_ss_ss_wide_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_weights*g_bf.nof_signal_paths);
- CONSTANT c_ram_bf_weights_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.nof_signal_paths*g_bf.nof_weights);
- CONSTANT c_ram_st_sst_bf_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units*g_bf.stat_data_sz*g_bf.nof_weights*c_nof_complex);
- CONSTANT c_reg_st_sst_bf_addr_w : NATURAL := ceil_log2(c_bf_max_nof_bf_units)*2;
- CONSTANT c_reg_diag_db_adr_w : NATURAL := 5;
-
- -- 10GbE offload
- CONSTANT c_reg_dp_offload_tx_adr_w : NATURAL := 1;
- CONSTANT c_reg_dp_offload_tx_hdr_dat_nof_words : NATURAL := field_nof_words(c_fn_beamformer_udp_offload_hdr_field_arr, c_word_w); -- = 26 32b words
- CONSTANT c_reg_dp_offload_tx_hdr_dat_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_dat_nof_words); -- = 5
- CONSTANT c_reg_dp_offload_tx_hdr_ovr_nof_words : NATURAL := c_fn_beamformer_udp_offload_hdr_field_arr'LENGTH; -- = 23 override bits; one for each field; each bit in its own 32b register.
- CONSTANT c_reg_dp_offload_tx_hdr_ovr_adr_w : NATURAL := ceil_log2(c_reg_dp_offload_tx_hdr_ovr_nof_words); -- = 5
-
- -- tr_10GbE
- CONSTANT c_reg_tr_10GbE_adr_w : NATURAL := 13;
- CONSTANT c_nof_mdio : NATURAL := 3;
- CONSTANT c_xaui_mosi_addr_w : NATURAL := 9; --2^9 = range of 512 addresses
- CONSTANT c_max_nof_xaui_inst : NATURAL := 4;
- CONSTANT c_reg_tr_xaui_addr_w : NATURAL := ceil_log2(c_max_nof_xaui_inst* pow2(c_xaui_mosi_addr_w)); -- 4* 512 = 2048 addresses -> 11 address bits.
- CONSTANT c_pkt_len : NATURAL := 176; -- Let tr_10GbE FIFO buffer one full packet before releasing it
-
- -- BF offload
- CONSTANT c_hdr_nof_words : NATURAL := c_eth_total_header_nof_words;
+END apertif_unb1_fn_beamformer;
- CONSTANT c_dp_ram_mm_nof_words : NATURAL := c_hdr_nof_words * (c_tse_data_w/c_word_w);
- CONSTANT c_dp_ram_mm_adr_w : NATURAL := ceil_log2(g_bf.nof_bf_units * pow2(ceil_log2(c_dp_ram_mm_nof_words)));
- CONSTANT c_dp_reg_mm_nof_words : NATURAL := 1;
- CONSTANT c_dp_reg_mm_adr_w : NATURAL := ceil_log2(g_bf.nof_bf_units * pow2(ceil_log2(c_dp_reg_mm_nof_words)));
+ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
- CONSTANT c_reg_dp_split_nof_words : NATURAL := 1;
- CONSTANT c_reg_dp_split_adr_w : NATURAL := ceil_log2(g_bf.nof_bf_units * pow2(ceil_log2(c_reg_dp_split_nof_words)));
+ CONSTANT c_use_phy : t_c_unb1_board_use_phy := (1, 1, 1, 0, 0, 0, 0, 1);
+ CONSTANT c_fw_version : t_unb1_board_fw_version := (3, 1); -- firmware version x.y
+ CONSTANT c_tr_mesh : t_c_unb1_board_tr := c_unb1_board_tr_mesh;
- CONSTANT c_reg_dp_pkt_merge_nof_words : NATURAL := 1;
- CONSTANT c_reg_dp_pkt_merge_adr_w : NATURAL := ceil_log2(c_eth_nof_udp_ports * pow2(ceil_log2(c_reg_dp_pkt_merge_nof_words)));
-
-- System
SIGNAL cs_sim : STD_LOGIC;
SIGNAL xo_clk : STD_LOGIC;
+ SIGNAL xo_rst : STD_LOGIC;
SIGNAL xo_rst_n : STD_LOGIC;
SIGNAL cal_clk : STD_LOGIC;
SIGNAL mm_clk : STD_LOGIC;
@@ -175,8 +124,9 @@ ARCHITECTURE str OF fn_beamformer IS
SIGNAL dp_rst : STD_LOGIC;
SIGNAL dp_clk : STD_LOGIC;
SIGNAL dp_pps : STD_LOGIC;
+ SIGNAL sa_rst : STD_LOGIC;
- SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb_nof_chip_w-1 DOWNTO 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
+ SIGNAL this_chip_id : STD_LOGIC_VECTOR(c_unb1_board_nof_chip_w-1 DOWNTO 0); -- [2:0], so range 0-3 for FN and range 4-7 BN
-- PIOs
SIGNAL pout_debug_wave : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);
@@ -191,11 +141,12 @@ ARCHITECTURE str OF fn_beamformer IS
-- Interface: 10GbE
CONSTANT c_nof_10GbE_offload_streams : NATURAL := 1;
+ CONSTANT c_pkt_len : NATURAL := 176; -- Let tr_10GbE FIFO buffer one full packet before releasing it
SIGNAL xaui_tx_arr : t_xaui_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL xaui_rx_arr : t_xaui_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL unb_xaui_tx_arr : t_unb_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
- SIGNAL unb_xaui_rx_arr : t_unb_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_tx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
+ SIGNAL unb_xaui_rx_arr : t_unb1_board_xaui_sl_2arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL mdio_mdc_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL mdio_mdat_in_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0);
SIGNAL mdio_mdat_oen_arr : STD_LOGIC_VECTOR(c_nof_10GbE_offload_streams-1 DOWNTO 0);
@@ -230,8 +181,8 @@ ARCHITECTURE str OF fn_beamformer IS
SIGNAL eth1g_ram_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL eth1g_ram_miso : t_mem_miso;
-- . tr_mesh
- SIGNAL tx_serial_2arr : t_unb_mesh_sl_2arr;
- SIGNAL rx_serial_2arr : t_unb_mesh_sl_2arr;
+ SIGNAL tx_serial_2arr : t_unb1_board_mesh_sl_2arr;
+ SIGNAL rx_serial_2arr : t_unb1_board_mesh_sl_2arr;
-- . tr_nonbonded with diagnostics
SIGNAL reg_tr_nonbonded_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_tr_nonbonded_miso : t_mem_miso;
@@ -281,15 +232,107 @@ ARCHITECTURE str OF fn_beamformer IS
SIGNAL reg_tr_xaui_mosi : t_mem_mosi;
SIGNAL reg_tr_xaui_miso : t_mem_miso;
- SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_nof_mdio-1 DOWNTO 0);
- SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_nof_mdio-1 DOWNTO 0);
+ SIGNAL reg_mdio_mosi_arr : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
+ SIGNAL reg_mdio_miso_arr : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
BEGIN
+ -----------------------------------------------------------------------------
+ -- General control function
+ -----------------------------------------------------------------------------
+ u_ctrl : ENTITY unb1_board_lib.ctrl_unb1_board
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_design_name => g_design_name,
+ g_design_note => g_design_note,
+ g_stamp_date => g_stamp_date,
+ g_stamp_time => g_stamp_time,
+ g_stamp_svn => g_stamp_svn,
+ g_fw_version => c_fw_version,
+ g_mm_clk_freq => c_unb1_board_mm_clk_freq_50M,
+ g_use_phy => c_use_phy,
+ g_udp_offload => TRUE,
+ g_aux => c_unb1_board_aux,
+ g_udp_offload_nof_streams => c_eth_nof_udp_ports
+ )
+ PORT MAP (
+ -- Clock an reset signals
+ cs_sim => cs_sim,
+ xo_clk => xo_clk,
+ xo_rst => xo_rst,
+ xo_rst_n => xo_rst_n,
+
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
+ mm_rst => mm_rst,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ dp_pps => dp_pps,
+ dp_rst_in => dp_rst,
+ dp_clk_in => dp_clk,
+
+ this_chip_id => this_chip_id,
+
+ -- Toggle WDI
+ pout_debug_wave => pout_debug_wave,
+ pout_wdi => pout_wdi,
+ pin_pps => pin_pps,
+
+ -- MM buses
+ -- . Manual WDI override
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
+
+ -- . System_info
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
+
+ -- . UniBoard I2C sensors
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
+
+ -- eth1g
+ eth1g_tse_clk => eth1g_tse_clk, -- 125 MHz from xo_clk PLL in SOPC system
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
+
+ -- eth1g UDP streaming ports to offload BF out
+ udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
+ udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
+
+ -- FPGA pins
+ -- . General
+ CLK => CLK,
+ PPS => PPS,
+ WDI => WDI,
+ INTA => INTA,
+ INTB => INTB,
+ -- . Others
+ VERSION => VERSION,
+ ID => ID,
+ TESTIO => TESTIO,
+ -- . I2C Interface to Sensors
+ sens_sc => sens_sc,
+ sens_sd => sens_sd,
+ -- . 1GbE Control Interface
+ ETH_clk => ETH_clk,
+ ETH_SGIN => ETH_SGIN,
+ ETH_SGOUT => ETH_SGOUT
+ );
+
-----------------------------------------------------------------------------
-- Node function
-----------------------------------------------------------------------------
- u_node_fn_beamformer : ENTITY work.node_fn_beamformer
+ u_node_fn_beamformer : ENTITY work.node_apertif_unb1_fn_beamformer
GENERIC MAP(
g_use_bf => g_use_bf
)
@@ -357,407 +400,17 @@ BEGIN
rx_serial_2arr => rx_serial_2arr
);
- -----------------------------------------------------------------------------
- -- SOPC system
- -----------------------------------------------------------------------------
- u_sopc : ENTITY work.sopc_fn_beamformer
- PORT MAP (
- -- 1) global signals:
- clk_0 => xo_clk, -- PLL reference = 25 MHz from ETH_clk pin
- reset_n => xo_rst_n,
- mm_clk => mm_clk, -- PLL clk[0] = 125 MHz system clock that the NIOS2 and the MM bus run on
- cal_clk => cal_clk, -- PLL clk[1] = 40 MHz calibration clock for the IO reconfiguration
- tse_clk => eth1g_tse_clk, -- PLL clk[2] = 125 MHz dedicated clock for the 1 Gbit Ethernet unit
-
- -- the_altpll_0
- areset_to_the_altpll_0 => '0',
- locked_from_the_altpll_0 => mm_locked,
- phasedone_from_the_altpll_0 => OPEN,
-
- -- the_avs_eth_0
- coe_clk_export_from_the_avs_eth_0 => OPEN,
- coe_reset_export_from_the_avs_eth_0 => eth1g_mm_rst,
- coe_tse_address_export_from_the_avs_eth_0 => eth1g_tse_mosi.address(c_unb_mm_reg_default.reg_tse_adr_w-1 DOWNTO 0),
- coe_tse_write_export_from_the_avs_eth_0 => eth1g_tse_mosi.wr,
- coe_tse_writedata_export_from_the_avs_eth_0 => eth1g_tse_mosi.wrdata(c_word_w-1 DOWNTO 0),
- coe_tse_read_export_from_the_avs_eth_0 => eth1g_tse_mosi.rd,
- coe_tse_readdata_export_to_the_avs_eth_0 => eth1g_tse_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_tse_waitrequest_export_to_the_avs_eth_0 => eth1g_tse_miso.waitrequest,
- coe_reg_address_export_from_the_avs_eth_0 => eth1g_reg_mosi.address(c_unb_mm_reg_default.reg_eth_adr_w-1 DOWNTO 0),
- coe_reg_write_export_from_the_avs_eth_0 => eth1g_reg_mosi.wr,
- coe_reg_writedata_export_from_the_avs_eth_0 => eth1g_reg_mosi.wrdata(c_word_w-1 DOWNTO 0),
- coe_reg_read_export_from_the_avs_eth_0 => eth1g_reg_mosi.rd,
- coe_reg_readdata_export_to_the_avs_eth_0 => eth1g_reg_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_irq_export_to_the_avs_eth_0 => eth1g_reg_interrupt,
- coe_ram_address_export_from_the_avs_eth_0 => eth1g_ram_mosi.address(c_unb_mm_reg_default.ram_eth_adr_w-1 DOWNTO 0),
- coe_ram_write_export_from_the_avs_eth_0 => eth1g_ram_mosi.wr,
- coe_ram_writedata_export_from_the_avs_eth_0 => eth1g_ram_mosi.wrdata(c_word_w-1 DOWNTO 0),
- coe_ram_read_export_from_the_avs_eth_0 => eth1g_ram_mosi.rd,
- coe_ram_readdata_export_to_the_avs_eth_0 => eth1g_ram_miso.rddata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_unb_sens
- coe_address_export_from_the_reg_unb_sens => reg_unb_sens_mosi.address(c_unb_mm_reg_default.reg_unb_sens_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_unb_sens => OPEN,
- coe_read_export_from_the_reg_unb_sens => reg_unb_sens_mosi.rd,
- coe_readdata_export_to_the_reg_unb_sens => reg_unb_sens_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_unb_sens => OPEN,
- coe_write_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wr,
- coe_writedata_export_from_the_reg_unb_sens => reg_unb_sens_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_tr_nonbonded_mesh
- coe_address_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.address(c_unb_mm_reg_default.reg_tr_nonbonded_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_read_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.rd,
- coe_readdata_export_to_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_tr_nonbonded_mesh => OPEN,
- coe_write_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wr,
- coe_writedata_export_from_the_reg_tr_nonbonded_mesh => reg_tr_nonbonded_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_diagnostics_mesh
- coe_address_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.address(c_unb_mm_reg_default.reg_diagnostics_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_read_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.rd,
- coe_readdata_export_to_the_reg_diagnostics_mesh => reg_diagnostics_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_diagnostics_mesh => OPEN,
- coe_write_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wr,
- coe_writedata_export_from_the_reg_diagnostics_mesh => reg_diagnostics_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_diag_data_buffer
- coe_address_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.address(c_unb_mm_reg_default.ram_diag_db_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_ram_diag_data_buffer => OPEN,
- coe_read_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_ram_diag_data_buffer => ram_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_ram_diag_data_buffer => OPEN,
- coe_write_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_ram_diag_data_buffer => ram_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_diag_data_buffer
- coe_address_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.address(c_reg_diag_db_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_diag_data_buffer => OPEN,
- coe_read_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.rd,
- coe_readdata_export_to_the_reg_diag_data_buffer => reg_diag_data_buf_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_diag_data_buffer => OPEN,
- coe_write_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wr,
- coe_writedata_export_from_the_reg_diag_data_buffer => reg_diag_data_buf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_bsn_monitor
- coe_address_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.address(c_unb_mm_reg_default.reg_bsn_monitor_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_bsn_monitor => OPEN,
- coe_read_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.rd,
- coe_readdata_export_to_the_reg_bsn_monitor => reg_bsn_monitor_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_bsn_monitor => OPEN,
- coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
- coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_pio_debug_wave
- out_port_from_the_pio_debug_wave => pout_debug_wave,
-
- -- the_pio_pps
- in_port_to_the_pio_pps => pin_pps,
-
- -- the_pio_system_info: actually a avs_common_mm instance
- coe_clk_export_from_the_pio_system_info => OPEN,
- coe_reset_export_from_the_pio_system_info => OPEN,
- coe_address_export_from_the_pio_system_info => reg_unb_system_info_mosi.address(c_unb_mm_reg_default.reg_unb_system_info_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_pio_system_info => reg_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_pio_system_info => reg_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_pio_system_info => reg_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_pio_system_info => reg_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_rom_system_info
- coe_clk_export_from_the_rom_system_info => OPEN,
- coe_reset_export_from_the_rom_system_info => OPEN,
- coe_address_export_from_the_rom_system_info => rom_unb_system_info_mosi.address(c_unb_mm_reg_default.rom_unb_system_info_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_rom_system_info => rom_unb_system_info_mosi.rd,
- coe_readdata_export_to_the_rom_system_info => rom_unb_system_info_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_rom_system_info => rom_unb_system_info_mosi.wr,
- coe_writedata_export_from_the_rom_system_info => rom_unb_system_info_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_pio_wdi
- out_port_from_the_pio_wdi => pout_wdi,
-
- -- the_reg_wdi: Manual WDI override; causes FPGA reconfiguration if WDI is enabled (g_use_phy).
- coe_clk_export_from_the_reg_wdi => OPEN,
- coe_reset_export_from_the_reg_wdi => OPEN,
- coe_address_export_from_the_reg_wdi => reg_wdi_mosi.address(0),
- coe_read_export_from_the_reg_wdi => reg_wdi_mosi.rd,
- coe_readdata_export_to_the_reg_wdi => reg_wdi_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_wdi => reg_wdi_mosi.wr,
- coe_writedata_export_from_the_reg_wdi => reg_wdi_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_st_sst
- coe_address_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.address(c_ram_st_sst_bf_addr_w-1 DOWNTO 0),
- coe_clk_export_from_the_ram_st_sst => OPEN,
- coe_read_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.rd,
- coe_readdata_export_to_the_ram_st_sst => ram_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_ram_st_sst => OPEN,
- coe_write_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wr,
- coe_writedata_export_from_the_ram_st_sst => ram_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_st_sst
- coe_address_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.address(c_reg_st_sst_bf_addr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_st_sst => OPEN,
- coe_read_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.rd,
- coe_readdata_export_to_the_reg_st_sst => reg_st_sst_bf_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_st_sst => OPEN,
- coe_write_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wr,
- coe_writedata_export_from_the_reg_st_sst => reg_st_sst_bf_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_ss_ss_wide
- coe_address_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.address(c_ram_ss_ss_wide_addr_w-1 DOWNTO 0),
- coe_clk_export_from_the_ram_ss_ss_wide => OPEN,
- coe_read_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.rd,
- coe_readdata_export_to_the_ram_ss_ss_wide => ram_ss_ss_wide_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_ram_ss_ss_wide => OPEN,
- coe_write_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wr,
- coe_writedata_export_from_the_ram_ss_ss_wide => ram_ss_ss_wide_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_bf_weights
- coe_address_export_from_the_ram_bf_weights => ram_bf_weights_mosi.address(c_ram_bf_weights_addr_w-1 DOWNTO 0),
- coe_clk_export_from_the_ram_bf_weights => OPEN,
- coe_read_export_from_the_ram_bf_weights => ram_bf_weights_mosi.rd,
- coe_readdata_export_to_the_ram_bf_weights => ram_bf_weights_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_ram_bf_weights => OPEN,
- coe_write_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wr,
- coe_writedata_export_from_the_ram_bf_weights => ram_bf_weights_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_bg_diag_bg
- coe_address_export_from_the_reg_diag_bg => reg_diag_bg_mosi.address(c_reg_diag_bg_addr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_diag_bg => OPEN,
- coe_read_export_from_the_reg_diag_bg => reg_diag_bg_mosi.rd,
- coe_readdata_export_to_the_reg_diag_bg => reg_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_diag_bg => OPEN,
- coe_write_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wr,
- coe_writedata_export_from_the_reg_diag_bg => reg_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_diag_bg
- coe_address_export_from_the_ram_diag_bg => ram_diag_bg_mosi.address(c_ram_diag_bg_addr_w-1 DOWNTO 0),
- coe_clk_export_from_the_ram_diag_bg => OPEN,
- coe_read_export_from_the_ram_diag_bg => ram_diag_bg_mosi.rd,
- coe_readdata_export_to_the_ram_diag_bg => ram_diag_bg_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_ram_diag_bg => OPEN,
- coe_write_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wr,
- coe_writedata_export_from_the_ram_diag_bg => ram_diag_bg_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_ram_from_mm
- coe_clk_export_from_the_reg_dp_ram_from_mm => OPEN,
- coe_reset_export_from_the_reg_dp_ram_from_mm => OPEN,
- coe_address_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.address(c_dp_reg_mm_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.rd,
- coe_readdata_export_to_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wr,
- coe_writedata_export_from_the_reg_dp_ram_from_mm => reg_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_ram_dp_ram_from_mm
- coe_clk_export_from_the_ram_dp_ram_from_mm => OPEN,
- coe_reset_export_from_the_ram_dp_ram_from_mm => OPEN,
- coe_address_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.address(c_dp_ram_mm_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.rd,
- coe_readdata_export_to_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wr,
- coe_writedata_export_from_the_ram_dp_ram_from_mm => ram_dp_ram_from_mm_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_split
- coe_clk_export_from_the_reg_dp_split => OPEN,
- coe_reset_export_from_the_reg_dp_split => OPEN,
- coe_address_export_from_the_reg_dp_split => reg_dp_split_mosi.address(c_reg_dp_split_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_dp_split => reg_dp_split_mosi.rd,
- coe_readdata_export_to_the_reg_dp_split => reg_dp_split_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_dp_split => reg_dp_split_mosi.wr,
- coe_writedata_export_from_the_reg_dp_split => reg_dp_split_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_pkt_merge
- coe_clk_export_from_the_reg_dp_pkt_merge => OPEN,
- coe_reset_export_from_the_reg_dp_pkt_merge => OPEN,
- coe_address_export_from_the_reg_dp_pkt_merge => reg_dp_pkt_merge_mosi.address(c_reg_dp_pkt_merge_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_dp_pkt_merge => reg_dp_pkt_merge_mosi.rd,
- coe_readdata_export_to_the_reg_dp_pkt_merge => reg_dp_pkt_merge_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_dp_pkt_merge => reg_dp_pkt_merge_mosi.wr,
- coe_writedata_export_from_the_reg_dp_pkt_merge => reg_dp_pkt_merge_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx
- coe_address_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.address(0),
- coe_clk_export_from_the_reg_dp_offload_tx => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx => reg_dp_offload_tx_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_dp_offload_tx => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx => reg_dp_offload_tx_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx_hdr_dat
- coe_address_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.address(c_reg_dp_offload_tx_hdr_dat_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_dp_offload_tx_hdr_dat => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx_hdr_dat => reg_dp_offload_tx_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_dp_offload_tx_hdr_ovr
- coe_address_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.address(c_reg_dp_offload_tx_hdr_ovr_adr_w-1 DOWNTO 0),
- coe_clk_export_from_the_reg_dp_offload_tx_hdr_ovr => OPEN,
- coe_read_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.rd,
- coe_readdata_export_to_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_reset_export_from_the_reg_dp_offload_tx_hdr_ovr => OPEN,
- coe_write_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.wr,
- coe_writedata_export_from_the_reg_dp_offload_tx_hdr_ovr => reg_dp_offload_tx_hdr_ovr_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_tr_10GbE
- coe_clk_export_from_the_reg_tr_10GbE => OPEN,
- coe_reset_export_from_the_reg_tr_10GbE => OPEN,
- coe_address_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.address(c_reg_tr_10GbE_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.rd,
- coe_readdata_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_waitrequest_export_to_the_reg_tr_10GbE => reg_tr_10GbE_miso.waitrequest,
- coe_write_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wr,
- coe_writedata_export_from_the_reg_tr_10GbE => reg_tr_10GbE_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_mdio_0
- coe_clk_export_from_the_reg_mdio_0 => OPEN,
- coe_reset_export_from_the_reg_mdio_0 => OPEN,
- coe_address_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).address(c_unb_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).rd,
- coe_readdata_export_to_the_reg_mdio_0 => reg_mdio_miso_arr(0).rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).wr,
- coe_writedata_export_from_the_reg_mdio_0 => reg_mdio_mosi_arr(0).wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_mdio_1
- coe_clk_export_from_the_reg_mdio_1 => OPEN,
- coe_reset_export_from_the_reg_mdio_1 => OPEN,
- coe_address_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).address(c_unb_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).rd,
- coe_readdata_export_to_the_reg_mdio_1 => reg_mdio_miso_arr(1).rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).wr,
- coe_writedata_export_from_the_reg_mdio_1 => reg_mdio_mosi_arr(1).wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_mdio_2
- coe_clk_export_from_the_reg_mdio_2 => OPEN,
- coe_reset_export_from_the_reg_mdio_2 => OPEN,
- coe_address_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).address(c_unb_mm_reg_default.reg_mdio_adr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).rd,
- coe_readdata_export_to_the_reg_mdio_2 => reg_mdio_miso_arr(2).rddata(c_word_w-1 DOWNTO 0),
- coe_write_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).wr,
- coe_writedata_export_from_the_reg_mdio_2 => reg_mdio_mosi_arr(2).wrdata(c_word_w-1 DOWNTO 0),
-
- -- the_reg_tr_xaui
- coe_clk_export_from_the_reg_tr_xaui => OPEN,
- coe_reset_export_from_the_reg_tr_xaui => OPEN,
- coe_address_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.address(c_reg_tr_xaui_addr_w-1 DOWNTO 0),
- coe_read_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.rd,
- coe_readdata_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.rddata(c_word_w-1 DOWNTO 0),
- coe_waitrequest_export_to_the_reg_tr_xaui => reg_tr_xaui_miso.waitrequest,
- coe_write_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wr,
- coe_writedata_export_from_the_reg_tr_xaui => reg_tr_xaui_mosi.wrdata(c_word_w-1 DOWNTO 0)
- );
-
- -----------------------------------------------------------------------------
- -- General control function
- -----------------------------------------------------------------------------
- u_ctrl : ENTITY unb_common_lib.ctrl_unb_common
- GENERIC MAP (
- -- General
- g_design_name => g_design_name,
- g_stamp_date => g_stamp_date,
- g_stamp_time => g_stamp_time,
- g_stamp_svn => g_stamp_svn,
- g_design_note => g_design_note,
- g_fw_version => g_fw_version,
- -- Use PHY Interface
- g_use_phy => g_use_phy,
- -- Auxiliary Interface
- g_aux => g_aux,
- -- Offload BF out(0)
- g_udp_offload => TRUE
- )
- PORT MAP (
- --
- -- >>> SOPC system with conduit peripheral MM bus
- --
- -- System
- cs_sim => cs_sim,
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
- mm_rst => mm_rst,
-
- dp_rst => dp_rst,
- dp_clk => dp_clk,
- dp_pps => dp_pps,
- dp_rst_in => dp_rst,
- dp_clk_in => dp_clk,
-
- this_chip_id => this_chip_id,
-
- -- PIOs
- pout_debug_wave => pout_debug_wave,
- pout_wdi => pout_wdi,
- pin_pps => pin_pps,
-
- -- System_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
-
- -- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
-
- -- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
-
- -- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
-
- -- eth1g UDP streaming ports to offload BF out
- udp_tx_sosi_arr => eth1g_udp_tx_sosi_arr,
- udp_tx_siso_arr => eth1g_udp_tx_siso_arr,
-
- --
- -- >>> Ctrl FPGA pins
- --
- -- General
- CLK => CLK,
- PPS => PPS,
- WDI => WDI,
- INTA => INTA,
- INTB => INTB,
-
- -- Others
- VERSION => VERSION,
- ID => ID,
- TESTIO => TESTIO,
-
- -- I2C Interface to Sensors
- sens_sc => sens_sc,
- sens_sd => sens_sd,
-
- ETH_clk => ETH_clk,
- ETH_SGIN => ETH_SGIN,
- ETH_SGOUT => ETH_SGOUT
- );
-
-----------------------------------------------------------------------------
-- Mesh I/O
-----------------------------------------------------------------------------
- no_tr_mesh : IF g_use_phy.tr_mesh=0 GENERATE
+ no_tr_mesh : IF c_use_phy.tr_mesh=0 GENERATE
rx_serial_2arr <= (OTHERS=>(OTHERS=>'0'));
END GENERATE;
- gen_tr_mesh : IF g_use_phy.tr_mesh/=0 GENERATE
- u_mesh_io : ENTITY unb_common_lib.unb_mesh_io
+ gen_tr_mesh : IF c_use_phy.tr_mesh/=0 GENERATE
+ u_mesh_io : ENTITY unb1_board_lib.unb1_board_mesh_io
GENERIC MAP (
- g_bus_w => g_tr_mesh.bus_w
+ g_bus_w => c_tr_mesh.bus_w
)
PORT MAP (
tx_serial_2arr => tx_serial_2arr,
@@ -778,42 +431,65 @@ BEGIN
-----------------------------------------------------------------------------
-- Interface : 10GbE
-----------------------------------------------------------------------------
+ u_areset_sa_rst : ENTITY common_lib.common_areset
+ GENERIC MAP(
+ g_rst_level => '1',
+ g_delay_len => 4
+ )
+ PORT MAP(
+ clk => SA_CLK,
+ in_rst => '0',
+ out_rst => sa_rst
+ );
+
u_tr_10GbE: ENTITY tr_10GbE_lib.tr_10GbE
GENERIC MAP(
- g_sim => g_sim,
- g_sim_level => 0,
- g_nof_macs => c_nof_10GbE_offload_streams,
- g_use_mdio => TRUE,
- g_pkt_len => c_pkt_len
+ g_sim => g_sim,
+ g_sim_level => 0,
+ g_nof_macs => c_nof_10GbE_offload_streams,
+ g_use_mdio => TRUE,
+ g_tx_fifo_fill => c_pkt_len,
+ g_tx_fifo_size => 2*c_pkt_len,
+ g_rx_fifo_size => 2*c_pkt_len
)
- PORT MAP (
- mm_rst => mm_rst,
- mm_clk => mm_clk,
+
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => SA_CLK,
+ tr_ref_rst_156 => sa_rst,
- tr_clk => SA_CLK,
+ -- Calibration & reconfig clock
+ cal_rec_clk => mm_clk, --cal_clk, # required for XAUI
+
+ -- MM interface
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
- cal_rec_clk => mm_clk, --cal_clk, # required for XAUI
+ reg_mac_mosi => reg_tr_10GbE_mosi,
+ reg_mac_miso => reg_tr_10GbE_miso,
- dp_rst => dp_rst,
- dp_clk => dp_clk,
+ xaui_mosi => reg_tr_xaui_mosi,
+ xaui_miso => reg_tr_xaui_miso,
- snk_out_arr => dp_offload_tx_src_in_arr,
- snk_in_arr => dp_offload_tx_src_out_arr,
+ mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
+ mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
- reg_mac_mosi => reg_tr_10GbE_mosi,
- reg_mac_miso => reg_tr_10GbE_miso,
- xaui_mosi => reg_tr_xaui_mosi,
- xaui_miso => reg_tr_xaui_miso,
- mdio_mosi_arr => reg_mdio_mosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
- mdio_miso_arr => reg_mdio_miso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0),
+ -- DP interface
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
- xaui_tx_out_arr => xaui_tx_arr,
- xaui_rx_in_arr => xaui_rx_arr,
+ snk_out_arr => dp_offload_tx_src_in_arr,
+ snk_in_arr => dp_offload_tx_src_out_arr,
- mdio_rst => SI_FN_RSTN,
- mdio_mdc_arr => mdio_mdc_arr,
- mdio_mdat_in_arr => mdio_mdat_in_arr,
- mdio_mdat_oen_arr => mdio_mdat_oen_arr
+ -- Serial XAUI IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr,
+
+ -- MDIO interface
+ mdio_rst => SI_FN_RSTN,
+ mdio_mdc_arr => mdio_mdc_arr,
+ mdio_mdat_in_arr => mdio_mdat_in_arr,
+ mdio_mdat_oen_arr => mdio_mdat_oen_arr
);
-- Wire together different types
@@ -822,7 +498,7 @@ BEGIN
xaui_rx_arr(i) <= unb_xaui_rx_arr(i);
END GENERATE;
- u_front_io : ENTITY unb_common_lib.unb_front_io
+ u_front_io : ENTITY unb1_board_lib.unb1_board_front_io
GENERIC MAP (
g_nof_xaui => c_nof_10GbE_offload_streams
)
@@ -851,7 +527,7 @@ BEGIN
-----------------------------------------------------------------------------
-- DP offload TX : BF out -> 10GbE
-----------------------------------------------------------------------------
- u_fn_beamformer_udp_offload : ENTITY work.fn_beamformer_udp_offload
+ u_fn_beamformer_udp_offload : ENTITY work.apertif_unb1_fn_beamformer_udp_offload
PORT MAP (
mm_rst => mm_rst,
mm_clk => mm_clk,
@@ -873,8 +549,7 @@ BEGIN
reg_dp_offload_tx_hdr_ovr_mosi => reg_dp_offload_tx_hdr_ovr_mosi,
reg_dp_offload_tx_hdr_ovr_miso => reg_dp_offload_tx_hdr_ovr_miso
);
-
-
+
END;
diff --git a/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd b/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
index 5127be33e7..c9317b9bc0 100644
--- a/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
+++ b/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload.vhd
@@ -26,36 +26,38 @@
-- because the same header field definition is also used by dp_offload_rx in
-- design apertif_fn_qdcor.
-LIBRARY IEEE, common_lib, work, mm_lib, unb_common_lib, tse_lib, dp_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, tech_tse_lib, dp_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
-USE unb_common_lib.unb_common_pkg.ALL;
-USE tse_lib.tse_pkg.ALL;
-USE tse_lib.eth_layers_pkg.ALL;
-USE tse_lib.eth_pkg.ALL;
-USE work.fn_beamformer_udp_offload_pkg.ALL;
+USE common_lib.common_network_layers_pkg.ALL;
+USE common_lib.common_network_total_header_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.apertif_unb1_fn_beamformer_udp_offload_pkg.ALL;
-ENTITY fn_beamformer_udp_offload IS
+ENTITY apertif_unb1_fn_beamformer_udp_offload IS
PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
-
- dp_rst : IN STD_LOGIC;
- dp_clk : IN STD_LOGIC;
-
- snk_in_arr : IN t_dp_sosi_arr(3 DOWNTO 0); -- 4 BF unit outputs
-
- src_out_arr : OUT t_dp_sosi_arr(0 DOWNTO 0);
- src_in_arr : IN t_dp_siso_arr(0 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
-
- ID : IN STD_LOGIC_VECTOR(c_unb_aux.id_w-1 DOWNTO 0);
-
- reg_dp_offload_tx_mosi : IN t_mem_mosi := c_mem_mosi_rst;
- reg_dp_offload_tx_miso : OUT t_mem_miso := c_mem_miso_rst;
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+
+ dp_rst : IN STD_LOGIC;
+ dp_clk : IN STD_LOGIC;
+
+ snk_in_arr : IN t_dp_sosi_arr(3 DOWNTO 0); -- 4 BF unit outputs
+
+ src_out_arr : OUT t_dp_sosi_arr(0 DOWNTO 0);
+ src_in_arr : IN t_dp_siso_arr(0 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy);
+
+ ID : IN STD_LOGIC_VECTOR(c_unb1_board_aux.id_w-1 DOWNTO 0);
+
+ reg_dp_offload_tx_mosi : IN t_mem_mosi := c_mem_mosi_rst;
+ reg_dp_offload_tx_miso : OUT t_mem_miso := c_mem_miso_rst;
reg_dp_offload_tx_hdr_dat_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_dp_offload_tx_hdr_dat_miso : OUT t_mem_miso := c_mem_miso_rst;
@@ -63,25 +65,25 @@ ENTITY fn_beamformer_udp_offload IS
reg_dp_offload_tx_hdr_ovr_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_dp_offload_tx_hdr_ovr_miso : OUT t_mem_miso := c_mem_miso_rst
);
-END fn_beamformer_udp_offload;
+END apertif_unb1_fn_beamformer_udp_offload;
-ARCHITECTURE wrap OF fn_beamformer_udp_offload IS
+ARCHITECTURE wrap OF apertif_unb1_fn_beamformer_udp_offload IS
CONSTANT c_nof_offload_streams : NATURAL := 1;
-- Override ('1') only the Ethernet fields so we can use MM defaults there.
- CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_fn_beamformer_udp_offload_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111101"&"0011"&"100";
+ CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_apertif_unb1_fn_beamformer_udp_offload_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111101"&"0011"&"100";
CONSTANT c_bf_out_compl_dat_w : NATURAL := 8;
CONSTANT c_data_w : NATURAL := 64; -- 4 BF units * 8b complex
- CONSTANT c_header_overhead_bytes : NATURAL := field_slv_out_len(c_fn_beamformer_udp_offload_hdr_field_arr) / c_byte_w;
+ CONSTANT c_header_overhead_bytes : NATURAL := field_slv_out_len(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr) / c_byte_w;
CONSTANT c_max_frame_len : NATURAL := 9018;
CONSTANT c_frame_nof_words : NATURAL := (c_max_frame_len * c_byte_w ) / c_data_w;
- CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len-c_header_overhead_bytes-c_eth_crc_len;
+ CONSTANT c_max_udp_payload_len : NATURAL := c_max_frame_len - c_header_overhead_bytes - c_network_eth_crc_len;
CONSTANT c_max_udp_payload_nof_words : NATURAL := (c_max_udp_payload_len * c_byte_w) / c_data_w;
CONSTANT c_max_nof_words_per_block : NATURAL := 256;
@@ -127,7 +129,7 @@ BEGIN
g_max_nof_blocks_per_packet => c_max_nof_blocks_per_packet,
g_def_nof_blocks_per_packet => c_def_nof_blocks_per_packet,
g_output_fifo_depth => c_frame_nof_words,
- g_hdr_field_arr => c_fn_beamformer_udp_offload_hdr_field_arr,
+ g_hdr_field_arr => c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr,
g_hdr_field_ovr_init => c_hdr_field_ovr_init
)
PORT MAP (
@@ -165,13 +167,13 @@ BEGIN
-- Wire the hardwired header fields to DP signals and ID
---------------------------------------------------------------------------------------
gen_slv_hard_fields : FOR i IN 0 TO c_nof_offload_streams-1 GENERATE
- hdr_fields_in_arr(i)(field_hi(c_fn_beamformer_udp_offload_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_fn_beamformer_udp_offload_hdr_field_arr, "eth_src_mac" )) <= x"00228608" & id_backplane & id_chip;
- hdr_fields_in_arr(i)(field_hi(c_fn_beamformer_udp_offload_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_fn_beamformer_udp_offload_hdr_field_arr, "udp_src_port" )) <= x"D0" & ID;
- hdr_fields_in_arr(i)(field_hi(c_fn_beamformer_udp_offload_hdr_field_arr, "udp_dst_port" ) DOWNTO field_lo(c_fn_beamformer_udp_offload_hdr_field_arr, "udp_dst_port" )) <= x"D0" & ID;
- hdr_fields_in_arr(i)(field_hi(c_fn_beamformer_udp_offload_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_fn_beamformer_udp_offload_hdr_field_arr, "ip_src_addr" )) <= x"0A63" & id_backplane & INCR_UVEC(id_chip, 1);
+ hdr_fields_in_arr(i)(field_hi(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "eth_src_mac" )) <= x"00228608" & id_backplane & id_chip;
+ hdr_fields_in_arr(i)(field_hi(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "udp_src_port" )) <= x"D0" & ID;
+ hdr_fields_in_arr(i)(field_hi(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "udp_dst_port" ) DOWNTO field_lo(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "udp_dst_port" )) <= x"D0" & ID;
+ hdr_fields_in_arr(i)(field_hi(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "ip_src_addr" )) <= x"0A63" & id_backplane & INCR_UVEC(id_chip, 1);
- hdr_fields_in_arr(i)(field_hi(c_fn_beamformer_udp_offload_hdr_field_arr, "dp_sync" ) DOWNTO field_lo(c_fn_beamformer_udp_offload_hdr_field_arr, "dp_sync" )) <= slv(dp_offload_tx_snk_in_arr(i).sync);
- hdr_fields_in_arr(i)(field_hi(c_fn_beamformer_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_fn_beamformer_udp_offload_hdr_field_arr, "dp_bsn" )) <= dp_offload_tx_snk_in_arr(i).bsn(63 DOWNTO 0);
+ hdr_fields_in_arr(i)(field_hi(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "dp_sync" ) DOWNTO field_lo(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "dp_sync" )) <= slv(dp_offload_tx_snk_in_arr(i).sync);
+ hdr_fields_in_arr(i)(field_hi(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "dp_bsn" ) DOWNTO field_lo(c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr, "dp_bsn" )) <= dp_offload_tx_snk_in_arr(i).bsn(63 DOWNTO 0);
END GENERATE;
END wrap;
diff --git a/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload_pkg.vhd b/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload_pkg.vhd
index 4317253534..4d9d8349f1 100644
--- a/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload_pkg.vhd
+++ b/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer_udp_offload_pkg.vhd
@@ -25,37 +25,37 @@ USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_field_pkg.ALL;
-PACKAGE fn_beamformer_udp_offload_pkg IS
+PACKAGE apertif_unb1_fn_beamformer_udp_offload_pkg IS
- CONSTANT c_fn_beamformer_udp_offload_nof_hdr_fields : NATURAL := 3+12+4+3; -- 448b; 7 64b words
+ CONSTANT c_apertif_unb1_fn_beamformer_udp_offload_nof_hdr_fields : NATURAL := 3+12+4+3; -- 448b; 7 64b words
-- Notes:
-- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10
-- . Default ip_total_length and udp_total_length valid for 188 beamlets * 64b
- CONSTANT c_fn_beamformer_udp_offload_hdr_field_arr : t_common_field_arr(c_fn_beamformer_udp_offload_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"AABBCCDDEEFF") ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
- ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
- ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
- ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
- ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1546) ),
- ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
- ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
- ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
- ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
- ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
- ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(55147) ),
- ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
- ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"0A0A0A0A") ),
- ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
- ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1526) ),
- ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
- ( field_name_pad("dp_reserved" ), "RW", 47, field_default(0) ),
- ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
- ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) );
+ CONSTANT c_apertif_unb1_fn_beamformer_udp_offload_hdr_field_arr : t_common_field_arr(c_apertif_unb1_fn_beamformer_udp_offload_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"AABBCCDDEEFF") ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
+ ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ),
+ ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ),
+ ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ),
+ ( field_name_pad("ip_total_length" ), "RW", 16, field_default(1546) ),
+ ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ),
+ ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ),
+ ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ),
+ ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ),
+ ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(55147) ),
+ ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"0A0A0A0A") ),
+ ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("udp_total_length" ), "RW", 16, field_default(1526) ),
+ ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ),
+ ( field_name_pad("dp_reserved" ), "RW", 47, field_default(0) ),
+ ( field_name_pad("dp_sync" ), "RW", 1, field_default(0) ),
+ ( field_name_pad("dp_bsn" ), "RW", 64, field_default(0) ) );
-END fn_beamformer_udp_offload_pkg;
+END apertif_unb1_fn_beamformer_udp_offload_pkg;
-PACKAGE BODY fn_beamformer_udp_offload_pkg IS
-END fn_beamformer_udp_offload_pkg;
+PACKAGE BODY apertif_unb1_fn_beamformer_udp_offload_pkg IS
+END apertif_unb1_fn_beamformer_udp_offload_pkg;
diff --git a/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/node_apertif_unb1_fn_beamformer.vhd b/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/node_apertif_unb1_fn_beamformer.vhd
index 85d2097889..58e7487da1 100644
--- a/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/node_apertif_unb1_fn_beamformer.vhd
+++ b/applications/apertif/apertif_unb1_fn_beamformer/src/vhdl/node_apertif_unb1_fn_beamformer.vhd
@@ -19,20 +19,20 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, dp_lib, bf_lib, unb_common_lib, tse_lib, diag_lib, fn_bf_lib, fn_terminal_db_lib;
+LIBRARY IEEE, common_lib, unb1_board_lib, eth_lib, tech_tse_lib, dp_lib, bf_lib, unb1_fn_bf_lib, unb1_fn_terminal_db_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE unb1_board_lib.unb1_board_pkg.ALL;
+USE unb1_board_lib.unb1_board_peripherals_pkg.ALL;
+USE eth_lib.eth_pkg.ALL;
+USE tech_tse_lib.tech_tse_pkg.ALL;
+USE tech_tse_lib.tb_tech_tse_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE bf_lib.bf_pkg.ALL;
-USE tse_lib.tse_pkg.ALL;
-USE unb_common_lib.unb_common_pkg.ALL;
-USE tse_lib.eth_layers_pkg.ALL;
-USE tse_lib.eth_pkg.ALL;
-b
-hdl_lib_uses = common technology m
-ENTITY node_fn_beamformer IS
+
+ENTITY node_apertif_unb1_fn_beamformer IS
GENERIC(
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0;
@@ -42,16 +42,14 @@ ENTITY node_fn_beamformer IS
g_use_block_gen : BOOLEAN := FALSE; -- TRUE overrides terminal output and feeds BG output to the BF instead.
-- Stream properties
g_nof_streams : NATURAL := 16;
--- g_data_w : NATURAL := 32;
g_bf : t_c_bf := c_bf;
- g_bf_weights_file_name : STRING := "../../../../../dsp/bf/build/data/weights"; -- default file location for synthesis
+ g_bf_weights_file_name : STRING := "../../../../../dsp/bf/build/data/weights" -- default file location for synthesis
-- Auxiliary Interface
- g_aux : t_c_unb_aux := c_unb_aux
);
PORT(
-- System
- chip_id : IN STD_LOGIC_VECTOR(g_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
+ chip_id : IN STD_LOGIC_VECTOR(c_unb1_board_aux.chip_id_w-1 DOWNTO 0); -- [2:0]
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC; -- 50 MHz from xo_clk PLL in SOPC system
@@ -108,12 +106,12 @@ ENTITY node_fn_beamformer IS
-- Mesh interface level
-- . Serial (tr_nonbonded)
- tx_serial_2arr : OUT t_unb_mesh_sl_2arr; -- Tx
- rx_serial_2arr : IN t_unb_mesh_sl_2arr:= (OTHERS=>(OTHERS=>'0')) -- Rx support for diagnostics
+ tx_serial_2arr : OUT t_unb1_board_mesh_sl_2arr; -- Tx
+ rx_serial_2arr : IN t_unb1_board_mesh_sl_2arr:= (OTHERS=>(OTHERS=>'0')) -- Rx support for diagnostics
);
-END node_fn_beamformer;
+END node_apertif_unb1_fn_beamformer;
-ARCHITECTURE str OF node_fn_beamformer IS
+ARCHITECTURE str OF node_apertif_unb1_fn_beamformer IS
CONSTANT c_weights_write_only : BOOLEAN := TRUE;
-- Use default RAM init files. The RAM init file for simulation lies one ../ level further way then for synthesis
@@ -131,7 +129,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Node function: Beam Former + BF UDP offload + block generator
-----------------------------------------------------------------------------
- u_node_fn_bf : ENTITY fn_bf_lib.node_fn_bf
+ u_node_fn_bf : ENTITY unb1_fn_bf_lib.node_unb1_fn_bf
GENERIC MAP(
g_bf => c_bf,
g_bf_offload => g_use_bf_offload,
@@ -191,7 +189,7 @@ BEGIN
-----------------------------------------------------------------------------
-- Node function: Terminals + data buffer
-----------------------------------------------------------------------------
- u_node_fn_terminal_db : ENTITY fn_terminal_db_lib.node_fn_terminal_db
+ u_node_fn_terminal_db : ENTITY unb1_fn_terminal_db_lib.node_unb1_fn_terminal_db
GENERIC MAP(
g_sim => g_sim,
g_sim_level => g_sim_level,
@@ -199,7 +197,7 @@ BEGIN
-- Terminals interface
g_multi_unb => TRUE,
-- Auxiliary Interface
- g_aux => c_unb_aux
+ g_aux => c_unb1_board_aux
)
PORT MAP(
-- System
--
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