diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index 3cbebfeac2ec96c169dc8c842e7c9ab36b815113..5bacbf6f914899367355baa0d73ea57d7eb6522b 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -162,6 +162,7 @@ BEGIN
u_ctrl : ENTITY unb2_board_lib.ctrl_unb2_board
GENERIC MAP (
g_sim => g_sim,
+ g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
index 59d59ffb0e76b0d35e77e15bfbcda5aceb615ba2..6fd8be0f5ec1eb3e958b02be83cd5e35db5f54d9 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
@@ -20,7 +20,7 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2_board_lib, dp_lib, eth_lib, diag_lib;
+LIBRARY IEEE, common_lib, technology_lib, unb2_board_lib, dp_lib, eth_lib, diag_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -33,10 +33,12 @@ USE unb2_board_lib.unb2_board_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
USE work.unb2_test_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
ENTITY udp_stream IS
GENERIC (
g_sim : BOOLEAN := FALSE;
+ g_technology : NATURAL := c_tech_select_default;
g_nof_streams : NATURAL;
g_data_w : NATURAL;
@@ -156,6 +158,7 @@ BEGIN
-----------------------------------------------------------------------------
u_mms_diag_block_gen: ENTITY diag_lib.mms_diag_block_gen
GENERIC MAP (
+ g_technology => g_technology,
g_nof_streams => g_nof_streams,
g_buf_dat_w => g_data_w,
g_buf_addr_w => ceil_log2(TO_UINT(c_bg_ctrl.samples_per_packet)),
@@ -185,6 +188,7 @@ BEGIN
gen_dp_fifo_sc : FOR i IN 0 TO g_nof_streams-1 GENERATE --FIXME : Daniel: we also need this fifo to pass on the BSN (47b) and sync (1b); set generics accordingly
u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
GENERIC MAP (
+ g_technology => g_technology,
g_data_w => g_data_w,
g_bsn_w => 47,
g_use_bsn => TRUE,
@@ -209,6 +213,7 @@ BEGIN
-----------------------------------------------------------------------------
u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx
GENERIC MAP (
+ g_technology => g_technology,
g_nof_streams => g_nof_streams,
g_data_w => g_data_w,
g_use_complex => FALSE,
@@ -324,6 +329,7 @@ BEGIN
u_diag_data_buffer : ENTITY diag_lib.mms_diag_data_buffer
GENERIC MAP (
+ g_technology => g_technology,
g_nof_streams => g_nof_streams,
g_data_w => 32, --g_data_w, --FIXME
g_buf_nof_data => 1024,
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index 710123c2af85602ca0d100eb359f65889326da25..d379bf61174d53bd71c176f7cbb0d2f2858b06b4 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -438,6 +438,7 @@ BEGIN
u_ctrl : ENTITY unb2_board_lib.ctrl_unb2_board
GENERIC MAP (
g_sim => g_sim,
+ g_technology => g_technology,
g_design_name => g_design_name,
g_design_note => g_design_note,
g_stamp_date => g_stamp_date,
@@ -752,6 +753,7 @@ BEGIN
u_udp_stream_1GbE : ENTITY work.udp_stream
GENERIC MAP (
g_sim => g_sim,
+ g_technology => g_technology,
g_nof_streams => c_nof_streams_1GbE,
g_data_w => c_data_w_32,
g_bg_block_size => c_def_1GbE_block_size,
@@ -825,6 +827,7 @@ BEGIN
u_udp_stream_10GbE : ENTITY work.udp_stream
GENERIC MAP (
g_sim => g_sim,
+ g_technology => g_technology,
g_nof_streams => c_nof_streams_qsfp + c_nof_streams_ring + c_nof_streams_back0 + c_nof_streams_back1,
g_data_w => c_data_w_64,
g_bg_block_size => c_bg_block_size,
@@ -868,9 +871,9 @@ BEGIN
u_tr_10GbE_qsfp_and_ring: ENTITY unb2_board_lib.unb2_board_10gbe -- QSFP and Ring lines
GENERIC MAP (
- g_technology => g_technology,
g_sim => g_sim,
g_sim_level => 1,
+ g_technology => g_technology,
g_nof_macs => c_nof_streams_qsfp + c_nof_streams_ring,
g_tx_fifo_fill => c_def_10GbE_block_size,
g_tx_fifo_size => c_def_10GbE_block_size*2
@@ -962,9 +965,9 @@ BEGIN
-- u_tr_10GbE_back: ENTITY unb2_board_lib.unb2_board_10gbe -- BACK lines
-- GENERIC MAP (
--- g_technology => g_technology,
-- g_sim => g_sim,
-- g_sim_level => 1,
+-- g_technology => g_technology,
-- g_nof_macs => c_nof_streams_back0,
-- g_tx_fifo_fill => c_def_10GbE_block_size,
-- g_tx_fifo_size => c_def_10GbE_block_size*2
@@ -1023,10 +1026,6 @@ BEGIN
-- );
-
-
-
-
u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
@@ -1067,6 +1066,7 @@ BEGIN
red_led_arr => qsfp_red_led_arr,
QSFP_LED => QSFP_LED
);
+
u_front_led : ENTITY unb2_board_lib.unb2_board_qsfp_leds
GENERIC MAP (
g_sim => g_sim,
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index fb88b3d556d06b088cf16ff6dea4f0ca6b047878..51dc1feb84e8eccb4d9e618a66050c23955e8f13 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -486,6 +486,7 @@ BEGIN
u_mms_unb2_board_system_info : ENTITY work.mms_unb2_board_system_info
GENERIC MAP (
g_sim => g_sim,
+ g_technology => g_technology,
g_design_name => g_design_name,
g_fw_version => g_fw_version,
g_stamp_date => g_stamp_date,
@@ -629,6 +630,7 @@ BEGIN
u_mms_ppsh : ENTITY ppsh_lib.mms_ppsh
GENERIC MAP (
+ g_technology => g_technology,
g_st_clk_freq => g_dp_clk_freq
)
PORT MAP (
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
index 8b67b4b6d702f7c810b1dbd41b68514c6ac60e0a..7e70d05b559657793da91a2be966549d49b55ed6 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -19,15 +19,17 @@
--
-------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, common_lib, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.unb2_board_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
ENTITY mms_unb2_board_system_info IS
GENERIC (
g_sim : BOOLEAN := FALSE;
+ g_technology : NATURAL := c_tech_arria10;
g_design_name : STRING;
g_fw_version : t_unb2_board_fw_version := c_unb2_board_fw_version; -- firmware version x.y
g_stamp_date : NATURAL := 0;
@@ -119,6 +121,7 @@ BEGIN
u_common_rom : ENTITY common_lib.common_rom
GENERIC MAP (
+ g_technology => g_technology,
g_ram => c_mm_rom,
g_init_file => c_mif_name
)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
index 2f2c4d9d581056ee7af8841887804039939d8dc5..96ae8dc74dd007749a9ceafa6f9b081e45e2085e 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -22,17 +22,18 @@
-- Purpose : MMS for unb2_fpga_sens
-- Description: See unb2_fpga_sens.vhd
-LIBRARY IEEE, common_lib;
+LIBRARY IEEE, technology_lib, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
ENTITY mms_unb2_fpga_sens IS
GENERIC (
g_sim : BOOLEAN := FALSE;
- g_technology : NATURAL;
+ g_technology : NATURAL := c_tech_arria10;
g_temp_high : NATURAL := 85
);
PORT (
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_10gbe.vhd
index b0108aa9f11a8b852d0040e4b9b55b3eeb54f942..0e20daf7fa74ad820411658cec7714a840fb111a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_10gbe.vhd
@@ -31,9 +31,9 @@ USE work.unb2_board_pkg.ALL;
ENTITY unb2_board_10gbe IS
GENERIC (
- g_technology : NATURAL := c_tech_arria10;
- g_sim : BOOLEAN := FALSE;
+ g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 1; -- 0 = use IP; 1 = use fast serdes model
+ g_technology : NATURAL := c_tech_arria10;
g_nof_macs : NATURAL;
g_tx_fifo_fill : NATURAL := 10; -- Release tx packet only when sufficiently data is available,
g_tx_fifo_size : NATURAL := 256; -- 2 * 32b * 256 = 2 M9K (DP interface has 64b data, so at least 2 M9K needed)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
index 6be0a05095e7eba93f2f87b6d239b3ac9b5ae4ff..eb233b1ac5546e80db457f343112f05d94548181 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -22,17 +22,18 @@
-- Purpose: Provide MM slave register for unb2_fpga_sens
--
-LIBRARY IEEE, common_lib, fpga_sense_lib;
+LIBRARY IEEE, common_lib, technology_lib, fpga_sense_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
ENTITY unb2_fpga_sens_reg IS
GENERIC (
g_sim : BOOLEAN;
- g_technology : NATURAL;
+ g_technology : NATURAL := c_tech_arria10;
g_sens_nof_result : NATURAL := 1;
g_temp_high : NATURAL := 85
);