From b4d536383921fd2f07ad20563ad7cba5ddb6cfc3 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Thu, 4 Mar 2021 14:33:44 +0100
Subject: [PATCH] sdc fix for JESD clocks
---
.../lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
index 596f58dba3..72f271d102 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc.sdc
@@ -90,12 +90,15 @@ set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_nat
#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
+set_false_path -from [get_clocks {u_revision|u_ctrl|\gen_mm_clk_hardware:u_unb2b_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk2}] -to [get_clocks {u_revision|u_ait|u_jesd204b|\gen_ip_arria10_e1sg:u0|u_ip_arria10_e1sg_jesd204b|\gen_jesd204b_rx:gen_jesd204b_rx_corepll_freqsel:u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz|iopll_0|frame_clk}]
+set_false_path -from [get_clocks {u_revision|u_ctrl|\gen_mm_clk_hardware:u_unb2b_board_clk125_pll|\gen_fractional_pll:u_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk2}] -to [get_clocks {u_revision|u_ait|u_jesd204b|\gen_ip_arria10_e1sg:u0|u_ip_arria10_e1sg_jesd204b|\gen_jesd204b_rx:gen_jesd204b_rx_corepll_freqsel:u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz|iopll_0|link_clk}]
+
# false paths added for the jesd test design
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*corepll_200MHz|link_clk}]
-set_false_path -from [get_clocks {*corepll_200MHz|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
-set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*corepll_200MHz|frame_clk}]
-set_false_path -from [get_clocks {*corepll_200MHz|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+#set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*corepll_200MHz|link_clk}]
+#set_false_path -from [get_clocks {*corepll_200MHz|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+#set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*corepll_200MHz|frame_clk}]
+#set_false_path -from [get_clocks {*corepll_200MHz|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
# Constraint on the SYSREF input pin
# Adjust this to account for any board trace difference between SYSREF and REFCLK
--
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