diff --git a/libraries/io/tr_nonbonded/hdllib.cfg b/libraries/io/tr_nonbonded/hdllib.cfg
index 10b7137074e31590bef51e4aec352c1ce07e6cf0..980685534200390ec2bf696f246994ef129ccf05 100644
--- a/libraries/io/tr_nonbonded/hdllib.cfg
+++ b/libraries/io/tr_nonbonded/hdllib.cfg
@@ -12,5 +12,4 @@ synth_files =
$UNB/Firmware/modules/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
test_bench_files =
- $UNB/Firmware/modules/tr_nonbonded/tb/vhdl/tb_serdes.vhd
$UNB/Firmware/modules/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
diff --git a/libraries/technology/transceiver/hdllib.cfg b/libraries/technology/transceiver/hdllib.cfg
index 58e0237f13a3beb76892ad143b05681b235f806b..abd20a12f3df647e1a73537318e87d13366d3b8c 100644
--- a/libraries/technology/transceiver/hdllib.cfg
+++ b/libraries/technology/transceiver/hdllib.cfg
@@ -22,3 +22,4 @@ synth_files =
tech_transceiver_arria10_48.vhd
test_bench_files =
+ tb_sim_transceiver_serdes.vhd
diff --git a/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd b/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e3d046c7399c77581ce7c2b2aac8f8181f65f9f5
--- /dev/null
+++ b/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd
@@ -0,0 +1,154 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- Purpose:
+-- Model a basic serializer->deserializer link and verify received data
+-- Description:
+-- Data generator -> Serializer -> Deserializer -> Data verification
+-- Usage:
+-- as x
+-- run 2200 ns
+-- Observe:
+-- . user tx_in on serializer == user rx_out on deserializer
+-- . serial_line carries 4 bytes per serialized word. Each
+-- byte is followed by its 2 valid bits and is sent LSb first.
+
+LIBRARY IEEE, common_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_sim_transceiver_serdes IS
+END ENTITY tb_sim_transceiver_serdes;
+
+ARCHITECTURE tb of tb_sim_transceiver_serdes IS
+
+ CONSTANT c_tr_clk_period : TIME := 6.4 ns; -- 156.25 MHz
+
+ CONSTANT c_data_w : NATURAL := 32;
+ CONSTANT c_line_rate : NATURAL := 6250;
+
+ SIGNAL enable : STD_LOGIC := '1';
+ SIGNAL ready : STD_LOGIC;
+
+ SIGNAL tr_clk : STD_LOGIC := '0';
+ SIGNAL tr_rst : STD_LOGIC := '1';
+
+ SIGNAL tx_in : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+ SIGNAL tx_in_val : STD_LOGIC;
+ SIGNAL tx_in_ctrl : STD_LOGIC_VECTOR(c_data_w/c_byte_w-1 DOWNTO 0);
+
+ SIGNAL tx_clk : STD_LOGIC;
+ SIGNAL tx_rst : STD_LOGIC;
+
+ SIGNAL serial_line : STD_LOGIC;
+
+ SIGNAL rx_clk : STD_LOGIC;
+ SIGNAL rx_rst : STD_LOGIC;
+
+ SIGNAL rx_out : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+ SIGNAL rx_out_val : STD_LOGIC;
+ SIGNAL rx_out_ctrl : STD_LOGIC_VECTOR(c_data_w/c_byte_w-1 DOWNTO 0);
+
+ SIGNAL verify_en : STD_LOGIC := '0';
+ SIGNAL rd_ready : STD_LOGIC;
+ SIGNAL prev_rx_out : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
+
+
+BEGIN
+
+ tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2;
+ tr_rst <= '0' AFTER c_tr_clk_period*10;
+
+ p_ready: PROCESS
+ BEGIN
+ ready <= '0';
+ WAIT UNTIL tx_rst = '0';
+ WHILE TRUE LOOP
+ ready <= '1';
+ WAIT FOR c_tr_clk_period*50;
+ ready <= '0';
+ WAIT FOR c_tr_clk_period*50;
+ END LOOP;
+ END PROCESS;
+
+ -- Model FIFO output with c_rl = 1 and counter data starting at 0
+ proc_common_gen_data(1, 0, tx_rst, tx_clk, enable, ready, tx_in, tx_in_val);
+
+ gen_fanout: FOR i IN c_data_w/c_byte_w-1 DOWNTO 0 GENERATE
+ tx_in_ctrl(i) <= tx_in_val;
+ END GENERATE;
+
+ u_ser: ENTITY work.serializer
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_line_rate => c_line_rate
+ )
+ PORT MAP (
+
+ tr_clk => tr_clk,
+ tr_rst => tr_rst,
+
+ tx_clk => tx_clk,
+ tx_rst => tx_rst,
+
+ tx_in_data => tx_in,
+ tx_in_ctrl => tx_in_ctrl,
+
+ tx_out => serial_line
+ );
+
+ u_des: ENTITY work.deserializer
+ GENERIC MAP (
+ g_data_w => c_data_w,
+ g_line_rate => c_line_rate
+ )
+ PORT MAP (
+
+ tr_clk => tr_clk,
+ tr_rst => tr_rst,
+
+ rx_clk => rx_clk,
+ rx_rst => rx_rst,
+
+ rx_out_data => rx_out,
+ rx_out_ctrl => rx_out_ctrl,
+
+ rx_in => serial_line
+ );
+
+ p_verify_en: PROCESS
+ BEGIN
+ verify_en <= '0';
+ WAIT UNTIL rx_rst = '0';
+ WAIT FOR c_tr_clk_period*5;
+ verify_en <= '1';
+ WAIT;
+ END PROCESS;
+
+ rx_out_val <= andv(rx_out_ctrl);
+
+ -- Verify dut output incrementing data
+ proc_common_verify_data(1, rx_clk, verify_en, rd_ready, rx_out_val, rx_out, prev_rx_out);
+
+END tb;