diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 5532ed3cbf3710ef4d5c7caf599dc4563df1c81a..9ede2c9dceda45d1e95f99e258ace804c1d37a2a 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -323,18 +323,18 @@ BEGIN
         av_writedata               => reset_seq_mosi_arr(i).wrdata(31 downto 0),
         av_write                   => reset_seq_mosi_arr(i).wr,
         irq                        => open,
-        clk                        => mm_clk,
+        clk                        => mm_clk,                  -- use clk = mm_clk for av_* port
         csr_reset                  => mm_rst,
-        reset1_dsrt_qual           => core_pll_locked_reg,     -- Registered copy of the the core pll_locked
+        reset1_dsrt_qual           => core_pll_locked_reg,     -- core pll_locked synchronised to clk = mm_clk domain
         reset2_dsrt_qual           => '1',                     -- Tied to '1' in example design. Tx xcvr is not used.
         reset5_dsrt_qual           => rx_xcvr_ready_in_arr(i),
         reset_in0                  => mm_rst,
-        reset_out0                 => pll_reset_async_arr(i),        -- Use channel 0 to reset the core pll
+        reset_out0                 => pll_reset_async_arr(i),  -- Use channel 0 to reset the core pll
         reset_out1                 => xcvr_rst_arr(i),         -- Use channel 1 to reset the transceiver reset controller
         reset_out2                 => open,
         reset_out3                 => open,
         reset_out4                 => open,
-        reset_out5                 => rx_avs_rst_arr(i), -- mm_clk domain
+        reset_out5                 => rx_avs_rst_arr(i),       -- in mm_clk domain
         reset_out6                 => rxlink_rst_async_arr(i),
         reset_out7                 => rxframe_rst_async_arr(i)
       );
@@ -464,7 +464,8 @@ BEGIN
 
     u_common_areset_pll_locked : ENTITY common_lib.common_areset
     GENERIC MAP (
-      g_rst_level => '0' -- synchronises the rising edge input.
+      g_in_rst_level => '0',  -- synchronises the rising edge of input in_rst.
+      g_rst_level    => '0'
     )
     PORT MAP (
       in_rst  => core_pll_locked, 
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index 44d48af186c2691e98c150bd1cef97d9b7dda1d0..a08c3e105ce6fd8604ea80f9f1af358456f90c19 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -323,18 +323,18 @@ BEGIN
         av_writedata               => reset_seq_mosi_arr(i).wrdata(31 downto 0),
         av_write                   => reset_seq_mosi_arr(i).wr,
         irq                        => open,
-        clk                        => mm_clk,
+        clk                        => mm_clk,                  -- use clk = mm_clk for av_* port
         csr_reset                  => mm_rst,
-        reset1_dsrt_qual           => core_pll_locked_reg,     -- Registered copy of the the core pll_locked
+        reset1_dsrt_qual           => core_pll_locked_reg,     -- core pll_locked synchronised to clk = mm_clk domain
         reset2_dsrt_qual           => '1',                     -- Tied to '1' in example design. Tx xcvr is not used.
         reset5_dsrt_qual           => rx_xcvr_ready_in_arr(i),
         reset_in0                  => mm_rst,
-        reset_out0                 => pll_reset_async_arr(i),        -- Use channel 0 to reset the core pll
+        reset_out0                 => pll_reset_async_arr(i),  -- Use channel 0 to reset the core pll
         reset_out1                 => xcvr_rst_arr(i),         -- Use channel 1 to reset the transceiver reset controller
         reset_out2                 => open,
         reset_out3                 => open,
         reset_out4                 => open,
-        reset_out5                 => rx_avs_rst_arr(i), -- mm_clk domain
+        reset_out5                 => rx_avs_rst_arr(i),       -- in mm_clk domain
         reset_out6                 => rxlink_rst_async_arr(i),
         reset_out7                 => rxframe_rst_async_arr(i)
       );
@@ -464,7 +464,8 @@ BEGIN
 
     u_common_areset_pll_locked : ENTITY common_lib.common_areset
     GENERIC MAP (
-      g_rst_level => '0' -- synchronises the rising edge input.
+      g_in_rst_level => '0',  -- synchronises the rising edge of input in_rst.
+      g_rst_level    => '0'
     )
     PORT MAP (
       in_rst  => core_pll_locked,