From b42adbe22e97d999f27035684f137a472f535072 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Fri, 19 Dec 2014 16:17:13 +0000
Subject: [PATCH] Added modelsim_compile_ip_files for
ddr3_uphy_4g_800_master/copy_hex_files.tcl
---
libraries/io/ddr/hdllib.cfg | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/libraries/io/ddr/hdllib.cfg b/libraries/io/ddr/hdllib.cfg
index 9871fb590d..cf4bbeb7b8 100644
--- a/libraries/io/ddr/hdllib.cfg
+++ b/libraries/io/ddr/hdllib.cfg
@@ -1,19 +1,26 @@
hdl_lib_name = io_ddr
hdl_library_clause_name = io_ddr_lib
-hdl_lib_uses = common technology tech_ddr tech_ddr3 dp diag
+hdl_lib_uses = technology tech_ddr tech_ddr3 common dp diagnostics
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+
synth_files =
src/vhdl/io_ddr_driver_flush_ctrl.vhd
src/vhdl/io_ddr_driver.vhd
src/vhdl/io_ddr.vhd
test_bench_files =
- src/vhdl/tb_io_ddr.vhd
+ tb/vhdl/tb_io_ddr.vhd
-quartus_qip_files =
+modelsim_search_libraries =
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip
+# altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+# altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip twentynm twentynm_hssi twentynm_hip
--
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