diff --git a/libraries/technology/tse/tb_tech_tse.vhd b/libraries/technology/tse/tb_tech_tse.vhd
index ce074ce5673c8b798bdc26a7f934adb1e5cebddd..5c43594f5cb322abd32f0a8a382cdfd934214401 100644
--- a/libraries/technology/tse/tb_tech_tse.vhd
+++ b/libraries/technology/tse/tb_tech_tse.vhd
@@ -50,7 +50,7 @@ ENTITY tb_tech_tse IS
     --   g_data_type = c_tb_tech_tse_data_type_counter  = 1
     g_data_type  : NATURAL := c_tb_tech_tse_data_type_symbols;
     g_sim        : BOOLEAN := TRUE;
-    g_sim_level  : NATURAL := 1;    -- 0 = use IP; 1 = use fast serdes model;
+    g_sim_level  : NATURAL := 0;    -- 0 = use IP; 1 = use fast serdes model;
     g_tb_end     : BOOLEAN := TRUE  -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
   );
   PORT (
@@ -100,7 +100,9 @@ ARCHITECTURE tb OF tb_tech_tse IS
   SIGNAL mm_init           : STD_LOGIC := '1';
   SIGNAL mm_miso           : t_mem_miso;
   SIGNAL mm_mosi           : t_mem_mosi;
-  
+  SIGNAL mm_wrdata         : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- for view in Wave window
+  SIGNAL mm_rddata         : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- for view in Wave window
+
   SIGNAL mm_psc_access     : STD_LOGIC;
 
   -- TSE MAC transmit interface
@@ -116,6 +118,7 @@ ARCHITECTURE tb OF tb_tech_tse IS
   -- . The tb is the ST sink
   SIGNAL rx_sosi           : t_dp_sosi;
   SIGNAL rx_siso           : t_dp_siso;
+  SIGNAL rx_data           : STD_LOGIC_VECTOR(c_word_w-1 DOWNTO 0);  -- for view in Wave window
   -- . MAC specific
   SIGNAL rx_mac_out        : t_tech_tse_rx_mac;
 
@@ -143,6 +146,10 @@ BEGIN
   total_header_loopback.eth <= c_eth_header_loopback;
   total_header_etherlen.eth <= c_eth_header_etherlen;
 
+  mm_wrdata <= mm_mosi.wrdata(c_word_w-1 DOWNTO 0);
+  mm_rddata <= mm_miso.rddata(c_word_w-1 DOWNTO 0);
+  rx_data <= rx_sosi.data(c_word_w-1 DOWNTO 0);
+
   p_mm_setup : PROCESS
   BEGIN
     mm_init  <= '1';