diff --git a/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd b/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd new file mode 100644 index 0000000000000000000000000000000000000000..b5ff2afd080cef974a3a3aaa16275712376262f9 --- /dev/null +++ b/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd @@ -0,0 +1,202 @@ + +------------------------------------------------------------------------------- +-- +-- Copyright (C) 2012 +-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/> +-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- +------------------------------------------------------------------------------- + +LIBRARY IEEE, common_lib, dp_lib; +USE IEEE.STD_LOGIC_1164.ALL; +USE common_lib.common_pkg.ALL; +USE common_lib.common_mem_pkg.ALL; +USE dp_lib.dp_stream_pkg.ALL; +USE work.ddr3_pkg.ALL; + +ENTITY mms_ddr3 IS + GENERIC ( + g_sim : BOOLEAN := FALSE; + g_ddr : t_c_ddr3_phy := c_ddr3_phy_4g; + g_mts : NATURAL := 800; + g_phy : NATURAL := 1; + g_wr_data_w : NATURAL := c_ddr3_ctlr_data_w; + g_wr_use_ctrl : BOOLEAN := FALSE; + g_wr_fifo_depth : NATURAL := 128; + g_rd_fifo_depth : NATURAL := 256; + g_rd_data_w : NATURAL := c_ddr3_ctlr_data_w; + g_flush_wr_fifo : BOOLEAN := FALSE; + g_flush_sop : BOOLEAN := FALSE; + g_flush_sop_channel : BOOLEAN := FALSE; + g_flush_sop_start_channel : NATURAL := 0; + g_flush_nof_channels : NATURAL := 0 + ); + PORT ( + mm_rst : IN STD_LOGIC; + mm_clk : IN STD_LOGIC; + + ctlr_ref_clk : IN STD_LOGIC; + ctlr_rst : IN STD_LOGIC; -- asynchronous reset input to controller + + ctlr_gen_clk : OUT STD_LOGIC; -- Controller generated clock + ctlr_gen_rst : OUT STD_LOGIC; + + wr_clk : IN STD_LOGIC; + wr_rst : IN STD_LOGIC; + + wr_sosi : IN t_dp_sosi; + wr_siso : OUT t_dp_siso; + + flush_ena : IN STD_LOGIC; + + rd_sosi : OUT t_dp_sosi; + rd_siso : IN t_dp_siso; + + rd_clk : IN STD_LOGIC; + rd_rst : IN STD_LOGIC; + + rd_fifo_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (c_ddr3_ctlr_data_w/g_rd_data_w) )-1 DOWNTO 0); + + -- On chip termination busses + ser_term_ctrl_out : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + par_term_ctrl_out : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); + + ser_term_ctrl_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0'); + par_term_ctrl_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0'); + + -- MM registers + ctrl_mosi : IN t_mem_mosi := c_mem_mosi_rst; + ctrl_miso : OUT t_mem_miso; + + rd_data_mosi : IN t_mem_mosi := c_mem_mosi_rst; + rd_data_miso : OUT t_mem_miso := c_mem_miso_rst; + + -- SO-DIMM Memory Bank + ddr3_in : IN t_ddr3_phy_in; + ddr3_io : INOUT t_ddr3_phy_io; + ddr3_ou : OUT t_ddr3_phy_ou + ); +END mms_ddr3; + + +ARCHITECTURE str OF mms_ddr3 IS + + SIGNAL i_ctlr_gen_rst : STD_LOGIC; + SIGNAL i_ctlr_gen_clk : STD_LOGIC; + + -- ctrl & status DDR3 driver + SIGNAL dvr_start_addr : t_ddr3_addr; + SIGNAL dvr_end_addr : t_ddr3_addr; + + SIGNAL dvr_en : STD_LOGIC; + SIGNAL dvr_wr_not_rd : STD_LOGIC; + SIGNAL dvr_done : STD_LOGIC; + + -- DDR3 controller status + SIGNAL ctlr_init_done : STD_LOGIC; + SIGNAL ctlr_rdy : STD_LOGIC; + +BEGIN + + ctlr_gen_clk <= i_ctlr_gen_clk; + ctlr_gen_rst <= i_ctlr_gen_rst; + + u_ddr3: ENTITY work.ddr3 + GENERIC MAP( + g_ddr => g_ddr, + g_mts => g_mts, + g_phy => g_phy, + g_wr_data_w => g_wr_data_w, + g_wr_use_ctrl => g_wr_use_ctrl, + g_wr_fifo_depth => g_wr_fifo_depth, + g_rd_fifo_depth => g_rd_fifo_depth, + g_rd_data_w => g_rd_data_w, + g_flush_wr_fifo => g_flush_wr_fifo, + g_flush_sop => g_flush_sop, + g_flush_sop_channel => g_flush_sop_channel, + g_flush_sop_start_channel => g_flush_sop_start_channel, + g_flush_nof_channels => g_flush_nof_channels + ) + PORT MAP ( + ctlr_ref_clk => ctlr_ref_clk, + ctlr_rst => ctlr_rst, + + phy_in => ddr3_in, + phy_io => ddr3_io, + phy_ou => ddr3_ou, + + ctlr_gen_clk => i_ctlr_gen_clk, + ctlr_gen_rst => i_ctlr_gen_rst, + + ctlr_init_done => ctlr_init_done, + + ctlr_rdy => ctlr_rdy, + dvr_start_addr => dvr_start_addr, + dvr_end_addr => dvr_end_addr, + + dvr_done => dvr_done, + dvr_wr_not_rd => dvr_wr_not_rd, + dvr_en => dvr_en, + + wr_clk => wr_clk, + wr_rst => wr_rst, + + wr_sosi => wr_sosi, + wr_siso => wr_siso, + + flush_ena => flush_ena, + + rd_sosi => rd_sosi, + rd_siso => rd_siso, + + rd_clk => rd_clk, + rd_rst => rd_rst, + + ser_term_ctrl_out => ser_term_ctrl_out, + par_term_ctrl_out => par_term_ctrl_out, + + ser_term_ctrl_in => ser_term_ctrl_in, + par_term_ctrl_in => par_term_ctrl_in, + + rd_fifo_usedw => rd_fifo_usedw + ); + + u_ddr3_reg: ENTITY work.ddr3_reg + GENERIC MAP( + g_ddr => g_ddr + ) + PORT MAP ( + mm_rst => mm_rst, + mm_clk => mm_clk, + st_rst => wr_rst, + st_clk => wr_clk, + + sla_in => ctrl_mosi, + sla_out => ctrl_miso, + + st_en_evt => dvr_en, + st_wr_not_rd => dvr_wr_not_rd, + + st_start_addr => dvr_start_addr, + st_end_addr => dvr_end_addr, + + st_done => dvr_done, + st_init_done => ctlr_init_done, + st_ctlr_rdy => ctlr_rdy + ); + +END str; +