From b3aee28e3f4942f2bc0f9b4a638dd20f7e1b9167 Mon Sep 17 00:00:00 2001
From: Pepping <pepping>
Date: Thu, 25 Jun 2015 11:41:03 +0000
Subject: [PATCH] UPdated names
---
.../reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd | 8 ++---
.../reorder/tb/vhdl/tb_mmf_reorder_row.vhd | 8 ++---
.../base/reorder/tb/vhdl/tb_reorder_col.vhd | 10 +++---
.../reorder/tb/vhdl/tb_tb_reorder_col.vhd | 34 +++++++++----------
4 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd
index 15906e3c08..c2ae2b07d2 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd
@@ -50,7 +50,7 @@ USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
-ENTITY tb_mmf_ss_parallel IS
+ENTITY tb_mmf_reorder_matrix IS
GENERIC(
g_nof_inputs : NATURAL := 4;
g_nof_internals : NATURAL := 8;
@@ -60,9 +60,9 @@ ENTITY tb_mmf_ss_parallel IS
g_frame_size_out : NATURAL := 16;
g_nof_frames : NATURAL := 1
);
-END tb_mmf_ss_parallel;
+END tb_mmf_reorder_matrix;
-ARCHITECTURE tb OF tb_mmf_ss_parallel IS
+ARCHITECTURE tb OF tb_mmf_reorder_matrix IS
CONSTANT c_sim : BOOLEAN := TRUE;
@@ -239,7 +239,7 @@ BEGIN
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
- u_dut : ENTITY work.ss_parallel
+ u_dut : ENTITY work.reorder_matrix
GENERIC MAP(
g_nof_inputs => g_nof_inputs,
g_nof_internals => g_nof_internals,
diff --git a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
index d7dffdfab1..2823fb5645 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
@@ -50,7 +50,7 @@ USE mm_lib.mm_file_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE diag_lib.diag_pkg.ALL;
-ENTITY tb_mmf_ss_reorder IS
+ENTITY tb_mmf_reorder_row IS
GENERIC(
g_nof_inputs : NATURAL := 8;
g_nof_outputs : NATURAL := 16;
@@ -62,9 +62,9 @@ ENTITY tb_mmf_ss_reorder IS
g_pipeline_out : NATURAL := 1; -- pipeline out_data
g_nof_frames : NATURAL := 1
);
-END tb_mmf_ss_reorder;
+END tb_mmf_reorder_row;
-ARCHITECTURE tb OF tb_mmf_ss_reorder IS
+ARCHITECTURE tb OF tb_mmf_reorder_row IS
CONSTANT c_sim : BOOLEAN := TRUE;
@@ -229,7 +229,7 @@ BEGIN
----------------------------------------------------------------------------
-- DUT: Device Under Test
----------------------------------------------------------------------------
- u_dut : ENTITY work.ss_reorder
+ u_dut : ENTITY work.reorder_row
GENERIC MAP(
g_nof_inputs => g_nof_inputs,
g_nof_outputs => g_nof_outputs,
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
index 761c4bddbc..f051077c71 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
@@ -43,7 +43,7 @@ USE dp_lib.tb_dp_pkg.ALL;
-- Remark:
-- . Use tb_tb_ss for multi-tb DUT verification.
-ENTITY tb_ss IS
+ENTITY tb_reorder_col IS
GENERIC (
-- Flow control
g_mode_in_en : NATURAL := 0; -- use 0 for active in_sosi.valid control
@@ -69,10 +69,10 @@ ENTITY tb_ss IS
g_use_output_rl_adapter : BOOLEAN := FALSE -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2
);
-END tb_ss;
+END tb_reorder_col;
-ARCHITECTURE tb OF tb_ss IS
+ARCHITECTURE tb OF tb_reorder_col IS
CONSTANT clk_period : TIME := 10 ns;
@@ -224,7 +224,7 @@ BEGIN
WAIT;
END PROCESS;
- u_reverse_ss : ENTITY work.ss
+ u_reverse_ss : ENTITY work.reorder_col
GENERIC MAP (
g_use_output_rl_adapter => g_use_output_rl_adapter,
g_dsp_data_w => c_dsp_data_w,
@@ -255,7 +255,7 @@ BEGIN
------------------------------------------------------------------------------
in_sosi <= dp_sosi WHEN g_reverse_ss_map=FALSE ELSE reverse_sosi;
- u_dut_ss : ENTITY work.ss
+ u_dut_ss : ENTITY work.reorder_col
GENERIC MAP (
g_use_output_rl_adapter => g_use_output_rl_adapter,
g_dsp_data_w => c_dsp_data_w,
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
index 63d04a3dc2..d11a9c4f27 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
@@ -22,10 +22,10 @@
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-ENTITY tb_tb_ss IS
-END tb_tb_ss;
+ENTITY tb_tb_reorder_col IS
+END tb_tb_reorder_col;
-ARCHITECTURE tb OF tb_tb_ss IS
+ARCHITECTURE tb OF tb_tb_reorder_col IS
CONSTANT c_nof_sync : NATURAL := 20;
CONSTANT c_reverse_ss_map : BOOLEAN := TRUE;
@@ -43,24 +43,24 @@ BEGIN
-- g_nof_ch_sel : NATURAL := 31;
-- g_use_output_rl_adapter : BOOLEAN := FALSE; -- when true adapt output RL to 1 else the output RL is equal to c_retrieve_lat=2
- u_act_act_32_32 : ENTITY work.tb_ss GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 32, FALSE);
- u_act_act_32_24 : ENTITY work.tb_ss GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 24, FALSE);
- u_rnd_act_32_32_rl : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 32, TRUE);
- u_rnd_act_32_32 : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 32, FALSE);
- u_rnd_act_32_24 : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 24, FALSE);
+ u_act_act_32_32 : ENTITY work.tb_reorder_col GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 32, FALSE);
+ u_act_act_32_24 : ENTITY work.tb_reorder_col GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 24, FALSE);
+ u_rnd_act_32_32_rl : ENTITY work.tb_reorder_col GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 32, TRUE);
+ u_rnd_act_32_32 : ENTITY work.tb_reorder_col GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 32, FALSE);
+ u_rnd_act_32_24 : ENTITY work.tb_reorder_col GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 24, FALSE);
- u_act_act_32_31 : ENTITY work.tb_ss GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 31, FALSE);
- u_rnd_act_32_31 : ENTITY work.tb_ss GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 31, FALSE);
+ u_act_act_32_31 : ENTITY work.tb_reorder_col GENERIC MAP (0, 0, c_nof_sync, c_reverse_ss_map, 32, 31, FALSE);
+ u_rnd_act_32_31 : ENTITY work.tb_reorder_col GENERIC MAP (1, 0, c_nof_sync, c_reverse_ss_map, 32, 31, FALSE);
- u_act_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
- u_rnd_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (1, 1, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
+ u_act_toggle_32_16 : ENTITY work.tb_reorder_col GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
+ u_rnd_toggle_32_16 : ENTITY work.tb_reorder_col GENERIC MAP (1, 1, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
- u_act_toggle_32_15 : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, FALSE);
- u_rnd_toggle_32_15 : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, FALSE);
+ u_act_toggle_32_15 : ENTITY work.tb_reorder_col GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, FALSE);
+ u_rnd_toggle_32_15 : ENTITY work.tb_reorder_col GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, FALSE);
- u_rnd_toggle_32_15_rl : ENTITY work.tb_ss GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, TRUE);
+ u_rnd_toggle_32_15_rl : ENTITY work.tb_reorder_col GENERIC MAP (0, 1, c_nof_sync, c_reverse_ss_map, 32, 15, TRUE);
- u_act_invert_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (0, 2, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
- u_rnd_invert_toggle_32_16 : ENTITY work.tb_ss GENERIC MAP (1, 2, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
+ u_act_invert_toggle_32_16 : ENTITY work.tb_reorder_col GENERIC MAP (0, 2, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
+ u_rnd_invert_toggle_32_16 : ENTITY work.tb_reorder_col GENERIC MAP (1, 2, c_nof_sync, c_reverse_ss_map, 32, 16, FALSE);
END tb;
--
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