diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index 159cc2b5ed8f7b630c5909477ffcd0e91ca783e4..2c87641ca55b5a52ce9c4437f4849274ac674de3 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -26,7 +26,6 @@ regression_test_vhdl =
modelsim_copy_files =
$RADIOHDL_WORK/libraries/io/i2c/tb/data data
$RADIOHDL_WORK/libraries/base/diag/src/data data
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
@@ -35,7 +34,6 @@ quartus_copy_files =
quartus/sopc_unb1_bn_capture.sopc .
$RADIOHDL_WORK/libraries/io/i2c/tb/data data
$RADIOHDL_WORK/libraries/base/diag/src/data data
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index cd32b3ec5e81964ef2a3d9e3e701170608ad756d..9368e22ad325e4676b993d61512b0b9fd1f7b785 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -17,8 +17,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
$RADIOHDL_WORK/libraries/base/diag/src/data data
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
@@ -26,7 +24,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_bn_terminal_bg.sopc .
$RADIOHDL_WORK/libraries/base/diag/src/data data
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_ddr3/doc/README b/boards/uniboard1/designs/unb1_ddr3/doc/README
index 4134e5df3170b97aa95b4ef5b8a1f7e3d89180b9..245bf3a6d18d008fe28c5331559e1e9029bdaca1 100644
--- a/boards/uniboard1/designs/unb1_ddr3/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3/doc/README
@@ -14,7 +14,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb1
# in Modelsim do:
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 8cfde04c82aa49fb2701012f596429de1ada0b5f..89321855be5b9591595b7b3c57d742d82ba8f64f 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -17,18 +17,15 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_ddr3.sopc .
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
index 489688ec457794329f95d5d2c59c6efadd7f370e..752cd16ede33b354a27132fe3b03100b5651b530 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
@@ -14,7 +14,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb1
# in Modelsim do:
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 23d49faca31ece9b8e32a2bf93ee0e4e621d1bb6..3deda821337e0d7909ffb96b8dc5c75c6f716e43 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -17,7 +17,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
modelsim_compile_ip_files =
$RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -28,7 +27,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb_ddr3_transpose.sopc .
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index bb2137004fb411473abe12b4106ce889016e5607..908c0f97085a4bdaa5d9fb02a1ce8d20162e681d 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -16,15 +16,12 @@ test_bench_files =
[modelsim_project_file]
#modelsim_copy_files = src/hex hex
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_fn_terminal_db.sopc .
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_heater/doc/README b/boards/uniboard1/designs/unb1_heater/doc/README
index a907cf2b91ffcb459d93f9ef3954d44bc0757e43..594a16f0a29361fba3ca26bf8e6a7eadbcc71127 100644
--- a/boards/uniboard1/designs/unb1_heater/doc/README
+++ b/boards/uniboard1/designs/unb1_heater/doc/README
@@ -16,7 +16,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb1
# in Modelsim do:
diff --git a/boards/uniboard1/designs/unb1_heater/hdllib.cfg b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
index 2e8fbc26e47c66ec476e9c63b1e6fafe06df3b9f..3124faa9b5ec78cd53c1007ea48847f895d0d4ee 100644
--- a/boards/uniboard1/designs/unb1_heater/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
@@ -15,8 +15,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
@@ -24,7 +22,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/qsys_unb1_heater.qsys .
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/README b/boards/uniboard1/designs/unb1_minimal/doc/README
index d85df74cd153f712b2dcd7dabac0ac6106ced633..ded73efee23c6be34c666d0214d892eb7852fd16 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/README
+++ b/boards/uniboard1/designs/unb1_minimal/doc/README
@@ -18,7 +18,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb1
# in Modelsim do:
diff --git a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
index 4d82a8de6e274515ac47014aeaed757ae303a309..f78ab28d3cb8808fe0e41c5887748c3b6deec7ab 100644
--- a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
@@ -15,8 +15,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index e56f106393f30eaebd6b2caf8797854ea5be96c4..f7db8733bd9c89611f906dfd740d56ecf1524ef2 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -17,8 +17,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
src/hex hex
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
@@ -27,7 +25,6 @@ synth_top_level_entity =
quartus_copy_files =
quartus/qsys_unb1_terminal_bg_mesh_db.qsys .
src/hex hex
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus_qsf_files =
$RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index 9eca9c326ae3ef0a160f23e4234264c9c77ca751..75278e69b1186ff8f2db354d61270fca7510887c 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -46,7 +46,7 @@ The following revisions are available for unb1_test (see the directories in ../r
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb1
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard1/designs/unb1_test/hdllib.cfg b/boards/uniboard1/designs/unb1_test/hdllib.cfg
index d84c1f1b2137f50ce0e0b86ad8fc97357163cd70..65ddbb4c7cb5c30cb8f9847d9d15b4ee594fac00 100644
--- a/boards/uniboard1/designs/unb1_test/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/hdllib.cfg
@@ -17,10 +17,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index f1eecf8d27bb9bcd935d29a680d97f070b765ead..5e10bf15e3c51ad17bf3c4ebfd9ca25b5ae84c84 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -15,7 +15,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
# src/hex hex
@@ -25,7 +24,6 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus/qsys_unb1_tr_10GbE.qsys .
# src/hex/ hex
diff --git a/boards/uniboard2/designs/unb2_minimal/doc/README b/boards/uniboard2/designs/unb2_minimal/doc/README
index d4c4b3ef19935eaddc50b6dd1d38bcd328db7e9c..f4204c933d59b49110552aab6142f5ba53636e87 100644
--- a/boards/uniboard2/designs/unb2_minimal/doc/README
+++ b/boards/uniboard2/designs/unb2_minimal/doc/README
@@ -26,7 +26,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2
# in Modelsim do:
diff --git a/boards/uniboard2/designs/unb2_test/doc/README b/boards/uniboard2/designs/unb2_test/doc/README
index 5c311198c8fb13862603499e0706edad56f58ab6..aa1962e9b773c201dbba3a04cadebc5c81df3fbd 100644
--- a/boards/uniboard2/designs/unb2_test/doc/README
+++ b/boards/uniboard2/designs/unb2_test/doc/README
@@ -54,7 +54,7 @@ The following revisions are available for unb2_test (see the directories in ../r
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
index 45d88bd21b9f2bd7d296df1929051fe45efe5a7b..45784227e7324df032f996bb8777826d80bb5042 100644
--- a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
@@ -26,7 +26,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2a
# in Modelsim do:
diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
index 552ed433c518889dfce99210f34f3a5f342229e3..2f15b2b53286cc98102d152c0d7f427ee7f2fc5d 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
@@ -28,7 +28,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2a
# in Modelsim do:
diff --git a/boards/uniboard2a/designs/unb2a_test/doc/README.txt b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
index 4d8244dfcf3ee35e771167de7beabdd10aa47134..c0cbdbec17f87a5ea1586f2547db6eef790c86a3 100644
--- a/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
@@ -53,7 +53,7 @@ The following revisions are available for unb2a_test (see the directories in ../
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2a
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
index 4958c61efd971a89c4784bcd8119226a5cfefe28..986591f6bd898cba4a9fbae3f7a6993cc8bab2e9 100644
--- a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
@@ -26,7 +26,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2b
# in Modelsim do:
diff --git a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
index 01014dc0fc3dc13e4f0f05f6dbe55a326a10deb2..cad8b1c16ab141d979202f288102f8b79ebb9e16 100644
--- a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
@@ -15,14 +15,11 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
diff --git a/boards/uniboard2b/designs/unb2b_jesd/doc/README b/boards/uniboard2b/designs/unb2b_jesd/doc/README
index a8ee798172b26c69d51affd65034e1d8b8b5b3c6..2ad1b66249653ab4cf25626064a59ebb2afca74f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/doc/README
+++ b/boards/uniboard2b/designs/unb2b_jesd/doc/README
@@ -37,7 +37,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2b
# in Modelsim do:
diff --git a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
index 534dac3205b85021a62dcc84a3525f5dc9928a79..dc01f1470182e33f393473bf917dc96820c9928c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
@@ -15,14 +15,11 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
diff --git a/boards/uniboard2b/designs/unb2b_minimal/doc/README b/boards/uniboard2b/designs/unb2b_minimal/doc/README
index 1c12d1247f00e6840156da2dc3302355e46a0ba1..e503e227fe2b0070887787aa3ae5023e69140b6c 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/doc/README
+++ b/boards/uniboard2b/designs/unb2b_minimal/doc/README
@@ -28,7 +28,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2b
# in Modelsim do:
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index 2fdf2728e16d86411d5f017b63c36f9e3a65406e..c14007d56250625c914f10559a915a752fbea450 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -15,13 +15,11 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
diff --git a/boards/uniboard2b/designs/unb2b_test/doc/README.txt b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
index 7dbf81984351624dd2eafbc0701c3b960c403318..f704e92177b0f38d859d870a7e0acd8183fe14bb 100644
--- a/boards/uniboard2b/designs/unb2b_test/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
@@ -53,7 +53,7 @@ The following revisions are available for unb2b_test (see the directories in ../
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2b
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard2b/designs/unb2b_test/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/hdllib.cfg
index 3745d759255a82e6a87a6bd55dc63f7a851e54fe..e22cda32474b5f54b09826ac4b58e4695ea42eb3 100644
--- a/boards/uniboard2b/designs/unb2b_test/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/hdllib.cfg
@@ -17,10 +17,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/boards/uniboard2c/designs/unb2c_heater/doc/README.txt b/boards/uniboard2c/designs/unb2c_heater/doc/README.txt
index 79694e18e8133fcc8720b7266b90967286687efe..d906ab22d9536e2b8d68d9b76666314c45e1b0a4 100644
--- a/boards/uniboard2c/designs/unb2c_heater/doc/README.txt
+++ b/boards/uniboard2c/designs/unb2c_heater/doc/README.txt
@@ -26,7 +26,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2c
# in Modelsim do:
diff --git a/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg b/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
index d4412328b9681a9925e206877d1dcbdf88e3a942..385dbb59a6925d92e91c658378d1c501adf4af57 100644
--- a/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_heater/hdllib.cfg
@@ -15,21 +15,18 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
-
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_heater_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_heater/quartus/unb2c_heater_pins.tcl b/boards/uniboard2c/designs/unb2c_heater/quartus/unb2c_heater_pins.tcl
index e99fb59c459dab329d3d13cc82d2b46497f8231a..236269c156df5a03803144b912fb41eedabfade7 100644
--- a/boards/uniboard2c/designs/unb2c_heater/quartus/unb2c_heater_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_heater/quartus/unb2c_heater_pins.tcl
@@ -18,4 +18,4 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_jesd/doc/README b/boards/uniboard2c/designs/unb2c_jesd/doc/README
index 6c27ae37d1e5161f83ccff1c89d829ecd56971ef..40f1369f26ab5ff61b04fa8ee67edb394d0dda84 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/doc/README
+++ b/boards/uniboard2c/designs/unb2c_jesd/doc/README
@@ -37,7 +37,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2c
# in Modelsim do:
diff --git a/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
index 6de0ac38e2c41d76dfa95534a219dbab6734dc5e..74dd04a7b4c72bce1921dac14bf648ecf7da05e4 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/hdllib.cfg
@@ -15,18 +15,16 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
quartus/unb2c_jesd.sdc
diff --git a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
index 11abd8a9c0b224f7a08d2cf01fb2c50c53612f5d..e580c1600a3dc583d8c5cebea32f2a9b3dfe9c2b 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node0/hdllib.cfg
@@ -20,7 +20,7 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
quartus/unb2c_jesd_node0.sdc
diff --git a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
index 7d946e583e2561ce47c505309cb56bc020eb9326..7a59e62d82807f96856aeb647449f417d9ade20e 100644
--- a/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_jesd/revisions/unb2c_jesd_node3/hdllib.cfg
@@ -20,7 +20,7 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
quartus/unb2c_jesd_node3.sdc
diff --git a/boards/uniboard2c/designs/unb2c_minimal/doc/README b/boards/uniboard2c/designs/unb2c_minimal/doc/README
index 5e13e9cf030fc7ace33c3d97892b82849545d600..e07a7e406002b2628db57a2491a74a2dacf2c367 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/doc/README
+++ b/boards/uniboard2c/designs/unb2c_minimal/doc/README
@@ -28,7 +28,7 @@ Simulation
----------
Modelsim instructions:
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2c
# in Modelsim do:
diff --git a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
index c6024ae9717836ca600b940fe0f128cdea3ee151..56e214f2466ed59c77fd93296955e7e8b0818829 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
@@ -15,20 +15,18 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
index 121b2146078a8a40e0687b404a7a53232f48fcb9..ae417258f888c910d593c6ab6e5117615ebbd36f 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/doc/README.txt b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
index 10f984b71e861cfca34a2950fbb8cab09659fcce..7721fb02fb40a0cd449fca37662d44549324568a 100644
--- a/boards/uniboard2c/designs/unb2c_test/doc/README.txt
+++ b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
@@ -53,7 +53,7 @@ The following revisions are available for unb2c_test (see the directories in ../
Simulation
----------
# in bash do:
- rm $UNB/Software/python/sim/* # (optional)
+ rm $SIM_DIR/* # (optional)
run_modelsim unb2c
Further Modelsim instructions: see the README file in the ../revisions/* directories
diff --git a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
index c98b1f0172f93e8cbd8a1caf5b7f13e68c12f6b3..cff24fd96bd74e5c838947956eb17fee22aeaa33 100644
--- a/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/hdllib.cfg
@@ -17,10 +17,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2c.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/quartus/unb2c_test_pins.tcl b/boards/uniboard2c/designs/unb2c_test/quartus/unb2c_test_pins.tcl
index 0bc636cbf0a4008e2948d0cd86c926662df19e82..de0a720193bdd4f5abd6984cd3375a3409741151 100644
--- a/boards/uniboard2c/designs/unb2c_test/quartus/unb2c_test_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/quartus/unb2c_test_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
+source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
index 94d56cf841676a500fd685cc41325faf682236c2..de860d3ffb575f7eb18cc911a9c506739e8da20b 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
@@ -45,14 +45,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
quartus/unb2c_test_10GbE.sdc
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_10GbE_pins.tcl
diff --git a/init_hdl.sh b/init_hdl.sh
index fd1a853c1e81daa421d7f33776dd7f634b9e142c..fc129403f130e8db1f0bf63f010fa97f247bde5f 100644
--- a/init_hdl.sh
+++ b/init_hdl.sh
@@ -54,3 +54,7 @@ done
if [ -z "${RADIOHDL_GEAR}" ]; then
. ../radiohdl/init_radiohdl.sh
fi
+
+if [ -z "${UPE_GEAR}" ]; then
+ . ../upe_gear/init_upe.sh
+fi
diff --git a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
index f70babcff017d97ab122c1f8c0f700cc838dd16a..7653a297db1aee4c8c3135ee8b1e70c34cfa4612 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
@@ -37,7 +37,7 @@ PACKAGE mm_file_unb_pkg IS
CONSTANT c_mmf_unb_nof_pn : NATURAL := c_mmf_unb_nof_fn + c_mmf_unb_nof_bn; -- = 8
-- use fixed central directory to ease use of Python test case with Modelsim
- CONSTANT c_mmf_unb_file_path : STRING := "$UNB/Software/python/sim/";
+ CONSTANT c_mmf_unb_file_path : STRING := "$SIM_DIR/";
-- create mmf file prefix that is unique per slave
FUNCTION mmf_unb_file_prefix(sys: t_c_mmf_unb_sys; node: NATURAL) RETURN STRING;
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index 553407d82e6b40c953da4f1d08dcc042f96e40aa..a9c17c9c3bbbf81bc2fed71ffd2886dce1691fe7 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -44,6 +44,11 @@ regression_test_vhdl =
[modelsim_project_file]
-
+modelsim_copy_files =
+ #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+ src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
+quartus_copy_files =
+ #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+ src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
\ No newline at end of file
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
index 21621a58dff936de7f1420b870172d9caca69434..78cfca72bd307a5d516047cf40a897c494e8fc9a 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
@@ -10,9 +10,9 @@
#
#
-# request TCL package from ACDS 17.0
+# request TCL package from ACDS 18.0
#
-package require -exact qsys 17.0
+package require -exact qsys 18.0
#
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
index 1d9473211b4f12c609a38297f04888887af9304f..9e7b8318d144b2f72a2c742cb23d42de83578492 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb1.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | ../../../../io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_pkg.vhd syn, sim
+# | ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | ../../../../technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
index 1d9473211b4f12c609a38297f04888887af9304f..9e7b8318d144b2f72a2c742cb23d42de83578492 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | ../../../../io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_pkg.vhd syn, sim
+# | ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | ../../../../technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
index 1d9473211b4f12c609a38297f04888887af9304f..9e7b8318d144b2f72a2c742cb23d42de83578492 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2a.tcl
@@ -9,14 +9,14 @@
# | ASTRON 2014.07.23.09:36:00
# | MM slave port to conduit for the ETH module
# |
-# | $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+# | ../../../../io/eth/src/vhdl/avs2_eth_coe.vhd
# |
# | ./avs2_eth_coe.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/technology/tse/tech_tse_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_pkg.vhd syn, sim
+# | ../../../../base/dp/src/vhdl/dp_stream_pkg.vhd syn, sim
+# | ../../../../technology/tse/tech_tse_pkg.vhd syn, sim
# | ./eth_pkg.vhd syn, sim
-# | $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
+# | ../../../../base/common/src/vhdl/common_network_layers_pkg.vhd syn, sim
# |
# +-----------------------------------
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
index 21621a58dff936de7f1420b870172d9caca69434..78cfca72bd307a5d516047cf40a897c494e8fc9a 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe_hw_unb2b.tcl
@@ -10,9 +10,9 @@
#
#
-# request TCL package from ACDS 17.0
+# request TCL package from ACDS 18.0
#
-package require -exact qsys 17.0
+package require -exact qsys 18.0
#
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index 4286581aace7feb963ddf2079aaf09ce9ca52ed6..02e4adb554aec475da941a60d7c76bd2fd9e58b9 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -7,6 +7,7 @@ hdl_lib_technology =
synth_files =
technology_pkg.vhd
$HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+
test_bench_files =
regression_test_vhdl =
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
index 7c0f26937ab74d5506c2c6f7c86819dd716cae3a..d2c1cac94d7a915467598e00158b226912f78133 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
vmap alt_em10g32_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
index 1ae3f80bee1f937e1768e23182102435153f2cef..48b8eadb18ffe222be00011f1a9d45c2e88cd8a9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap alt_mem_if_jtag_master_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
index 4be28d783af91ce2de691ed2b2d25979228d60fc..0fdc6a880e087a7f252a0ffa7071d286d0bdc84f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
vmap altclkctrl_180 ./work/
vcom "$IP_DIR/../altclkctrl_180/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_180_uuznxiq.vhd" -work altclkctrl_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
index 1d61a0aec4070b87b5c723eb203784db48758d61..d6b2ba13b801ab542ffb812499cd045bcd976b4a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
vmap altera_asmi_parallel_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
index 7f1f5797ff27449640d5c61ffd7dfa69411275a3..af0c7159fd9aeb9898dd708d829011e65639f3e7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_avalon_mm_bridge_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
index 32aad9d5c1d887c995296b361d7591a6468b6013..edf94714dd03299d19c6edb8b7e661399c6246a8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
@@ -30,17 +30,17 @@
#
vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
- vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_yroldmy.vhd" -work altera_avalon_onchip_memory2_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+ vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
index a28af3acd153156cddbc199a4c42a11f405c2397..db85d837ed13d5ed34522941592c314fd4cd9a4c 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_packets_to_master_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
index 51d850450c56961cd959351d242feca34018c30f..ee66c060b0e7e1ca395e7dae50698d29a8bd7cdb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_sc_fifo_180 ./work/
vlog "$IP_DIR/../altera_avalon_sc_fifo_180/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
index f779ec921f150c5785ca9083eb10327c2afdbebd..1a6e4e1ee4bb0e5a2c60a0180f457e2140ab51eb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_bytes_to_packets_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
index 288cfc78e3977b6ed4cee998b70b950a4217bb55..5399369f80dc9e53407739de92814c1c9cc6cd84 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_packets_to_bytes_180 ./work/
vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_180/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
index 04119490cc72a68a433aaa8b6ec7cbdc1b302d07..543fd5e973a9516aa61464633a21b1da9a5850c9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
@@ -29,42 +29,42 @@
#vlib ./work/ ;# Assume library work already exist
#
vmap altera_emif_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180_dzobyri.v" -work altera_emif_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180_lwknerq.v" -work altera_emif_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180_ebfu2ha.v" -work altera_emif_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180_nz3mdxa.v" -work altera_emif_180
vmap altera_emif_arch_nf_180 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.sv" -work altera_emif_arch_nf_180
# ddr4_4g_2000
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.sv" -work altera_emif_arch_nf_180
# ddr4_8g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi.sv" -work altera_emif_arch_nf_180
# ddr4_8g_2400
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_180
@@ -110,52 +110,52 @@ set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_24
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_180
vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
vmap altera_reset_controller_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_180
vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_180
vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
vmap altera_avalon_mm_bridge_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
index ab5916d893518abc4e4f33a3bb050bf85bbf8a9f..15a326cec8dafbcca19edd4ae0e243717e06c3b6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
@@ -30,28 +30,28 @@
vmap altera_emif_arch_nf_180 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.sv" -work altera_emif_arch_nf_180
# ddr4_4g_2000
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.sv" -work altera_emif_arch_nf_180
# ddr4_8g_1600
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi_io_aux.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_spx5pgi.sv" -work altera_emif_arch_nf_180
# ddr4_8g_2400
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
index 495f63d7f66fdbc97e489ec2a0b6cb76dff03f91..385052319b67e2009b1716c5e17db4df155d65a6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.v" -work altera_emif_cal_slave_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
index 392ed02a9ed2909aa46cb32251acb20a9aac4133..a5c3c36590b3094a82f565e9245dee42e7ecbd76 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
@@ -31,10 +31,10 @@
vmap altera_eth_tse_180 ./work/
# tse_sgmii_gx
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180_dm7dxyq.vhd" -work altera_eth_tse_180
# tse_sgmii_lvds
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180_zsww75y.vhd" -work altera_eth_tse_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
index decc49bbd68243c20d01fd01aa6170e8f675e4bd..ebfe3676cb19cb08a431b9203e96a6590c0d6bfe 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
@@ -28,6 +28,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_avalon_arbiter_180 ./work/
vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_180/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
index 53eec840307e3dddb80d749be624136d23631885..358035beda539eb04f5474b0b081a44f89b8bf16 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_mac_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
index 8bafa44ba2986bdb60297ae97de15809324ed787..7bb7d7873ed59c1df6cc54ff92de5c988dd65190 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_nf_lvds_terminator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
index 783b7647943c93cb49d9efab106c087081018ee3..01f18f57979d83e0f571442af961ae5312ee8a2a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_nf_phyip_terminator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
index 60d253da4700e6f78653bbccb2cccb6f3c425296..5f0cbdfbe7f9ec6e8e393ea20b8a4590cd96e6ea 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_pcs_pma_nf_lvds_180 ./work/
@@ -39,7 +39,7 @@ vmap altera_eth_tse_pcs_pma_nf_lvds_180 ./work/
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
+ #vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_lvds_180/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_lvds_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
index 7e1cd85b20e9aa5f38f610eaf4ec52c83c92ca01..c5d8719befd1072ee3d2bd73432fe5b382afa189 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_pcs_pma_nf_phyip_180 ./work/
@@ -42,7 +42,7 @@ vmap altera_eth_tse_pcs_pma_nf_phyip_180 ./work/
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_enc8b10b.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_top_autoneg.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_carrier_sense.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
- vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
+ #vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_clk_gen.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_div.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_sgmii_clk_enable.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
vlog "$IP_DIR/../altera_eth_tse_pcs_pma_nf_phyip_180/sim/mentor/altera_tse_rx_encapsulation.v" -work altera_eth_tse_pcs_pma_nf_phyip_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
index 555b4b1dc1acfb37562276564adaf388a2748b87..7d2db270093e09c09dc540b0c577063d6cc9a345 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
@@ -30,12 +30,12 @@
vmap altera_iopll_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_180_fp6fpla.vo" -work altera_iopll_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_180_abkdtja.vo" -work altera_iopll_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk200sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_qkytlfy.vo" -work altera_iopll_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
index cbcb8e1c93c8a0bc05fcade73c1db535bddc2cb5..8a6590e8bfa054ded07453f84d72a7fb3b49ad07 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
@@ -30,8 +30,8 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_ip_col_if_180 ./work/
- vlog "$IP_DIR/../altera_ip_col_if_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_180_bnb3mmy.v" -work altera_ip_col_if_180
+ vlog "$IP_DIR/../altera_ip_col_if_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_ip_col_if_180_jvd2zcq.v" -work altera_ip_col_if_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
index 8ef738a50d0a4127a5c7061e6b62699208add475..7855db26f8e5a63f80266935f967b88efec513a8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_jtag_dc_streaming_180 ./work/
vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
index b2c37f6a32e1cb0541a0684ee65e98fbdc317b23..0638a7a9520818a6dc10f6621e4bd549eee72d7a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_lvds_180 ./work/
vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_og2byry.vhd" -work altera_lvds_180
vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_zfbfxeq.vhd" -work altera_lvds_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
index 007e68b3552f5b8ba2ab72cda7fdb9201be82d00..763b27886008cbbb58ceef4c7af44f8475861e43 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
@@ -27,12 +27,12 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_lvds_core20_180 ./work/
- vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_180
- vlog "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
+ vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20.sv" -work altera_lvds_core20_180
+ vlog "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
vcom "$IP_DIR/../altera_lvds_core20_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_180_5a5vzei.vhd" -work altera_lvds_core20_180
- vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20.sv" -work altera_lvds_core20_180
- vlog "$IP_DIR/../altera_lvds_core20_180/sim/mentor/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
+ vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20.sv" -work altera_lvds_core20_180
+ vlog "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20_pll.v" -work altera_lvds_core20_180
vcom "$IP_DIR/../altera_lvds_core20_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_core20_180_kmpu4hy.vhd" -work altera_lvds_core20_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
index 35e558134d0ba248367ca538034ed85615fad1ab..80bd106da1914b57491732edf57ce30133229073 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_merlin_master_translator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
index 8e0c1568b518869cea072ae96e89b1b586c5d40e..abeccdc26435224da3598c2864522aa281d814b5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_merlin_slave_translator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
index 5079b120b623ef648fc60acbe22f4903539cce71..260516ca230f890a50041bc00838d86108f880ff 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
index 9501b499a48ffc02fda0766728a39867d88192e5..4923e9411fd1cb74b2162c30701fad84431b389b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vmap altera_remote_update_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
index 11bc0e4488a765e20b8f411acf03eb0427925476..27a2935517fe106c7374ae001c78310471dcb8ea 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vmap altera_remote_update_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
index 3677b0d802b257e01957060a0d8d60ab837c1e06..56f7ad4cbbda4691a6b9506ad554fb48c9be9d4b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_reset_controller_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
index 71be275f7fec509f9843550d70be6af80de45e1d..abf16a6330d3a5ff6fe320552e9448b3621d882f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
vmap altera_common_sv_packages ./work/
vmap altera_xcvr_atx_pll_a10_180 ./work/
@@ -50,6 +50,6 @@ vmap altera_xcvr_atx_pll_a10_180 ./work/
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/a10_xcvr_atx_pll.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_pll_embedded_debug.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/mentor/alt_xcvr_pll_avmm_csr.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_atx_pll_rcfg_opt_logic_3gt7q7a.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/ip_arria10_e1sg_transceiver_pll_10g_altera_xcvr_atx_pll_a10_180_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_atx_pll_a10_180/sim/alt_xcvr_atx_pll_rcfg_opt_logic_fdgop6i.sv" -L altera_common_sv_packages -work altera_xcvr_atx_pll_a10_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
index de3daa636de26cea6160d610e6abf7cc20d85452..278e32120b0b7699dc9134174091aababe1f8232 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
vmap altera_xcvr_fpll_a10_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
index 52b59ba51f260ca5b8e1125f695ee47a6c97f242..55ea004c209d891beb081b060bb31ce7764c2f02 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap altera_xcvr_native_a10_180 ./work/
vmap altera_common_sv_packages ./work/
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48//sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
# common dependencies
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
@@ -64,35 +64,35 @@ set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbas
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/reconfig/altera_xcvr_native_a10_reconfig_parameters.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_48
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_otmjdta.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_48_altera_xcvr_native_a10_180_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_24
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_edf7tdy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_12
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_uyp7wca.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_4
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_5bntvuq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_3
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_exiqljq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_s7t4kxy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# tse_sgmii_gx
-#set IP_DIR "$env(RADIOHDL)/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/generated/sim"
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
- vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q6y47ey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
+ vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
index efa554752b5b63b0f851024a8b4d08322d0964c4..687d9bf2eb56786c3ce70397b91a7cc46b65b486 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
vmap altera_xcvr_reset_control_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
index 1a9afe12391e5cf7f444637ea4e807d215fb7c66..79d78a02f240dca1c415e8d0655f644126eb3838 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap channel_adapter_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
index d0311d5b15da9a9e386885effc08df8f3e2f7f1f..dd0ebe9a6983d3c418dc741ba141c5c6e0a65899 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
@@ -30,10 +30,10 @@
#
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap timing_adapter_180 ./work/
- vlog -sv "$IP_DIR/../timing_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_180_osazali.sv" -work timing_adapter_180
+ vlog -sv "$IP_DIR/../timing_adapter_180/sim/ip_arria10_e1sg_ddr4_8g_1600_timing_adapter_180_ewif6gi.sv" -work timing_adapter_180
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 1dd44233827b9024d1843aefddae3c100fd659ca..3d395b250cfca9e836d1b0c2b0e1ad56f47e5551 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
vcom "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 2fb36c8f2837d83cd6a14e4d60c6d4860790171a..e4bf3a3d8940c34b163531350cf77e5c6402bdb5 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index ba381883b7ff53eea294476ed4c7964f385da470..cf358c071bf54f072d98f0b63121a4f689d0a5ec 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
vmap altmult_complex_180 ./work/
vlog "$IP_DIR/../altmult_complex_180/synth/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.v" -work altmult_complex_180
#vlog "$IP_DIR/ip_arria10_e1sg_complex_mult_bb.v"
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index f2340e9c0b3396191ab668270c2b03239dae0973..b261fdd280e2ea5bcfc866dfa8b35250bcb56ffe 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index 6cff9fd980fabad075b1f9b189a6cc18ee680546..b36839e7c83697574b720f848e19297be32b82d3 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# OUTDATED AND NOT USED!!
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_180 ./work/
@@ -46,7 +46,7 @@ if {$IPMODEL=="PHY"} {
vcom "$IP_DIR/ip_arria10_ddio_in_1.vhd"
- set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_out_1_altera_gpio_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index f37749c422e32c23f900ed357a53554405a8294e..049a6ef228e39ed326022ff1f0d3a95b892dd12f 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -18,8 +18,8 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 2b12ee54636a8be29c114ecce7ad906af56f3f2a..45e98a1c47c1cdb750252cbc8127c4b8c522e99b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index bdfae1a527ec7360a9b635fadaad450739db397a..f881b77a856ecf14cdd998a97aeb7f399009c6a1 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index 53a802adb6f922eec4493a399ba2b15520732403..bb05a34afe0f020702ca784f11baa36adb2ed9a8 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index b66ce87ea766c71e152a06af1aa5a8e4ab02839f..1650d44f51fa3f3044d92b4f95ef255c00257cbf 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index 071b89b37c141a229d86cf908135def66a7ce972..1394d1d34b471707e8a33267468f54f99bd6207a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index e3f92714a83dcba04450a80ee38d3241bf2d002a..8b021c649079174643f4865f00e51914a5d9c997 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index a8eaa493ac3393b0bbebdb602f4899e53c37fb39..2cfbbd059dcf6e3019c3a096a5a80134b437337d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index b8807be1cbac9e867a056e1109fc3b78eb58830b..63035b8e07cf7d4c2fab84dd72af2a901f992a48 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index c56d4e91ac0ae8415517841e40cfc662afa4abe5..d7825e3efccb1b18a4fbc75e91125692ee7ddfd1 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 73fa6f8f5cb184d7c358a03796294b5ce0f29bbe..2638a04129dcefb3efba4a0a34592ae7cba6381d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index 1c94289e4d03d0cd87864442dcd74619393057bb..e1a1ada8b9df39c2a88790b9e7c2107a134d0cdf 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index a85380c61312ffdadf6d576ef01e280872adccea..35a821a428baccf96d358096efd150f4fe3a0099 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index 2e7823626a535a6f2706e337d5d3c32e2fd9ae8d..a708e8034288473042353c0399da5b1e911d2580 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index c24a4453fb09031527b604d89d7475d075b3e972..cb20b751c9200f10605bc6a094fcf85c1741da75 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index 3e676ef14e722598489a37a607136cdc4dcdaa49..1f003afd9b87762c816f1489a7b13e2a25cbca59 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index d2d006e2d481e00f05910e4dfc475332b3b93f42..88fb5e8af9c9b49f57f739f9f1582b281ca95fa2 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index 0e5423362c380d4ccbb445b10987a6d13f6ae7c2..f93c3aa93962977cf4ee463ef6f74334ac921081 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index 34c167c2497a22c7007173ad80330ed6b4206e69..0c3631101ad1539dbe263e445c8b1fcd5246f675 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index 905108fd60f8a981c997c71d2c59e22041661706..7d453434694e4580eae0dce1ddcac777a90d8d72 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index c56852378e4dcf2d109222a790d47ed0c9e1d2a8..aecf94dba75fa49f6bfd0abaa96016f08bcea4d1 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index f7ef50002f70065e1d834ead6bea36d2dcc8c917..1c211f6ce77eab1736f2cdb2293dc4304b866453 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
vcom "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 08af64258001803ea9686b948edbfdc10803a66c..8baf093d8acfa333d161d9bb74c5255017caa205 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -19,7 +19,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index cc872305e161b0cf98793f58b1e12a667709a0f1..8d098b26ceb1370b059ca79aa43962b836ce3e2e 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
vmap ip_arria10_e1sg_mult_add4 ./work/
vmap altera_mult_add_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index fbbe1b65ff3129a58295dd3a7f56cbda22d61e09..ea8fcb393b6adc0ff7a367cbc523904718395e74 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index dc2b3c96ca25f18a7841942c2dad42e4f328bfd1..4914557dcbf6e8011aaaabd48f793397caf55446 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index f607c01d581180894d6286da324a0147a7eb2001..2736172286780eef136f59560c695e36175ecae3 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index 132cf13a39329e6285987fed19743f4ffabcf3b7..ba97097939ca4de7b4a7a139c604614f9f2b37eb 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index 0cce3fc118b064405f3fc2f237c2b4a02a45b4b3..94616624b526848a0e4b0c8717d4689323dc6a03 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index 932f302d9d96624112fafbc1e7dc83ce92c495a2..6a653bed8e598ff98f9d053f348709a2ff126639 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index 3ec7a3f76d6c860faae85bf5ac5a382fcb0a91dc..3a060c4715c7aba668425aa5038bd97499e30e4f 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index 8b564fb73544411f119b7e2e0e34cf1b81844e11..f63bb14398415de260495a90bd9aa70900ea1aed 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index 16c61f7f28d85da50a849bec60e5bf8d761d2b25..31257d769e70a8d1dd370da0c2fa8117d34d8af6 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index e26265c54cd9a986be536c0949dcd2143349d98c..615c1c48fa0d844ea7845145659dfdf8ca3b48e1 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index 08c36c7e6bcc2a280e0dcba3453d8ba55f3654a9..1343afc3b59a5e9269152b2004812ae90625603b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index 5c0565879faeac0947fed6c7571e4103242fca50..39e0cd631e72644f1d203e6246b3e77b332265e8 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index abcdbf22cc16c47fcadfc702ea2e9482c9095a73..d18342e3f5b6c088b1bf6e2fd5d7c3c7c8052276 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index b9156b864897ed9d78b03580ed0fd2b0fe7463e5..1770bb5f7782fc68ff8f718df218d3203306034a 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index 629cba7f7a4e8cec7f9c2a37dc9ae7898bcb7c1d..edfbbf4c076bd1b13d4585581613c7852b6f8a5c 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index 68c9111689a661c1e9b5a928a5f32bd955efc0eb..be6b835b4b71ca53fe0866975eafc68a02e34b81 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index 7368bf10991125a08073858188d8e74eb31bfa22..40eb599bd5eeca7d2b25ad20a2ecbd476ff9b671 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index a91bebfc952e54d693b1279867e91e545a756d12..d270a6265bc624ef99883794931b78f88e83bd5b 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index b5719ceac4d032ff9c92abcb5cb3216bd8c19634..054104dc07c3b24b524a7788406455f2a9fb01f3 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index ea142b01622532d6cb79ed852ebedf97fb158b56..141472385b783d24ddbaeec56d95475194a95e27 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index 3511f9a0ed21b8660e4f4b2da5c4adfbaa66273d..f8fb076632d1d86a5d74b02e2955fba283668de2 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
vmap altera_temp_sense_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index 3a8ba97963858f302a0dc8f46c81cdbf77771892..dc7c730a2a04dd8aeceebf329166991f094349d7 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -16,7 +16,7 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index f617a12f5d9d209864d412bd664683c5c9a82b4d..e62b1ca32fe1b8a4193c2430560173f2a1683a2b 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index 6329d7b22f54e43a657e947c681bdddac1fbebcf..dd46f8828c49145ff271bd4e5b14337efc84f590 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index ba94e344a2ca081d030668981ecf969b07b1727c..11105df2aa676cf5ba385c58df0d9d1baaf61c13 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 60010795b023c1a122b3d5e90ec47dd1b340e4c1..845503837a5dfe9426d87ab1bb73b5b783452931 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index fd5a7bc7719f94555af255293aff785d34418539..a708530bf8c518ffe2fde52eb1429107c1e0e8bc 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index aa73121a3ee10b311f75cabfba33af3301b33850..773136b36096cea98d84092d774e3d25c1db2664 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 0ad509c4025e59ea36f83da13c80677d38d06345..87293d4a5f12876019d2b7d5d54a5d096f152139 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index d3794145930c67bd250f2f82c12375a1f68ca3c8..701ee178494a83be2a135ec4af244aacdfcae21e 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index 0833cb18e8f07bb5152068ce939d05aba2378e06..a1f71285b5e64a3f00788fa4c6b41d89ff31c8bb 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index 8fa8802924a08a317941e21f0f36d3932a5e2b7e..cd49f3f7c3dd6915594bd1429e64fc2644586c81 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index 836cee4bf3453795b5a61e6bce19b02c9a815dc4..d8cfa66c847d5e9da0d6eb5ed42b1ed9796760f3 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index bdd12be22408232f0669599bac4485ea440656f2..665debaad2883da7b3bdea3b76a9e8fdf91a87d6 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index 383a8782680eab7d6254a00963132ca681559e02..cf074f0e1289216d80eb041de92b8aa70362d851 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index d49c7f2bd1e2ad1d0aac544eb528015ded4a0e35..50f05c573ab1ddd8830edecdb15ff1edaeaf32e1 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index 94f8d367a2eb08ffba6af223ef99ba13f607cbba..33ff4e89d52bf16f33c80575ded3d2fa8b12e1ca 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 3e605c0391cb56c3aa26e987ec4db1d5371d2452..407be614316506e93eb94c72fc9431b08a1adbea 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index 1fc77affb68809f428646014ab2513854bcc38cb..bb52a542f9bafa95f952930ec469aad1dd88f17f 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index faaf0e7c04dac38ce875cf364921dd7e105bde6f..f4641c545e4a779fd590c6e3a595b3222c5af0cb 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -18,7 +18,7 @@ modelsim_compile_ip_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index c8e891987bb324caeb48769adbd1055678e9d4ad..0d545f56085d38f564ecf515fb55d4b47b39aab2 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(HDL_BUILD_DIR)/unb2b/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
vmap ip_arria10_e1sg_voltage_sense ./work/
vmap altera_voltage_sensor_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index 1c29d76bf22a8c1da8d0c2cc9e91999fa9244a87..31f2ef1a72c10398288456b6229f87847570601a 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -17,7 +17,7 @@ test_bench_files =
[quartus_project_file]
quartus_qip_files =
- $HDL_BUILD_DIR/unb2b/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =