diff --git a/libraries/technology/ip_arria10/hdllib.cfg b/libraries/technology/ip_arria10/hdllib.cfg new file mode 100644 index 0000000000000000000000000000000000000000..1e0e0c75375179ab301c25ad98d9adb55a49ced6 --- /dev/null +++ b/libraries/technology/ip_arria10/hdllib.cfg @@ -0,0 +1,11 @@ +hdl_lib_name = ip_arria10 +hdl_library_clause_name = ip_arria10_lib +hdl_lib_uses = + +build_sim_dir = $HDL_BUILD_DIR +build_synth_dir = + +synth_files = + ip_arria10_ram_crw_crw.vhd + +test_bench_files = diff --git a/libraries/technology/ip_arria10/ip_arria10_ram_crw_crw.vhd b/libraries/technology/ip_arria10/ip_arria10_ram_crw_crw.vhd new file mode 100644 index 0000000000000000000000000000000000000000..5f75a7747db5f1a2a52926f1473f6ceed2de83cb --- /dev/null +++ b/libraries/technology/ip_arria10/ip_arria10_ram_crw_crw.vhd @@ -0,0 +1,244 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altera_syncram + +-- ============================================================ +-- File Name: ip_arria10_ram_crw_crw.vhd +-- Megafunction Name(s): +-- altera_syncram +-- +-- Simulation Library Files(s): +-- altera_lnsim +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1a10.2 Build 359 02/04/2014 SJ Full Version +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_lnsim; +USE altera_lnsim.altera_lnsim_components.all; + +ENTITY ip_arria10_ram_crw_crw IS + PORT + ( + address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + address_b : IN STD_LOGIC_VECTOR (4 DOWNTO 0); + clock_a : IN STD_LOGIC := '1'; + clock_b : IN STD_LOGIC ; + data_a : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + data_b : IN STD_LOGIC_VECTOR (17 DOWNTO 0); + enable_a : IN STD_LOGIC := '1'; + enable_b : IN STD_LOGIC := '1'; + rden_a : IN STD_LOGIC := '1'; + rden_b : IN STD_LOGIC := '1'; + wren_a : IN STD_LOGIC := '0'; + wren_b : IN STD_LOGIC := '0'; + q_a : OUT STD_LOGIC_VECTOR (17 DOWNTO 0); + q_b : OUT STD_LOGIC_VECTOR (17 DOWNTO 0) + ); +END ip_arria10_ram_crw_crw; + + +ARCHITECTURE SYN OF ip_arria10_ram_crw_crw IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (17 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0); + +BEGIN + q_a <= sub_wire0(17 DOWNTO 0); + q_b <= sub_wire1(17 DOWNTO 0); + + altera_syncram_component : altera_syncram + GENERIC MAP ( + address_reg_b => "CLOCK1", + clock_enable_input_a => "NORMAL", + clock_enable_input_b => "NORMAL", + clock_enable_output_a => "BYPASS", + clock_enable_output_b => "BYPASS", + indata_reg_b => "CLOCK1", + init_file => "fft_3n1024sin.hex", + intended_device_family => "Arria 10", + lpm_type => "altera_syncram", + numwords_a => 32, + numwords_b => 32, + operation_mode => "BIDIR_DUAL_PORT", + outdata_aclr_a => "NONE", + outdata_aclr_b => "NONE", + outdata_reg_a => "UNREGISTERED", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ", + widthad_a => 5, + widthad_b => 5, + width_a => 18, + width_b => 18, + width_byteena_a => 1, + width_byteena_b => 1 + ) + PORT MAP ( + clock0 => clock_a, + clocken1 => enable_b, + wren_a => wren_a, + clock1 => clock_b, + rden_a => rden_a, + wren_b => wren_b, + address_a => address_a, + data_a => data_a, + rden_b => rden_b, + address_b => address_b, + clocken0 => enable_a, + data_b => data_b, + q_a => sub_wire0, + q_b => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "5" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria 10" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "576" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "fft_3n1024sin.hex" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "0" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "1" +-- Retrieval info: PRIVATE: rden NUMERIC "1" +-- Retrieval info: LIBRARY: altera_lnsim altera_lnsim.altera_lnsim_components.all +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: INIT_FILE STRING "fft_3n1024sin.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altera_syncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "18" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" +-- Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]" +-- Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]" +-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" +-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" +-- Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]" +-- Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]" +-- Retrieval info: USED_PORT: enable_a 0 0 0 0 INPUT VCC "enable_a" +-- Retrieval info: USED_PORT: enable_b 0 0 0 0 INPUT VCC "enable_b" +-- Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]" +-- Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]" +-- Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a" +-- Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b" +-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" +-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" +-- Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0 +-- Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 +-- Retrieval info: CONNECT: @clocken0 0 0 0 0 enable_a 0 0 0 0 +-- Retrieval info: CONNECT: @clocken1 0 0 0 0 enable_b 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0 +-- Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0 +-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0 +-- Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 +-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 +-- Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0 +-- Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ram_crw_crw.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ram_crw_crw.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ram_crw_crw.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ram_crw_crw.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ram_crw_crw_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ram_crw_crw_waveforms.html TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_arria10_ram_crw_crw_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_lnsim