From b28b7e1c87ff0dc8e01907c8d5bc35445a4a5162 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 22 Dec 2014 12:12:45 +0000
Subject: [PATCH] Added func_tech_ddr_dq_address() and
func_tech_ddr_ctrl_address().
---
libraries/technology/ddr/tech_ddr_pkg.vhd | 52 +++++++++++++++++------
1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index dd82d7973d..3911f580c6 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -60,7 +60,7 @@ PACKAGE tech_ddr_pkg IS
FUNCTION func_tech_ddr_module_size( c_ddr : t_c_tech_ddr) RETURN NATURAL; -- return DDR module size in GByte
CONSTANT c_tech_ddr_max : t_c_tech_ddr := ("none", 800, TRUE, 16, 16, 10, 3, 64, 8, 8, 2, 2, 2, 1, 2, 14, 4, 2, 64, 7); -- maximum ranges for record field definitions
- CONSTANT c_tech_ddr_4g_800m : t_c_tech_ddr := ("none", 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 2, 1, 2, 14, 4, 2, 64, 7);
+ CONSTANT c_tech_ddr_4g : t_c_tech_ddr := ("none", 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 2, 1, 2, 14, 4, 2, 64, 7);
CONSTANT c_tech_ddr3_4g_800m_master : t_c_tech_ddr := ("DDR3", 800, TRUE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 2, 1, 2, 14, 4, 2, 64, 7);
CONSTANT c_tech_ddr3_4g_800m_slave : t_c_tech_ddr := ("DDR3", 800, FALSE, 15, 15, 10, 3, 64, 8, 8, 2, 2, 2, 1, 2, 14, 4, 2, 64, 7);
@@ -111,23 +111,23 @@ PACKAGE tech_ddr_pkg IS
chip : STD_LOGIC_VECTOR(c_tech_ddr_max.cs_w_w -1 DOWNTO 0);
bank : STD_LOGIC_VECTOR(c_tech_ddr_max.ba_w -1 DOWNTO 0);
row : STD_LOGIC_VECTOR(c_tech_ddr_max.a_row_w-1 DOWNTO 0);
- column : STD_LOGIC_VECTOR(c_tech_ddr_max.a_col_w-1 DOWNTO 0);
+ col : STD_LOGIC_VECTOR(c_tech_ddr_max.a_col_w-1 DOWNTO 0);
END RECORD;
TYPE t_tech_ddr_addr_arr IS ARRAY(NATURAL RANGE <>) OF t_tech_ddr_addr;
- CONSTANT c_tech_ddr_addr_lo : t_tech_ddr_addr := ((OTHERS=>'0'),
- (OTHERS=>'0'),
- (OTHERS=>'0'),
- (OTHERS=>'0'));
- CONSTANT c_tech_ddr_addr_hi_4gb_800m : t_tech_ddr_addr := ((OTHERS=>'1'),
- (OTHERS=>'1'),
- (OTHERS=>'1'),
- TO_UVEC(2**c_tech_ddr_4g_800m.a_col_w-c_tech_ddr_4g_800m.rsl, c_tech_ddr_max.a_col_w));
- CONSTANT c_tech_ddr_addr_hi_sim : t_tech_ddr_addr := ((OTHERS=>'0'),
- (OTHERS=>'0'),
- TO_UVEC(3, c_tech_ddr_max.a_row_w),
- TO_UVEC(2**c_tech_ddr_4g_800m.a_col_w-c_tech_ddr_4g_800m.rsl, c_tech_ddr_max.a_col_w));
+ CONSTANT c_tech_ddr_addr_lo : t_tech_ddr_addr := ((OTHERS=>'0'),
+ (OTHERS=>'0'),
+ (OTHERS=>'0'),
+ (OTHERS=>'0'));
+ CONSTANT c_tech_ddr_addr_hi_4gb : t_tech_ddr_addr := ((OTHERS=>'1'),
+ (OTHERS=>'1'),
+ (OTHERS=>'1'),
+ TO_UVEC(2**c_tech_ddr_4g.a_col_w-c_tech_ddr_4g.rsl, c_tech_ddr_max.a_col_w));
+
+ FUNCTION func_tech_ddr_dq_address( dq_address : STD_LOGIC_VECTOR; g_tech_ddr : t_c_tech_ddr ) RETURN t_tech_ddr_addr;
+ FUNCTION func_tech_ddr_dq_address( ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_dq_address_w : NATURAL) RETURN STD_LOGIC_VECTOR;
+ FUNCTION func_tech_ddr_ctrl_address(ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_ctrl_address_w : NATURAL) RETURN STD_LOGIC_VECTOR;
-- PHY MM access signal record
CONSTANT c_tech_ddr_max_ctrl_address_w : NATURAL := 32; -- >= func_tech_ddr_ctrl_address_w(c_tech_ddr_max);
@@ -182,6 +182,30 @@ PACKAGE BODY tech_ddr_pkg IS
RETURN 2**(c_module_nof_bytes_w-c_1GB_w);
END;
+ FUNCTION func_tech_ddr_dq_address(dq_address : STD_LOGIC_VECTOR; g_tech_ddr : t_c_tech_ddr) RETURN t_tech_ddr_addr IS
+ VARIABLE v_ddr_addr : t_tech_ddr_addr := c_tech_ddr_addr_lo;
+ BEGIN
+ v_ddr_addr.chip(g_tech_ddr.cs_w_w -1 DOWNTO 0) := dq_address(g_tech_ddr.cs_w_w+g_tech_ddr.ba_w+g_tech_ddr.a_w+g_tech_ddr.a_col_w-1 DOWNTO g_tech_ddr.ba_w+g_tech_ddr.a_w+g_tech_ddr.a_col_w);
+ v_ddr_addr.bank(g_tech_ddr.ba_w -1 DOWNTO 0) := dq_address( g_tech_ddr.ba_w+g_tech_ddr.a_w+g_tech_ddr.a_col_w-1 DOWNTO g_tech_ddr.a_w+g_tech_ddr.a_col_w);
+ v_ddr_addr.row( g_tech_ddr.a_w -1 DOWNTO 0) := dq_address( g_tech_ddr.a_w+g_tech_ddr.a_col_w-1 DOWNTO g_tech_ddr.a_col_w);
+ v_ddr_addr.col( g_tech_ddr.a_col_w-1 DOWNTO 0) := dq_address( g_tech_ddr.a_col_w-1 DOWNTO 0);
+ RETURN v_ddr_addr;
+ END;
+
+ FUNCTION func_tech_ddr_dq_address(ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_dq_address_w : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ BEGIN
+ RETURN RESIZE_UVEC(ddr_addr.chip(g_tech_ddr.cs_w_w -1 DOWNTO 0) &
+ ddr_addr.bank(g_tech_ddr.ba_w -1 DOWNTO 0) &
+ ddr_addr.row( g_tech_ddr.a_row_w-1 DOWNTO 0) &
+ ddr_addr.col( g_tech_ddr.a_col_w-1 DOWNTO 0), c_dq_address_w);
+ END;
+
+ FUNCTION func_tech_ddr_ctrl_address(ddr_addr : t_tech_ddr_addr; g_tech_ddr : t_c_tech_ddr; c_ctrl_address_w : NATURAL) RETURN STD_LOGIC_VECTOR IS
+ CONSTANT c_dq_address_w : NATURAL := func_tech_ddr_dq_address_w(g_tech_ddr);
+ CONSTANT c_dq_address : STD_LOGIC_VECTOR(c_dq_address_w-1 DOWNTO 0) := func_tech_ddr_dq_address(ddr_addr, g_tech_ddr, c_dq_address_w);
+ BEGIN
+ RETURN RESIZE_UVEC(c_dq_address(c_dq_address_w-1 DOWNTO g_tech_ddr.rsl_w), c_ctrl_address_w);
+ END;
END tech_ddr_pkg;
--
GitLab