diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index e95d804fc699c49196b5e95764f559a01854ca91..573c1a56f9f3c6b1f054c8b8d5af998d8b1ca4cc 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -227,7 +227,7 @@ regression_test_vhdl =
     tb/vhdl/tb_tb_common_fanout_tree.vhd
     tb/vhdl/tb_tb_common_multiplexer.vhd
     tb/vhdl/tb_tb_common_operation_tree.vhd
-    #tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd  -- fails for unb2c
+    tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd 
     tb/vhdl/tb_tb_common_reorder_symbol.vhd
     tb/vhdl/tb_tb_common_rl.vhd
     tb/vhdl/tb_tb_common_rl_register.vhd
diff --git a/libraries/base/reorder/hdllib.cfg b/libraries/base/reorder/hdllib.cfg
index 0c4ce6f94ca7807fb3e5ce862cdc3210ba3efa8d..724281760afb7b26b69150853ab1ca7d9f862780 100644
--- a/libraries/base/reorder/hdllib.cfg
+++ b/libraries/base/reorder/hdllib.cfg
@@ -42,7 +42,7 @@ test_bench_files =
 
 regression_test_vhdl = 
     tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd   
-#    tb/vhdl/tb_tb_reorder_col.vhd    -- fails in unb2c
+    tb/vhdl/tb_tb_reorder_col.vhd 
 
 
 [modelsim_project_file]
diff --git a/libraries/base/ss/hdllib.cfg b/libraries/base/ss/hdllib.cfg
index 5495225a46843b0bd87369f65a8c7a09676ad46b..9012550aa85e882e533a24727448e18ae6199a47 100644
--- a/libraries/base/ss/hdllib.cfg
+++ b/libraries/base/ss/hdllib.cfg
@@ -20,7 +20,7 @@ test_bench_files =
     tb/vhdl/tb_tb_ss.vhd
 
 regression_test_vhdl = 
-#    tb/vhdl/tb_tb_ss.vhd  -- fails in unb2c
+    tb/vhdl/tb_tb_ss.vhd
 
 
 [modelsim_project_file]
diff --git a/libraries/io/tr_10GbE/hdllib.cfg b/libraries/io/tr_10GbE/hdllib.cfg
index 54cb4c2231fd4901b47a77a0221911fe4da9391c..8030f1911dbc7862e363fd50b7588b8b5b833f29 100644
--- a/libraries/io/tr_10GbE/hdllib.cfg
+++ b/libraries/io/tr_10GbE/hdllib.cfg
@@ -14,7 +14,7 @@ test_bench_files =
     tb/vhdl/tb_tb_tr_10GbE.vhd
 
 regression_test_vhdl = 
-#    tb/vhdl/tb_tb_tr_10GbE.vhd -- fails in unb2c
+    tb/vhdl/tb_tb_tr_10GbE.vhd
 
 
 [modelsim_project_file]
diff --git a/libraries/technology/eth_10g/hdllib.cfg b/libraries/technology/eth_10g/hdllib.cfg
index 2e4e4150d889ff951b799a0e470c39f3c70722cf..4c7a63445a617edfbe77926df45e4b1d38d32bba 100644
--- a/libraries/technology/eth_10g/hdllib.cfg
+++ b/libraries/technology/eth_10g/hdllib.cfg
@@ -26,7 +26,7 @@ test_bench_files =
     tb_tb_tech_eth_10g.vhd
     
 regression_test_vhdl = 
-#    tb_tb_tech_eth_10g.vhd -- fails in unb2c
+    tb_tb_tech_eth_10g.vhd
 
 [modelsim_project_file]
 
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
index 7e4d82cefceacecd4814eb924098c5d4a2eea6a6..7ce0b6dba3b12c0443e089b4c50d445356b55c77 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
@@ -71,6 +71,7 @@ ARCHITECTURE SYN OF ip_arria10_e2sg_ram_cr_cw IS
           outdata_aclr_b  : string;
           outdata_reg_b  : string;
           power_up_uninitialized  : string;
+          read_during_write_mode_mixed_ports : string;
           widthad_a  : integer;
           widthad_b  : integer;
           width_a  : integer;
@@ -116,6 +117,7 @@ BEGIN
             outdata_aclr_b  => "NONE",
             outdata_reg_b  => c_outdata_reg_b,
             power_up_uninitialized  => "FALSE",
+            read_during_write_mode_mixed_ports => "OLD_DATA",
             widthad_a  => g_adr_w,
             widthad_b  => g_adr_w,
             width_a  => g_dat_w,
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
index 833ac0341320c43d29064b7ca3aac725d3c3bc49..caaf0ae91d4774cacc7096bbf23eec18cfacc121 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
@@ -80,6 +80,7 @@ ARCHITECTURE SYN OF ip_arria10_e2sg_ram_crw_crw IS
           power_up_uninitialized  : string;
           read_during_write_mode_port_a  : string;
           read_during_write_mode_port_b  : string;
+          read_during_write_mode_mixed_ports : string;
           widthad_a  : integer;
           widthad_b  : integer;
           width_a  : integer;
@@ -137,6 +138,7 @@ BEGIN
             power_up_uninitialized  => "FALSE",
             read_during_write_mode_port_a  => "NEW_DATA_NO_NBE_READ",
             read_during_write_mode_port_b  => "NEW_DATA_NO_NBE_READ",
+            read_during_write_mode_mixed_ports => "OLD_DATA",
             widthad_a  => g_adr_w,
             widthad_b  => g_adr_w,
             width_a  => g_dat_w,