From b13605d267632c88f27cafe7988ea2fc2c6f1570 Mon Sep 17 00:00:00 2001
From: Reinier van der Walle <walle@astron.nl>
Date: Tue, 15 Dec 2020 10:18:41 +0100
Subject: [PATCH] renamed ta2_unb2b_channel_cross -> ta2_channel_cross
---
.../bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg | 2 +-
.../ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd | 4 ++--
.../hdllib.cfg | 10 ++++------
.../ta2_channel_cross.vhd} | 14 ++++++--------
4 files changed, 13 insertions(+), 17 deletions(-)
rename applications/ta2/ip/{ta2_unb2b_channel_cross => ta2_channel_cross}/hdllib.cfg (53%)
rename applications/ta2/ip/{ta2_unb2b_channel_cross/ta2_unb2b_channel_cross.vhd => ta2_channel_cross/ta2_channel_cross.vhd} (95%)
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
index 068a40afbf..603eece27e 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
@@ -1,6 +1,6 @@
hdl_lib_name = lofar2_unb2b_ring_bsp
hdl_library_clause_name = lofar2_unb2b_ring_bsp_lib
-hdl_lib_uses_synth = common technology dp unb2b_board diag ta2_unb2b_channel_cross ta2_unb2b_10GbE ta2_unb2b_mm_io
+hdl_lib_uses_synth = common technology dp unb2b_board diag ta2_channel_cross ta2_unb2b_10GbE ta2_unb2b_mm_io
hdl_lib_uses_sim =
hdl_lib_technology = ip_arria10_e1sg
hdl_lib_include_ip =
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index c079af5e23..7d0e278297 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -31,7 +31,7 @@
-- . M&C
-- --------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, diag_lib, ta2_unb2b_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib;
+LIBRARY IEEE, common_lib, unb2b_board_lib, technology_lib, dp_lib, diag_lib, ta2_channel_cross_lib, ta2_unb2b_10gbe_lib, ta2_unb2b_mm_io_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE common_lib.common_pkg.ALL;
@@ -469,7 +469,7 @@ BEGIN
-----------------------------------------------------------------------------
-- kernel clock crossing for from/to lane sosi
-----------------------------------------------------------------------------
- u_ta2_unb2b_channel_cross : ENTITY ta2_unb2b_channel_cross_lib.ta2_unb2b_channel_cross
+ u_ta2_channel_cross : ENTITY ta2_channel_cross_lib.ta2_channel_cross
GENERIC MAP(
g_nof_streams => 1,
g_nof_bytes => 8,
diff --git a/applications/ta2/ip/ta2_unb2b_channel_cross/hdllib.cfg b/applications/ta2/ip/ta2_channel_cross/hdllib.cfg
similarity index 53%
rename from applications/ta2/ip/ta2_unb2b_channel_cross/hdllib.cfg
rename to applications/ta2/ip/ta2_channel_cross/hdllib.cfg
index fe1dce8b99..5aacfba5f2 100644
--- a/applications/ta2/ip/ta2_unb2b_channel_cross/hdllib.cfg
+++ b/applications/ta2/ip/ta2_channel_cross/hdllib.cfg
@@ -1,12 +1,12 @@
-hdl_lib_name = ta2_unb2b_channel_cross
-hdl_library_clause_name = ta2_unb2b_channel_cross_lib
+hdl_lib_name = ta2_channel_cross
+hdl_library_clause_name = ta2_channel_cross_lib
hdl_lib_uses_synth = common technology dp
hdl_lib_uses_sim =
-hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_technology =
hdl_lib_include_ip =
synth_files =
- ta2_unb2b_channel_cross.vhd
+ ta2_channel_cross.vhd
test_bench_files =
regression_test_vhdl =
@@ -19,10 +19,8 @@ synth_top_level_entity =
quartus_copy_files =
quartus_qsf_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
diff --git a/applications/ta2/ip/ta2_unb2b_channel_cross/ta2_unb2b_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
similarity index 95%
rename from applications/ta2/ip/ta2_unb2b_channel_cross/ta2_unb2b_channel_cross.vhd
rename to applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index dcbe1ccbaa..68a19952f6 100644
--- a/applications/ta2/ip/ta2_unb2b_channel_cross/ta2_unb2b_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -19,14 +19,14 @@
-- Author:
-- . Reinier van der Walle
-- Purpose:
--- . Provide general I/O interface (BSP) for OpenCL kernel on Arria10
+-- . Provide general I/O interface (BSP) for OpenCL kernel
-- Description:
-- . This core consists of:
-- . SOP/EOP insertion (kernel channel only carries data and valid)
-- . Dual clock FIFO
-- . Clock domain transition between kernel_clk and dp_clk
-- . Details:
--- . This core was developed for use on the Uniboard2b.
+-- . This core was developed for use with OpenCL IO channels.
-- . g_nof_bytes is used to indicate the number of bytes used, this should be between 1 and 64.
-- . The data field of the ST-avalon interface is also used to provide
-- . SOP, EOP and empty meta-data. The implementation of a g_nof_bytes=8 variant is shown below.
@@ -49,7 +49,7 @@ USE common_lib.common_pkg.ALL;
USE dp_lib.dp_stream_pkg.ALL;
USE technology_lib.technology_pkg.ALL;
-ENTITY ta2_unb2b_channel_cross IS
+ENTITY ta2_channel_cross IS
GENERIC (
g_nof_streams : NATURAL;
g_nof_bytes : POSITIVE; -- Max = 64
@@ -74,10 +74,10 @@ ENTITY ta2_unb2b_channel_cross IS
kernel_snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
);
-END ta2_unb2b_channel_cross;
+END ta2_channel_cross;
-ARCHITECTURE str OF ta2_unb2b_channel_cross IS
+ARCHITECTURE str OF ta2_channel_cross IS
CONSTANT c_data_w : NATURAL := c_byte_w * g_nof_bytes;
CONSTANT c_empty_w : NATURAL := ceil_log2(g_nof_bytes);
@@ -97,7 +97,7 @@ ARCHITECTURE str OF ta2_unb2b_channel_cross IS
BEGIN
- ASSERT g_nof_bytes <= 64 REPORT "g_nof_bytes of ta2_unb2b_channel_cross is configured higher than 64" SEVERITY ERROR;
+ ASSERT g_nof_bytes <= 64 REPORT "g_nof_bytes of ta2_channel_cross is configured higher than 64" SEVERITY ERROR;
gen_streams: FOR stream IN 0 TO g_nof_streams-1 GENERATE
-- dp_snk_in -> kernel_src_out
@@ -127,7 +127,6 @@ BEGIN
---------------------------------------------------------------------------------------
u_dp_fifo_dc_tx : ENTITY dp_lib.dp_fifo_dc
GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
g_data_w => c_data_w,
g_empty_w => c_empty_w,
g_use_empty => TRUE,
@@ -191,7 +190,6 @@ BEGIN
---------------------------------------------------------------------------------------
u_dp_fifo_dc_rx : ENTITY dp_lib.dp_fifo_dc
GENERIC MAP (
- g_technology => c_tech_arria10_e1sg,
g_data_w => c_data_w,
g_empty_w => c_empty_w,
g_use_empty => TRUE,
--
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