diff --git a/libraries/io/eth/eth.peripheral.yaml b/libraries/io/eth/eth.peripheral.yaml
index 321706436eb9bc52210d67d1da407f3fb5c71fb5..c30ec856fb0ba28317a8f81e0819266a6bcdc014 100644
--- a/libraries/io/eth/eth.peripheral.yaml
+++ b/libraries/io/eth/eth.peripheral.yaml
@@ -25,14 +25,644 @@ peripherals:
# MM port for registers in the TSE IP [1]
- mm_port_name: AVS_ETH_0_TSE
mm_port_type: REG
- mm_port_description: "Registers in the TSE IP [1], handled by the Nios microprocessor."
+ mm_port_span: 1024 * MM_BUS_SIZE # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
+ mm_port_description: |
+ "Registers in the TSE IP [1], handled by the Nios microprocessor.
+ All addresses are multiplied by 4 as the last 2 bits of the address
+ are removed in VHDL."
fields:
- - - field_name: registers
- field_description: ""
- number_of_fields: 1024 # = c_tech_tse_byte_addr_w in tech_tse_pkg.vhd
- address_offset: 0x0
+ - - field_name: rev
+ field_description: |
+ ". Bits[15:0]—Set to the current version of the IP.
+ . Bits[31:16]—Customer specific revision, specified by the
+ CUST_VERSION parameter defined in the top-level file
+ generated for the instance of the IP. These bits are set to
+ 0 during the configuration of the IP."
+ address_offset: 0x00 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: scratch
+ field_description: |
+ "Scratch register. Provides a memory location for you to test
+ the device memory operation."
+ address_offset: 0x01 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: command_config
+ field_description: |
+ "MAC configuration register. Use this register to control and
+ configure the MAC function. The MAC function starts
+ operation as soon as the transmit and receive enable bits in
+ this register are turned on. Intel, therefore, recommends
+ that you configure this register last."
+ address_offset: 0x02 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: mac_0
+ field_description: |
+ "6-byte MAC primary address. The first four most significant
+ bytes of the MAC address occupy mac_0 in reverse order.
+ The last two bytes of the MAC address occupy the two least
+ significant bytes of mac_1 in reverse order.
+ For example, if the MAC address is 00-1C-23-17-4A-CB, the
+ following assignments are made:
+ mac_0 = 0x17231c00
+ mac_1 = 0x0000CB4a
+ Ensure that you configure these registers with a valid MAC
+ address if you disable the promiscuous mode (PROMIS_EN
+ bit in command_config = 0)"
+ address_offset: 0x03 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: mac_1
+ field_description: |
+ "see mac_0"
+ address_offset: 0x04 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: frm_length
+ field_description: |
+ ". Bits[15:0]—16-bit maximum frame length in bytes. The
+ IP checks the length of receive frames against this value.
+ Typical value is 1518.
+ In the 10/100 Mbps and 1000 Mbps small MAC
+ variations, this register is RO and the maximum frame
+ length is fixed to 1518.
+ . Bits[31:16]—unused."
+ address_offset: 0x05 * 4 * MM_BUS_SIZE
access_mode: RW
+ - - field_name: pause_quant
+ field_description: |
+ ". Bits[15:0]—16-bit pause quanta. Use this register to
+ specify the pause quanta to be sent to remote devices
+ when the local device is congested. The IP sets the
+ pause quanta (P1, P2) field in pause frames to the value
+ of this register.
+ The 10/100 Mbps and 1000 Mbps small MAC variations
+ do not support flow control.
+ . Bits[31:16]—unused."
+ address_offset: 0x06 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_section_empty
+ field_description: |
+ "Variable-length section-empty threshold of the receive FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold. This threshold is typically set to (FIFO Depth –
+ 16)."
+ address_offset: 0x07 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_section_full
+ field_description: |
+ "Variable-length section-full threshold of the receive FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x08 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_section_empty
+ field_description: |
+ "Variable-length section-empty threshold of the transmit
+ FIFO buffer. Use the depth of your FIFO buffer to determine
+ this threshold. This threshold is typically set to (FIFO Depth
+ – 16)."
+ address_offset: 0x09 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_section_full
+ field_description: |
+ "Variable-length section-full threshold of the transmit FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0A * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_almost_empty
+ field_description: |
+ "Variable-length almost-empty threshold of the receive FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0B * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_almost_full
+ field_description: |
+ "Variable-length almost-full threshold of the receive FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0C * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_almost_empty
+ field_description: |
+ "Variable-length almost-empty threshold of the transmit FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0D * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_almost_full
+ field_description: |
+ "Variable-length almost-full threshold of the transmit FIFO
+ buffer. Use the depth of your FIFO buffer to determine this
+ threshold."
+ address_offset: 0x0E * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: mdio_addr0
+ field_description: |
+ ". Bits[4:0]—5-bit PHY address. Set these registers to the
+ addresses of any connected PHY devices you want to
+ access. The mdio_addr0 and mdio_addr1 registers
+ contain the addresses of the PHY whose registers are
+ mapped to MDIO Space 0 and MDIO Space 1
+ respectively.
+ . Bits[31:5]—unused. Set to read-only value of 0."
+ address_offset: 0x0F * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: mdio_addr1
+ field_description: |
+ "see mdio_addr0"
+ address_offset: 0x10 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: holdoff_quant
+ field_description: |
+ ". Bit[15:0]—16-bit holdoff quanta. When you enable the
+ flow control, use this register to specify the gap between
+ consecutive XOFF requests.
+ . Bits[31:16]—unused."
+ address_offset: 0x11 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_ipg_length
+ field_description: |
+ ". Bits[4:0]—minimum IPG. Valid values are between 8 and
+ 26 byte-times. If this register is set to an invalid value,
+ the MAC still maintains a typical minimum IPG value of
+ 12 bytes between packets, although a read back to the
+ register reflects the invalid value written.
+ In the 10/100 Mbps and 1000 Mbps small MAC
+ variations, this register is RO and the register is set to a
+ fixed value of 12.
+ . Bits[31:5]—unused. Set to read-only value 0"
+ address_offset: 0x17 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: aMacID
+ field_description: |
+ "The MAC address. This register is wired to the primary MAC address
+ in the mac_0 and mac_1 registers."
+ address_offset: 0x18 * 4 * MM_BUS_SIZE
+ access_mode: RO
+ user_width: 64
+ radix: uint64
+
+ - - field_name: aFramesTransmittedOK
+ field_description: |
+ "The number of frames that are successfully transmitted including the
+ pause frames."
+ address_offset: 0x1A * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aFramesReceivedOK
+ field_description: |
+ "The number of frames that are successfully received including the
+ pause frames."
+ address_offset: 0x1B * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aFrameCheckSequenceErrors
+ field_description: |
+ "The number of receive frames with CRC error."
+ address_offset: 0x1C * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aAlignmentErrors
+ field_description: |
+ "The number of receive frames with alignment error."
+ address_offset: 0x1D * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aOctetsTransmittedOK
+ field_description: |
+ "The number of data and padding octets that are successfully
+ transmitted"
+ address_offset: 0x1E * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aOctetsReceivedOK
+ field_description: |
+ "The number of data and padding octets that are successfully
+ received, including pause frames."
+ address_offset: 0x1F * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aTxPAUSEMACCtrlFrames
+ field_description: |
+ "The number of pause frames transmitted."
+ address_offset: 0x20 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: aRxPAUSEMACCtrlFrames
+ field_description: |
+ "The number received pause frames received."
+ address_offset: 0x21 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifInErrors
+ field_description: |
+ "The number of errored frames received."
+ address_offset: 0x22 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifOutErrors
+ field_description: |
+ "The number of transmit frames with one the following errors:
+ . FIFO overflow error
+ . FIFO underflow error
+ . Frames that encounter late or excessive collision occasions
+ . Errors defined by the user application"
+ address_offset: 0x23 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifInUcastPkts
+ field_description: |
+ "The number of valid unicast frames received."
+ address_offset: 0x24 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifInMulticastPkts
+ field_description: |
+ "The number of valid multicast frames received. The count does not
+ include pause frames."
+ address_offset: 0x25 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifInBroadcastPkts
+ field_description: |
+ "The number of valid broadcast frames received."
+ address_offset: 0x26 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifOutUcastPkts
+ field_description: |
+ "The number of valid unicast and erroneous frames transmitted, as
+ well as unicast frames transmitted during late and excessive collision
+ occasions."
+ address_offset: 0x28 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifOutMulticastPkts
+ field_description: |
+ "The number of valid multicast frames transmitted, as well as
+ multicast frames transmitted during late and excessive collision
+ occasions, excluding pause frames."
+ address_offset: 0x29 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: ifOutBroadcastPkts
+ field_description: |
+ "The number of valid and erroneous broadcast frames transmitted, as
+ well as broadcast frames transmitted during late and excessive
+ collision occasions."
+ address_offset: 0x2A * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsDropEvents
+ field_description: |
+ "The number of frames that are dropped due to MAC internal errors
+ when FIFO buffer overflow persists."
+ address_offset: 0x2B * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsOctets
+ field_description: |
+ "The total number of octets received. This count includes both good
+ and errored frames."
+ address_offset: 0x2C * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts
+ field_description: |
+ "The total number of good and errored frames received."
+ address_offset: 0x2D * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsUndersizePkts
+ field_description: |
+ "The number of frames received with length less than 64 bytes,
+ including pause frames. This count does not include errored frames."
+ address_offset: 0x2E * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsOversizePkts
+ field_description: |
+ "The number of frames received that are longer than the value
+ configured in the frm_length register. This count does not include
+ errored frames."
+ address_offset: 0x2F * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts64Octets
+ field_description: |
+ "The number of 64-byte frames received. This count includes good and
+ errored frames"
+ address_offset: 0x30 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts65to127Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 65 and 127 bytes."
+ address_offset: 0x31 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts128to255Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 128 and 255 bytes."
+ address_offset: 0x32 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts256to511Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 256 and 511 bytes."
+ address_offset: 0x33 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts512to1023Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 512 and 1023 bytes."
+ address_offset: 0x34 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts1024to1518Octets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 1024 and 1518 bytes."
+ address_offset: 0x35 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsPkts1519toXOctets
+ field_description: |
+ "The number of received good and errored frames between the length
+ of 1519 and the maximum frame length configured in the
+ frm_length register."
+ address_offset: 0x36 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsJabbers
+ field_description: |
+ "Too long frames with CRC error."
+ address_offset: 0x37 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: etherStatsFragments
+ field_description: |
+ "Too short frames with CRC error."
+ address_offset: 0x38 * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: tx_cmd_stat
+ field_description: |
+ "Specifies how the MAC function processes transmit frames. When you
+ turn on the Align packet headers to 32-bit boundaries option."
+ address_offset: 0x3A * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_cmd_stat
+ field_description: |
+ "Specifies how the MAC function processes receive frames. When you
+ turn on the Align packet headers to 32-bit boundaries option"
+ address_offset: 0x3B * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: msb_aOctetsTransmittedOK
+ field_description: |
+ "Upper 32 bits of the respective statistics counters. By default all
+ statistics counters are 32 bits wide. These statistics counters can be
+ extended to 64 bits by turning on the Enable 64-bit byte counters
+ parameter.
+ To read the counter, read the lower 32 bits first, then followed by the
+ extended statistic counter bits"
+ address_offset: 0x3C * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: msb_aOctetsReceivedOK
+ field_description: |
+ "see msb_aOctetsTransmittedOK"
+ address_offset: 0x3D * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: msb_etherStatsOctets
+ field_description: |
+ "see msb_aOctetsTransmittedOK"
+ address_offset: 0x3E * 4 * MM_BUS_SIZE
+ access_mode: RO
+
+ - - field_name: pcs_control
+ field_description: |
+ "PCS control register. Use this register to control and
+ configure the PCS function."
+ address_offset: ( 0x80 + 0x00 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_status
+ field_description: |
+ "Status register. Provides information on the operation of the
+ PCS function."
+ address_offset: ( 0x80 + 0x01 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_phy_identifier_msb
+ field_description: |
+ "32-bit PHY identification register. This register is set to the
+ value of the PHY ID parameter. Bits 31:16 are written to
+ word offset 0x02. Bits 15:0 are written to word offset 0x03."
+ address_offset: ( 0x80 + 0x02 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_phy_identifier_lsb
+ field_description: |
+ "see pcs_phy_identifier_msb"
+ address_offset: ( 0x80 + 0x03 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_dev_ability
+ field_description: |
+ "Use this register to advertise the device abilities to a link
+ partner during auto-negotiation. In SGMII MAC mode, the
+ PHY does not use this register during auto-negotiation."
+ address_offset: ( 0x80 + 0x04 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_partner_ability
+ field_description: |
+ "Contains the device abilities advertised by the link partner
+ during auto-negotiation."
+ address_offset: ( 0x80 + 0x05 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_an_expansion
+ field_description: |
+ "Auto-negotiation expansion register. Contains the PCS
+ function capability and auto-negotiation status."
+ address_offset: ( 0x80 + 0x06 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_scratch
+ field_description: |
+ "Scratch register. Provides a memory location to test register
+ read and write operations."
+ address_offset: ( 0x80 + 0x10 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_rev
+ field_description: |
+ "The PCS function revision. Always set to the current version
+ of the IP."
+ address_offset: ( 0x80 + 0x11 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RO
+
+ - - field_name: pcs_link_timer_lsb
+ field_description: |
+ "21-bit auto-negotiation link timer. Set the link timer value
+ from 0 to 16 ms in 8 ns steps (125 MHz clock periods). The
+ reset value sets the link timer to 10 ms.
+ . Bits 15:0 are written to word offset 0x12. Bit 0 of word
+ offset 0x12 is always set to 0, thus any value written to
+ it is ignored.
+ . Bits 20:16 are written to word offset 0x13. The
+ remaining bits are reserved and always set to 0."
+ address_offset: ( 0x80 + 0x12 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_link_timer_msb
+ field_description: |
+ "see pcs_link_timer_lsb"
+ address_offset: ( 0x80 + 0x13 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: pcs_if_mode
+ field_description: |
+ "Interface mode. Use this register to specify the operating
+ mode of the PCS function; 1000BASE-X or SGMII."
+ address_offset: ( 0x80 + 0x14 ) * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: tx_period
+ field_description: |
+ "Clock period for timestamp adjustment on the transmit
+ datapath. The period register is multiplied by the number of
+ stages separating actual timestamp and the GMII bus.
+ . Bits 0 to 15: Period in fractional nanoseconds
+ (TX_PERIOD_FNS).
+ . Bits 16 to 24: Period in nanoseconds (TX_PERIOD_NS).
+ . Bits 25 to 31: Not used.
+ The default value for the period is 0. For 125 MHz clock, set this
+ register to 8 ns."
+ address_offset: 0xD0 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: tx_adjust_fns
+ field_description: |
+ "Timing adjustment in fractional nanoseconds"
+ address_offset: 0xD1 * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: tx_adjust_ns
+ field_description: |
+ "Timing adjustment in nanoseconds."
+ address_offset: 0xD2 * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: rx_period
+ field_description: |
+ "Clock period for timestamp adjustment on the receive datapath.
+ The period register is multiplied by the number of stages
+ separating actual timestamp and the GMII bus.
+ . Bits 0 to 15: Period in fractional nanoseconds
+ (RX_PERIOD_FNS).
+ . Bits 16 to 24: Period in nanoseconds (RX_PERIOD_NS).
+ . Bits 25 to 31: Not used.
+ The default value for the period is 0. For 125 MHz clock, set this
+ register to 8 ns."
+ address_offset: 0xD3 * 4 * MM_BUS_SIZE
+ access_mode: RW
+
+ - - field_name: rx_adjust_fns
+ field_description: |
+ "Timing adjustment in fractional nanoseconds."
+ address_offset: 0xD4 * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: rx_adjust_ns
+ field_description: |
+ "Timing adjustment in nanoseconds."
+ address_offset: 0xD5 * 4 * MM_BUS_SIZE
+ mm_width: 16
+ access_mode: RW
+
+ - - field_name: measure_valid
+ field_description: |
+ "Indicates whether the DL measurement values are
+ valid. 0: Not valid, 1: Valid"
+ address_offset: 0xE1 * 4 * MM_BUS_SIZE
+ mm_width: 1
+ bit_offset: 0
+ access_mode: RO
+
+ - - field_name: dl_reset
+ field_description: |
+ "Deterministic latency (DL) soft reset."
+ address_offset: 0xE1 * 4 * MM_BUS_SIZE
+ mm_width: 1
+ bit_offset: 1
+ access_mode: RW
+
+ - - field_name: tx_delay
+ field_description: |
+ "TX datapath latency.
+ Displays the TX datapath DL measurement values
+ measured in the i_dl_sampling_clk cycles.
+ measure_valid must be set prior taking the
+ measurement."
+ address_offset: 0xE2 * 4 * MM_BUS_SIZE
+ mm_width: 21
+ access_mode: RO
+
+ - - field_name: rx_delay
+ field_description: |
+ "RX datapath latency
+ Displays the RX datapath DL measurement values
+ measured in the i_dl_sampling_clk cycles.
+ measure_valid must be set prior taking the
+ measurement"
+ address_offset: 0xE3 * 4 * MM_BUS_SIZE
+ mm_width: 21
+ access_mode: RO
+
# MM port for registers in eth_mm_registers.vhd in the ETH module [2]
- mm_port_name: AVS_ETH_0_REG
mm_port_type: REG