diff --git a/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt b/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt new file mode 100644 index 0000000000000000000000000000000000000000..cc8af7d4b1e6f53f0f391450573548bd4527508f --- /dev/null +++ b/applications/lofar2/doc/prestudy/station2_sdp_transient_buffer.txt @@ -0,0 +1,19 @@ +Detailed design: Transient Buffer function (LIFT) + + +1) DDR4 memory per receiver input + +Bottom up: + +Per FPGA there are S_pn = 12 receiver inputs. +Per FPGA there are N_ddr = 2 DDR4 modules of V_ddr = 8 GByte each. +==> Per recveiver input N_ddr * V_ddr / S_pn = 1.33 GByte. +The receiver input data rate is f_adc = 200 MHz and sample width is W_adc = 14 b. +Assume the samples are stored in 16 b (= 2 bytes), this creates 16/14 = 14 % storage overhead +Assume 4 % storage overhead for packet header information +==> Per recveiver input T_tbuf = 1.33 GByte / (2 byte/sample) / 1.04 / f_adc = 3.2 sec maximum storage time. +==> 192 * 1.33 = 256 GByte / LB for T_tbuf = 3.2 s + +Hoe streng is de 3.33 s, mag 3.2 s ook ? +Moeten we nog grotere 16 GByte modules gaan aanschaffen en te testen met unb2c, zodat we 2x zoveel storage tijd hebben ? +