From affc8cada99caa9780f91e819d79a95ce84b19fd Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Thu, 5 Nov 2020 13:11:59 +0100
Subject: [PATCH] L2SDP-180, process review coments 4
---
libraries/base/common/src/vhdl/common_variable_delay.vhd | 6 ++----
.../base/common/tb/vhdl/tb_common_variable_delay.vhd | 9 ++++-----
.../base/common/tb/vhdl/tb_mms_common_variable_delay.vhd | 3 +++
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd
index e9399733c6..847bb54e53 100644
--- a/libraries/base/common/src/vhdl/common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd
@@ -22,7 +22,7 @@
-- Purpose:
-- . Delay input pulse by number of given delay cycles
-- Description:
--- . delay input pulse by nof_cycles_delay
+-- . delay input pulse by delay number of cycles
-- . output pulse is derived from low-high transition of input pulse.
-- . the actual pulse delay will be delay + 1, due to implementation latency of 1 clk cycle
-- --------------------------------------------------------------------------
@@ -31,7 +31,6 @@ LIBRARY IEEE, technology_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE work.common_pkg.ALL;
-
ENTITY common_variable_delay IS
GENERIC (
g_max_delay : NATURAL := 200 * 10**6
@@ -47,7 +46,6 @@ ENTITY common_variable_delay IS
);
END common_variable_delay;
-
ARCHITECTURE rtl OF common_variable_delay IS
SIGNAL i_out_val : STD_LOGIC;
@@ -71,7 +69,7 @@ BEGIN
END IF;
ELSE
nxt_delay_cnt <= delay_cnt + 1;
- IF (delay_cnt+1) = delay THEN
+ IF delay_cnt+1 = delay THEN
nxt_out_val <= '1';
END IF;
END IF;
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index c917a51f13..8e91b07b72 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -51,7 +51,6 @@ ARCHITECTURE tb OF tb_common_variable_delay IS
SIGNAL enable : STD_LOGIC := '0';
SIGNAL trigger : STD_LOGIC := '0';
SIGNAL trigger_dly : STD_LOGIC := '0';
- SIGNAL clk_cnt : NATURAL := 0;
BEGIN
clk <= (NOT clk) OR tb_end AFTER c_clk_period/2;
@@ -60,8 +59,8 @@ BEGIN
-- generate trigger signal
proc_common_gen_pulse(c_trigger_interval/2, c_trigger_interval, '1', rst, clk, trigger);
-
p_in_stimuli : PROCESS
+ VARIABLE clk_cnt : NATURAL := 0;
BEGIN
delay <= 0;
enable <= '0';
@@ -78,13 +77,13 @@ BEGIN
-- check if counted clk's = c_trigger_latency + delay
FOR i IN c_delay_arr'RANGE LOOP
delay <= c_delay_arr(i);
- clk_cnt <= 0;
+ clk_cnt := 0;
proc_common_wait_until_lo_hi(clk, trigger);
WHILE trigger_dly = '0' LOOP
- clk_cnt <= clk_cnt + 1;
+ clk_cnt := clk_cnt + 1;
proc_common_wait_some_cycles(clk, 1);
END LOOP;
- ASSERT clk_cnt = (c_trigger_latency + delay) REPORT "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency+delay) SEVERITY ERROR;
+ ASSERT clk_cnt = c_trigger_latency + delay REPORT "delay failure, got " & int_to_str(clk_cnt) & ", expect " & int_to_str(c_trigger_latency+delay) SEVERITY ERROR;
proc_common_wait_some_cycles(clk, 10);
END LOOP;
diff --git a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
index 198edb5007..39d08e87c6 100644
--- a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
@@ -23,6 +23,9 @@
-- . test bench for mms_common_variable_delay.vhd to test enable by signal mm interface
-- Description:
-- . see common_variable_delay.vhd
+-- . Only verifies mm control of enable.
+-- . Detailde verification of trigger has been done already in tb_common_variable_delay.vhd.
+-- . Here it is sufficient to use Wave window to view effect of enable on trigger.
-- --------------------------------------------------------------------------
LIBRARY IEEE;
--
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