diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index 25ce70e55c70b36afc7aa122149714156636045e..8c751dcb3925ac03f4ed0bdf0110c3a66c36865d 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -203,9 +203,9 @@ BEGIN
clk => clk,
rst => rst,
- out_of => out_of,
- out_sosi => out_sosi,
- out_adr => out_adr,
+ inp_of => out_of,
+ inp_sosi => out_sosi,
+ inp_adr => out_adr,
dvr_mosi => dvr_mosi,
wr_sosi => wr_sosi,
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index f9e9548fc75e838fbe6cba5565eb49cf2539cb3a..67a471ccf8bf7afed700c5788704fad3a61cfcc7 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -46,9 +46,9 @@ ENTITY ddrctrl_controller IS
rst : IN STD_LOGIC;
-- ddrctrl_input
- out_of : IN NATURAL;
- out_sosi : IN t_dp_sosi;
- out_adr : IN NATURAL;
+ inp_of : IN NATURAL;
+ inp_sosi : IN t_dp_sosi;
+ inp_adr : IN NATURAL;
-- io_ddr
dvr_mosi : OUT t_mem_ctlr_mosi;
@@ -100,7 +100,7 @@ BEGIN
q_reg <= d_reg WHEN rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
- p_state : PROCESS(q_reg, rst, out_of, out_sosi, out_adr)
+ p_state : PROCESS(q_reg, rst, inp_of, inp_sosi, inp_adr)
VARIABLE v : t_reg := c_t_reg_init;
@@ -116,12 +116,12 @@ BEGIN
WHEN WRITING =>
- IF TO_UVEC(out_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN -- if adr mod c_burstsize = 0
+ IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN -- if adr mod c_burstsize = 0
v.dvr_mosi.burstbegin := '1';
- IF out_adr = 0 THEN
+ IF inp_adr = 0 THEN
v.dvr_mosi.address := TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
ELSE
- v.dvr_mosi.address := TO_UVEC(out_adr-c_burstsize, dvr_mosi.address'length);
+ v.dvr_mosi.address := TO_UVEC(inp_adr-c_burstsize, dvr_mosi.address'length);
END IF;
ELSE
v.dvr_mosi.burstbegin := '0';
@@ -129,26 +129,26 @@ BEGIN
v.dvr_mosi.burstsize := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
- v.wr_sosi := out_sosi;
+ v.wr_sosi := inp_sosi;
WHEN SET_STOP =>
--setting a stop address dependend on the g_stop_percentage
- IF out_adr+c_pof_ma >= c_max_adr THEN
- v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_adr) := TO_UVEC(out_adr-c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO c_bitshift_adr);
+ IF inp_adr+c_pof_ma >= c_max_adr THEN
+ v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_adr) := TO_UVEC(inp_adr-c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO c_bitshift_adr);
ELSE
- v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_adr) := TO_UVEC(out_adr+c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO c_bitshift_adr);
+ v.stop_adr(c_adr_w-1 DOWNTO c_bitshift_adr) := TO_UVEC(inp_adr+c_pof_ma, c_adr_w)(c_adr_w-1 DOWNTO c_bitshift_adr);
END IF;
v.stop_adr(c_bitshift_adr-1 DOWNTO 0) := c_zeros;
-- still a write cyle
- IF TO_UVEC(out_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN -- adr mod 64 = 0
+ IF TO_UVEC(inp_adr, c_adr_w)(c_bitshift_adr-1 DOWNTO 0) = c_zeros THEN -- adr mod 64 = 0
v.dvr_mosi.burstbegin := '1';
- IF out_adr = 0 THEN
+ IF inp_adr = 0 THEN
v.dvr_mosi.address := TO_UVEC(c_max_adr-c_burstsize, dvr_mosi.address'length);
ELSE
- v.dvr_mosi.address := TO_UVEC(out_adr-c_burstsize, dvr_mosi.address'length);
+ v.dvr_mosi.address := TO_UVEC(inp_adr-c_burstsize, dvr_mosi.address'length);
END IF;
ELSE
v.dvr_mosi.burstbegin := '0';
@@ -156,7 +156,7 @@ BEGIN
v.dvr_mosi.burstsize := TO_UVEC(c_burstsize, dvr_mosi.burstsize'length);
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
- v.wr_sosi := out_sosi;
+ v.wr_sosi := inp_sosi;
@@ -180,7 +180,7 @@ BEGIN
v.state := RESET;
ELSIF stop_in = '1' THEN
v.state := SET_STOP;
- ELSIF v.stop_adr = TO_UVEC(out_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
+ ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING;
ELSIF v.stopped = '1' THEN
v.state := IDLE;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 6aef30ec40fee904bbad129a9ede8ad50cbc9e4c..f8cd65c9fe6f30181826bee45af27cbab47febe4 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -137,38 +137,19 @@ BEGIN
-- filling the input data vectors with the corresponding numbers
- make_data_0 : FOR J IN 0 TO c_sim_length-1 LOOP
- in_data_cnt <= in_data_cnt+1;
- fill_in_sosi_arr_0 : FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
+ run_multiple_times : FOR K in 0 TO 4 LOOP
+ make_data : FOR J IN 0 TO c_sim_length-1 LOOP
+ in_data_cnt <= in_data_cnt+1;
+ fill_in_sosi_arr_0 : FOR I IN 0 TO g_nof_streams-1 LOOP
+ in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
+ END LOOP;
+ WAIT FOR c_clk_period*1;
END LOOP;
- in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
- bsn <= ADD_UVEC(bsn, "0001", c_dp_stream_bsn_w);
- WAIT FOR c_clk_period*1;
- END LOOP;
-
- -- sending a stop signal
- stop_in <= '1';
-
- -- filling the input data vectors with the corresponding numbers
- make_data_1 : FOR J IN 0 TO c_sim_length-1 LOOP
- in_data_cnt <= in_data_cnt+1;
- fill_in_sosi_arr_1 : FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
- END LOOP;
- in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
- bsn <= ADD_UVEC(bsn, "0001", c_dp_stream_bsn_w);
- WAIT FOR c_clk_period*1;
- stop_in <= '0';
- END LOOP;
- make_data_2 : FOR J IN 0 TO c_sim_length-1 LOOP
- in_data_cnt <= in_data_cnt+1;
- fill_in_sosi_arr_2 : FOR I IN 0 TO g_nof_streams-1 LOOP
- in_sosi_arr(I).data(g_data_w-1 DOWNTO 0) <= c_total_vector(g_data_w*(I+1)+J*c_in_data_w-1 DOWNTO g_data_w*I+J*c_in_data_w);
- END LOOP;
- in_sosi_arr(0).bsn(c_dp_stream_bsn_w-1 DOWNTO 0) <= bsn(c_dp_stream_bsn_w-1 DOWNTO 0);
- bsn <= ADD_UVEC(bsn, "0001", c_dp_stream_bsn_w);
- WAIT FOR c_clk_period*1;
+ IF k = 2 THEN
+ stop_in <= '1';
+ ELSE
+ stop_in <= '0';
+ END IF;
END LOOP;
test_running <= '0';
wr_not_rd <= '0';