From af18841218bbc555688448ca73a975421c6e0299 Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Mon, 8 Jan 2018 15:44:44 +0000
Subject: [PATCH] Declared mm_file component in mm_file_pkg.vhd to avoid having
to do it in each tb or mmm file.
---
.../src/vhdl/arts_unb1_sc4_bg_mm_master.vhd | 19 -------------------
.../src/vhdl/mmm_arts_unb2a_sc4_fwd.vhd | 17 -----------------
.../src/vhdl/mmm_arts_unb2b_sc4_fwd.vhd | 18 ------------------
.../designs/rfidb/src/vhdl/mmm_unb1_rfidb.vhd | 18 ------------------
.../io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd | 16 ----------------
libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd | 16 ----------------
libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd | 16 ----------------
.../src/vhdl/mmm_unb1_eth_10g.vhd | 15 ---------------
8 files changed, 135 deletions(-)
diff --git a/applications/arts/designs/arts_unb1_sc4_bg/src/vhdl/arts_unb1_sc4_bg_mm_master.vhd b/applications/arts/designs/arts_unb1_sc4_bg/src/vhdl/arts_unb1_sc4_bg_mm_master.vhd
index 144cf29239..597a2d2370 100644
--- a/applications/arts/designs/arts_unb1_sc4_bg/src/vhdl/arts_unb1_sc4_bg_mm_master.vhd
+++ b/applications/arts/designs/arts_unb1_sc4_bg/src/vhdl/arts_unb1_sc4_bg_mm_master.vhd
@@ -112,25 +112,6 @@ ARCHITECTURE str OF arts_unb1_sc4_bg_mm_master IS
SIGNAL i_eth1g_reg_miso : t_mem_miso;
SIGNAL mm_rst_n : STD_LOGIC ;
SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
-
- ----------------------------------------------------------------------------
- -- mm_file component
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_mm_clk_period : TIME := c_mm_clk_period;
- g_update_on_change : BOOLEAN := FALSE;
- g_mm_rd_latency : NATURAL := 1
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
COMPONENT qsys_mm_master IS
PORT (
diff --git a/applications/arts/designs/arts_unb2a_sc4_fwd/src/vhdl/mmm_arts_unb2a_sc4_fwd.vhd b/applications/arts/designs/arts_unb2a_sc4_fwd/src/vhdl/mmm_arts_unb2a_sc4_fwd.vhd
index ffc4c1443c..410f71b424 100644
--- a/applications/arts/designs/arts_unb2a_sc4_fwd/src/vhdl/mmm_arts_unb2a_sc4_fwd.vhd
+++ b/applications/arts/designs/arts_unb2a_sc4_fwd/src/vhdl/mmm_arts_unb2a_sc4_fwd.vhd
@@ -167,23 +167,6 @@ ARCHITECTURE str OF mmm_arts_unb2a_sc4_fwd IS
SIGNAL sim_eth1g_eth1_reg_mosi : t_mem_mosi;
SIGNAL i_reset_n : STD_LOGIC;
- ----------------------------------------------------------------------------
- -- mm_file component
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_update_on_change : BOOLEAN := FALSE;
- g_mm_rd_latency : NATURAL := 1
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
BEGIN
----------------------------------------------------------------------------
diff --git a/applications/arts/designs/arts_unb2b_sc4_fwd/src/vhdl/mmm_arts_unb2b_sc4_fwd.vhd b/applications/arts/designs/arts_unb2b_sc4_fwd/src/vhdl/mmm_arts_unb2b_sc4_fwd.vhd
index cbf4ae50aa..b71eb0b76e 100644
--- a/applications/arts/designs/arts_unb2b_sc4_fwd/src/vhdl/mmm_arts_unb2b_sc4_fwd.vhd
+++ b/applications/arts/designs/arts_unb2b_sc4_fwd/src/vhdl/mmm_arts_unb2b_sc4_fwd.vhd
@@ -167,24 +167,6 @@ ARCHITECTURE str OF mmm_arts_unb2b_sc4_fwd IS
SIGNAL sim_eth1g_eth1_reg_mosi : t_mem_mosi;
SIGNAL i_reset_n : STD_LOGIC;
- ----------------------------------------------------------------------------
- -- mm_file component
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_update_on_change : BOOLEAN := FALSE;
- g_mm_rd_latency : NATURAL := 1
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
-
BEGIN
----------------------------------------------------------------------------
diff --git a/applications/rfidb/designs/rfidb/src/vhdl/mmm_unb1_rfidb.vhd b/applications/rfidb/designs/rfidb/src/vhdl/mmm_unb1_rfidb.vhd
index f8851fa42b..cb4825057f 100644
--- a/applications/rfidb/designs/rfidb/src/vhdl/mmm_unb1_rfidb.vhd
+++ b/applications/rfidb/designs/rfidb/src/vhdl/mmm_unb1_rfidb.vhd
@@ -189,24 +189,6 @@ ARCHITECTURE str OF mmm_unb1_rfidb IS
CONSTANT c_nof_power_detector_addr_w : NATURAL := ceil_log2(pow2(ceil_log2(c_nof_power_detect)));
CONSTANT c_reg_power_detector_multi_addr_w : NATURAL := c_reg_power_detector_addr_w + c_nof_power_detector_addr_w;
- ----------------------------------------------------------------------------
- -- mm_file component
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_mm_clk_period : TIME := c_mm_clk_period;
- g_update_on_change : BOOLEAN := FALSE;
- g_mm_rd_latency : NATURAL := 1
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
BEGIN
----------------------------------------------------------------------------
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
index 76464bc124..f91c082f14 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
@@ -103,22 +103,6 @@ ARCHITECTURE tb OF tb_ddr3_transpose IS
SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL ram_ss_ss_transp_miso : t_mem_miso := c_mem_miso_rst;
- ----------------------------------------------------------------------------
- -- Component declaration of mm_file
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_update_on_change : BOOLEAN := FALSE
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
-- Compose the Constants for the DUT
CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (g_wr_chunksize,
g_wr_nof_chunks,
diff --git a/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
index 4929e3c839..1747720b58 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
@@ -88,22 +88,6 @@ ARCHITECTURE tb OF tb_mms_ddr3 IS
SIGNAL reg_ddr3_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_ddr3_miso : t_mem_miso := c_mem_miso_rst;
- ----------------------------------------------------------------------------
- -- Component declaration of mm_file
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_update_on_change : BOOLEAN := FALSE
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
-- Compose the Constants for the DUT
CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
CONSTANT c_mts : NATURAL := 800;--1066; --800
diff --git a/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
index a5237f672e..e4aa56f962 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
@@ -96,22 +96,6 @@ ARCHITECTURE tb OF tb_seq_ddr3 IS
SIGNAL reg_ddr3_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_ddr3_miso : t_mem_miso := c_mem_miso_rst;
- ----------------------------------------------------------------------------
- -- Component declaration of mm_file
- ----------------------------------------------------------------------------
- COMPONENT mm_file
- GENERIC(
- g_file_prefix : STRING;
- g_update_on_change : BOOLEAN := FALSE
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi;
- mm_master_in : IN t_mem_miso
- );
- END COMPONENT;
-
-- Compose the Constants for the DUT
CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (g_wr_chunksize,
g_wr_nof_chunks,
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index 8f04e437f6..0acdd308d3 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -238,21 +238,6 @@ ARCHITECTURE str OF mmm_unb1_eth_10g IS
SIGNAL mm_rst_n : STD_LOGIC ;
SIGNAL sim_eth1g_reg_mosi : t_mem_mosi;
- COMPONENT mm_file IS
- GENERIC (
- g_file_prefix : STRING ;
- g_mm_clk_period : TIME := 8 ns;
- g_update_on_change : BOOLEAN := FALSE;
- g_mm_rd_latency : NATURAL := 1
- );
- PORT (
- mm_rst : IN STD_LOGIC;
- mm_clk : IN STD_LOGIC;
- mm_master_out : OUT t_mem_mosi := c_mem_mosi_rst;
- mm_master_in : IN t_mem_miso := c_mem_miso_rst
- );
- END COMPONENT mm_file;
-
COMPONENT qsys_unb1_eth_10g IS
PORT (
reg_diag_bg_reset_export : out std_logic;
--
GitLab