From aef102a085341aac6bb6969c12b6fa11a7ce52ac Mon Sep 17 00:00:00 2001
From: donker <donker@astron.nl>
Date: Wed, 21 Dec 2022 15:14:12 +0100
Subject: [PATCH] L2SDP-880, backup changes
---
.../designs/lofar2_unb2b_adc/doc/README | 2 +-
.../quartus/lofar2_unb2b_adc_pins.tcl | 4 +-
.../lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg | 96 ++---
.../lofar2_unb2b_adc_full/hdllib.cfg | 74 ++--
.../lofar2_unb2b_adc_one_node/hdllib.cfg | 52 +--
.../src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd | 2 +-
.../quartus/lofar2_unb2b_beamformer_pins.tcl | 4 +-
.../hdllib.cfg | 112 ++---
.../hdllib.cfg | 112 ++---
.../lofar2_unb2b_filterbank/hdllib.cfg | 4 +-
.../quartus/lofar2_unb2b_filterbank_pins.tcl | 4 +-
.../lofar2_unb2b_filterbank_full/hdllib.cfg | 102 ++---
.../hdllib.cfg | 94 ++--
.../quartus/lofar2_unb2b_ring_pins.tcl | 4 +-
.../lofar2_unb2b_ring_full/hdllib.cfg | 80 ++--
.../lofar2_unb2b_ring_one/hdllib.cfg | 80 ++--
.../designs/lofar2_unb2b_ring_opencl/Makefile | 2 +-
.../host/src/main.cpp | 2 +-
.../quartus/lofar2_unb2b_sdp_station_pins.tcl | 4 +-
.../disturb2_unb2b_sdp_station_full_pins.tcl | 8 +-
.../hdllib.cfg | 178 ++++----
...isturb2_unb2b_sdp_station_full_wg_pins.tcl | 6 +-
.../hdllib.cfg | 178 ++++----
.../lofar2_unb2b_sdp_station_adc/hdllib.cfg | 170 ++++----
.../lofar2_unb2b_sdp_station_adc_pins.tcl | 4 +-
.../lofar2_unb2b_sdp_station_bf/hdllib.cfg | 178 ++++----
.../lofar2_unb2b_sdp_station_bf_pins.tcl | 6 +-
.../lofar2_unb2b_sdp_station_fsub/hdllib.cfg | 178 ++++----
.../lofar2_unb2b_sdp_station_fsub_pins.tcl | 4 +-
.../lofar2_unb2b_sdp_station_full/hdllib.cfg | 178 ++++----
.../lofar2_unb2b_sdp_station_full_pins.tcl | 8 +-
.../hdllib.cfg | 178 ++++----
.../lofar2_unb2b_sdp_station_full_wg_pins.tcl | 6 +-
.../hdllib.cfg | 178 ++++----
...lofar2_unb2b_sdp_station_xsub_one_pins.tcl | 4 +-
.../hdllib.cfg | 178 ++++----
...ofar2_unb2b_sdp_station_xsub_ring_pins.tcl | 6 +-
.../designs/lofar2_unb2c_ddrctrl/hdllib.cfg | 64 +--
.../quartus/lofar2_unb2c_ddrctrl_pins.tcl | 2 +-
.../quartus/lofar2_unb2c_filterbank_pins.tcl | 4 +-
.../lofar2_unb2c_filterbank_full/hdllib.cfg | 90 ++--
.../hdllib.cfg | 90 ++--
.../quartus/lofar2_unb2c_ring_pins.tcl | 4 +-
.../lofar2_unb2c_ring_full/hdllib.cfg | 76 ++--
.../lofar2_unb2c_ring_one/hdllib.cfg | 76 ++--
.../quartus/lofar2_unb2c_sdp_station_pins.tcl | 4 +-
.../disturb2_unb2c_sdp_station_full_pins.tcl | 8 +-
.../hdllib.cfg | 174 ++++----
...isturb2_unb2c_sdp_station_full_wg_pins.tcl | 6 +-
.../hdllib.cfg | 174 ++++----
.../lofar2_unb2c_sdp_station_adc/hdllib.cfg | 166 +++----
.../lofar2_unb2c_sdp_station_adc_pins.tcl | 4 +-
.../lofar2_unb2c_sdp_station_bf/hdllib.cfg | 174 ++++----
.../lofar2_unb2c_sdp_station_bf_pins.tcl | 6 +-
.../hdllib.cfg | 174 ++++----
.../lofar2_unb2c_sdp_station_bf_ring_pins.tcl | 8 +-
.../lofar2_unb2c_sdp_station_fsub/hdllib.cfg | 174 ++++----
.../lofar2_unb2c_sdp_station_fsub_pins.tcl | 4 +-
.../lofar2_unb2c_sdp_station_full/hdllib.cfg | 174 ++++----
.../lofar2_unb2c_sdp_station_full_pins.tcl | 8 +-
.../hdllib.cfg | 174 ++++----
.../lofar2_unb2c_sdp_station_full_wg_pins.tcl | 6 +-
.../hdllib.cfg | 174 ++++----
...lofar2_unb2c_sdp_station_xsub_one_pins.tcl | 4 +-
.../hdllib.cfg | 174 ++++----
...ofar2_unb2c_sdp_station_xsub_ring_pins.tcl | 6 +-
.../hardware/lofar2_unb2b_ring_bsp/hdllib.cfg | 4 +-
.../scripts/pre_flow_pr.tcl | 20 +-
.../ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg | 8 +-
.../ta2_unb2b_bsp/scripts/pre_flow_pr.tcl | 20 +-
.../ta2/designs/ta2_unb2b_mm_demo/Makefile | 2 +-
.../ta2_unb2b_mm_demo/host/src/main.cpp | 2 +-
.../ta2/designs/ta2_unb2b_qsfp_demo/Makefile | 2 +-
.../ta2_unb2b_qsfp_demo/host/src/main.cpp | 2 +-
applications/ta2/doc/README.txt | 20 +-
.../ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl | 2 +-
.../ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl | 2 +-
.../ta2/ip/ta2_unb2b_40GbE/hdllib.cfg | 4 +-
.../ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl | 2 +-
.../ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.tcl | 2 +-
.../ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl | 2 +-
.../ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.tcl | 2 +-
.../designs/unb1_bn_capture/hdllib.cfg | 16 +-
.../quartus/unb1_bn_capture_pins.tcl | 10 +-
.../designs/unb1_bn_terminal_bg/hdllib.cfg | 12 +-
.../quartus/unb1_bn_terminal_bg_pins.tcl | 12 +-
boards/uniboard1/designs/unb1_ddr3/doc/README | 4 +-
boards/uniboard1/designs/unb1_ddr3/hdllib.cfg | 10 +-
.../unb1_ddr3/quartus/unb1_ddr3_pins.tcl | 4 +-
.../designs/unb1_ddr3_reorder/doc/README | 4 +-
.../quartus/unb1_ddr3_reorder_pins.tcl | 2 +-
.../unb1_ddr3_reorder_dual_rank/hdllib.cfg | 10 +-
.../unb1_ddr3_reorder_single_rank/hdllib.cfg | 10 +-
.../designs/unb1_ddr3_transpose/doc/README | 4 +-
.../designs/unb1_ddr3_transpose/hdllib.cfg | 10 +-
.../quartus/unb1_ddr3_transpose_pins.tcl | 2 +-
.../designs/unb1_fn_terminal_db/hdllib.cfg | 6 +-
.../uniboard1/designs/unb1_heater/doc/README | 4 +-
.../uniboard1/designs/unb1_heater/hdllib.cfg | 6 +-
.../unb1_heater/quartus/unb1_heater_pins.tcl | 8 +-
.../uniboard1/designs/unb1_minimal/doc/README | 10 +-
.../designs/unb1_minimal/doc/sopc-to-qsys.txt | 2 +-
.../uniboard1/designs/unb1_minimal/hdllib.cfg | 2 +-
.../quartus/unb1_minimal_pins.tcl | 8 +-
.../unb1_minimal_mm_arbiter/hdllib.cfg | 6 +-
.../revisions/unb1_minimal_qsys/hdllib.cfg | 6 +-
.../unb1_minimal_qsys_wo_pll/hdllib.cfg | 6 +-
.../revisions/unb1_minimal_sopc/hdllib.cfg | 6 +-
.../unb1_terminal_bg_mesh_db/hdllib.cfg | 8 +-
boards/uniboard1/designs/unb1_test/doc/README | 14 +-
.../unb1_test/quartus/unb1_test_pins.tcl | 4 +-
.../revisions/unb1_test_10GbE/hdllib.cfg | 6 +-
.../unb1_test_10GbE_tx_only/hdllib.cfg | 6 +-
.../revisions/unb1_test_1GbE/hdllib.cfg | 6 +-
.../quartus/unb1_test_1GbE_pins.tcl | 4 +-
.../revisions/unb1_test_all/hdllib.cfg | 12 +-
.../revisions/unb1_test_ddr/hdllib.cfg | 12 +-
.../quartus/unb1_test_ddr_pins.tcl | 4 +-
.../unb1_test_ddr_16g_MB_I/hdllib.cfg | 10 +-
.../quartus/unb1_test_ddr_16g_MB_I_pins.tcl | 2 +-
.../unb1_test_ddr_16g_MB_II/hdllib.cfg | 10 +-
.../quartus/unb1_test_ddr_pins_16g_MB_II.tcl | 2 +-
.../unb1_test_ddr_16g_MB_I_II/hdllib.cfg | 10 +-
.../unb1_test_ddr_16g_MB_I_II_pins.tcl | 4 +-
.../revisions/unb1_test_ddr_MB_I/hdllib.cfg | 10 +-
.../revisions/unb1_test_ddr_MB_II/hdllib.cfg | 10 +-
.../unb1_test_ddr_MB_I_II/hdllib.cfg | 10 +-
.../quartus/unb1_test_ddr_pins.tcl | 4 +-
.../designs/unb1_tr_10GbE/hdllib.cfg | 8 +-
.../uniboard1/libraries/unb1_board/hdllib.cfg | 4 +-
.../quartus/pinning/BACK_NODE_allpins.tcl | 4 +-
.../quartus/pinning/BACK_NODE_pins.tcl | 6 +-
.../quartus/pinning/COMMON_NODE_pins.tcl | 16 +-
.../quartus/pinning/FRONT_NODE_allpins.tcl | 4 +-
.../quartus/pinning/FRONT_NODE_pins.tcl | 6 +-
.../quartus/pinning/pins_tr_back_pcs.tcl | 4 +-
.../quartus/pinning/pins_tr_front_pcs.tcl | 8 +-
.../quartus/pinning/pins_tr_front_pcs_clk.tcl | 2 +-
.../quartus/pinning/pins_tr_mesh_pcs.tcl | 4 +-
.../unb1_board/quartus/unb1_board.qsf | 2 +-
.../unb1_board/quartus/unb1_board_head.qsf | 4 +-
.../unb1_board/quartus/unb1_board_tail.qsf | 4 +-
boards/uniboard2/designs/unb2_led/hdllib.cfg | 4 +-
.../unb2_led/quartus/unb2_minimal_pins.tcl | 2 +-
.../uniboard2/designs/unb2_minimal/doc/README | 10 +-
.../uniboard2/designs/unb2_minimal/hdllib.cfg | 6 +-
.../quartus/unb2_minimal_pins.tcl | 2 +-
boards/uniboard2/designs/unb2_test/doc/README | 10 +-
.../unb2_test/quartus/unb2_test_pins.tcl | 6 +-
.../revisions/unb2_test_10GbE/hdllib.cfg | 6 +-
.../quartus/unb2_test_10GbE_pins.tcl | 4 +-
.../revisions/unb2_test_1GbE/hdllib.cfg | 6 +-
.../quartus/unb2_test_1GbE_pins.tcl | 2 +-
.../revisions/unb2_test_all/hdllib.cfg | 6 +-
.../quartus/unb2_test_all_pins.tcl | 6 +-
.../revisions/unb2_test_ddr_MB_I/hdllib.cfg | 8 +-
.../quartus/unb2_test_ddr_MB_I_pins.tcl | 4 +-
.../revisions/unb2_test_ddr_MB_II/hdllib.cfg | 8 +-
.../quartus/unb2_test_ddr_MB_II_pins.tcl | 4 +-
.../unb2_test_ddr_MB_I_II/hdllib.cfg | 8 +-
.../quartus/unb2_test_ddr_MB_I_II_pins.tcl | 4 +-
.../unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd | 2 +-
.../unb2_board/quartus/unb2_board.qsf | 2 +-
.../designs/unb2a_heater/doc/README.txt | 10 +-
.../designs/unb2a_heater/hdllib.cfg | 6 +-
.../quartus/unb2a_heater_pins.tcl | 2 +-
.../uniboard2a/designs/unb2a_led/hdllib.cfg | 4 +-
.../unb2a_led/quartus/unb2a_minimal_pins.tcl | 2 +-
.../designs/unb2a_minimal/doc/README.txt | 18 +-
.../designs/unb2a_minimal/hdllib.cfg | 6 +-
.../quartus/unb2a_minimal_pins.tcl | 2 +-
.../designs/unb2a_test/doc/README.txt | 16 +-
.../unb2a_test/quartus/unb2a_test_pins.tcl | 6 +-
.../revisions/unb2a_test_10GbE/hdllib.cfg | 8 +-
.../quartus/unb2a_test_10GbE_pins.tcl | 4 +-
.../revisions/unb2a_test_1GbE/hdllib.cfg | 6 +-
.../quartus/unb2a_test_1GbE_pins.tcl | 2 +-
.../revisions/unb2a_test_all/hdllib.cfg | 6 +-
.../quartus/unb2a_test_all_pins.tcl | 6 +-
.../revisions/unb2a_test_ddr_MB_I/hdllib.cfg | 8 +-
.../quartus/unb2a_test_ddr_MB_I_pins.tcl | 4 +-
.../revisions/unb2a_test_ddr_MB_II/hdllib.cfg | 8 +-
.../quartus/unb2a_test_ddr_MB_II_pins.tcl | 4 +-
.../unb2a_test_ddr_MB_I_II/hdllib.cfg | 8 +-
.../quartus/unb2a_test_ddr_MB_I_II_pins.tcl | 4 +-
.../src/vhdl/qsys_unb2a_test_pkg.vhd | 2 +-
boards/uniboard2a/doc/unb2a_release_notes.txt | 20 +-
.../unb2a_board/quartus/unb2a_board.qsf | 2 +-
.../designs/unb2b_arp_ping/doc/README | 10 +-
.../designs/unb2b_arp_ping/hdllib.cfg | 4 +-
.../quartus/unb2b_minimal_pins.tcl | 2 +-
.../designs/unb2b_heater/doc/README.txt | 10 +-
.../designs/unb2b_heater/hdllib.cfg | 50 +--
.../quartus/unb2b_heater_pins.tcl | 2 +-
.../uniboard2b/designs/unb2b_jesd/hdllib.cfg | 2 +-
.../revisions/unb2b_jesd_node0/hdllib.cfg | 2 +-
.../revisions/unb2b_jesd_node3/hdllib.cfg | 2 +-
.../designs/unb2b_minimal/doc/README | 4 +-
.../designs/unb2b_minimal/hdllib.cfg | 50 +--
.../quartus/unb2b_minimal_pins.tcl | 2 +-
.../revisions/unb2b_minimal_125m/hdllib.cfg | 52 +--
.../designs/unb2b_test/doc/README.txt | 16 +-
.../unb2b_test/quartus/unb2b_test_pins.tcl | 6 +-
.../revisions/unb2b_test_10GbE/hdllib.cfg | 8 +-
.../quartus/unb2b_test_10GbE_pins.tcl | 4 +-
.../unb2b_test_ddr_MB_I_II/hdllib.cfg | 112 ++---
.../quartus/unb2b_test_ddr_MB_I_II_pins.tcl | 4 +-
.../src/vhdl/qsys_unb2b_test_pkg.vhd | 2 +-
.../unb2b_board/quartus/unb2b_board.qsf | 2 +-
.../uniboard2c/designs/unb2c_led/hdllib.cfg | 4 +-
.../unb2c_led/quartus/unb2c_minimal_pins.tcl | 2 +-
.../designs/unb2c_minimal/doc/README.txt | 6 +-
.../designs/unb2c_minimal/hdllib.cfg | 46 +-
.../quartus/unb2c_minimal_pins.tcl | 2 +-
.../designs/unb2c_test/doc/README.txt | 12 +-
.../revisions/unb2c_test_10GbE/hdllib.cfg | 136 +++---
.../quartus/unb2c_test_10GbE_pins.tcl | 4 +-
.../revisions/unb2c_test_1GbE_I/hdllib.cfg | 136 +++---
.../quartus/unb2c_test_1GbE_I_pins.tcl | 2 +-
.../revisions/unb2c_test_1GbE_II/hdllib.cfg | 136 +++---
.../quartus/unb2c_test_1GbE_II_pins.tcl | 2 +-
.../revisions/unb2c_test_ddr/hdllib.cfg | 136 +++---
.../quartus/unb2c_test_ddr_pins.tcl | 4 +-
.../revisions/unb2c_test_ddr_16G/hdllib.cfg | 130 +++---
.../revisions/unb2c_test_heater/hdllib.cfg | 136 +++---
.../quartus/unb2c_test_heater_pins.tcl | 2 +-
.../revisions/unb2c_test_jesd204b/hdllib.cfg | 136 +++---
.../quartus/unb2c_test_jesd204b_pins.tcl | 4 +-
.../revisions/unb2c_test_minimal/hdllib.cfg | 136 +++---
.../quartus/unb2c_test_minimal_pins.tcl | 2 +-
.../unb2c_board/quartus/unb2c_board.qsf | 2 +-
doc/erko_hdl_design_article.txt | 2 +-
doc/erko_howto_tools.txt | 18 +-
doc/erko_radiohdl_article.txt | 4 +-
hdl_user_components.ipx | 2 +-
init_hdl.sh | 20 +-
libraries/base/common/hdllib.cfg | 2 +-
.../dp/designs/unb1_dp_offload/hdllib.cfg | 8 +-
libraries/base/dp/hdllib.cfg | 2 +-
libraries/base/reorder/hdllib.cfg | 2 +-
.../dsp/bf/designs/unb1_fn_bf/hdllib.cfg | 6 +-
.../designs/unb1_correlator/hdllib.cfg | 6 +-
.../dsp/correlator/tb/vhdl/tb_correlator.vhd | 2 +-
libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd | 2 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd | 2 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd | 2 +-
.../dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd | 4 +-
.../dsp/filter/src/python/diff_lofar_coefs | 404 +++++++++---------
.../dsp/filter/src/python/diff_pfir_coefs | 26 +-
.../filter/src/python/fil_ppf_create_mifs.py | 4 +-
.../dsp/filter/src/python/recreate_4wb_mifs | 4 +-
.../dsp/filter/src/python/recreate_pfir_mifs | 6 +-
.../dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd | 4 +-
.../tb/vhdl/tb_fil_ppf_wide_file_data.vhd | 4 +-
.../tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd | 2 +-
libraries/dsp/verify_pfb/hdllib.cfg | 6 +-
libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt | 18 +-
libraries/dsp/wpfb/hdllib.cfg | 6 +-
.../dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd | 4 +-
.../dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd | 4 +-
libraries/io/ddr/hdllib.cfg | 10 +-
libraries/io/ddr3/hdllib.cfg | 10 +-
libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd | 4 +-
.../io/eth/designs/unb1_eth_10g/hdllib.cfg | 6 +-
libraries/io/eth/hdllib.cfg | 8 +-
.../technology/ddr/tech_ddr_component_pkg.vhd | 22 +-
.../ddr/tech_ddr_mem_model_component_pkg.vhd | 4 +-
libraries/technology/hdllib.cfg | 6 +-
.../ip_arria10/clkbuf_global/compile_ip.tcl | 2 +-
.../ip_arria10/clkbuf_global/hdllib.cfg | 2 +-
.../ip_arria10/complex_mult/README.txt | 2 +-
.../ip_arria10/complex_mult/compile_ip.tcl | 2 +-
.../ip_arria10/complex_mult/hdllib.cfg | 2 +-
.../technology/ip_arria10/ddio/README.txt | 2 +-
.../technology/ip_arria10/ddio/compile_ip.tcl | 4 +-
.../technology/ip_arria10/ddio/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_4g_1600/compile_ip.tcl | 2 +-
.../ddr4_4g_1600/copy_hex_files.tcl | 2 +-
.../ip_arria10/ddr4_4g_1600/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_4g_2000/compile_ip.tcl | 2 +-
.../ddr4_4g_2000/copy_hex_files.tcl | 2 +-
.../ip_arria10/ddr4_4g_2000/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_8g_2400/compile_ip.tcl | 2 +-
.../ddr4_8g_2400/copy_hex_files.tcl | 2 +-
.../ip_arria10/ddr4_8g_2400/hdllib.cfg | 2 +-
.../ip_arria10/ddr4_mem_model_141/README.txt | 14 +-
.../ddr4_mem_model_141/compile_ip.tcl | 4 +-
.../ddr4_mem_model_141/diff_mem_model.sh | 2 +-
.../ip_arria10/ddr4_mem_model_141/hdllib.cfg | 2 +-
.../technology/ip_arria10/fifo/README.txt | 2 +-
.../flash/asmi_parallel/compile_ip.tcl | 2 +-
.../ip_arria10/flash/asmi_parallel/hdllib.cfg | 2 +-
.../flash/remote_update/compile_ip.tcl | 2 +-
.../ip_arria10/flash/remote_update/hdllib.cfg | 2 +-
.../fractional_pll_clk125/compile_ip.tcl | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 2 +-
.../fractional_pll_clk200/compile_ip.tcl | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 2 +-
.../technology/ip_arria10/mac_10g/README.txt | 2 +-
.../ip_arria10/mac_10g/compile_ip.tcl | 4 +-
.../technology/ip_arria10/mac_10g/hdllib.cfg | 4 +-
.../ip_arria10/phy_10gbase_r/README.txt | 2 +-
.../ip_arria10/phy_10gbase_r/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r/hdllib.cfg | 2 +-
.../phy_10gbase_r_12/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r_12/hdllib.cfg | 2 +-
.../phy_10gbase_r_24/compile_ip.tcl | 2 +-
.../ip_arria10/phy_10gbase_r_24/hdllib.cfg | 2 +-
.../ip_arria10/phy_10gbase_r_4/compile_ip.tcl | 2 +-
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.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 4 +-
.../ip_arria10_e2sg/tse_sgmii_gx/README.txt | 4 +-
.../tse_sgmii_gx/compile_ip.tcl | 2 +-
.../ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg | 4 +-
.../ip_arria10_e2sg/tse_sgmii_lvds/README.txt | 4 +-
.../tse_sgmii_lvds/compile_ip.tcl | 2 +-
.../ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg | 4 +-
.../voltage_sense/compile_ip.tcl | 2 +-
.../ip_arria10_e2sg/voltage_sense/hdllib.cfg | 4 +-
.../clkbuf_global/compile_ip.tcl | 2 +-
.../clkbuf_global/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/complex_mult/README.txt | 2 +-
.../complex_mult/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/complex_mult/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/ddio/README.txt | 2 +-
.../ip_arria10_e3sge3/ddio/compile_ip.tcl | 4 +-
.../ip_arria10_e3sge3/ddio/hdllib.cfg | 2 +-
.../ddr4_4g_1600/compile_ip.tcl | 2 +-
.../ddr4_4g_1600/copy_hex_files.tcl | 2 +-
.../ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg | 2 +-
.../ddr4_4g_2000/compile_ip.tcl | 2 +-
.../ddr4_4g_2000/copy_hex_files.tcl | 2 +-
.../ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg | 2 +-
.../ddr4_8g_1600/compile_ip.tcl | 2 +-
.../ddr4_8g_1600/copy_hex_files.tcl | 2 +-
.../ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg | 2 +-
.../ddr4_8g_2400/compile_ip.tcl | 2 +-
.../ddr4_8g_2400/copy_hex_files.tcl | 2 +-
.../ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/fifo/README.txt | 2 +-
.../flash/asmi_parallel/compile_ip.tcl | 2 +-
.../flash/asmi_parallel/hdllib.cfg | 2 +-
.../flash/remote_update/compile_ip.tcl | 2 +-
.../flash/remote_update/hdllib.cfg | 2 +-
.../fractional_pll_clk125/compile_ip.tcl | 2 +-
.../fractional_pll_clk125/hdllib.cfg | 2 +-
.../fractional_pll_clk200/compile_ip.tcl | 2 +-
.../fractional_pll_clk200/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/mac_10g/README.txt | 2 +-
.../ip_arria10_e3sge3/mac_10g/compile_ip.tcl | 4 +-
.../ip_arria10_e3sge3/mac_10g/hdllib.cfg | 4 +-
.../mult_add4/compile_ip.tcl | 2 +-
.../phy_10gbase_r/compile_ip.tcl | 2 +-
.../phy_10gbase_r/hdllib.cfg | 2 +-
.../phy_10gbase_r_12/compile_ip.tcl | 2 +-
.../phy_10gbase_r_12/hdllib.cfg | 2 +-
.../phy_10gbase_r_24/compile_ip.tcl | 2 +-
.../phy_10gbase_r_24/hdllib.cfg | 2 +-
.../phy_10gbase_r_4/compile_ip.tcl | 2 +-
.../phy_10gbase_r_4/hdllib.cfg | 2 +-
.../phy_10gbase_r_48/compile_ip.tcl | 2 +-
.../phy_10gbase_r_48/hdllib.cfg | 2 +-
.../pll_clk125/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/pll_clk125/hdllib.cfg | 2 +-
.../pll_clk200/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/pll_clk200/hdllib.cfg | 2 +-
.../pll_clk25/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/pll_clk25/hdllib.cfg | 2 +-
.../pll_xgmii_mac_clocks/compile_ip.tcl | 2 +-
.../pll_xgmii_mac_clocks/hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/ram/README.txt | 2 +-
.../temp_sense/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/temp_sense/hdllib.cfg | 2 +-
.../transceiver_pll_10g/compile_ip.tcl | 2 +-
.../transceiver_pll_10g/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../transceiver_reset_controller_1/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../transceiver_reset_controller_4/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../hdllib.cfg | 2 +-
.../ip_arria10_e3sge3/tse_sgmii_gx/README.txt | 4 +-
.../tse_sgmii_gx/compile_ip.tcl | 2 +-
.../ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg | 2 +-
.../tse_sgmii_lvds/README.txt | 4 +-
.../tse_sgmii_lvds/compile_ip.tcl | 2 +-
.../tse_sgmii_lvds/hdllib.cfg | 2 +-
.../voltage_sense/compile_ip.tcl | 2 +-
.../voltage_sense/hdllib.cfg | 2 +-
.../ddr3_mem_model/compile_ip.tcl | 2 +-
.../ip_stratixiv/ddr3_mem_model/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../ddr3_uphy_16g_dual_rank_800/hdllib.cfg | 4 +-
.../ddr3_uphy_4g_800_master/compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../ddr3_uphy_4g_800_master/hdllib.cfg | 4 +-
.../ddr3_uphy_4g_800_slave/compile_ip.tcl | 2 +-
.../ddr3_uphy_4g_800_slave/copy_hex_files.tcl | 2 +-
.../ddr3_uphy_4g_800_slave/hdllib.cfg | 2 +-
.../compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../hdllib.cfg | 4 +-
.../compile_ip.tcl | 2 +-
.../copy_hex_files.tcl | 2 +-
.../hdllib.cfg | 4 +-
.../technology/ip_stratixiv/flash/hdllib.cfg | 2 +-
.../ip_stratixiv/mac_10g/compile_ip.tcl | 2 +-
.../ip_stratixiv/mac_10g/hdllib.cfg | 2 +-
.../ip_stratixiv/phy_xaui/compile_ip.tcl | 2 +-
.../ip_stratixiv/phy_xaui/compile_ip_soft.tcl | 2 +-
.../ip_stratixiv/phy_xaui/hdllib.cfg | 4 +-
.../mac_10g/tech_mac_10g_component_pkg.vhd | 2 +-
.../technology/tse/tech_tse_component_pkg.vhd | 16 +-
786 files changed, 4570 insertions(+), 4570 deletions(-)
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/doc/README b/applications/lofar2/designs/lofar2_unb2b_adc/doc/README
index 35b46c0a8b..edb74b356a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/doc/README
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/doc/README
@@ -9,7 +9,7 @@ Quick steps to compile
generate_ip_libs unb2b
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+ $HDL_WORK/libraries/technology/technology_select_pkg.vhd
-> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl
index da85c19f65..9244ccb60c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/quartus/lofar2_unb2b_adc_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg
index d2d66a2cb7..ef40079698 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/hdllib.cfg
@@ -25,7 +25,7 @@ quartus_copy_files =
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
../../quartus/lofar2_unb2b_adc.sdc
@@ -36,54 +36,54 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_6ch_200MHz/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_6ch_200MHz/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_3.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_4.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_5.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_6.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_7.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_8.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_nios2_gen2_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_3.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_4.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_5.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_6.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_7.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_8.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_nios2_gen2_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
index 2edaaa6255..fc8bd8e67f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/hdllib.cfg
@@ -29,7 +29,7 @@ quartus_copy_files =
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
../../quartus/lofar2_unb2b_adc.sdc
@@ -40,43 +40,43 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_full/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_full/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jesd204b.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
index 9779c2a248..29ba8f0685 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/hdllib.cfg
@@ -28,13 +28,13 @@ quartus_copy_files =
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_pre_files =
../../quartus/lofar2_unb2b_adc.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_adc_pins.tcl
@@ -42,31 +42,31 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_one_node/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc_one_node/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_adc/ip/qsys_lofar2_unb2b_adc/qsys_lofar2_unb2b_adc_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index c8d5c25862..c0e0c53696 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -27,7 +27,7 @@ PACKAGE qsys_lofar2_unb2b_adc_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
- -- $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
+ -- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
-----------------------------------------------------------------------------
component qsys_lofar2_unb2b_adc is
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
index 851a631d74..d4023a141d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/quartus/lofar2_unb2b_beamformer_pins.tcl
@@ -19,9 +19,9 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
# unb2b_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
#
#=====================
# QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg
index 2a794ca3f2..51d2dc58c7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/hdllib.cfg
@@ -20,18 +20,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_beamformer.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_beamformer.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_beamformer_pins.tcl
@@ -39,60 +39,60 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer_one_node/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer_one_node/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/hdllib.cfg
index d3bd995b59..248bb88cd7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/hdllib.cfg
@@ -20,18 +20,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_beamformer.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_beamformer_256MHz.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_beamformer_pins.tcl
@@ -39,60 +39,60 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer_one_node_256MHz/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer_one_node_256MHz/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_beamformer/ip/qsys_lofar2_unb2b_beamformer/qsys_lofar2_unb2b_beamformer_timer_0.ip
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_filterbank/hdllib.cfg
index 93d1ea62af..991c0be800 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/hdllib.cfg
@@ -18,8 +18,8 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
src/data data
[quartus_project_file]
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank_pins.tcl
index da85c19f65..9244ccb60c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/quartus/lofar2_unb2b_filterbank_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg
index 755479f56e..b30519171a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/hdllib.cfg
@@ -20,18 +20,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_filterbank.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_filterbank.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_filterbank_pins.tcl
@@ -39,54 +39,54 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank_full/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank_full/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_enable.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_enable.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_stat_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_jesd_ctrl.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/hdllib.cfg
index cb30c6f691..da80c20962 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/hdllib.cfg
@@ -20,18 +20,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_filterbank.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_filterbank_256MHz.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_filterbank_pins.tcl
@@ -39,50 +39,50 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank_full_256MHz/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank_full_256MHz/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_filterbank/ip/qsys_lofar2_unb2b_filterbank/qsys_lofar2_unb2b_filterbank_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl
index ca41236b96..e59b18c7d7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/quartus/lofar2_unb2b_ring_pins.tcl
@@ -18,9 +18,9 @@
# Derived from lofar2_unb2b_sdp_station_pins.tcl and unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl.
# We cannot source unb2b_10GbE_pins.tcl as it causes synthesis errors when assignments are defined
# for transceiver pins that are not in the top-level design
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
# unb2b_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
#
#=====================
# QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg
index 071e3cc01f..3f4e585e18 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/hdllib.cfg
@@ -22,16 +22,16 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_ring.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_ring_pins.tcl
@@ -39,44 +39,44 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_full/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_full/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg
index 5a3a7349ae..dbcc6b9dde 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/hdllib.cfg
@@ -22,16 +22,16 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_ring.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2b_ring_pins.tcl
@@ -39,44 +39,44 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_one/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring_one/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_diag_bg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_rx.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_bsn_monitor_v2_ring_tx.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_diag_bg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_bsn_at_sync.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_block_validate_err.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_lane.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_dp_xonoff_local.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_ring_lane_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_ring/ip/qsys_lofar2_unb2b_ring/qsys_lofar2_unb2b_ring_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
index fca2daaed3..2369c30f37 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/Makefile
@@ -23,7 +23,7 @@ endif
UNB2B_BSP=lofar2_unb2b_ring_bsp
# Compile directory
-BUILDDIR=$(RADIOHDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
+BUILDDIR=$(HDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
##############################
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
index a26be673bb..eb495f9ccd 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
+++ b/applications/lofar2/designs/lofar2_unb2b_ring_opencl/host/src/main.cpp
@@ -23,7 +23,7 @@
* . Test the lofar2_unb2b_ring OpenCL application in emulator
* Description:
* . Run: -> make lofar2_unb2b_ring
-* . Navigate to -> cd $RADIOHDL_WORK/unb2b/OpenCL/lofar2_unb2b_ring/bin
+* . Navigate to -> cd $HDL_WORK/unb2b/OpenCL/lofar2_unb2b_ring/bin
* . Execute -> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
* *********************************************************************** */
#include <CL/cl_ext_intelfpga.h>
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
index 736d08b812..a134bc9977 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
@@ -19,9 +19,9 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
# unb2b_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
#
#=====================
# QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl
index b85bc78b08..950d72471a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full_pins.tcl
@@ -18,9 +18,9 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg
index fc9f9b0be2..d59ee987fc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -22,18 +22,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
disturb2_unb2b_sdp_station_full_pins.tcl
@@ -41,91 +41,91 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+ $HDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl
index 689b010fb8..5a2689dbd5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg_pins.tcl
@@ -18,8 +18,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
index c94035c6cf..58d08abe19 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -22,18 +22,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
disturb2_unb2b_sdp_station_full_wg_pins.tcl
@@ -41,91 +41,91 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+ $HDL_BUILD_DIR/unb2b/quartus/disturb2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
index 47e72aafd1..839400dd1f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/hdllib.cfg
@@ -26,7 +26,7 @@ quartus_copy_files =
../../src/data data
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
@@ -37,91 +37,91 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_adc/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_adc/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl
index 1951a9467d..8c991166e1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc_pins.tcl
@@ -18,7 +18,7 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
index cbc98f7daa..79b8a20c51 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/hdllib.cfg
@@ -18,7 +18,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -26,18 +26,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
lofar2_unb2b_sdp_station_bf_pins.tcl
@@ -45,91 +45,91 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_bf/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_bf/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl
index 4c0efdf4ec..1672b0bbb8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf_pins.tcl
@@ -18,8 +18,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
index a44d4c512b..dc55442463 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/hdllib.cfg
@@ -19,24 +19,24 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
lofar2_unb2b_sdp_station_fsub_pins.tcl
@@ -44,91 +44,91 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_fsub/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_fsub/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl
index 1951a9467d..8c991166e1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub_pins.tcl
@@ -18,7 +18,7 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
index d42226b852..7281d24cac 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -22,18 +22,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
lofar2_unb2b_sdp_station_full_pins.tcl
@@ -41,91 +41,91 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl
index b85bc78b08..950d72471a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full_pins.tcl
@@ -18,9 +18,9 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg
index 8c6453b5bb..14859fd073 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -22,18 +22,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
lofar2_unb2b_sdp_station_full_wg_pins.tcl
@@ -41,91 +41,91 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_full_wg/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
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+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl
index 689b010fb8..5a2689dbd5 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg_pins.tcl
@@ -18,8 +18,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
index b1e3cfd9e4..76ce67ed20 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/hdllib.cfg
@@ -19,24 +19,24 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
lofar2_unb2b_sdp_station_xsub_one_pins.tcl
@@ -44,91 +44,91 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_one/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_one/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
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+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl
index 1951a9467d..8c991166e1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one_pins.tcl
@@ -18,7 +18,7 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
index 84b35008e1..aa6235c94f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/hdllib.cfg
@@ -15,7 +15,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -23,18 +23,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
# use lofar2_unb2b_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2b_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ #$HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
@@ -42,91 +42,91 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_ring/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station_xsub_ring/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_ram_st_bst.ip
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+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/lofar2_unb2b_sdp_station/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
index 29347861db..97ab5f9c74 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring_pins.tcl
@@ -18,8 +18,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/lofar2_unb2b_sdp_station_ring_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
index b04f1f5de3..bc2b72485e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/hdllib.cfg
@@ -29,10 +29,10 @@ quartus_copy_files =
src/data data
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/lofar2_unb2c_ddrctrl_pins.tcl
@@ -40,38 +40,38 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_bsn_buf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_data_buf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_wg_wideband_arr.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_stop_in.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_io_ddr.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_bsn_buf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_data_buf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_ram_wg_wideband_arr.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_stop_in.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_wg_wideband_arr.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_io_ddr.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ddrctrl/ip/qsys_lofar2_unb2c_ddrctrl/qsys_lofar2_unb2c_ddrctrl_reg_ddrctrl_ctrl_state.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl_pins.tcl
index a1a336bbef..9815b4c119 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/quartus/lofar2_unb2c_ddrctrl_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
# module I:
set_location_assignment PIN_AP20 -to MB_I_OU.a[0]
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/quartus/lofar2_unb2c_filterbank_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_filterbank/quartus/lofar2_unb2c_filterbank_pins.tcl
index 1ff32447a5..6a53d3230e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/quartus/lofar2_unb2c_filterbank_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/quartus/lofar2_unb2c_filterbank_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/hdllib.cfg
index 1b5687d9fb..244663c8e8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/hdllib.cfg
@@ -23,12 +23,12 @@ quartus_copy_files =
../../quartus .
../../src/data data
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_filterbank.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_filterbank.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2c_filterbank_pins.tcl
@@ -36,50 +36,50 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank_full/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank_full/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_cpu_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/hdllib.cfg
index b9ea0422e6..fe8384f70e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/hdllib.cfg
@@ -23,12 +23,12 @@ quartus_copy_files =
../../quartus .
../../src/data data
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_filterbank.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_filterbank_256MHz.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2c_filterbank_pins.tcl
@@ -36,50 +36,50 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank_full_256MHz/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank_full_256MHz/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_jesd.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_cpu_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_ram_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_diag_data_buf_jesd.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_filterbank/ip/qsys_lofar2_unb2c_filterbank/qsys_lofar2_unb2c_filterbank_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/quartus/lofar2_unb2c_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_ring/quartus/lofar2_unb2c_ring_pins.tcl
index 603c8c4518..b8fa0d156c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/quartus/lofar2_unb2c_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/quartus/lofar2_unb2c_ring_pins.tcl
@@ -19,9 +19,9 @@
# We cannot source unb2c_10GbE_pins.tcl as it causes synthesis errors when assignments are defined
# for transceiver pins that are not in the top-level design
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
# unb2c_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
#
#=====================
# QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/hdllib.cfg
index d5e9b8343c..5855e2a31f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/hdllib.cfg
@@ -23,16 +23,16 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_ring.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2c_ring_pins.tcl
@@ -40,42 +40,42 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring_full/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring_full/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_diag_bg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_diag_bg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_bsn_at_sync.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_err.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_lane.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_local.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_lane_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_cpu_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_diag_bg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_rx.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_tx.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_diag_bg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_bsn_at_sync.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_err.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_lane.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_local.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_lane_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/hdllib.cfg
index abd7c7dc1c..996cf1ec01 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/hdllib.cfg
@@ -23,16 +23,16 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_ring.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_ring.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
../../quartus/lofar2_unb2c_ring_pins.tcl
@@ -40,42 +40,42 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring_one/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring_one/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_diag_bg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_rx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_tx.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_diag_bg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_bsn_at_sync.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_err.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_lane.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_local.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_lane_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_cpu_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_diag_bg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_rx.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_bsn_monitor_v2_ring_tx.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_diag_bg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_bsn_at_sync.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_block_validate_err.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_lane.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_dp_xonoff_local.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_ring_lane_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_ring/ip/qsys_lofar2_unb2c_ring/qsys_lofar2_unb2c_ring_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
index 99176de668..667bf5cd7f 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
@@ -19,9 +19,9 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
# unb2c_jesd204_pins contains undesired QSFP pinning
-#source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
#
#=====================
# QSFP pins
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl
index 273a627af9..7c8ae99801 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full_pins.tcl
@@ -18,9 +18,9 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg
index 1b6f161754..3d8521e7b5 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -22,18 +22,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
disturb2_unb2c_sdp_station_full_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
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+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl
index 4ceebdedad..538fc0a716 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg_pins.tcl
@@ -18,8 +18,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg
index bc7d3a1b7e..0ef2f15b98 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -22,18 +22,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
disturb2_unb2c_sdp_station_full_wg_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/disturb2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
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+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
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+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
index ae6e481694..3974ff09a4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/hdllib.cfg
@@ -27,7 +27,7 @@ quartus_copy_files =
../../src/data data
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
@@ -38,89 +38,89 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_adc/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_adc/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl
index b689b7d674..1b7902b1c0 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc_pins.tcl
@@ -18,7 +18,7 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
index 685ae42cc2..e2282099aa 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/hdllib.cfg
@@ -19,7 +19,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -27,18 +27,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
lofar2_unb2c_sdp_station_bf_pins.tcl
@@ -46,90 +46,90 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_bf/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_bf/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl
index 64f05f6634..11e645ad0e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf_pins.tcl
@@ -18,8 +18,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg
index 728eb3310d..37e0022b42 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/hdllib.cfg
@@ -16,7 +16,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -24,18 +24,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
lofar2_unb2c_sdp_station_bf_ring_pins.tcl
@@ -43,90 +43,90 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_bf_ring/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_bf_ring/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl
index 5a869c76f2..9d10b75d99 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring_pins.tcl
@@ -18,9 +18,9 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
index b7f54f3ab5..35f81be106 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/hdllib.cfg
@@ -19,24 +19,24 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
lofar2_unb2c_sdp_station_fsub_pins.tcl
@@ -44,89 +44,89 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_fsub/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_fsub/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl
index b689b7d674..1b7902b1c0 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub_pins.tcl
@@ -18,7 +18,7 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
index 65ebcc129e..6c64a49c7e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -22,18 +22,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
lofar2_unb2c_sdp_station_full_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_full/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_full/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
index 273a627af9..7c8ae99801 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full_pins.tcl
@@ -18,9 +18,9 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg
index a410171732..d76f06556d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -22,18 +22,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
lofar2_unb2c_sdp_station_full_wg_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_full_wg/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
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+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl
index 4ceebdedad..538fc0a716 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg_pins.tcl
@@ -18,8 +18,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_beamlets_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
index f0be972daf..01ef5febaf 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/hdllib.cfg
@@ -19,24 +19,24 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
lofar2_unb2c_sdp_station_xsub_one_pins.tcl
@@ -44,89 +44,89 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_xsub_one/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_xsub_one/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
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+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl
index b689b7d674..1b7902b1c0 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one_pins.tcl
@@ -18,7 +18,7 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
index 159fb7bde4..0cb7f8525d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/hdllib.cfg
@@ -14,7 +14,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
# Overwrite bf weights with sim data
../../tb/data data
@@ -22,18 +22,18 @@ modelsim_copy_files =
synth_top_level_entity =
quartus_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../../../../
../../quartus .
../../src/data data
- $RADIOHDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
+ $HDL_WORK/libraries/dsp/filter/src/hex data # FIR filter coefficients
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
# use lofar2_unb2c_sdp_station.sdc instead because BCK_REF_CLK is 200MHz, not 644.33MHz.
quartus_sdc_files =
../../quartus/lofar2_unb2c_sdp_station.sdc
- #$RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ #$HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
@@ -41,89 +41,89 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_xsub_ring/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station_xsub_ring/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
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- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_common_mm_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_avs_eth_0.ip
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+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_onchip_memory2_0.ip
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+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_bf_weights.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_equalizer_gains.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_fil_coefs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_ss_ss_wide.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_histogram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_st_xsq.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_ram_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_aduh_monitor.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bf_scale.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_align_v2_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_aligned_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_beamlet_output.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_bst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_rx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_ring_tx_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_rx_align_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_sst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_monitor_v2_xst_offload.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_source_v2.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_crosslets_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_bsn_at_sync_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_block_validate_err_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_selector.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_shiftram.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_dp_xonoff.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_hdr_dat.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nof_crosslets.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_nw_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_bf.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_ring_lane_info_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_sdp_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_si.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_enable_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_bst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_sst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_stat_hdr_dat_xst.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_eth10g.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_tr_10gbe_mac.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_reg_wg.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/lofar2_unb2c_sdp_station/ip/qsys_lofar2_unb2c_sdp_station/qsys_lofar2_unb2c_sdp_station_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
index 78cb5f4e82..303c41785c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring_pins.tcl
@@ -18,8 +18,8 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
-source $::env(RADIOHDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_jesd_pins.tcl
+source $::env(HDL_WORK)/applications/lofar2/designs/lofar2_unb2c_sdp_station/quartus/lofar2_unb2c_sdp_station_ring_pins.tcl
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
index 7affbbc077..a323e859c4 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/hdllib.cfg
@@ -28,10 +28,10 @@ quartus_copy_files =
./ .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/pre_flow_pr.tcl b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/pre_flow_pr.tcl
index b0ce83474f..09d3d0ca24 100755
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/pre_flow_pr.tcl
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/scripts/pre_flow_pr.tcl
@@ -54,13 +54,13 @@ if {[catch {set sdk_root $::env(INTELFPGAOCLSDKROOT)} result]} {
# Make sure RadioHDL installation exists
-post_message "Checking for RadioHDL installation, environment should have RADIOHDL_BUILD_DIR defined"
-if {[catch {set radiohdl_build $::env(RADIOHDL_BUILD_DIR)} result]} {
- post_message -type error "RadioHDL installation not found. Make sure RADIOHDL_BUILD_DIR are correctly set"
+post_message "Checking for RadioHDL installation, environment should have HDL_BUILD_DIR defined"
+if {[catch {set radiohdl_build $::env(HDL_BUILD_DIR)} result]} {
+ post_message -type error "RadioHDL installation not found. Make sure HDL_BUILD_DIR are correctly set"
post_message -type error "Terminating pre-flow script"
exit 2
} else {
- post_message "RADIOHDL_BUILD_DIR=$::env(RADIOHDL_BUILD_DIR)"
+ post_message "HDL_BUILD_DIR=$::env(HDL_BUILD_DIR)"
}
# Load OpenCL BSP utility functions
@@ -99,8 +99,8 @@ if {$revision_name eq "flat"} {
}
# Copy qsf file
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf"] == 1} {
- file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf radiohdl_components.qsf
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf"] == 1} {
+ file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf radiohdl_components.qsf
} else {
post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
@@ -109,16 +109,16 @@ if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_na
}
# Copy memory initialization files
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex"] == 1} {
- file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex onchip_memory2_0.hex
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex"] == 1} {
+ file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex onchip_memory2_0.hex
} else {
post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
post_message -type error "Terminating pre-flow script"
exit 2
}
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif"] == 1} {
- file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif $board_name.mif
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif"] == 1} {
+ file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif $board_name.mif
} else {
post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
index d7a2b9f42b..55b81d9db4 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
./ .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
@@ -37,8 +37,8 @@ quartus_vhdl_files =
quartus_qip_files =
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
+ $HDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/pre_flow_pr.tcl b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/pre_flow_pr.tcl
index 438f99f0a1..e9ce740ac3 100755
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/pre_flow_pr.tcl
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/scripts/pre_flow_pr.tcl
@@ -54,13 +54,13 @@ if {[catch {set sdk_root $::env(INTELFPGAOCLSDKROOT)} result]} {
# Make sure RadioHDL installation exists
-post_message "Checking for RadioHDL installation, environment should have RADIOHDL_BUILD_DIR defined"
-if {[catch {set radiohdl_build $::env(RADIOHDL_BUILD_DIR)} result]} {
- post_message -type error "RadioHDL installation not found. Make sure RADIOHDL_BUILD_DIR are correctly set"
+post_message "Checking for RadioHDL installation, environment should have HDL_BUILD_DIR defined"
+if {[catch {set radiohdl_build $::env(HDL_BUILD_DIR)} result]} {
+ post_message -type error "RadioHDL installation not found. Make sure HDL_BUILD_DIR are correctly set"
post_message -type error "Terminating pre-flow script"
exit 2
} else {
- post_message "RADIOHDL_BUILD_DIR=$::env(RADIOHDL_BUILD_DIR)"
+ post_message "HDL_BUILD_DIR=$::env(HDL_BUILD_DIR)"
}
# Load OpenCL BSP utility functions
@@ -99,8 +99,8 @@ if {$revision_name eq "flat"} {
}
# Copy qsf file
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf"] == 1} {
- file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf radiohdl_components.qsf
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf"] == 1} {
+ file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.qsf radiohdl_components.qsf
} else {
post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
@@ -109,16 +109,16 @@ if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_na
}
# Copy memory initialization files
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex"] == 1} {
- file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex onchip_memory2_0.hex
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex"] == 1} {
+ file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/onchip_memory2_0.hex onchip_memory2_0.hex
} else {
post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
post_message -type error "Terminating pre-flow script"
exit 2
}
-if {[file exists "$::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif"] == 1} {
- file copy -force $::env(RADIOHDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif $board_name.mif
+if {[file exists "$::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif"] == 1} {
+ file copy -force $::env(HDL_BUILD_DIR)/unb2b/quartus/$board_name/$board_name.mif $board_name.mif
} else {
post_message -type error "It seems that the BSP has not been initialized yet, please execute the following commands and try again:"
post_message -type error "quartus_config unb2b; run_qsys unb2b $board_name board.qsys"
diff --git a/applications/ta2/designs/ta2_unb2b_mm_demo/Makefile b/applications/ta2/designs/ta2_unb2b_mm_demo/Makefile
index 7a1ca2b438..75d6c4bce5 100644
--- a/applications/ta2/designs/ta2_unb2b_mm_demo/Makefile
+++ b/applications/ta2/designs/ta2_unb2b_mm_demo/Makefile
@@ -23,7 +23,7 @@ endif
UNB2B_BSP=ta2_unb2b_bsp
# Compile directory
-BUILDDIR=$(RADIOHDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
+BUILDDIR=$(HDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
##############################
diff --git a/applications/ta2/designs/ta2_unb2b_mm_demo/host/src/main.cpp b/applications/ta2/designs/ta2_unb2b_mm_demo/host/src/main.cpp
index 4eca458dff..4bdf250471 100644
--- a/applications/ta2/designs/ta2_unb2b_mm_demo/host/src/main.cpp
+++ b/applications/ta2/designs/ta2_unb2b_mm_demo/host/src/main.cpp
@@ -23,7 +23,7 @@
* . Test the ta2_unb2b_mm_demo OpenCL application in emulator
* Description:
* . Run: -> make ta2_unb2b_mm_demo
-* . Navigate to -> cd $RADIOHDL_WORK/unb2b/OpenCL/ta2_unb2b_mm_demo/bin
+* . Navigate to -> cd $HDL_WORK/unb2b/OpenCL/ta2_unb2b_mm_demo/bin
* . Execute -> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
* *********************************************************************** */
#include <CL/cl_ext_intelfpga.h>
diff --git a/applications/ta2/designs/ta2_unb2b_qsfp_demo/Makefile b/applications/ta2/designs/ta2_unb2b_qsfp_demo/Makefile
index cf5531d951..ee717fbe16 100644
--- a/applications/ta2/designs/ta2_unb2b_qsfp_demo/Makefile
+++ b/applications/ta2/designs/ta2_unb2b_qsfp_demo/Makefile
@@ -23,7 +23,7 @@ endif
UNB2B_BSP=ta2_unb2b_bsp
# Compile directory
-BUILDDIR=$(RADIOHDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
+BUILDDIR=$(HDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(abspath $(dir $(lastword $(MAKEFILE_LIST))))))
##############################
diff --git a/applications/ta2/designs/ta2_unb2b_qsfp_demo/host/src/main.cpp b/applications/ta2/designs/ta2_unb2b_qsfp_demo/host/src/main.cpp
index 0aa76d704d..aa7d7fb0bd 100644
--- a/applications/ta2/designs/ta2_unb2b_qsfp_demo/host/src/main.cpp
+++ b/applications/ta2/designs/ta2_unb2b_qsfp_demo/host/src/main.cpp
@@ -23,7 +23,7 @@
* . Test the ta2_unb2b_qsfp_demo OpenCL application in emulator
* Description:
* . Run: -> make ta2_unb2b_qsfp_demo
-* . Navigate to -> cd $RADIOHDL_WORK/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
+* . Navigate to -> cd $HDL_WORK/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
* . Execute -> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
* *********************************************************************** */
#include <CL/cl_ext_intelfpga.h>
diff --git a/applications/ta2/doc/README.txt b/applications/ta2/doc/README.txt
index 9edf518126..903444cfca 100644
--- a/applications/ta2/doc/README.txt
+++ b/applications/ta2/doc/README.txt
@@ -37,13 +37,13 @@ The ta2 project folder contains 4 sub-folders:
export QUARTUS_ROOTDIR=$INTEL_ROOTDIR/quartus
export QSYS_ROOTDIR=$INTEL_ROOTDIR/quartus/sopc_builder/bin
- export RADIOHDL_WORK=${GIT}/hdl
+ export HDL_WORK=${GIT}/hdl
export RADIOHDL_CONFIG=${GIT}/radiohdl/config
- export RADIOHDL_BUILD_DIR=${RADIOHDL_WORK}/build
+ export HDL_BUILD_DIR=${HDL_WORK}/build
export INTELOCLSDKROOT=$INTEL_ROOTDIR/hld
export INTELFPGAOCLSDKROOT=$INTEL_ROOTDIR/hld
- export AOCL_BOARD_PACKAGE_ROOT=$RADIOHDL_WORK/applications/ta2/bsp
+ export AOCL_BOARD_PACKAGE_ROOT=$HDL_WORK/applications/ta2/bsp
export PATH=$PATH:$INTEL_ROOTDIR/hld/bin
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$INTELOCLSDKROOT/host/linux64/lib
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$AOCL_BOARD_PACKAGE_ROOT/linux64/lib
@@ -69,14 +69,14 @@ The example application used is "ta2_unb2b_qsfp_demo", this application generate
to 40GbE and 10GbE. In emulation, this design is verified by comparing the 10GbE and 40GbE outputs to check if
the data is identical. If that is the case, the output will state "PASSED".
-- Navigate to $RADIOHDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
+- Navigate to $HDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
- First we need to compile the OpenCL application for emulation and compile the host code. This can be done by
the provided Makefile. Execute the command:
-> make ta2_unb2b_qsfp_demo
- This creates the executable "host" and the aocx file "ta2_unb2b_qsfp_demo.aocx" located at:
- $RADIOHDL_BUILD_DIR/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
+ $HDL_BUILD_DIR/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
- First navigate to that directory and then run this executable using the following commands:
- -> cd $RADIOHDL_BUILD_DIR/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
+ -> cd $HDL_BUILD_DIR/unb2b/OpenCL/ta2_unb2b_qsfp_demo/bin
-> CL_CONTEXT_EMULATOR_DEVICE_INTELFPGA=1 ./host
- At the end of the application output you should see "PASSED".
@@ -85,7 +85,7 @@ the data is identical. If that is the case, the output will state "PASSED".
The example application used is "ta2_unb2b_qsfp_demo", this application generates UDP packets and outputs them
to 40GbE and 10GbE. On hardware, you can verify the design by connecting a PC to the 40GbE (QSFP1) or
10GbE (QSFP0) output and check for incoming packets using tcpdump.
-- Navigate to $RADIOHDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
+- Navigate to $HDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
- This example design uses the "ta2_unb2b_bsp" OpenCL BSP. If you did not initialize the BSP already,
execute the commands below.
-> quartus_config unb2b; run_qsys unb2b name_of_your_BSP board.qsys;
@@ -96,7 +96,7 @@ to 40GbE and 10GbE. On hardware, you can verify the design by connecting a PC to
5. CREATING NEW OPENCL APPLICATION
-- Start by copying the example application located in $RADIOHDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
+- Start by copying the example application located in $HDL_WORK/applications/ta2/designs/ta2_unb2b_qsfp_demo
- rename the folder and ta2_unb2b_qsfp_demo.cl
- If you need to use a specific OpenCL BSP, open the Makefile and change the BSP Name into the name of the BSP
you want to use (see OVERVIEW).
@@ -106,7 +106,7 @@ to 40GbE and 10GbE. On hardware, you can verify the design by connecting a PC to
- With the provided makefile you can compile your application for UniBoard2b by executing:
make myApp.sof myApp.rbf
where "myApp" is the name of your .cl file
-- Note that by default your application is build in $RADIOHDL_BUILD_DIR/unb2b/OpenCL/myApp
+- Note that by default your application is build in $HDL_BUILD_DIR/unb2b/OpenCL/myApp
where "myApp" is the name of your design directory file. This directory includes the
Quartus project for analysis using the Quartus GUI.
- For emulation, you need to modify the host code located in host/src/main.cpp to fit your design.
@@ -139,7 +139,7 @@ script in $UPE_GEAR/peripherals
8. CREATING A NEW BSP
- BSPs are located in "$AOCL_BOARD_PACKAGE_ROOT/hardware" which is defined as
- "$RADIOHDL_WORK/applications/ta2/bsp/hardware"
+ "$HDL_WORK/applications/ta2/bsp/hardware"
- To create a new BSP it is easiest to copy an existing one. In this example we would make a copy of the
directory "ta2_unb2b_bsp" and rename it to example_bsp.
- inside the new folder "example_bsp" we need to change 2 files: board_spec.xml and hdllib.cfg
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl
index dc445ef7c5..3ce40bf35c 100755
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.tcl
@@ -1,5 +1,5 @@
post_message "Running ta2_unb2b_10GbE script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
#============================================================
# Files and basic settings
#============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl
index 0efe60d92c..ca34c982b7 100755
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.tcl
@@ -1,5 +1,5 @@
post_message "Running ta2_unb2b_1GbE script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
#============================================================
# Files and basic settings
#============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg b/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
index 5b31bc919c..a44367c089 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/hdllib.cfg
@@ -20,5 +20,5 @@ quartus_copy_files =
arria10_40g_atx_pll.ip .
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
+ $HDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_mac.ip
+ $HDL_BUILD_DIR/unb2b/quartus/ta2_unb2b_40GbE/arria10_40g_atx_pll.ip
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl
index 9745011213..84cd116af1 100755
--- a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.tcl
@@ -1,5 +1,5 @@
post_message "Running ta2_unb2b_40GbE script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
#============================================================
# Files and basic settings
#============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.tcl b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.tcl
index 703ef65a76..8327d3bcaa 100755
--- a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.tcl
+++ b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.tcl
@@ -1,5 +1,5 @@
post_message "Running ta2_unb2b_ddr script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
#============================================================
# Files and basic settings
#============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl
index 577113d356..87b4840b27 100755
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.tcl
@@ -1,5 +1,5 @@
post_message "Running ta2_unb2b_jesd204b script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
#============================================================
# Files and basic settings
#============================================================
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.tcl b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.tcl
index f175d824e5..3b68ee9c15 100755
--- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.tcl
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.tcl
@@ -1,5 +1,5 @@
post_message "Running ta2_unb2b_mm_io script"
-set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
+set radiohdl_build $::env(HDL_BUILD_DIR)
#============================================================
# Files and basic settings
#============================================================
diff --git a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
index 567a97eff3..2b487e3ad5 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_capture/hdllib.cfg
@@ -7,7 +7,7 @@ hdl_lib_technology = ip_stratixiv
synth_files =
# Commented unb1_bn_capture.vhd and SOPC because only the node is reused.
# The SOPC causes a simulation error if it not there, because it is instantiated as an entity
- #$RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
+ #$HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.vhd
src/vhdl/unb1_bn_capture_pkg.vhd
src/vhdl/unb1_bn_capture_input.vhd
src/vhdl/node_unb1_bn_capture.vhd
@@ -24,27 +24,27 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/io/i2c/tb/data data
- $RADIOHDL_WORK/libraries/base/diag/src/data data
+ $HDL_WORK/libraries/io/i2c/tb/data data
+ $HDL_WORK/libraries/base/diag/src/data data
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_bn_capture.sopc .
- $RADIOHDL_WORK/libraries/io/i2c/tb/data data
- $RADIOHDL_WORK/libraries/base/diag/src/data data
+ $HDL_WORK/libraries/io/i2c/tb/data data
+ $HDL_WORK/libraries/base/diag/src/data data
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_bn_capture_pins.tcl
-quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
+quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_capture/sopc_unb1_bn_capture.qip
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
diff --git a/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl b/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
index f2cfef868f..24c6bc2723 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
+++ b/boards/uniboard1/designs/unb1_bn_capture/quartus/unb1_bn_capture_pins.tcl
@@ -1,13 +1,13 @@
# Pin assignments
# -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
# -- 1GbE Control Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
# -- I2C Interface to Sensors
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
# -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
# -- BN_BI ADC pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
index db644b06b4..077e3e4c42 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
+ $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.vhd
src/vhdl/node_unb1_bn_terminal_bg.vhd
src/vhdl/unb1_bn_terminal_bg.vhd
@@ -16,25 +16,25 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/base/diag/src/data data
+ $HDL_WORK/libraries/base/diag/src/data data
[quartus_project_file]
synth_top_level_entity =
quartus_copy_files =
quartus/sopc_unb1_bn_terminal_bg.sopc .
- $RADIOHDL_WORK/libraries/base/diag/src/data data
+ $HDL_WORK/libraries/base/diag/src/data data
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_bn_terminal_bg_pins.tcl
-quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
+quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_bn_terminal_bg/sopc_unb1_bn_terminal_bg.qip
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl b/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
index 0a38a91c5b..5429d45602 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/quartus/unb1_bn_terminal_bg_pins.tcl
@@ -1,14 +1,14 @@
# Pin assignments
# -- GENERAL: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
# -- 1GbE Control Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
# -- I2C Interface to Sensors
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
# -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
# -- Mesh pins.
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_mesh_tr_clk_pin.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_nocmu_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3/doc/README b/boards/uniboard1/designs/unb1_ddr3/doc/README
index dcc27dd233..cb0a9e2e22 100644
--- a/boards/uniboard1/designs/unb1_ddr3/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3/doc/README
@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3] in RadionHDL
--------------------------------------------------------------
Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC:
run_sopc unb1 unb1_ddr3
diff --git a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
index 05d368e3eb..4ab692dee2 100644
--- a/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
+ $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.vhd
src/vhdl/node_unb1_ddr3.vhd
src/vhdl/mmm_unb1_ddr3.vhd
src/vhdl/unb1_ddr3.vhd
@@ -19,7 +19,7 @@ test_bench_files =
modelsim_copy_files =
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
synth_top_level_entity =
@@ -28,17 +28,17 @@ quartus_copy_files =
quartus/sopc_unb1_ddr3.sopc .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3/sopc_unb1_ddr3.qip
quartus_tcl_files =
quartus/unb1_ddr3_pins.tcl
quartus/unb1_ddr3_pins_constraints.tcl
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl b/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
index caedfb746e..25f3867aad 100644
--- a/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3/quartus/unb1_ddr3_pins.tcl
@@ -20,8 +20,8 @@
###############################################################################
# -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
# -- include the clock pin
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
index 43dcd7791d..5b3888c84c 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/doc/README
@@ -2,8 +2,8 @@ Quick steps to compile and use design [unb1_ddr3_reorder] in RadioHDL
--------------------------------------------------------------
Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC:
run_sopc unb1 unb1_ddr3_reorder
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
index 9834de8f9a..1de832edae 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/quartus/unb1_ddr3_reorder_pins.tcl
@@ -20,7 +20,7 @@
###############################################################################
# -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
# -- include the clock pin
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_general_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
index 8d92055e78..cb54b4954d 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
+ $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.vhd
../../src/vhdl/node_unb1_ddr3_reorder.vhd
../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,8 +42,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $HDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_dual_rank/sopc_unb1_ddr3_reorder.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
index a995636301..aa6cbdbaea 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_single_rank_800_master
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
+ $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.vhd
../../src/vhdl/node_unb1_ddr3_reorder.vhd
../../src/vhdl/mmm_unb1_ddr3_reorder.vhd
../../src/vhdl/unb1_ddr3_reorder.vhd
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -33,7 +33,7 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
../../quartus/unb1_ddr3_reorder_pins.tcl
@@ -42,8 +42,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
- $RADIOHDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_WORK/build/unb1/quartus/unb1_ddr3_reorder_single_rank/sopc_unb1_ddr3_reorder.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README b/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
index d2fd86f43c..7236c4c411 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_ddr3_transpose] in RadionHDL
Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC and QSYS:
run_sopc unb1 unb1_ddr3_transpose
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
index 3c859fd55b..67e8810fd9 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology = ip_stratixiv
hdl_lib_include_ip = ip_stratixiv_ddr3_uphy_4g_800_master
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
+ $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.vhd
src/vhdl/mmm_unb1_ddr3_transpose.vhd
src/vhdl/unb1_ddr3_transpose.vhd
@@ -19,7 +19,7 @@ test_bench_files =
modelsim_copy_files =
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -29,7 +29,7 @@ quartus_copy_files =
quartus/sopc_unb_ddr3_transpose.sopc .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_ddr3_transpose_pins.tcl
@@ -38,8 +38,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_ddr3_transpose/sopc_unb_ddr3_transpose.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
index 1f162d6353..d3143f5c52 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/quartus/unb1_ddr3_transpose_pins.tcl
@@ -3,5 +3,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_other_pins.tc
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
index 449b3d5636..1d39585b0a 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
+ $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.vhd
src/vhdl/mmm_unb1_fn_terminal_db.vhd
src/vhdl/unb1_fn_terminal_db.vhd
@@ -24,13 +24,13 @@ quartus_copy_files =
quartus/sopc_unb1_fn_terminal_db.sopc .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_fn_terminal_db_pins.tcl
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_fn_terminal_db/sopc_unb1_fn_terminal_db.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_heater/doc/README b/boards/uniboard1/designs/unb1_heater/doc/README
index 4b3e99c67c..9f98f9ab08 100644
--- a/boards/uniboard1/designs/unb1_heater/doc/README
+++ b/boards/uniboard1/designs/unb1_heater/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_heater] in RadionHDL
Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC and QSYS:
run_qsys unb1 unb1_heater
diff --git a/boards/uniboard1/designs/unb1_heater/hdllib.cfg b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
index b142a97e96..7d927f97f9 100644
--- a/boards/uniboard1/designs/unb1_heater/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_heater/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
quartus/qsys_unb1_heater.qsys .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_heater_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_heater/qsys_unb1_heater/synthesis/qsys_unb1_heater.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl b/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
index ff00994603..18d3f53057 100644
--- a/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
+++ b/boards/uniboard1/designs/unb1_heater/quartus/unb1_heater_pins.tcl
@@ -19,8 +19,8 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/README b/boards/uniboard1/designs/unb1_minimal/doc/README
index a0085f2f59..d6d943c2fd 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/README
+++ b/boards/uniboard1/designs/unb1_minimal/doc/README
@@ -4,8 +4,8 @@ Quick steps to compile and use design [unb1_minimal] in RadionHDL
Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py
Generate MMM for SOPC and QSYS:
run_sopc unb1 unb1_minimal_sopc
@@ -58,12 +58,12 @@ Convert .sof to .rbf:
Send to LCU capture5:
- scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/ # QSYS
+ scp $HDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_qsys.rbf capture5:~/rbf/ # QSYS
or:
- scp $RADIOHDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/ # SOPC
+ scp $HDL_WORK/build/quartus/unb1_minimal_qsys/unb1_minimal_sopc.rbf capture5:~/rbf/ # SOPC
# Now login on capture5 and use pythonscript to program flash:
- cd $RADIOHDL_WORK/boards/uniboard1/designs/unb1_minimal/tb/python
+ cd $HDL_WORK/boards/uniboard1/designs/unb1_minimal/tb/python
# for example use frontnode 0 on uniboard 0:
python tc_unb1_minimal.py --gn 0 --seq REGMAP,FLASH -s ~/rbf/unb1_minimal_qsys.rbf # QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt b/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
index 883ec70f72..7e1166a161 100644
--- a/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
+++ b/boards/uniboard1/designs/unb1_minimal/doc/sopc-to-qsys.txt
@@ -37,7 +37,7 @@ run: rm -rf ~/svn/UniBoard_FP7/RadioHDL/trunk/build/*
../../quartus/qsys_unb1_minimal.qsys .
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+ $HDL_BUILD_DIR/quartus/unb1_minimal/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
11. For future compilations the file qsys_unb1_minimal.qsys
(after SOPC->QSYS it is this file: ~/RadioHDL/trunk/build/quartus/unb1_minimal/sopc_unb1_minimal.qsys)
diff --git a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
index 83c59ab9e8..f78ab28d3c 100644
--- a/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
+ $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.vhd
src/vhdl/qsys_unb1_minimal_pkg.vhd
src/vhdl/mmm_unb1_minimal.vhd
src/vhdl/unb1_minimal.vhd
diff --git a/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl b/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
index ff00994603..18d3f53057 100644
--- a/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
+++ b/boards/uniboard1/designs/unb1_minimal/quartus/unb1_minimal_pins.tcl
@@ -19,8 +19,8 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
index 13fa7738f7..5ebd2daf7e 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
qsys_unb1_minimal_mm_arbiter.qsys .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_minimal_pins.tcl
@@ -32,7 +32,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_mm_arbiter/qsys_unb1_minimal_mm_arbiter/synthesis/qsys_unb1_minimal_mm_arbiter.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
index 0cb052797c..bcf12edfc3 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../quartus/qsys_unb1_minimal.qsys .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_minimal_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys/qsys_unb1_minimal/synthesis/qsys_unb1_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
index ba9098f82f..980f92714a 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
../../quartus/qsys_wo_pll_unb1_minimal.qsys .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_minimal_pins.tcl
@@ -34,7 +34,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal/synthesis/qsys_wo_pll_unb1_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
index 872744005a..38f930dfce 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
../../quartus/sopc_unb1_minimal.sopc .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_minimal_pins.tcl
@@ -32,7 +32,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_minimal_sopc/sopc_unb1_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
index 0179234f75..460efd6411 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
+ $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.v
src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -27,16 +27,16 @@ quartus_copy_files =
src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_terminal_bg_mesh_db_pins.tcl
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_terminal_bg_mesh_db/qsys_unb1_terminal_bg_mesh_db/synthesis/qsys_unb1_terminal_bg_mesh_db.qip
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/doc/README b/boards/uniboard1/designs/unb1_test/doc/README
index 9939ae7eeb..56275c5acb 100644
--- a/boards/uniboard1/designs/unb1_test/doc/README
+++ b/boards/uniboard1/designs/unb1_test/doc/README
@@ -16,16 +16,16 @@ The following revisions are available for unb1_test (see the directories in ../r
-> In case of a new installation, the IP's have to be generated for Stratix IV.
- In the: $RADIOHDL_WORK/libraries/technology/ip_stratixiv
+ In the: $HDL_WORK/libraries/technology/ip_stratixiv
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+ $HDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb1
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb1
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb1
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb1
2. Generate MMM for QSYS (select one of these revisions):
@@ -91,7 +91,7 @@ Convert .sof to .rbf:
Send to LCU (capture5):
# for example the unb1_test_10GbE revision:
- scp $RADIOHDL_WORK/build/quartus/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.rbf capture5:~/rbf/
+ scp $HDL_WORK/build/quartus/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.rbf capture5:~/rbf/
# Now login on capture5 and use pythonscript to program flash:
cd unb1_test/tb/python
@@ -118,10 +118,10 @@ defining the pinning:
2. unb1_test_ddr_MB_I_II_pins_constraints.tcl (pin attributes like termination etc..)
The 2nd tcl file can be created with Quartus. Here are the steps:
-- generate the IP's by running: $RADIOHDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
+- generate the IP's by running: $HDL_WORK/libraries/technology/ip_stratixiv/generate-all-ip.sh
- Start synthesis in the Quartus GUI. Only the Analysis step!!
- Then in Quartus click: Tools/TclScripts.
- Open the Tcl file: $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
+ Open the Tcl file: $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_p0_pin_assignments.tcl
Click Run.
- Then Continue synthesis with Fitter, or restart with Analysis.
- Copy the generated build/unb1_test_ddr_MB_I_II.qsf file to ./designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_MB_I_II_pins_constraints.tcl
diff --git a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
index 27ecdf6551..5a9cbf2f03 100644
--- a/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/quartus/unb1_test_pins.tcl
@@ -85,6 +85,6 @@ set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
# -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
index cd2f29bacf..1557c1cb2a 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_10GbE_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
index 78d24bed85..e51c661b00 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_10GbE_tx_only_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_10GbE_tx_only/qsys_unb1_test/synthesis/qsys_unb1_test.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
index aca536d5a7..7f32db6b5b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_1GbE_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_1GbE/qsys_unb1_test/synthesis/qsys_unb1_test.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
index 27ecdf6551..5a9cbf2f03 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/quartus/unb1_test_1GbE_pins.tcl
@@ -85,6 +85,6 @@ set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SI_FN_2_RX[3]
# -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
index 1640cf177a..db8a29de1e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
../../quartus/unb1_test_pins.tcl
@@ -40,9 +40,9 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_all/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
index 64c9950b5d..69e98d5ae9 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_pins.tcl
@@ -40,9 +40,9 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
- #$RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.qip
+ #$HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
index bac6c86884..ff94589deb 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/quartus/unb1_test_ddr_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
index 45d53b348e..6af099891e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/hdllib.cfg
@@ -18,7 +18,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
@@ -29,10 +29,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_16g_MB_I_pins.tcl
@@ -41,8 +41,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
index e6c6cd90d5..a554f7d656 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/quartus/unb1_test_ddr_16g_MB_I_pins.tcl
@@ -25,5 +25,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
index e6ab3a6e1e..39406f4387 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_pins_16g_MB_II.tcl
@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
index f4fac0a19d..010d8290f1 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/quartus/unb1_test_ddr_pins_16g_MB_II.tcl
@@ -25,5 +25,5 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
index c686e3dc31..c8da98b6d6 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_16g_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
index bac6c86884..ff94589deb 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/quartus/unb1_test_ddr_16g_MB_I_II_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
index a82fc8400e..3ad90bc209 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
index 02712a8aa2..0edfab36e2 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/hdllib.cfg
@@ -17,7 +17,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -28,10 +28,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_MB_I_pins.tcl
@@ -40,8 +40,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
index e299f48600..32662cbc7e 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/hdllib.cfg
@@ -16,7 +16,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
@@ -27,10 +27,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
quartus_tcl_files =
quartus/unb1_test_ddr_MB_I_II_pins.tcl
@@ -39,8 +39,8 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_test_ddr_MB_I_II/qsys_unb1_test/synthesis/qsys_unb1_test.qip
+ $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
index bac6c86884..ff94589deb 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/quartus/unb1_test_ddr_pins.tcl
@@ -25,6 +25,6 @@ source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_1Gbe_pins.tcl
source $::env(UNB)/Firmware/designs/unb_common/src/tcl/COMMON_NODE_sensor_pins.tcl
# -- include ddr3 pins
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_I_rec_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/src/tcl/COMMON_NODE_ddr_II_rec_pins.tcl
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
index 2fdbe5db8c..ae30f59231 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
+ $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.v
src/vhdl/mmm_unb1_tr_10GbE.vhd
src/vhdl/unb1_tr_10GbE.vhd
@@ -28,7 +28,7 @@ quartus_copy_files =
# src/hex/ hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_tr_10GbE_pins.tcl
@@ -36,10 +36,10 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_tr_10GbE/qsys_unb1_tr_10GbE/synthesis/qsys_unb1_tr_10GbE.qip
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/boards/uniboard1/libraries/unb1_board/hdllib.cfg b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
index f9b219ceaa..1f76436ec6 100644
--- a/boards/uniboard1/libraries/unb1_board/hdllib.cfg
+++ b/boards/uniboard1/libraries/unb1_board/hdllib.cfg
@@ -43,9 +43,9 @@ synth_files =
src/vhdl/unb1_board_peripherals_pkg.vhd
- # For BN the $RADIOHDL_WORK/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is
+ # For BN the $HDL_WORK/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd is
# referred to directly in the apertif_unb1_bn_filterbank library.
- # For FN a copy of $RADIOHDL_WORK/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+ # For FN a copy of $HDL_WORK/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
# is taken via this unb1_board library:
src/vhdl/node_unb1_fn_terminal_db.vhd
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
index b18c31a46b..2ce61db040 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_allpins.tcl
@@ -23,7 +23,7 @@
# Pin assignments
# -- Common
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
# -- Back Node specific
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
index c023237cd6..f6814e377c 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_pins.tcl
@@ -23,10 +23,10 @@
# Back node specific pin assignments
# -- Backplane Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_tr_pins.tcl
# -- FN to BN Interface added 08-01-2010
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_mesh_pins.tcl
# -- ADC Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/BACK_NODE_adc_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
index fa264372aa..6996180edc 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
@@ -23,22 +23,22 @@
# Common pin assignments for front_node and back_node
# -- General: clk, pps, wdi, inta, intb
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_general_pins.tcl
# -- FPGA Interconnects Front-Node Back-Node
# Clocks only as transceiver pins are now different (08-01-2010)
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
-#source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_clk_pins.tcl
+#source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_tr_pins.tcl
# -- 1GbE Control Interface
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_1Gbe_pins.tcl
# -- SO-DIMM Memory Banks I and II
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_I_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_ddr_II_pins.tcl
# -- I2C Interface to Sensors
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_sensor_pins.tcl
# -- Other: version[1:0], id[7:0], testio[7:0]
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_other_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
index ba55f0e9e5..58070746bd 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_allpins.tcl
@@ -23,7 +23,7 @@
# Pin assignments
# -- Common
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/COMMON_NODE_pins.tcl
# -- Front Node specific
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
index afbd717cd6..54c26398da 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_pins.tcl
@@ -23,9 +23,9 @@
# Front node specific pin assignments
# -- Front Interface (10GbE)
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
# -- FN to BN Mesh Interface added 08-01-2010
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_mesh_pins.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
index d2a233a471..c122cf2f13 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_back_pcs.tcl
@@ -20,6 +20,6 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_back_pcs.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_back_pcs.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
index 856ec42e60..04529c1da7 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs.tcl
@@ -20,7 +20,7 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_0.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_1.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_2.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
index 22f4d234b2..6d398b9113 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_front_pcs_clk.tcl
@@ -20,7 +20,7 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/FRONT_NODE_tr_cntrl_pins.tcl
set_location_assignment PIN_AA2 -to SA_CLK
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SA_CLK
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
index 926e243c89..3cfc75dd90 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
+++ b/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tr_mesh_pcs.tcl
@@ -20,5 +20,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_tx_mesh_pcs.tcl
+source $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/pinning/pins_rx_mesh_pcs.tcl
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
index df08798116..5b320e4471 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
# Device:
set_global_assignment -name FAMILY "Stratix IV"
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
index 98f793e901..311bade3cc 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
# This file contains includes that should be added to another project QSF before
# user contraints and/or QIPs are added.
@@ -48,7 +48,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS128
# Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
+set_global_assignment -name SDC_FILE $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.sdc
# Pass compile stamps as generics (passed to top-level when $UNB_COMPILE_STAMPS is set)
if { [info exists ::env(UNB_COMPILE_STAMPS) ] } {
diff --git a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
index 821a28fa2d..61b7dcf2e6 100644
--- a/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
+++ b/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
@@ -22,12 +22,12 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
#
# This file contains includes that should be added to another project QSF after certain
# user contraints (DDR3 timing constraints for instance) have been included.
# Post Timing constraints
-set_global_assignment -name SDC_FILE $::env(RADIOHDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
+set_global_assignment -name SDC_FILE $::env(HDL_WORK)/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.sdc
diff --git a/boards/uniboard2/designs/unb2_led/hdllib.cfg b/boards/uniboard2/designs/unb2_led/hdllib.cfg
index 5ee94b1931..7fbc76b000 100644
--- a/boards/uniboard2/designs/unb2_led/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_led/hdllib.cfg
@@ -20,10 +20,10 @@ synth_top_level_entity =
quartus_copy_files =
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl b/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
index 23bcf027b1..ec996441dd 100644
--- a/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
+++ b/boards/uniboard2/designs/unb2_led/quartus/unb2_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_minimal/doc/README b/boards/uniboard2/designs/unb2_minimal/doc/README
index 037b0a8df8..e71eef635d 100644
--- a/boards/uniboard2/designs/unb2_minimal/doc/README
+++ b/boards/uniboard2/designs/unb2_minimal/doc/README
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2_minimal] in RadionHDL
-----------------------------------------------------------------
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
+ In the: $HDL_WORK/libraries/technology/ip_arria10
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+ $HDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
2. Generate MMM for QSYS:
@@ -105,7 +105,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
- make sure the 4 fpga icons have the device 10AX115U4F45ES
- right-click each fpga icon and attach flash device EPCQL1024
- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
+ (in $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
- right-click each EPCQL1024 and change file from <none> to output_file.jic
- select click each Program/Configure radiobutton
- click start and wait for 'Successful'
diff --git a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
index 93e521fbb0..5cea81da2e 100644
--- a/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus/qsys_unb2_minimal.qsys .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_minimal_pins.tcl
@@ -34,7 +34,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
+ $HDL_BUILD_DIR/unb2/quartus/unb2_minimal/qsys_unb2_minimal/synthesis/qsys_unb2_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl b/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
index 23bcf027b1..ec996441dd 100644
--- a/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
+++ b/boards/uniboard2/designs/unb2_minimal/quartus/unb2_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/doc/README b/boards/uniboard2/designs/unb2_test/doc/README
index 0dff5ebf0a..b08eeacfa9 100644
--- a/boards/uniboard2/designs/unb2_test/doc/README
+++ b/boards/uniboard2/designs/unb2_test/doc/README
@@ -25,18 +25,18 @@ The following revisions are available for unb2_test (see the directories in ../r
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
+ In the: $HDL_WORK/libraries/technology/ip_arria10
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+ $HDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2
2. Generate MMM for QSYS (select one of these revisions):
@@ -117,7 +117,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
- make sure the 4 fpga icons have the device 10AX115U4F45ES
- right-click each fpga icon and attach flash device EPCQL1024
- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
+ (in $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus)
- right-click each EPCQL1024 and change file from <none> to output_file.jic
- select click each Program/Configure radiobutton
- click start and wait for 'Successful'
diff --git a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
index 7df88096be..8ae5539c04 100644
--- a/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/quartus/unb2_test_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
index 94a1d7a4b5..795ac88ce9 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/hdllib.cfg
@@ -44,11 +44,11 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
quartus/unb2_test_10GbE.sdc
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_test_10GbE_pins.tcl
@@ -56,7 +56,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $HDL_BUILD_DIR/unb2/quartus/unb2_test_10GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
index e14bd851bb..74d121cc3a 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/quartus/unb2_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
index 71f2e12e3d..f88850166f 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_test_1GbE_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $HDL_BUILD_DIR/unb2/quartus/unb2_test_1GbE/qsys_unb2_test/synthesis/qsys_unb2_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
index 23bcf027b1..ec996441dd 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/quartus/unb2_test_1GbE_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
index 980805831d..f22d623cee 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/hdllib.cfg
@@ -49,11 +49,11 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_sdc_files =
quartus/unb2_test_10GbE.sdc
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
quartus_tcl_files =
quartus/unb2_test_all_pins.tcl
@@ -61,7 +61,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_all/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $HDL_BUILD_DIR/unb2/quartus/unb2_test_all/qsys_unb2_test/synthesis/qsys_unb2_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
index f979adc2ee..e28eaa9bd8 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/quartus/unb2_test_all_pins.tcl
@@ -19,6 +19,6 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
index 0e60dc6cc0..74da1480cd 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -33,16 +33,16 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I/qsys_unb2_test/synthesis/qsys_unb2_test.qip
quartus_tcl_files =
quartus/unb2_test_ddr_MB_I_pins.tcl
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
index 1830b7b880..c6ac15c9b4 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/quartus/unb2_test_ddr_MB_I_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
index 2d80edfff0..93d8693614 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -33,16 +33,16 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
quartus_tcl_files =
quartus/unb2_test_ddr_MB_II_pins.tcl
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
index 1830b7b880..c6ac15c9b4 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/quartus/unb2_test_ddr_MB_II_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
index 69ccd15818..8404211bf7 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/hdllib.cfg
@@ -22,7 +22,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -33,16 +33,16 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
+ $HDL_BUILD_DIR/unb2/quartus/unb2_test_ddr_MB_I_II/qsys_unb2_test/synthesis/qsys_unb2_test.qip
quartus_tcl_files =
quartus/unb2_test_ddr_MB_I_II_pins.tcl
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
+ $HDL_WORK/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
index 1830b7b880..c6ac15c9b4 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/quartus/unb2_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2/libraries/unb2_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index 94e14c4340..5e5c7a8b7b 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
- -- $RADIOHDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
+ -- $HDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
-----------------------------------------------------------------------------
component qsys_unb2_test is
diff --git a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
index 0cedbdb8b4..c64bca4f5b 100644
--- a/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
+++ b/boards/uniboard2/libraries/unb2_board/quartus/unb2_board.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
# Device:
set_global_assignment -name FAMILY "Arria 10"
diff --git a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
index 8788e379fa..0a9d91210c 100644
--- a/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_heater/doc/README.txt
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2a_heater] in RadionHDL
------------------------------------------------------------------
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
+ In the: $HDL_WORK/libraries/technology/ip_arria10_e3sge3
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+ $HDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
2. Generate MMM for QSYS:
@@ -107,7 +107,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
- make sure the 4 fpga icons have the device 10AX115U4F45ES
- right-click each fpga icon and attach flash device EPCQL1024
- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
+ (in $HDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
- right-click each EPCQL1024 and change file from <none> to output_file.jic
- select click each Program/Configure radiobutton
- click start and wait for 'Successful'
diff --git a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
index 606ea20f76..6650fbad38 100644
--- a/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus/qsys_unb2a_heater.qsys .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_heater_pins.tcl
@@ -34,7 +34,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_heater/qsys_unb2a_heater/synthesis/qsys_unb2a_heater.qip
+ $HDL_BUILD_DIR/unb2a/quartus/unb2a_heater/qsys_unb2a_heater/synthesis/qsys_unb2a_heater.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl b/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
index 3374b678b9..1a90a0c0ba 100644
--- a/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_heater/quartus/unb2a_heater_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
index 9d75b890c2..5aad148bc9 100644
--- a/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_led/hdllib.cfg
@@ -20,10 +20,10 @@ synth_top_level_entity =
quartus_copy_files =
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
index 3374b678b9..1a90a0c0ba 100644
--- a/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_led/quartus/unb2a_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
index 37859f9f84..01048d3872 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
@@ -2,19 +2,19 @@ Quick steps to compile and use design [unb2a_minimal] in RadionHDL
------------------------------------------------------------------
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
+ In the: $HDL_WORK/libraries/technology/ip_arria10_e3sge3
directory; run the bash script: ./generate-all-ip.sh
-> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
- cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+ cd $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
./run_patch.sh
-> In case of a fresh compilation, delete the build directory.
- rm -r $RADIOHDL_WORK/build
+ rm -r $HDL_WORK/build
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
2. Generate MMM for QSYS:
@@ -63,7 +63,7 @@ In case of needing the Quartus GUI for inspection (this starts the Quartus 15.1
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
Then click auto-detect; (click 4x ok)
- Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_minimal) for each FPGA
+ Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2a/quartus/unb2a_minimal) for each FPGA
Select the FPGA(s) which has to be programmed
Click 'start'
Using EPCS: See step 6 below.
@@ -98,7 +98,7 @@ For generating a Factory image .RBF file:
run_rbf unb2a --unb2_factory unb2a_minimal
-The .RBF file is now in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_minimal
+The .RBF file is now in $HDL_WORK/build/unb2a/quartus/unb2a_minimal
Now copy the .RBF file to the LCU host with 'scp'
(b)
@@ -109,7 +109,7 @@ Program User image:
Program Factory image:
python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2a_minimal.rbf
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $HDL_WORK/libraries/io/epcs/doc/README.txt
To start the User image:
python util_remu.py --unb 1 --fn 0 -n 6 # ignore timeout error
@@ -146,7 +146,7 @@ Then program the .JIC file (unb2a_minimal.jic) to EPCS flash:
(*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
+ (in $HDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
7.
diff --git a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
index d06919a710..2254a2298d 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus/qsys_unb2a_minimal.qsys .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_minimal_pins.tcl
@@ -34,7 +34,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
+ $HDL_BUILD_DIR/unb2a/quartus/unb2a_minimal/qsys_unb2a_minimal/synthesis/qsys_unb2a_minimal.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
index 3374b678b9..1a90a0c0ba 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_minimal/quartus/unb2a_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/doc/README.txt b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
index ce1710cbd2..e386edeb68 100644
--- a/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+++ b/boards/uniboard2a/designs/unb2a_test/doc/README.txt
@@ -25,17 +25,17 @@ The following revisions are available for unb2a_test (see the directories in ../
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3
+ In the: $HDL_WORK/libraries/technology/ip_arria10_e3sge3
directory; run the bash script: ./generate-all-ip.sh
-> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
- cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+ cd $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
./run_patch.sh
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2a
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2a
2. Generate MMM for QSYS (select one of these revisions):
@@ -80,7 +80,7 @@ load the project now from the build directory.
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
Then click auto-detect; (click 4x ok)
- Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_...) for each FPGA
+ Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2a/quartus/unb2a_test_...) for each FPGA
Select the FPGA(s) which has to be programmed
Click 'start'
Using EPCS: See step 6 below.
@@ -106,7 +106,7 @@ For generating a Factory image .RBF file:
run_rbf unb2a --unb2_factory unb2a_test_[revision]
-The .RBF file is now in $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_[revision]
+The .RBF file is now in $HDL_WORK/build/unb2a/quartus/unb2a_test_[revision]
Now copy the .RBF file to the LCU host with 'scp'
(b)
@@ -117,7 +117,7 @@ Program User image:
Program Factory image:
python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2a_test_[revision].rbf
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $HDL_WORK/libraries/io/epcs/doc/README.txt
To start the User image:
python util_remu.py --unb 1 --fn 0 -n 6 # ignore timeout error
@@ -151,7 +151,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
(*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
+ (in $HDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
7.
diff --git a/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl b/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
index c0483d1585..782190450d 100644
--- a/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/quartus/unb2a_test_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
index 22976e6d86..e1e4a6879c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/hdllib.cfg
@@ -44,14 +44,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_pre_files =
quartus/unb2a_test_10GbE.sdc
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board_pre.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_test_10GbE_pins.tcl
@@ -59,7 +59,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_10GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_10GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
index 7e83e4b07c..f21f96082e 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/quartus/unb2a_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
index 2baa5dd51a..20f578e031 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/hdllib.cfg
@@ -24,10 +24,10 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_test_1GbE_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_1GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_1GbE/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
index 3374b678b9..1a90a0c0ba 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/quartus/unb2a_test_1GbE_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
index c0fe8620de..b672864313 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/hdllib.cfg
@@ -50,11 +50,11 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_sdc_files =
quartus/unb2a_test_10GbE.sdc
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
quartus_tcl_files =
quartus/unb2a_test_all_pins.tcl
@@ -62,7 +62,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_all/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_all/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
index 91f930b06b..48d76653cd 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/quartus/unb2a_test_all_pins.tcl
@@ -19,6 +19,6 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
index 5886fa177c..ae89579bba 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -34,16 +34,16 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
quartus_tcl_files =
quartus/unb2a_test_ddr_MB_I_pins.tcl
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
index edf1e7422d..9eef78491c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/quartus/unb2a_test_ddr_MB_I_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
index e15377b23d..b4c532fc7f 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -34,16 +34,16 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
quartus_tcl_files =
quartus/unb2a_test_ddr_MB_II_pins.tcl
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
index edf1e7422d..9eef78491c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/quartus/unb2a_test_ddr_MB_II_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
index fd9199ad99..3d19a04a35 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/hdllib.cfg
@@ -23,7 +23,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -34,16 +34,16 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
+ $HDL_BUILD_DIR/unb2a/quartus/unb2a_test_ddr_MB_I_II/qsys_unb2a_test/synthesis/qsys_unb2a_test.qip
quartus_tcl_files =
quartus/unb2a_test_ddr_MB_I_II_pins.tcl
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
+ $HDL_WORK/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
index edf1e7422d..9eef78491c 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/quartus/unb2a_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_ddr_pins.tcl
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index 2f6c0284ea..012aacd396 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2a_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
- -- $RADIOHDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
+ -- $HDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
-----------------------------------------------------------------------------
component qsys_unb2a_test is
diff --git a/boards/uniboard2a/doc/unb2a_release_notes.txt b/boards/uniboard2a/doc/unb2a_release_notes.txt
index 18a1851942..4b8c0889c2 100644
--- a/boards/uniboard2a/doc/unb2a_release_notes.txt
+++ b/boards/uniboard2a/doc/unb2a_release_notes.txt
@@ -10,15 +10,15 @@ Date: Tue Apr 26 11:25:24 CEST 2016
This means that the firmware already flashed still shows a Uniboard 1 version in the python scripts.
-> So it will be good to re-flash unb2a_minimal.
The new .rbf file (factory image) is added in the build directory and the excisting .jic file is removed.
- Look at $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt Section 6b how to flash
- Also see $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/build/README.txt
+ Look at $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt Section 6b how to flash
+ Also see $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/build/README.txt
Date: Mon Apr 25 11:29:31 CEST 2016
- Added functionality to write to EPCQ flash.
Now it is possible to write a Factory- and User image
- See $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+ See $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
for instructions how to prepare images and how to write them in the flash
- Added functionality to perform Load from Flash with the REMU (remote update)
@@ -32,15 +32,15 @@ In this directory the following designs can be found:
- unb2a_minimal
a minimal design which is also programmed in the onboard EPCS flash.
- See: $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/ASTRON_unb2a_minimal.pdf
- $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
+ See: $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/ASTRON_unb2a_minimal.pdf
+ $HDL_WORK/boards/uniboard2a/designs/unb2a_minimal/doc/README.txt
- unb2_test
a test design with revisions testing each subsystem. Currently only the DDR4.
- See: $RADIOHDL_WORK/boards/uniboard2a/designs/unb2a_test/doc/README.txt
+ See: $HDL_WORK/boards/uniboard2a/designs/unb2a_test/doc/README.txt
@@ -49,7 +49,7 @@ In this directory the following designs can be found:
an Altera reference design originally downloaded from
www.alterawiki.com/wiki/High_Speed_Transceiver_Demo_Designs_For_Current_and_Older_Families
- See: $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/Arria10_SIBoard_24Ch_3_Phy_TTK_ES3/doc/*
+ See: $HDL_WORK/boards/uniboard2a/designs/altera_ref_designs/Arria10_SIBoard_24Ch_3_Phy_TTK_ES3/doc/*
@@ -58,9 +58,9 @@ In this directory the following designs can be found:
ddr4_micron46_mbIIskew
based on Altera's reference design, autogenerated from the QSYS IP-catalog in Quartus
- See: $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/*
- $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/README.txt
- $RADIOHDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/README.txt
+ See: $HDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/doc/*
+ $HDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/README.txt
+ $HDL_WORK/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/README.txt
diff --git a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
index b0c03d5eff..7b6403b395 100644
--- a/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
+++ b/boards/uniboard2a/libraries/unb2a_board/quartus/unb2a_board.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
# new in Quartus 16.0:
set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/doc/README b/boards/uniboard2b/designs/unb2b_arp_ping/doc/README
index eb5cae66ce..0bb92470be 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/doc/README
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/doc/README
@@ -5,19 +5,19 @@ On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL_WORK/libraries/technology/ip_arria10
+ In the: $HDL_WORK/libraries/technology/ip_arria10
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+ $HDL_WORK/libraries/technology/technology_select_pkg.vhd
-> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
-> Make sure you use the modified avs2_eth_coe_hw.tcl (see attachment of this e-mail), this file is placed in RadioHDL/trunk/libraries/io/eth/src/vhdl.
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
# 2. Generate MMM for QSYS:
# run_qsys unb2b unb2b_minimal
@@ -59,7 +59,7 @@ Synthesis
- Open the unb2b_minumal quartus project from the build directory.
- Open the qsys_unb2b_minimal.qsys file from the build directory.
- Generate the HDL files for the qsys using the GUI.
-- "cd $RADIOHDL_WORK/build/unb2b/quartus/unb2b_minimal"
+- "cd $HDL_WORK/build/unb2b/quartus/unb2b_minimal"
- "cp qsys_unb2b_minimal/qsys_unb2b_minimal* ."
- "run_app unb2b unb2b_minimal use=gen2"
- In Quartus, click the play button to compile the design.
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/hdllib.cfg b/boards/uniboard2b/designs/unb2b_arp_ping/hdllib.cfg
index fac36717d8..84065beb37 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/hdllib.cfg
@@ -21,10 +21,10 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
quartus/unb2b_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/quartus/unb2b_minimal_pins.tcl b/boards/uniboard2b/designs/unb2b_arp_ping/quartus/unb2b_minimal_pins.tcl
index 7f9cb9420a..f4f9023250 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/quartus/unb2b_minimal_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/quartus/unb2b_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
index b2f7defb7b..fa00229b73 100644
--- a/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_heater/doc/README.txt
@@ -2,17 +2,17 @@ Quick steps to compile and use design [unb2a_heater] in RadionHDL
------------------------------------------------------------------
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg
+ In the: $HDL_WORK/libraries/technology/ip_arria10_e1sg
directory; run the bash script: ./generate-all-ip.sh
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+ $HDL_WORK/libraries/technology/technology_select_pkg.vhd
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
2. Generate MMM for QSYS:
@@ -107,7 +107,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
- make sure the 4 fpga icons have the device 10AX115U4F45ES
- right-click each fpga icon and attach flash device EPCQL1024
- right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
+ (in $HDL_WORK/boards/uniboard2/libraries/unb2a_board/quartus)
- right-click each EPCQL1024 and change file from <none> to output_file.jic
- select click each Program/Configure radiobutton
- click start and wait for 'Successful'
diff --git a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
index 9d8ad66690..52b01f7dd2 100644
--- a/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_heater/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
quartus/unb2b_heater_pins.tcl
@@ -34,31 +34,31 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/qsys_unb2b_heater/qsys_unb2b_heater.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_heater.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_heater/ip/qsys_unb2b_heater/qsys_unb2b_heater_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
index 8201bf923e..61b11c1c4c 100644
--- a/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_heater/quartus/unb2b_heater_pins.tcl
@@ -18,4 +18,4 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
index 72f15b0a73..dc01f14701 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/hdllib.cfg
@@ -34,6 +34,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
index de64e7f039..a357b0ac5c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node0/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node0/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
index 324205ffa1..d4b0c462fc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/hdllib.cfg
@@ -31,6 +31,6 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node3/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_jesd_node3/qsys_unb2b_jesd/qsys_unb2b_jesd.qip
diff --git a/boards/uniboard2b/designs/unb2b_minimal/doc/README b/boards/uniboard2b/designs/unb2b_minimal/doc/README
index cc12cf8fa0..c8fe1e8592 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/doc/README
+++ b/boards/uniboard2b/designs/unb2b_minimal/doc/README
@@ -11,7 +11,7 @@ On uni-boards 26287-001..26287-005 (unb2b) the used FPGA is '10AX115U2F45E1SG'
generate_ip_libs unb2b
-> For compilation it might be necessary to check the .vhd file:
- $RADIOHDL_WORK/libraries/technology/technology_select_pkg.vhd
+ $HDL_WORK/libraries/technology/technology_select_pkg.vhd
-> Make sure you have set up the RadioHDL/trunk/tools/quartus/set_quartus script correctly to use quartus 17 for unb2b.
@@ -62,7 +62,7 @@ Synthesis
- Open the unb2b_minumal quartus project from the build directory.
- Open the qsys_unb2b_minimal.qsys file from the build directory.
- Generate the HDL files for the qsys using the GUI.
-- "cd $RADIOHDL_WORK/build/unb2b/quartus/unb2b_minimal"
+- "cd $HDL_WORK/build/unb2b/quartus/unb2b_minimal"
- "cp qsys_unb2b_minimal/qsys_unb2b_minimal* ."
- "run_app unb2b unb2b_minimal use=gen2"
- In Quartus, click the play button to compile the design.
diff --git a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
index 24d3d4a0fa..d6d7154a93 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/hdllib.cfg
@@ -23,10 +23,10 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
quartus/unb2b_minimal_pins.tcl
@@ -34,31 +34,31 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl b/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
index 7f9cb9420a..f4f9023250 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_minimal/quartus/unb2b_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg
index 87c0b0f7ef..cf2059e4e1 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/hdllib.cfg
@@ -22,14 +22,14 @@ quartus_copy_files =
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_pre_files =
quartus/unb2b_test_10GbE.sdc
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
../../quartus/unb2b_minimal_pins.tcl
@@ -37,31 +37,31 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal_125m/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal_125m/qsys_unb2b_minimal/qsys_unb2b_minimal.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_minimal/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_ram_scrap.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_test/doc/README.txt b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
index 31575a05f4..913f0b1333 100644
--- a/boards/uniboard2b/designs/unb2b_test/doc/README.txt
+++ b/boards/uniboard2b/designs/unb2b_test/doc/README.txt
@@ -25,17 +25,17 @@ The following revisions are available for unb2b_test (see the directories in ../
-> In case of a new installation, the IP's have to be generated for Arria10.
- In the: $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg
+ In the: $HDL_WORK/libraries/technology/ip_arria10_e1sg
directory; run the bash script: ./generate-all-ip.sh
-> The TSE IP gives a lot of critical warnings. To fix them, run this patch:
- cd $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds
+ cd $HDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds
./run_patch.sh
1. Start with the Oneclick Commands:
- python $RADIOHDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
- python $RADIOHDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
+ python $HDL_WORK/tools/oneclick/base/modelsim_config.py -t unb2b
+ python $HDL_WORK/tools/oneclick/base/quartus_config.py -t unb2b
2. Generate MMM for QSYS (select one of these revisions):
@@ -80,7 +80,7 @@ load the project now from the build directory.
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
Then click auto-detect; (click 4x ok)
- Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_...) for each FPGA
+ Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2b/quartus/unb2b_test_...) for each FPGA
Select the FPGA(s) which has to be programmed
Click 'start'
Using EPCS: See step 6 below.
@@ -106,7 +106,7 @@ For generating a Factory image .RBF file:
run_rbf unb2b --unb2_factory unb2b_test_[revision]
-The .RBF file is now in $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_[revision]
+The .RBF file is now in $HDL_WORK/build/unb2b/quartus/unb2b_test_[revision]
Now copy the .RBF file to the LCU host with 'scp'
(b)
@@ -117,7 +117,7 @@ Program User image:
Program Factory image:
python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2b_test_[revision].rbf
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $HDL_WORK/libraries/io/epcs/doc/README.txt
To start the User image:
python util_remu.py --unb 1 --fn 0 -n 6 # ignore timeout error
@@ -151,7 +151,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
(*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2b_board/quartus)
+ (in $HDL_WORK/boards/uniboard2/libraries/unb2b_board/quartus)
7.
diff --git a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
index 5269edaf0f..b4d826aa22 100644
--- a/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/quartus/unb2b_test_pins.tcl
@@ -19,7 +19,7 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
index cdaa8c7e78..0a7892e5be 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/hdllib.cfg
@@ -45,14 +45,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_sdc_pre_files =
quartus/unb2b_test_10GbE.sdc
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_tcl_files =
quartus/unb2b_test_10GbE_pins.tcl
@@ -60,7 +60,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_10GbE/qsys_unb2b_test/qsys_unb2b_test.qip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
index 7e83e4b07c..f21f96082e 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/quartus/unb2b_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2a/libraries/unb2a_board/quartus/pinning/unb2_10GbE_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg
index c016fc4ec9..98a33faf40 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/hdllib.cfg
@@ -19,7 +19,7 @@ modelsim_copy_files =
../../src/hex hex
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
[quartus_project_file]
@@ -30,70 +30,70 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/qsys_unb2b_test/qsys_unb2b_test.qip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/qsys_unb2b_test/qsys_unb2b_test.qip
quartus_tcl_files =
quartus/unb2b_test_ddr_MB_I_II_pins.tcl
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
+ $HDL_WORK/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.sdc
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_cpu_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_timer_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_avs_eth_1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_clk_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_cpu_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_pps.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_bg_1gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_1gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_10GbE.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_bsn_monitor_1GbE.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_bg_1gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_1gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_1gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_1gbe.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_back1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_eth10g_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_io_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_remu.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back0.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_back1.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_tr_10GbE_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_pmbus.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_unb_sens.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2b/quartus/unb2b_test_ddr_MB_I_II/ip/qsys_unb2b_test/qsys_unb2b_test_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl
index aeb8fe68eb..08edf304fe 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/quartus/unb2b_test_ddr_MB_I_II_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_ddr_pins.tcl
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index fd2eb84445..6b87cf4f53 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -26,7 +26,7 @@ PACKAGE qsys_unb2b_test_pkg IS
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
- -- $RADIOHDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
+ -- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
-----------------------------------------------------------------------------
component qsys_unb2b_test is
diff --git a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
index d9e35c4ada..7f9274079a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
+++ b/boards/uniboard2b/libraries/unb2b_board/quartus/unb2b_board.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
# new in Quartus 16.0:
set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
diff --git a/boards/uniboard2c/designs/unb2c_led/hdllib.cfg b/boards/uniboard2c/designs/unb2c_led/hdllib.cfg
index 4db139612d..5d04796737 100644
--- a/boards/uniboard2c/designs/unb2c_led/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_led/hdllib.cfg
@@ -19,10 +19,10 @@ synth_top_level_entity =
quartus_copy_files =
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_led/quartus/unb2c_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_led/quartus/unb2c_minimal_pins.tcl
index ae417258f8..62e37ddc54 100644
--- a/boards/uniboard2c/designs/unb2c_led/quartus/unb2c_minimal_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_led/quartus/unb2c_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt b/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt
index 33bcfbb2be..3c7e4f13a7 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt
+++ b/boards/uniboard2c/designs/unb2c_minimal/doc/README.txt
@@ -14,8 +14,8 @@ Steps to go:
-> In case of a new installation, the IP's have to be generated for Arria10.
- echo $RADIOHDL_BUILD_DIR # should be something like /home/user/git/hdl/build
- rm -r $RADIOHDL_BUILD_DIR/unb2c # optional
+ echo $HDL_BUILD_DIR # should be something like /home/user/git/hdl/build
+ rm -r $HDL_BUILD_DIR/unb2c # optional
compile_altera_simlibs unb2c
generate_ip_libs unb2c
@@ -56,7 +56,7 @@ load the project now from the build directory.
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
Then click auto-detect; (click 4x ok)
- Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2c/quartus/unb2c_test_...) for each FPGA
+ Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2c/quartus/unb2c_test_...) for each FPGA
Select the FPGA(s) which has to be programmed
Click 'start'
Using EPCS: See step 6 below.
diff --git a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
index 2989dd33ac..97eb7c5537 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_minimal/hdllib.cfg
@@ -25,10 +25,10 @@ quartus_copy_files =
quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_minimal_pins.tcl
@@ -36,29 +36,29 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/qsys_unb2c_minimal/qsys_unb2c_minimal.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_minimal/ip/qsys_unb2c_minimal/qsys_unb2c_minimal_timer_0.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
index ae417258f8..62e37ddc54 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_minimal/quartus/unb2c_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/doc/README.txt b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
index dc0de17d70..d05dc3625f 100644
--- a/boards/uniboard2c/designs/unb2c_test/doc/README.txt
+++ b/boards/uniboard2c/designs/unb2c_test/doc/README.txt
@@ -21,8 +21,8 @@ Steps to go:
-> In case of a new installation, the IP's have to be generated for Arria10.
- echo $RADIOHDL_BUILD_DIR # should be something like /home/user/git/hdl/build
- rm -r $RADIOHDL_BUILD_DIR/unb2c # optional
+ echo $HDL_BUILD_DIR # should be something like /home/user/git/hdl/build
+ rm -r $HDL_BUILD_DIR/unb2c # optional
compile_altera_simlibs unb2c
generate_ip_libs unb2c
@@ -67,7 +67,7 @@ load the project now from the build directory.
----------------
Using JTAG: Start the Quartus GUI and open: tools->programmer.
Then click auto-detect; (click 4x ok)
- Use 'change file' to select the correct .sof file (in $RADIOHDL_WORK/build/unb2c/quartus/unb2c_test_...) for each FPGA
+ Use 'change file' to select the correct .sof file (in $HDL_WORK/build/unb2c/quartus/unb2c_test_...) for each FPGA
Select the FPGA(s) which has to be programmed
Click 'start'
Using EPCS: See step 6 below.
@@ -93,7 +93,7 @@ For generating a Factory image .RBF file:
run_rbf unb2c --unb2_factory unb2c_test_[revision]
-The .RBF file is now in $RADIOHDL_WORK/build/unb2c/quartus/unb2c_test_[revision]
+The .RBF file is now in $HDL_WORK/build/unb2c/quartus/unb2c_test_[revision]
Now copy the .RBF file to the LCU host with 'scp'
(b)
@@ -104,7 +104,7 @@ Program User image:
Program Factory image:
python util_epcs.py --unb 1 --fn 0 -n 3 -s unb2c_test_[revision].rbf
--> For extra info on RBF files on Uniboard2, see: $RADIOHDL_WORK/libraries/io/epcs/doc/README.txt
+-> For extra info on RBF files on Uniboard2, see: $HDL_WORK/libraries/io/epcs/doc/README.txt
To start the User image:
python util_remu.py --unb 1 --fn 0 -n 6 # ignore timeout error
@@ -138,7 +138,7 @@ Then program the .JIC file (output_file.jic) to EPCS flash:
(*1) When error select correct SFL (serial flash loader) from Altera service request for each FPGA:
right-click each fpga and change file from <none> to sfl_enhanced_01_02e360dd.sof
- (in $RADIOHDL_WORK/boards/uniboard2/libraries/unb2c_board/quartus)
+ (in $HDL_WORK/boards/uniboard2/libraries/unb2c_board/quartus)
7.
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
index 9ef2e859c0..2a380a453b 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/hdllib.cfg
@@ -46,14 +46,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
quartus/unb2c_test_10GbE.sdc
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_10GbE_pins.tcl
@@ -61,72 +61,72 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_10GbE/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/unb2c_test_10GbE_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/unb2c_test_10GbE_pins.tcl
index 23b93a5ba2..d0fd38cd8a 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/unb2c_test_10GbE_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/quartus/unb2c_test_10GbE_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_10GbE_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
index 5e52adba61..3ceaa62dc2 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/hdllib.cfg
@@ -26,13 +26,13 @@ quartus_copy_files =
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_1GbE_I_pins.tcl
@@ -40,72 +40,72 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/qsys_unb2c_test/qsys_unb2c_test.qip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_I/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl
index ae417258f8..62e37ddc54 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/quartus/unb2c_test_1GbE_I_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg
index cbeea04e78..8a8afc0da5 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/hdllib.cfg
@@ -26,13 +26,13 @@ quartus_copy_files =
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_1GbE_II_pins.tcl
@@ -40,72 +40,72 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/qsys_unb2c_test/qsys_unb2c_test.qip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_1GbE_II/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl
index ae417258f8..62e37ddc54 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/quartus/unb2c_test_1GbE_II_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
index e922d19d89..6d3ea7c1f0 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/hdllib.cfg
@@ -32,14 +32,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
quartus/unb2c_test_ddr.sdc
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_ddr_pins.tcl
@@ -47,72 +47,72 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/qsys_unb2c_test/qsys_unb2c_test.qip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl
index e659f0faff..7411b8fb2f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/quartus/unb2c_test_ddr_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_ddr_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/hdllib.cfg
index 05fda726d0..a482d06925 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/hdllib.cfg
@@ -48,72 +48,72 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr_16G/qsys_unb2c_test/qsys_unb2c_test.qip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr_16G/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_ddr/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
index fea6d6b871..7f34f3c3e2 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/hdllib.cfg
@@ -30,14 +30,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
quartus/unb2c_test_heater.sdc
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_heater_pins.tcl
@@ -45,72 +45,72 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/qsys_unb2c_test/qsys_unb2c_test.qip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_heater/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl
index ae417258f8..62e37ddc54 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/quartus/unb2c_test_heater_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
index 2e6ecb1582..a6572309f8 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/hdllib.cfg
@@ -29,14 +29,14 @@ quartus_copy_files =
../../src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
quartus/unb2c_test_jesd204b.sdc
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_jesd204b_pins.tcl
@@ -44,72 +44,72 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/qsys_unb2c_test/qsys_unb2c_test.qip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_jesd204b/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl
index face7edbab..1bf7adba9f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/quartus/unb2c_test_jesd204b_pins.tcl
@@ -19,5 +19,5 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_jesd204b_pins.tcl
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
index ebf094c08a..58c95fbe7f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/hdllib.cfg
@@ -25,13 +25,13 @@ quartus_copy_files =
../../quartus .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
quartus_sdc_pre_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board_pre.sdc
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
+ $HDL_WORK/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.sdc
quartus_tcl_files =
quartus/unb2c_test_minimal_pins.tcl
@@ -39,72 +39,72 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/qsys_unb2c_test/qsys_unb2c_test.qip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/qsys_unb2c_test/qsys_unb2c_test.qip
quartus_ip_files =
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
- $RADIOHDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_avs2_eth_coe_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_clk_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jesd204b.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_jtag_uart_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_nios2_gen2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_onchip_memory2_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_jesd_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_pps.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_pio_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_ram_scrap.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_10GbE.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_input.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_scheduler.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_source.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_bsn.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_data_buffer_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_rx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_10gbe.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_tx_seq_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_dpmm_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_epcs.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_eth10g_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_temp_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_fpga_voltage_sens.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_heater.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_II.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_io_ddr_MB_I.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_ctrl.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_mmdp_data.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_remu.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_back1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_tr_10GbE_qsfp_ring.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_wdi.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_rom_system_info.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_timer_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_0.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_diag_bg_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_hdr_dat_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_bsn_monitor_v2_rx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_tx_eth_1.ip
+ $HDL_BUILD_DIR/unb2c/quartus/unb2c_test_minimal/ip/qsys_unb2c_test/qsys_unb2c_test_reg_strobe_total_count_rx_eth_1.ip
nios2_app_userflags = -DCOMPILE_FOR_GEN2_UNB2
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
index ae417258f8..62e37ddc54 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/quartus/unb2c_test_minimal_pins.tcl
@@ -19,4 +19,4 @@
#
###############################################################################
-source $::env(RADIOHDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
+source $::env(HDL_WORK)/boards/uniboard2c/libraries/unb2c_board/quartus/pinning/unb2c_minimal_pins.tcl
diff --git a/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf b/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
index 2eae7412c7..b803224f2a 100644
--- a/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
+++ b/boards/uniboard2c/libraries/unb2c_board/quartus/unb2c_board.qsf
@@ -22,7 +22,7 @@
# This QSF is sourced by other design QSF files.
# ==============================================
# Note: This file can ONLY BE SOURCED (use SOURCE_TCL_SCRIPT_FILE so it will be TCL interpreted), e.g.
-# by another QSF, otherwise many TCL commands such as "$::env(RADIOHDL_WORK)" do not work.
+# by another QSF, otherwise many TCL commands such as "$::env(HDL_WORK)" do not work.
# new in Quartus 16.0:
set_global_assignment -name NUM_PARALLEL_PROCESSORS 6
diff --git a/doc/erko_hdl_design_article.txt b/doc/erko_hdl_design_article.txt
index a1d2580441..d340955176 100644
--- a/doc/erko_hdl_design_article.txt
+++ b/doc/erko_hdl_design_article.txt
@@ -1,7 +1,7 @@
Reset : asynchronous or synchronous ?
-$RADIOHDL_WORK/applications/lofar2/doc/prestudy/
+$HDL_WORK/applications/lofar2/doc/prestudy/
Ref:
$RADIOHDL/tools/oneclick/doc/desp_firmware_dag_erko.txt
diff --git a/doc/erko_howto_tools.txt b/doc/erko_howto_tools.txt
index ffc317942e..1352dd18f4 100755
--- a/doc/erko_howto_tools.txt
+++ b/doc/erko_howto_tools.txt
@@ -54,12 +54,12 @@
> . ./init_hdl.sh
- * init_hdl.sh defines:
+ * inHDL_WORKines:
- RADIOHDL_WORK directory for where the source code resides
- - RADIOHDL_BUILD_DIR directory for where the targets will be build
- - HDL_IOFILE_SIM_DIR=${RADIOHDL_BUILD_DIR}/sim for simulating with Modelsim using file IO
+ - HDL_BUILD_DIR directory for where the targets will be build
+ - HDL_IOFILE_SIM_DIR=${HDL_BUILD_DIR}/sim for simulating with Modelsim using file IO
- * init_hdl.sh copies git user_components.ipx into Altera dir's
+ * init_hdHDL_WORKit user_components.ipx into Altera dir's
- cp ${RADIOHDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
* init_hdl.sh automatically also sources ../radiohdl/init_radiohdl.sh if necessary
@@ -71,7 +71,7 @@ source also radiohdl tools
* init_radiohdl.sh defines:
- RADIOHDL_GEAR directory of where the init_radiohdl.sh is located
- - RADIOHDL_BUILD_DIR = ${RADIOHDL_BUILD_DIR}/build if not already defined
+ - HDL_BUILD_DIR = ${HDL_BUILD_DIR}/build if not already defined
- RADIOHDL_CONFIG = ${RADIOHDL_GEAR}/config if not already defined
* init_radiohdl.sh extends:
@@ -198,7 +198,7 @@ sdp_firmware.py --host 10.99.0.250 -n 0:3 --write --image USER --file ../upe_gea
sdp_rw.py --host 10.99.0.250 -r firmware_version
sdp_firmware.py --host 10.99.0.250 -n 0:3 --reboot --image USER
sdp_rw.py --host 10.99.0.250 -r firmware_version
-
+HDL_WORK
*******************************************************************************
* RadioHDL with SVN
@@ -838,7 +838,7 @@ When screen is started, it reads its configuration parameters from
Screen settings according to our preferences using the .screenrc file.
Here is a sample ~/.screenrc configuration with customized status line and few
additional options:
-
+HDL_WORK
~/.screenrc
# Turn off the welcome message
startup_message off
@@ -850,11 +850,11 @@ vbell off
defscrollback 10000
# Customize the status line
-hardstatus alwayslastline
+hardHDL_WORKlastline
hardstatus string '%{= kG}[ %{G}%H %{g}][%= %{= kw}%?%-Lw%?%{r}(%{W}%n*%f%t%?(%u)%?%{r})%{w}%?%+Lw%?%?%= %{g}][%{B} %m-%d %{W}%c %{g}]'
Copy
-* uex in screen lijkt eerst niet op te starten,
+* ueHDL_WORKijkt eerst niet op te starten,
matlab wel dus het ligt niet aan GUI, daarna lukts uex wel.
* :kooistra@dop386:~/git/hdl> --> in gewone terminal
* ::kooistra@dop386:~/git/hdl> --> in screen terminal
diff --git a/doc/erko_radiohdl_article.txt b/doc/erko_radiohdl_article.txt
index 58b182f243..80e895d8c4 100644
--- a/doc/erko_radiohdl_article.txt
+++ b/doc/erko_radiohdl_article.txt
@@ -57,7 +57,7 @@ Features:
*******************************************************************************
* Open issues:
*******************************************************************************
-- Support more roots in RADIOHDL_WORK for searching HDL libraries
+- Support more roots in HDL_WORK for searching HDL libraries
- Central HDL_IO_FILE_SIM_DIR = build/sim --> Project local sim dir
- avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR
copies the last <buildset>, using more than one buildset at a time gices conflicts.
@@ -145,7 +145,7 @@ are then used by the other libraries.
* Simulation using file IO
*******************************************************************************
-HDL_IOFILE_SIM_DIR is set to ${RADIOHDL_BUILD_DIR}/sim and defines where Modelsim simulation
+HDL_IOFILE_SIM_DIR is set to ${HDL_BUILD_DIR}/sim and defines where Modelsim simulation
will keep temporary file IO files.
diff --git a/hdl_user_components.ipx b/hdl_user_components.ipx
index 4823cbc15a..f9d2121fe9 100644
--- a/hdl_user_components.ipx
+++ b/hdl_user_components.ipx
@@ -6,5 +6,5 @@
<!-- 0 in D:\svnroot\Uniboard\9.0 -->
<!-- -->
<!-- D:/svnroot/Uniboard/9.0 -->
- <path path="$RADIOHDL_WORK/libraries/**/*" />
+ <path path="$HDL_WORK/libraries/**/*" />
</library>
diff --git a/init_hdl.sh b/init_hdl.sh
index a64c66de2f..6c72df6cdd 100644
--- a/init_hdl.sh
+++ b/init_hdl.sh
@@ -43,19 +43,19 @@ if [ -z "${ALTERA_DIR}" ]; then
fi
# Figure out where this script is located and set environment variables accordingly
-export RADIOHDL_WORK="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
-echo "HDL environment will be setup for" $RADIOHDL_WORK
+export HDL_WORK="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+echo "HDL environment will be setup for" $HDL_WORK
# setup paths to build and config dir if not already defined by the user.
-export ARGS_WORK=${RADIOHDL_WORK}
-export RADIOHDL_BUILD_DIR=${RADIOHDL_WORK}/build
-if [[ ! -d "${RADIOHDL_BUILD_DIR}" ]]; then
+export ARGS_WORK=${HDL_WORK}
+export HDL_BUILD_DIR=${HDL_WORK}/build
+if [[ ! -d "${HDL_BUILD_DIR}" ]]; then
echo "make buil dir"
- echo "${RADIOHDL_BUILD_DIR}"
- mkdir "${RADIOHDL_BUILD_DIR}"
+ echo "${HDL_BUILD_DIR}"
+ mkdir "${HDL_BUILD_DIR}"
fi
# modelsim uses this sim dir for testing
-export HDL_IOFILE_SIM_DIR=${RADIOHDL_BUILD_DIR}/sim
+export HDL_IOFILE_SIM_DIR=${HDL_BUILD_DIR}/sim
if [[ ! -d "${HDL_IOFILE_SIM_DIR}" ]]; then
echo "make sim dir"
echo "${HDL_IOFILE_SIM_DIR}"
@@ -71,12 +71,12 @@ fi
for altera_dir in ${ALTERA_DIR}/*; do
if [[ -d "${altera_dir}" ]] && [[ ! -h "${altera_dir}" ]]; then
echo "copy git hdl_user_components.ipx to ${altera_dir}/ip/altera/user_components.ipx"
- cp ${RADIOHDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
+ cp ${HDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
fi
done
# source also radiohdl and args tools
. ../radiohdl/init_radiohdl.sh
-if [[ -d "${RADIOHDL_WORK}/../args" ]]; then
+if [[ -d "${HDL_WORK}/../args" ]]; then
. ../args/init_args.sh
fi
diff --git a/libraries/base/common/hdllib.cfg b/libraries/base/common/hdllib.cfg
index 81f4422437..a5aa29dd84 100644
--- a/libraries/base/common/hdllib.cfg
+++ b/libraries/base/common/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology =
synth_files =
- $RADIOHDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd
+ $HDL_WORK/libraries/base/common/src/vhdl/common_pkg.vhd
src/vhdl/common_str_pkg.vhd
src/vhdl/common_mem_pkg.vhd
src/vhdl/common_field_pkg.vhd
diff --git a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
index cca9e1d6c5..984cb4c6f5 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
+++ b/libraries/base/dp/designs/unb1_dp_offload/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
+ $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.vhd
src/vhdl/mmm_unb1_dp_offload.vhd
src/vhdl/unb1_dp_offload.vhd
@@ -26,8 +26,8 @@ quartus_copy_files =
src/hex hex
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_head.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board_tail.qsf
quartus_tcl_files =
quartus/unb1_dp_offload_pins.tcl
@@ -35,7 +35,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_dp_offload/sopc_unb1_dp_offload.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/libraries/base/dp/hdllib.cfg b/libraries/base/dp/hdllib.cfg
index 5ec867ca06..4dae8aaf5b 100644
--- a/libraries/base/dp/hdllib.cfg
+++ b/libraries/base/dp/hdllib.cfg
@@ -426,4 +426,4 @@ regression_test_vhdl =
[quartus_project_file]
quartus_copy_files =
- $RADIOHDL_WORK/libraries/base/dp/quartus_unb2c quartus_unb2c
+ $HDL_WORK/libraries/base/dp/quartus_unb2c quartus_unb2c
diff --git a/libraries/base/reorder/hdllib.cfg b/libraries/base/reorder/hdllib.cfg
index 724281760a..5ca2d878af 100644
--- a/libraries/base/reorder/hdllib.cfg
+++ b/libraries/base/reorder/hdllib.cfg
@@ -47,7 +47,7 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
index e424ea9d5f..a4ae352d90 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
+ $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.vhd
src/vhdl/mmm_unb1_fn_bf.vhd
src/vhdl/node_unb1_fn_bf.vhd
src/vhdl/unb1_fn_bf.vhd
@@ -24,14 +24,14 @@ synth_top_level_entity =
quartus_copy_files = quartus/sopc_unb1_fn_bf.sopc .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_fn_bf_constraints.tcl
quartus/unb1_fn_bf_pins.tcl
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_fn_bf/sopc_unb1_fn_bf.qip
nios2_app_userflags = -DCOMPILE_FOR_SOPC
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
index 04101e79be..8e19ad708f 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
+++ b/libraries/dsp/correlator/designs/unb1_correlator/hdllib.cfg
@@ -5,7 +5,7 @@ hdl_lib_uses_sim =
hdl_lib_technology = ip_stratixiv
synth_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
+ $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.v
src/vhdl/mmm_unb1_correlator.vhd
src/vhdl/unb1_correlator.vhd
@@ -23,7 +23,7 @@ quartus_copy_files =
quartus/qsys_unb1_correlator.qsys .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_correlator_pins.tcl
@@ -31,7 +31,7 @@ quartus_tcl_files =
quartus_vhdl_files =
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
+ $HDL_BUILD_DIR/unb1/quartus/unb1_correlator/qsys_unb1_correlator/synthesis/qsys_unb1_correlator.qip
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
index 896a25a6ad..63d1a25edc 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
@@ -266,7 +266,7 @@ BEGIN
g_sim => TRUE,
g_pass_through => FALSE,
g_rec_not_play => TRUE,
- g_rec_play_file => "$RADIOHDL_WORK/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
+ g_rec_play_file => "$HDL_WORK/libraries/dsp/correlator/tb/rec/correlator_src_out_arr0.rec",
g_record_invalid => FALSE
)
PORT MAP (
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
index 785430c6b0..03e4b1cd5b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
@@ -26,7 +26,7 @@
-- The g_data_file with input and expected output data is created by the
-- Matlab script:
--
--- $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
+-- $HDL_WORK/applications/apertif/matlab/run_pfft.m
--
-- yields:
--
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
index 6c155ee41d..dbc4808a25 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
@@ -22,7 +22,7 @@
-- Purpose: Multi-testbench for fft_r2_par using file data
-- Description:
-- Verify fft_r2_par using and data generated by Matlab
--- $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
+-- $HDL_WORK/applications/apertif/matlab/run_pfft.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
index ba5514038f..34a0dd394e 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
@@ -22,7 +22,7 @@
-- Purpose: Multi-testbench for fft_r2_pipe using file data
-- Description:
-- Verify fft_r2_pipe using and data generated by Matlab
--- $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
+-- $HDL_WORK/applications/apertif/matlab/run_pfft.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
index 9c2132abc6..bb9bd24684 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
@@ -23,8 +23,8 @@
-- Description:
-- Verify fft_r2_wide using and data generated by Matlab scripts:
--
--- - $RADIOHDL_WORK/applications/apertif/matlab/run_pfft.m
--- - $RADIOHDL_WORK/applications/apertif/matlab/run_pfft_complex.m
+-- - $HDL_WORK/applications/apertif/matlab/run_pfft.m
+-- - $HDL_WORK/applications/apertif/matlab/run_pfft_complex.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/filter/src/python/diff_lofar_coefs b/libraries/dsp/filter/src/python/diff_lofar_coefs
index 529bf5381f..7b82cee173 100755
--- a/libraries/dsp/filter/src/python/diff_lofar_coefs
+++ b/libraries/dsp/filter/src/python/diff_lofar_coefs
@@ -31,81 +31,81 @@
# the subband statistics will not peak low to 0 dB.
echo "1) Check that copies of LOFAR FIR coefficient reference files are equal"
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
+diff $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UPE_GEAR/apps/commissioning_apertif_beamformer/coeffs16384Kaiser-quant.dat
+diff $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $UNB/Firmware/modules/Lofar/pfs/src/data/Coeffs16384Kaiser-quant.dat
+diff $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-withdc.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_lofar_subband_16taps_1024points_16b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_lofar_subband_16taps_1024points_16b.dat
echo "2) Check that the local stored LOFAR FIR coefficients mif files are the same as in apertif_unb1_bn_filterbank"
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-diff coefs_wide4_p1024_t16_0.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
-diff coefs_wide4_p1024_t16_1.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
-diff coefs_wide4_p1024_t16_2.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
-diff coefs_wide4_p1024_t16_3.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
-diff coefs_wide4_p1024_t16_4.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
-diff coefs_wide4_p1024_t16_5.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
-diff coefs_wide4_p1024_t16_6.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
-diff coefs_wide4_p1024_t16_7.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
-diff coefs_wide4_p1024_t16_8.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
-diff coefs_wide4_p1024_t16_9.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
-diff coefs_wide4_p1024_t16_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
-diff coefs_wide4_p1024_t16_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
-diff coefs_wide4_p1024_t16_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
-diff coefs_wide4_p1024_t16_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
-diff coefs_wide4_p1024_t16_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
-diff coefs_wide4_p1024_t16_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
-diff coefs_wide4_p1024_t16_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
-diff coefs_wide4_p1024_t16_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
-diff coefs_wide4_p1024_t16_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
-diff coefs_wide4_p1024_t16_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
-diff coefs_wide4_p1024_t16_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
-diff coefs_wide4_p1024_t16_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
-diff coefs_wide4_p1024_t16_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
-diff coefs_wide4_p1024_t16_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
-diff coefs_wide4_p1024_t16_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
-diff coefs_wide4_p1024_t16_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
-diff coefs_wide4_p1024_t16_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
-diff coefs_wide4_p1024_t16_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
-diff coefs_wide4_p1024_t16_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
-diff coefs_wide4_p1024_t16_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
-diff coefs_wide4_p1024_t16_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
-diff coefs_wide4_p1024_t16_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
-diff coefs_wide4_p1024_t16_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
-diff coefs_wide4_p1024_t16_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
-diff coefs_wide4_p1024_t16_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
-diff coefs_wide4_p1024_t16_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
-diff coefs_wide4_p1024_t16_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
-diff coefs_wide4_p1024_t16_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
-diff coefs_wide4_p1024_t16_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
-diff coefs_wide4_p1024_t16_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
-diff coefs_wide4_p1024_t16_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
-diff coefs_wide4_p1024_t16_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
-diff coefs_wide4_p1024_t16_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
-diff coefs_wide4_p1024_t16_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
-diff coefs_wide4_p1024_t16_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
-diff coefs_wide4_p1024_t16_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
-diff coefs_wide4_p1024_t16_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
-diff coefs_wide4_p1024_t16_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
-diff coefs_wide4_p1024_t16_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
-diff coefs_wide4_p1024_t16_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
-diff coefs_wide4_p1024_t16_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
-diff coefs_wide4_p1024_t16_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
-diff coefs_wide4_p1024_t16_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
-diff coefs_wide4_p1024_t16_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
-diff coefs_wide4_p1024_t16_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
-diff coefs_wide4_p1024_t16_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
-diff coefs_wide4_p1024_t16_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
-diff coefs_wide4_p1024_t16_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
-diff coefs_wide4_p1024_t16_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
-diff coefs_wide4_p1024_t16_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
-diff coefs_wide4_p1024_t16_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
-diff coefs_wide4_p1024_t16_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
-diff coefs_wide4_p1024_t16_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
-diff coefs_wide4_p1024_t16_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
+cd $HDL_WORK/libraries/dsp/filter/src/hex
+diff coefs_wide4_p1024_t16_0.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
+diff coefs_wide4_p1024_t16_1.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
+diff coefs_wide4_p1024_t16_2.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
+diff coefs_wide4_p1024_t16_3.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
+diff coefs_wide4_p1024_t16_4.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
+diff coefs_wide4_p1024_t16_5.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
+diff coefs_wide4_p1024_t16_6.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
+diff coefs_wide4_p1024_t16_7.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
+diff coefs_wide4_p1024_t16_8.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
+diff coefs_wide4_p1024_t16_9.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
+diff coefs_wide4_p1024_t16_10.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
+diff coefs_wide4_p1024_t16_11.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
+diff coefs_wide4_p1024_t16_12.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
+diff coefs_wide4_p1024_t16_13.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
+diff coefs_wide4_p1024_t16_14.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
+diff coefs_wide4_p1024_t16_15.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
+diff coefs_wide4_p1024_t16_16.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
+diff coefs_wide4_p1024_t16_17.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
+diff coefs_wide4_p1024_t16_18.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
+diff coefs_wide4_p1024_t16_19.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
+diff coefs_wide4_p1024_t16_20.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
+diff coefs_wide4_p1024_t16_21.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
+diff coefs_wide4_p1024_t16_22.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
+diff coefs_wide4_p1024_t16_23.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
+diff coefs_wide4_p1024_t16_24.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
+diff coefs_wide4_p1024_t16_25.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
+diff coefs_wide4_p1024_t16_26.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
+diff coefs_wide4_p1024_t16_27.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
+diff coefs_wide4_p1024_t16_28.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
+diff coefs_wide4_p1024_t16_29.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
+diff coefs_wide4_p1024_t16_30.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
+diff coefs_wide4_p1024_t16_31.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
+diff coefs_wide4_p1024_t16_32.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
+diff coefs_wide4_p1024_t16_33.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
+diff coefs_wide4_p1024_t16_34.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
+diff coefs_wide4_p1024_t16_35.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
+diff coefs_wide4_p1024_t16_36.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
+diff coefs_wide4_p1024_t16_37.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
+diff coefs_wide4_p1024_t16_38.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
+diff coefs_wide4_p1024_t16_39.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
+diff coefs_wide4_p1024_t16_40.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
+diff coefs_wide4_p1024_t16_41.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
+diff coefs_wide4_p1024_t16_42.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
+diff coefs_wide4_p1024_t16_43.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
+diff coefs_wide4_p1024_t16_44.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
+diff coefs_wide4_p1024_t16_45.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
+diff coefs_wide4_p1024_t16_46.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
+diff coefs_wide4_p1024_t16_47.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
+diff coefs_wide4_p1024_t16_48.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
+diff coefs_wide4_p1024_t16_49.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
+diff coefs_wide4_p1024_t16_50.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
+diff coefs_wide4_p1024_t16_51.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
+diff coefs_wide4_p1024_t16_52.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
+diff coefs_wide4_p1024_t16_53.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
+diff coefs_wide4_p1024_t16_54.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
+diff coefs_wide4_p1024_t16_55.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
+diff coefs_wide4_p1024_t16_56.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
+diff coefs_wide4_p1024_t16_57.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
+diff coefs_wide4_p1024_t16_58.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
+diff coefs_wide4_p1024_t16_59.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
+diff coefs_wide4_p1024_t16_60.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
+diff coefs_wide4_p1024_t16_61.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
+diff coefs_wide4_p1024_t16_62.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
+diff coefs_wide4_p1024_t16_63.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
echo "3) Verify that the created reference LOFAR FIR coefficients mif files are equal to the local stored mif files"
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+cd $HDL_WORK/libraries/dsp/filter/src/hex
diff Coeffs16384Kaiser-quant_4wb_0.mif coefs_wide4_p1024_t16_0.mif
diff Coeffs16384Kaiser-quant_4wb_1.mif coefs_wide4_p1024_t16_1.mif
diff Coeffs16384Kaiser-quant_4wb_2.mif coefs_wide4_p1024_t16_2.mif
@@ -172,142 +172,142 @@ diff Coeffs16384Kaiser-quant_4wb_62.mif coefs_wide4_p1024_t16_62.mif
diff Coeffs16384Kaiser-quant_4wb_63.mif coefs_wide4_p1024_t16_63.mif
echo "4) Verify that the created reference LOFAR FIR coefficients mif files are equal to the mif files stored at apertif_unb1_bn_filterbank"
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-diff Coeffs16384Kaiser-quant_4wb_0.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
-diff Coeffs16384Kaiser-quant_4wb_1.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
-diff Coeffs16384Kaiser-quant_4wb_2.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
-diff Coeffs16384Kaiser-quant_4wb_3.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
-diff Coeffs16384Kaiser-quant_4wb_4.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
-diff Coeffs16384Kaiser-quant_4wb_5.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
-diff Coeffs16384Kaiser-quant_4wb_6.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
-diff Coeffs16384Kaiser-quant_4wb_7.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
-diff Coeffs16384Kaiser-quant_4wb_8.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
-diff Coeffs16384Kaiser-quant_4wb_9.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
-diff Coeffs16384Kaiser-quant_4wb_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
-diff Coeffs16384Kaiser-quant_4wb_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
-diff Coeffs16384Kaiser-quant_4wb_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
-diff Coeffs16384Kaiser-quant_4wb_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
-diff Coeffs16384Kaiser-quant_4wb_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
-diff Coeffs16384Kaiser-quant_4wb_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
-diff Coeffs16384Kaiser-quant_4wb_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
-diff Coeffs16384Kaiser-quant_4wb_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
-diff Coeffs16384Kaiser-quant_4wb_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
-diff Coeffs16384Kaiser-quant_4wb_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
-diff Coeffs16384Kaiser-quant_4wb_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
-diff Coeffs16384Kaiser-quant_4wb_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
-diff Coeffs16384Kaiser-quant_4wb_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
-diff Coeffs16384Kaiser-quant_4wb_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
-diff Coeffs16384Kaiser-quant_4wb_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
-diff Coeffs16384Kaiser-quant_4wb_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
-diff Coeffs16384Kaiser-quant_4wb_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
-diff Coeffs16384Kaiser-quant_4wb_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
-diff Coeffs16384Kaiser-quant_4wb_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
-diff Coeffs16384Kaiser-quant_4wb_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
-diff Coeffs16384Kaiser-quant_4wb_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
-diff Coeffs16384Kaiser-quant_4wb_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
-diff Coeffs16384Kaiser-quant_4wb_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
-diff Coeffs16384Kaiser-quant_4wb_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
-diff Coeffs16384Kaiser-quant_4wb_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
-diff Coeffs16384Kaiser-quant_4wb_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
-diff Coeffs16384Kaiser-quant_4wb_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
-diff Coeffs16384Kaiser-quant_4wb_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
-diff Coeffs16384Kaiser-quant_4wb_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
-diff Coeffs16384Kaiser-quant_4wb_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
-diff Coeffs16384Kaiser-quant_4wb_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
-diff Coeffs16384Kaiser-quant_4wb_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
-diff Coeffs16384Kaiser-quant_4wb_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
-diff Coeffs16384Kaiser-quant_4wb_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
-diff Coeffs16384Kaiser-quant_4wb_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
-diff Coeffs16384Kaiser-quant_4wb_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
-diff Coeffs16384Kaiser-quant_4wb_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
-diff Coeffs16384Kaiser-quant_4wb_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
-diff Coeffs16384Kaiser-quant_4wb_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
-diff Coeffs16384Kaiser-quant_4wb_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
-diff Coeffs16384Kaiser-quant_4wb_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
-diff Coeffs16384Kaiser-quant_4wb_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
-diff Coeffs16384Kaiser-quant_4wb_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
-diff Coeffs16384Kaiser-quant_4wb_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
-diff Coeffs16384Kaiser-quant_4wb_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
-diff Coeffs16384Kaiser-quant_4wb_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
-diff Coeffs16384Kaiser-quant_4wb_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
-diff Coeffs16384Kaiser-quant_4wb_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
-diff Coeffs16384Kaiser-quant_4wb_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
-diff Coeffs16384Kaiser-quant_4wb_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
-diff Coeffs16384Kaiser-quant_4wb_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
-diff Coeffs16384Kaiser-quant_4wb_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
-diff Coeffs16384Kaiser-quant_4wb_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
-diff Coeffs16384Kaiser-quant_4wb_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
+cd $HDL_WORK/libraries/dsp/filter/src/hex
+diff Coeffs16384Kaiser-quant_4wb_0.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_0.mif
+diff Coeffs16384Kaiser-quant_4wb_1.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_1.mif
+diff Coeffs16384Kaiser-quant_4wb_2.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_2.mif
+diff Coeffs16384Kaiser-quant_4wb_3.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_3.mif
+diff Coeffs16384Kaiser-quant_4wb_4.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_4.mif
+diff Coeffs16384Kaiser-quant_4wb_5.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_5.mif
+diff Coeffs16384Kaiser-quant_4wb_6.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_6.mif
+diff Coeffs16384Kaiser-quant_4wb_7.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_7.mif
+diff Coeffs16384Kaiser-quant_4wb_8.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_8.mif
+diff Coeffs16384Kaiser-quant_4wb_9.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_9.mif
+diff Coeffs16384Kaiser-quant_4wb_10.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_10.mif
+diff Coeffs16384Kaiser-quant_4wb_11.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_11.mif
+diff Coeffs16384Kaiser-quant_4wb_12.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_12.mif
+diff Coeffs16384Kaiser-quant_4wb_13.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_13.mif
+diff Coeffs16384Kaiser-quant_4wb_14.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_14.mif
+diff Coeffs16384Kaiser-quant_4wb_15.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_15.mif
+diff Coeffs16384Kaiser-quant_4wb_16.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_16.mif
+diff Coeffs16384Kaiser-quant_4wb_17.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_17.mif
+diff Coeffs16384Kaiser-quant_4wb_18.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_18.mif
+diff Coeffs16384Kaiser-quant_4wb_19.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_19.mif
+diff Coeffs16384Kaiser-quant_4wb_20.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_20.mif
+diff Coeffs16384Kaiser-quant_4wb_21.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_21.mif
+diff Coeffs16384Kaiser-quant_4wb_22.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_22.mif
+diff Coeffs16384Kaiser-quant_4wb_23.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_23.mif
+diff Coeffs16384Kaiser-quant_4wb_24.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_24.mif
+diff Coeffs16384Kaiser-quant_4wb_25.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_25.mif
+diff Coeffs16384Kaiser-quant_4wb_26.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_26.mif
+diff Coeffs16384Kaiser-quant_4wb_27.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_27.mif
+diff Coeffs16384Kaiser-quant_4wb_28.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_28.mif
+diff Coeffs16384Kaiser-quant_4wb_29.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_29.mif
+diff Coeffs16384Kaiser-quant_4wb_30.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_30.mif
+diff Coeffs16384Kaiser-quant_4wb_31.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_31.mif
+diff Coeffs16384Kaiser-quant_4wb_32.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_32.mif
+diff Coeffs16384Kaiser-quant_4wb_33.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_33.mif
+diff Coeffs16384Kaiser-quant_4wb_34.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_34.mif
+diff Coeffs16384Kaiser-quant_4wb_35.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_35.mif
+diff Coeffs16384Kaiser-quant_4wb_36.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_36.mif
+diff Coeffs16384Kaiser-quant_4wb_37.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_37.mif
+diff Coeffs16384Kaiser-quant_4wb_38.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_38.mif
+diff Coeffs16384Kaiser-quant_4wb_39.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_39.mif
+diff Coeffs16384Kaiser-quant_4wb_40.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_40.mif
+diff Coeffs16384Kaiser-quant_4wb_41.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_41.mif
+diff Coeffs16384Kaiser-quant_4wb_42.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_42.mif
+diff Coeffs16384Kaiser-quant_4wb_43.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_43.mif
+diff Coeffs16384Kaiser-quant_4wb_44.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_44.mif
+diff Coeffs16384Kaiser-quant_4wb_45.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_45.mif
+diff Coeffs16384Kaiser-quant_4wb_46.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_46.mif
+diff Coeffs16384Kaiser-quant_4wb_47.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_47.mif
+diff Coeffs16384Kaiser-quant_4wb_48.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_48.mif
+diff Coeffs16384Kaiser-quant_4wb_49.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_49.mif
+diff Coeffs16384Kaiser-quant_4wb_50.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_50.mif
+diff Coeffs16384Kaiser-quant_4wb_51.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_51.mif
+diff Coeffs16384Kaiser-quant_4wb_52.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_52.mif
+diff Coeffs16384Kaiser-quant_4wb_53.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_53.mif
+diff Coeffs16384Kaiser-quant_4wb_54.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_54.mif
+diff Coeffs16384Kaiser-quant_4wb_55.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_55.mif
+diff Coeffs16384Kaiser-quant_4wb_56.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_56.mif
+diff Coeffs16384Kaiser-quant_4wb_57.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_57.mif
+diff Coeffs16384Kaiser-quant_4wb_58.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_58.mif
+diff Coeffs16384Kaiser-quant_4wb_59.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_59.mif
+diff Coeffs16384Kaiser-quant_4wb_60.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_60.mif
+diff Coeffs16384Kaiser-quant_4wb_61.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_61.mif
+diff Coeffs16384Kaiser-quant_4wb_62.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_62.mif
+diff Coeffs16384Kaiser-quant_4wb_63.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_wide4_p1024_t16_63.mif
echo "5) Verify that the created reference LOFAR No DC FIR coefficients mif files are equal to the mif files stored at apertif_unb1_bn_filterbank"
# To create the *.mif use recreate_pfir_mifs or directly use:
-# python $RADIOHDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-diff Coeffs16384Kaiser-quant-nodc_4wb_0.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_0.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_1.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_1.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_2.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_2.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_3.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_3.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_4.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_4.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_5.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_5.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_6.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_6.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_7.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_7.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_8.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_8.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_9.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_9.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_10.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_10.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_11.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_11.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_12.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_12.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_13.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_13.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_14.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_14.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_15.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_15.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_16.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_16.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_17.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_17.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_18.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_18.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_19.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_19.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_20.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_20.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_21.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_21.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_22.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_22.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_23.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_23.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_24.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_24.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_25.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_25.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_26.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_26.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_27.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_27.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_28.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_28.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_29.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_29.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_30.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_30.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_31.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_31.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_32.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_32.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_33.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_33.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_34.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_34.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_35.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_35.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_36.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_36.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_37.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_37.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_38.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_38.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_39.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_39.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_40.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_40.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_41.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_41.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_42.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_42.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_43.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_43.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_44.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_44.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_45.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_45.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_46.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_46.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_47.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_47.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_48.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_48.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_49.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_49.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_50.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_50.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_51.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_51.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_52.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_52.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_53.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_53.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_54.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_54.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_55.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_55.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_56.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_56.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_57.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_57.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_58.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_58.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_59.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_59.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_60.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_60.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_61.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_61.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_62.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_62.mif
-diff Coeffs16384Kaiser-quant-nodc_4wb_63.mif $RADIOHDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_63.mif
+# python $HDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py -f $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
+cd $HDL_WORK/libraries/dsp/filter/src/hex
+diff Coeffs16384Kaiser-quant-nodc_4wb_0.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_0.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_1.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_1.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_2.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_2.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_3.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_3.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_4.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_4.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_5.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_5.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_6.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_6.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_7.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_7.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_8.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_8.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_9.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_9.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_10.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_10.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_11.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_11.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_12.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_12.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_13.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_13.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_14.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_14.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_15.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_15.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_16.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_16.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_17.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_17.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_18.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_18.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_19.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_19.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_20.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_20.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_21.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_21.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_22.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_22.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_23.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_23.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_24.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_24.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_25.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_25.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_26.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_26.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_27.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_27.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_28.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_28.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_29.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_29.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_30.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_30.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_31.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_31.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_32.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_32.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_33.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_33.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_34.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_34.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_35.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_35.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_36.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_36.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_37.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_37.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_38.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_38.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_39.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_39.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_40.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_40.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_41.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_41.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_42.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_42.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_43.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_43.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_44.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_44.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_45.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_45.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_46.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_46.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_47.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_47.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_48.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_48.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_49.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_49.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_50.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_50.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_51.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_51.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_52.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_52.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_53.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_53.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_54.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_54.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_55.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_55.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_56.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_56.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_57.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_57.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_58.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_58.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_59.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_59.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_60.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_60.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_61.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_61.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_62.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_62.mif
+diff Coeffs16384Kaiser-quant-nodc_4wb_63.mif $HDL_WORK/applications/apertif/designs/apertif_unb1_bn_filterbank/src/hex/coefs_nodc_wide4_p1024_t16_63.mif
echo "6) Set script exit directory"
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cd $HDL_WORK/libraries/dsp/filter/src/python
diff --git a/libraries/dsp/filter/src/python/diff_pfir_coefs b/libraries/dsp/filter/src/python/diff_pfir_coefs
index 84b0765968..55e74a18af 100755
--- a/libraries/dsp/filter/src/python/diff_pfir_coefs
+++ b/libraries/dsp/filter/src/python/diff_pfir_coefs
@@ -9,16 +9,16 @@
#
# Expected result is that this diff_pfir_coefs script does not report diff's
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_16b.dat ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_bypass_8taps_64points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat ../hex/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat
-diff $RADIOHDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_16b.dat ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_bypass_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_bypass_8taps_64points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_fircls1_8taps_32points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_fircls1_8taps_64points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_32points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_fircls1_8taps_64points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_32points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_8taps_64points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat ../hex/run_pfir_coeff_m_incrementing_8taps_64points_16b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat ../hex/run_pfir_coeff_m_incrementing_8taps_64points_9b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat
+diff $HDL_WORK/applications/apertif/matlab/data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat
diff --git a/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py b/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
index 2b18c920e5..003a49c3de 100644
--- a/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
+++ b/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
@@ -43,10 +43,10 @@
line argument and is only used to identify the input dat file.
A pfir_coeff_*.dat file can be created using Matlab:
- > $RADIOHDL_WORK/applications/apertif/matlab/run_pfir_coef.m
+ > $HDL_WORK/applications/apertif/matlab/run_pfir_coef.m
The result is then (dependend on the actual settings in run_pfir_coef.m):
- > $RADIOHDL_WORK/applications/apertif/matlab/data/pfir_coeff_incrementing_8taps_64points_16b.dat
+ > $HDL_WORK/applications/apertif/matlab/data/pfir_coeff_incrementing_8taps_64points_16b.dat
This coefficients dat file needs to be copied to the local ../hex directory,
because both the dat and the MIF files sare used in the VHDL testbenches.
diff --git a/libraries/dsp/filter/src/python/recreate_4wb_mifs b/libraries/dsp/filter/src/python/recreate_4wb_mifs
index f285a59c2b..80899c648d 100755
--- a/libraries/dsp/filter/src/python/recreate_4wb_mifs
+++ b/libraries/dsp/filter/src/python/recreate_4wb_mifs
@@ -2,7 +2,7 @@
#find . -name "*4wb_0.mif" - print
# It appears they only are created in the filter library:
-#cd $RADIOHDL_WORK/libraries/dsp/filter/src/hex/
+#cd $HDL_WORK/libraries/dsp/filter/src/hex/
#ll *4wb_0.mif
# yields:
# run_pfb_m_pfir_coeff_fircls1_16taps_32points_16b_4wb_0.mif
@@ -23,7 +23,7 @@
# any Python scripts that Hajee made to access the FIR coefficients in apertif_unb1_bn_filterbank
# will still also work for wpfb_unit_dev.
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cd $HDL_WORK/libraries/dsp/filter/src/python
python fil_ppf_create_mifs.py -f ../hex/run_pfb_m_pfir_coeff_fircls1_16taps_32points_16b.dat -t 16 -p 32 -w 4 -c 16
python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_15taps_128points_16b.dat -t 15 -p 128 -w 4 -c 16
diff --git a/libraries/dsp/filter/src/python/recreate_pfir_mifs b/libraries/dsp/filter/src/python/recreate_pfir_mifs
index 05bcc11aa0..2cda88e4e3 100755
--- a/libraries/dsp/filter/src/python/recreate_pfir_mifs
+++ b/libraries/dsp/filter/src/python/recreate_pfir_mifs
@@ -17,7 +17,7 @@
# > svn status -q ../hex
#
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cd $HDL_WORK/libraries/dsp/filter/src/python
# run_pfir.m
python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_15taps_128points_16b.dat -t 15 -p 128 -w 4 -c 16
@@ -37,9 +37,9 @@ python fil_ppf_create_mifs.py -f ../hex/run_pfb_complex_m_pfir_coeff_fircls1_16t
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat -t 16 -p 1024 -w 4 -c 16
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_lofar_subband_16taps_1024points_16b.dat -t 16 -p 1024 -w 4 -c 16
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat -t 16 -p 1024 -w 4 -c 16
-python fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat -t 16 -p 1024 -w 4 -c 16
+python fil_ppf_create_mifs.py -f $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant.dat -t 16 -p 1024 -w 4 -c 16
-python fil_ppf_create_mifs.py -f $RADIOHDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
+python fil_ppf_create_mifs.py -f $HDL_WORK/applications/apertif/matlab/data/Coeffs16384Kaiser-quant-nodc.dat -t 16 -p 1024 -w 4 -c 16
# run_pfir_coeff.m : channel filterbank (wb = 1)
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_bypass_8taps_64points_16b.dat -t 8 -p 64 -w 1 -c 16
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
index 11a108d75c..73c91c43ee 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
@@ -68,11 +68,11 @@
--
-- The reference dat file is generated by the Matlab program:
--
--- $RADIOHDL_WORK/applications/apertif/matlab/run_pfir_coeff.m
+-- $HDL_WORK/applications/apertif/matlab/run_pfir_coeff.m
--
-- The MIF files are generated by the Python script:
--
--- $RADIOHDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
+-- $HDL_WORK/libraries/dsp/filter/src/python/fil_ppf_create_mifs.py
--
-- The reference dat file and the MIF files use the same g_coefs_file_prefix.
-- For the reference dat file this prefix is expanded by nof_taps, nof_bands
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
index c56ad13945..819536b860 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
@@ -29,7 +29,7 @@
-- The g_coefs_file_prefix dat-file and g_data_file dat-file are created by
-- the Matlab script:
--
--- $RADIOHDL_WORK/applications/apertif/matlab/run_pfir.m
+-- $HDL_WORK/applications/apertif/matlab/run_pfir.m
--
-- yields:
--
@@ -51,7 +51,7 @@
-- The MIF files are generated from the g_coefs_file_prefix dat-file by
-- the Python script:
--
--- $RADIOHDL_WORK/libraries/dsp/filter/src/python/
+-- $HDL_WORK/libraries/dsp/filter/src/python/
-- python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_16taps_128points_16b.dat -t 16 -p 128 -w 1 -c 16
-- python fil_ppf_create_mifs.py -f ../hex/run_pfir_m_pfir_coeff_fircls1_16taps_128points_16b.dat -t 16 -p 128 -w 4 -c 16
--
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
index 68d1322523..8d35654818 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
@@ -22,7 +22,7 @@
-- Purpose: Multi-testbench for fil_ppf_wide using file data
-- Description:
-- Verify fil_ppf_wide using coefficients and data generated by
--- Matlab $RADIOHDL_WORK/applications/apertif/matlab/run_pfir.m
+-- Matlab $HDL_WORK/applications/apertif/matlab/run_pfir.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/verify_pfb/hdllib.cfg b/libraries/dsp/verify_pfb/hdllib.cfg
index 66bab97861..30d4c61348 100644
--- a/libraries/dsp/verify_pfb/hdllib.cfg
+++ b/libraries/dsp/verify_pfb/hdllib.cfg
@@ -21,14 +21,14 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../
../../base/diag/src/data data # WG
# APERTIF wpfb
../filter/src/hex data # PFIR filter coefficients
../wpfb/tb/data data
# LOFAR1 pfs + pft2
- $RADIOHDL_WORK/applications/lofar1/RSP/pfs/src/data data # FIR filter coefficients
- $RADIOHDL_WORK/applications/lofar1/RSP/pft2/src/data data # FFT twiddle factors
+ $HDL_WORK/applications/lofar1/RSP/pfs/src/data data # FIR filter coefficients
+ $HDL_WORK/applications/lofar1/RSP/pft2/src/data data # FFT twiddle factors
[quartus_project_file]
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt
index 1d46215a1a..24c2ae21fd 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.txt
@@ -3522,19 +3522,19 @@ cd /dop466_0/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/applications/apertif/m
--> run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_16b.dat
--> run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_18b.dat
-cp data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_fircls1_16taps_1024points_18b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_18b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_16b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cp data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_18b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_fircls1_16taps_1024points_18b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_16b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_no_dc_fircls1_16taps_1024points_18b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_16b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cp data/run_pfir_coeff_m_flat_hp_no_dc_fircls1_16taps_1024points_18b.dat $HDL_WORK/libraries/dsp/filter/src/hex
cd /dop466_0/kooistra/git/hdl
. ./init_hdl.sh
cd /dop466_0/kooistra/git/upe_gear
. ./init_upe.sh
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cd $HDL_WORK/libraries/dsp/filter/src/python
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_16b.dat -t 16 -p 1024 -w 1 -c 16
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_fircls1_16taps_1024points_18b.dat -t 16 -p 1024 -w 1 -c 18
@@ -3545,8 +3545,8 @@ python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_flat_hp_no_dc_fircls1_1
11 jan 2021: Create FIR bypass coefficients for LOFAR PFB:
cd /dop466_0/kooistra/svnroot/UniBoard_FP7/RadioHDL/trunk/applications/apertif/matlab
-cp data/run_pfir_coeff_m_bypass_16taps_1024points_16b.dat $RADIOHDL_WORK/libraries/dsp/filter/src/hex
-cd $RADIOHDL_WORK/libraries/dsp/filter/src/python
+cp data/run_pfir_coeff_m_bypass_16taps_1024points_16b.dat $HDL_WORK/libraries/dsp/filter/src/hex
+cd $HDL_WORK/libraries/dsp/filter/src/python
python fil_ppf_create_mifs.py -f ../hex/run_pfir_coeff_m_bypass_16taps_1024points_16b.dat -t 16 -p 1024 -w 1 -c 16
ll ../hex/run_pfir_coeff_m_bypass_16taps_1024points_16b*
-rw-r--r-- 1 kooistra kooistra 18236 Jan 11 16:35 ../hex/run_pfir_coeff_m_bypass_16taps_1024points_16b_1wb_0.mif
diff --git a/libraries/dsp/wpfb/hdllib.cfg b/libraries/dsp/wpfb/hdllib.cfg
index 52de82f92c..a604bf3dc6 100644
--- a/libraries/dsp/wpfb/hdllib.cfg
+++ b/libraries/dsp/wpfb/hdllib.cfg
@@ -23,14 +23,14 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- # Note: path $RADIOHDL_WORK is equivalent to relative path ../../../
+ # Note: path $HDL_WORK is equivalent to relative path ../../../
modelsim/wave_tb_mmf_wpfb_unit.do .
../filter/src/hex data
tb/data data
../../base/diag/src/data data # WG
# LOFAR1 pfs + pft2
- $RADIOHDL_WORK/applications/lofar1/RSP/pfs/src/data data # FIR filter coefficients
- $RADIOHDL_WORK/applications/lofar1/RSP/pft2/src/data data # Twiddle factors
+ $HDL_WORK/applications/lofar1/RSP/pfs/src/data data # FIR filter coefficients
+ $HDL_WORK/applications/lofar1/RSP/pft2/src/data data # Twiddle factors
[quartus_project_file]
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
index c76e25a5c8..4b681cf63c 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
@@ -23,8 +23,8 @@
-- Description:
-- Verify wpfb_unit_wide using and data generated by Matlab scripts:
--
--- - $RADIOHDL_WORK/applications/apertif/matlab/run_pfb.m
--- - $RADIOHDL_WORK/applications/apertif/matlab/run_pfb_complex.m
+-- - $HDL_WORK/applications/apertif/matlab/run_pfb.m
+-- - $HDL_WORK/applications/apertif/matlab/run_pfb_complex.m
--
-- Usage:
-- > as 4
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index caa83e1592..15516c1b90 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -25,8 +25,8 @@
-- Description:
-- This tb uses the Matlab stimuli and expected results obtained with:
--
--- $RADIOHDL_WORK/applications/apertif/matlab/run_pfb.m
--- $RADIOHDL_WORK/applications/apertif/matlab/run_pfb_complex.m
+-- $HDL_WORK/applications/apertif/matlab/run_pfb.m
+-- $HDL_WORK/applications/apertif/matlab/run_pfb_complex.m
--
-- For more description see:
-- . tb_fil_ppf_wide_file_data.vhd
diff --git a/libraries/io/ddr/hdllib.cfg b/libraries/io/ddr/hdllib.cfg
index 5855c3eb57..8bb8fa2a50 100644
--- a/libraries/io/ddr/hdllib.cfg
+++ b/libraries/io/ddr/hdllib.cfg
@@ -23,11 +23,11 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl # 4GB DDR3 model
- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl # 4GB DDR4 model
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl # Unb2b 4GB DDR4 driver
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl # Unb2b 8GB DDR4 driver
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl # Unb2c 8GB DDR4 driver
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl # 4GB DDR3 model
+ $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl # 4GB DDR4 model
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl # Unb2b 4GB DDR4 driver
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl # Unb2b 8GB DDR4 driver
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl # Unb2c 8GB DDR4 driver
[quartus_project_file]
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index fddc99e9c4..22aced656c 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -28,13 +28,13 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
- $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
- $RADIOHDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
+ $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_AC_ROM.hex .
+ $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_inst_ROM.hex .
+ $HDL_BUILD_DIR/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master/ip_stratixiv_ddr3_uphy_4g_800_master_s0_sequencer_mem.hex .
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
- #$RADIOHDL_WORK/libraries/io/ddr3/src/tcl/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ #$HDL_WORK/libraries/io/ddr3/src/tcl/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index aaca3d6c3c..a45392e234 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -121,7 +121,7 @@ PACKAGE ddr3_pkg IS
CONSTANT c_ddr3_seq : t_ddr3_seq := (64, 1, 16, 4, 0, 5);
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -173,7 +173,7 @@ PACKAGE ddr3_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
diff --git a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
index a090ba6f04..fe613ff4ae 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
+++ b/libraries/io/eth/designs/unb1_eth_10g/hdllib.cfg
@@ -21,15 +21,15 @@ synth_top_level_entity =
quartus_copy_files = quartus/qsys_unb1_eth_10g.qsys .
quartus_qsf_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.qsf
quartus_tcl_files =
quartus/unb1_eth_10g_pins.tcl
-quartus_qip_files = $RADIOHDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
+quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/unb1_eth_10g/qsys_unb1_eth_10g/synthesis/qsys_unb1_eth_10g.qip
quartus_sdc_files =
- $RADIOHDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
+ $HDL_WORK/boards/uniboard1/libraries/unb1_board/quartus/unb1_board.sdc
nios2_app_userflags = -DCOMPILE_FOR_QSYS
diff --git a/libraries/io/eth/hdllib.cfg b/libraries/io/eth/hdllib.cfg
index 39fcfc924d..ef29caf98d 100644
--- a/libraries/io/eth/hdllib.cfg
+++ b/libraries/io/eth/hdllib.cfg
@@ -58,10 +58,10 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
- src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+ #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+ src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
[quartus_project_file]
quartus_copy_files =
- #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
- src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $RADIOHDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
+ #src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_BUILD_DIR/<buildset_name>/avs2_eth_coe_hw.tcl
+ src/vhdl/avs2_eth_coe_hw_<buildset_name>.tcl $HDL_WORK/libraries/io/eth/src/vhdl/avs2_eth_coe_hw.tcl
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index 5c3918e3df..dd86633578 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -83,7 +83,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_800_slave IS
PORT (
@@ -134,7 +134,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_master IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -186,7 +186,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave.v
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
COMPONENT ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave IS
PORT (
@@ -237,7 +237,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from Verilog module $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
+ -- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_16g_dual_rank_800.v
COMPONENT ip_stratixiv_ddr3_uphy_16g_dual_rank_800 IS
PORT (
pll_ref_clk : IN STD_LOGIC; -- pll_ref_clk.clk
@@ -293,7 +293,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_1600.vhd
COMPONENT ip_arria10_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -331,7 +331,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_ddr4_4g_2000.vhd
COMPONENT ip_arria10_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -373,7 +373,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -449,7 +449,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -491,7 +491,7 @@ PACKAGE tech_ddr_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_1600.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_1600 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -604,7 +604,7 @@ PACKAGE tech_ddr_component_pkg IS
);
END COMPONENT;
- -- Manually derived VHDL entity from VHDL file $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
+ -- Manually derived VHDL entity from VHDL file $HDL_BUILD_DIR/sim/ip_arria10_e1sg_ddr4_4g_2000.vhd
COMPONENT ip_arria10_e1sg_ddr4_4g_2000 IS
PORT (
amm_ready_0 : out std_logic; -- ctrl_amm_avalon_slave_0.waitrequest_n
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index ebbb325b5f..5d89d1ff0a 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -32,7 +32,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
------------------------------------------------------------------------------
-- Manually derived VHDL entity from Verilog module alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv in:
- -- $RADIOHDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
+ -- $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_800_master_example_design/simulation/vhdl/submodules/
COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en IS
GENERIC (
@@ -86,7 +86,7 @@ PACKAGE tech_ddr_mem_model_component_pkg IS
------------------------------------------------------------------------------
-- Manually derived VHDL entity from ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd in:
- -- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
+ -- $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
COMPONENT ed_sim_altera_emif_mem_model_141_z3tvrmq IS
PORT (
mem_ck : in std_logic_vector(0 downto 0) := (others => '0'); -- mem_conduit_end.mem_ck
diff --git a/libraries/technology/hdllib.cfg b/libraries/technology/hdllib.cfg
index 09ec26b81a..02e4adb554 100644
--- a/libraries/technology/hdllib.cfg
+++ b/libraries/technology/hdllib.cfg
@@ -6,7 +6,7 @@ hdl_lib_technology =
synth_files =
technology_pkg.vhd
- $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+ $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
test_bench_files =
@@ -16,10 +16,10 @@ regression_test_vhdl =
[modelsim_project_file]
modelsim_copy_files =
- technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+ technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
[quartus_project_file]
quartus_copy_files =
- technology_select_pkg_<buildset_name>.vhd $RADIOHDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
+ technology_select_pkg_<buildset_name>.vhd $HDL_BUILD_DIR/<buildset_name>/technology_select_pkg.vhd
diff --git a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
index 44f305f0b1..5e5795ffac 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
index 102fa8aac0..f3f1864993 100644
--- a/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/clkbuf_global/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/complex_mult/README.txt b/libraries/technology/ip_arria10/complex_mult/README.txt
index c9a33bbdfc..2e863c2d4b 100644
--- a/libraries/technology/ip_arria10/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/complex_mult
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
index 55e6320c95..43acb41dbe 100644
--- a/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
index 962d1268ca..3dd7b59b67 100644
--- a/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/complex_mult/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddio/README.txt b/libraries/technology/ip_arria10/ddio/README.txt
index 1823e822ff..7ea3cfffa4 100755
--- a/libraries/technology/ip_arria10/ddio/README.txt
+++ b/libraries/technology/ip_arria10/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddio
Contents:
diff --git a/libraries/technology/ip_arria10/ddio/compile_ip.tcl b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
index ea28f210cf..5b113d8282 100644
--- a/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_BUILD_DIR)/"
+ set IP_DIR "$env(HDL_BUILD_DIR)/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_150 ./work/
@@ -52,7 +52,7 @@ if {$IPMODEL=="PHY"} {
} else {
# This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
- set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddio/sim/"
+ set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10/ddio/sim/"
vcom "$SIM_DIR/ip_arria10_ddio_in_1.vhd"
vcom "$SIM_DIR/ip_arria10_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10/ddio/hdllib.cfg b/libraries/technology/ip_arria10/ddio/hdllib.cfg
index 79383ba97b..312ee40a8f 100644
--- a/libraries/technology/ip_arria10/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/ddio/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
index 3e5f93390f..92b736708c 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
index b83177faa5..fca54fa813 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
index d6d5dd48ae..64e5fd4f76 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
index fb90cea0b3..ec106dc119 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
index 0126c5c44f..e0de434cf6 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
index 558f712cc2..08ffba7d5d 100644
--- a/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_2000/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
index 297be0f532..748f3779e1 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
index 7987c4b82e..dca56d5c3c 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
index 1687d60fab..c39af9c022 100644
--- a/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/ddr4_8g_2400/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
index 4921c9d617..910c066032 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model
1) DDR4 memory simulation model
2) Automated scripts and one time manual actions
@@ -11,7 +11,7 @@ README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model
The DDR memory model is obtained from the example design that can be generated with Qsys when a DDR IP component is defined.
The first DDR4 component that was created is available via:
- $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
+ $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys
Unfortunately the example design needs to be created via the GUI by pressing the 'Example Design...' button, because the qsys-generate command
that is used in ddr4_4g_1600/generate_ip.sh to create the component does not have an option to also create the example design. After that the
@@ -21,20 +21,20 @@ memory model have been copied to a fixed location in SVN. In this way it is no l
In the example design for ddr4_4g_1600 the generic core files of the DDR model are located at:
- $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141
+ $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_core_ddr4_141
The size specific entity of the DDR model is created in:
- $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+ $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
The generic core files of the DDR memory model are the same for every DDR size. These files only depend on the Quartus tool version as indicated by 141
(Quartus 14.1) in their name. Therefore the generic core files have been copied to:
- $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core
+ $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_core
The size specific DDR component file is copied to:
- $env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
+ $env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141/sim/ddr4_4g_1600/ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd
and other size DDR component files can be store there as well.
@@ -49,7 +49,7 @@ but it is good to manually check with Linux 'diff' as in diff_mem_model.sh that
2) Automated scripts and one time manual actions
-Relative to $RADIOHDL_WORK/libraries/technology/ip_arria10/:
+Relative to $HDL_WORK/libraries/technology/ip_arria10/:
- ddr4_4g_1600/ip_arria10_ddr4_4g_1600.qsys : Qsys definition file for size and speed specific DDR4 controller
- ddr4_4g_1600/generate_ip.sh : Use qsys-generate to create the size and speed specific DDR4 controller
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
index 94d8e8d0c5..821fd74386 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
@@ -20,9 +20,9 @@
#
#------------------------------------------------------------------------------
-# This file is based on Qsys-generated file $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/mentor/msim_setup.tcl.
+# This file is based on Qsys-generated file $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/mentor/msim_setup.tcl.
#
-set IP_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141"
+set IP_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10/ddr4_mem_model_141"
# Assume library work already exists
vmap ed_sim_altera_emif_mem_model_core_ddr4_141 ./work/
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
index bd39700d7f..68e362d61e 100755
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/diff_mem_model.sh
@@ -31,7 +31,7 @@
#
# eg:
#
-# ./diff_mem_model.sh $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design
+# ./diff_mem_model.sh $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design
#
EXAMPLE_DESIGN_DIR=${1}
diff --git a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
index bdd0226b24..40a46f994f 100644
--- a/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
+++ b/libraries/technology/ip_arria10/ddr4_mem_model_141/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/ddr4_mem_model_141/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fifo/README.txt b/libraries/technology/ip_arria10/fifo/README.txt
index 6db25b6412..bcf8b55de2 100755
--- a/libraries/technology/ip_arria10/fifo/README.txt
+++ b/libraries/technology/ip_arria10/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/fifo
Contents:
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
index 32237451dc..7ad84ee07b 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
vmap ip_arria10_asmi_parallel_altera_asmi_parallel_150 ./work/
diff --git a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
index a9fea8a6d5..2cb9e180fa 100644
--- a/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/flash/asmi_parallel/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
index bd002e3492..46836c8393 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
vmap ip_arria10_remote_update_altera_remote_update_core_150 ./work/
vmap ip_arria10_remote_update_altera_remote_update_150 ./work/
diff --git a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
index 32cacf3e6b..19f16cd59f 100644
--- a/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/flash/remote_update/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
index 851350a43c..80a62c6672 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
index f413ae490e..1fad6fdf3e 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
index 48d30f0d89..8d2f641fcc 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
index 1f2b253889..fc70aa70a0 100644
--- a/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/fractional_pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/mac_10g/README.txt b/libraries/technology/ip_arria10/mac_10g/README.txt
index c775402d02..0f920fa60e 100644
--- a/libraries/technology/ip_arria10/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/mac_10g
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
index a8883cc132..1865ab2bb0 100644
--- a/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
-set IP_TBDIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_TBDIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
index 6a1b1dd972..7c805fde97 100644
--- a/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/mac_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
index 464263f96b..abd378c329 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
index 794ca94e33..05fdc5ebb7 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
index dc9cdc38dd..52a125e4fe 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
index f40fb25902..4df7738bdc 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
index 574c29ca06..13f8d55b36 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
index 182a93de25..5ef95c261f 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
index 7aa111c072..ff54a5ae25 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
index 740989b115..4df2e0bdec 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
index 6438682b22..8a8e3288b3 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
index 2cf8040b19..53e06e4de1 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
index d280316c1b..81b7166429 100644
--- a/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/phy_10gbase_r_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
index e66921e0b3..ca650eea03 100644
--- a/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
index b6b6d86efd..19d0725eca 100644
--- a/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
index 9a1b5855e1..88558ac778 100644
--- a/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
index c3b7fa01be..24e8de5690 100644
--- a/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
index 58312af4c2..65f55bd48d 100644
--- a/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
index 3a1a86267a..87db4a4444 100644
--- a/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/pll_clk25/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
index d31c8671a7..20e438b4c1 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
index 7fb31eb197..0727a29341 100644
--- a/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/pll_xgmii_mac_clocks/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/ram/README.txt b/libraries/technology/ip_arria10/ram/README.txt
index 24ad4ab94e..bb10b06047 100755
--- a/libraries/technology/ip_arria10/ram/README.txt
+++ b/libraries/technology/ip_arria10/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ram
Contents:
diff --git a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
index 6404a59d66..e24b47eab8 100644
--- a/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
index 7712a5afed..42636b22f5 100644
--- a/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
#modelsim_compile_ip_files =
-# $RADIOHDL_WORK/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
+# $HDL_WORK/libraries/technology/ip_arria10/temp_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
index 950a6849ab..0ca0862832 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
index ab125a22db..d0e4500787 100644
--- a/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/transceiver_pll_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
index 0b48cda572..ede7525a7c 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
index 45b9e866ea..e4ca47ead5 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_1/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
index 0b9fd32f81..7e487453a1 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
index 8cb43574cb..fed5346f93 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
index a98ab3b950..4b2d7cd58b 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
index 02bdc47594..2cee6ec36d 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
index 8f4d76ddf3..2adc9e61a6 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
index e2f5fe2620..789b6203db 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
index a4a6db128f..89dc59e26a 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
index 9e5de0cc3e..22b2c4dba3 100644
--- a/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/transceiver_reset_controller_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
index fa105db173..8b20223537 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
-For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
index 3f4f14a00e..97a8f992de 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
index f4b67edbe2..640aca2305 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
index ae9545e000..0f0e3a3266 100755
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
Contents:
1) Porting
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
index a22e115699..a9062836f7 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
index a9294f7aa9..2a6caff441 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
index fd90e1ac9c..03e7c495f2 100644
--- a/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb2/qsys-generate/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb2/qsys-generate/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
index bd24313b84..dadb8b1d8d 100644
--- a/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
# There is no simulation model for the FPGA voltage sensor IP
#modelsim_compile_ip_files =
-# $RADIOHDL_WORK/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
+# $HDL_WORK/libraries/technology/ip_arria10/voltage_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
index ffa123ac21..d2c1cac94d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
vmap alt_em10g32_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
index 62619e221d..908a9e55be 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_em10g32_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
index 564cbf1d9c..48b8eadb18 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap alt_mem_if_jtag_master_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/hdllib.cfg
index 21f6ab7cfc..af862f267b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/alt_mem_if_jtag_master_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
index b8ff2a3d81..0fdc6a880e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
vmap altclkctrl_180 ./work/
vcom "$IP_DIR/../altclkctrl_180/sim/ip_arria10_e1sg_clkbuf_global_altclkctrl_180_uuznxiq.vhd" -work altclkctrl_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/hdllib.cfg
index d16da4aa98..867cff8d22 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altclkctrl_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
index e1847b95f2..d6b2ba13b8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
vmap altera_asmi_parallel_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/hdllib.cfg
index 6a653a1689..50a05632b5 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_asmi_parallel_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
index eafa959867..af0c7159fd 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_avalon_mm_bridge_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/hdllib.cfg
index 97f5b33a72..7b00cb0add 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$HDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/generated_tb/generated/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_mm_bridge_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
index 25d72fb06a..edf94714dd 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/hdllib.cfg
index 3f74f6bb14..2e8201b860 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_onchip_memory2_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
index f9b6566b87..db85d837ed 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_packets_to_master_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/hdllib.cfg
index 3289315446..e4cee3f822 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_packets_to_master_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
index 3f67e1b1ce..ee66c060b0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_sc_fifo_180 ./work/
vlog "$IP_DIR/../altera_avalon_sc_fifo_180/sim/altera_avalon_sc_fifo.v" -work altera_avalon_sc_fifo_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/hdllib.cfg
index 7bf034a3bc..ed16e284a7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_sc_fifo_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
index a2defb493f..1a6e4e1ee4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_bytes_to_packets_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/hdllib.cfg
index 55d4345da9..03860ad79b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_bytes_to_packets_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
index fa3ff32e9a..5399369f80 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_packets_to_bytes_180 ./work/
vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_180/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/hdllib.cfg
index 3b7ae8e33f..a854bb9e76 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_avalon_st_packets_to_bytes_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
index 9240118178..e9fe426fe4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
@@ -29,34 +29,34 @@
#vlib ./work/ ;# Assume library work already exist
#
vmap altera_avalon_mm_bridge_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_180/sim/altera_avalon_mm_bridge.v" -work altera_avalon_mm_bridge_180
vmap altera_emif_arch_nf_180 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_180
vcom "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.vhd" -work altera_emif_arch_nf_180
# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_180
vcom "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.vhd" -work altera_emif_arch_nf_180
# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama_io_aux.sv" -work altera_emif_arch_nf_180
vcom "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama.vhd" -work altera_emif_arch_nf_180
# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_180
@@ -102,62 +102,62 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/io_12_lane__nf5es_abphy.sv" -work altera_emif_arch_nf_180
vmap altera_reset_controller_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_180
vlog "$IP_DIR/../altera_reset_controller_180/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_180
vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vmap altera_avalon_onchip_memory2_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd" -work altera_avalon_onchip_memory2_180
vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.vhd" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.vhd" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.vhd" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.vhd" -work altera_emif_cal_slave_nf_180
vmap altera_emif_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_180_dzobyri.vhd" -work altera_emif_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_180_lwknerq.vhd" -work altera_emif_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_180_gt57qoa.vhd" -work altera_emif_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_emif_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_180_nz3mdxa.vhd" -work altera_emif_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/hdllib.cfg
index 1be2e657dc..924e8424e8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
index fa00f3d2fb..f242ec4ebb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
@@ -30,28 +30,28 @@
vmap altera_emif_arch_nf_180 ./work/
# ddr4_4g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y_io_aux.sv" -work altera_emif_arch_nf_180
vcom "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_arch_nf_180_ud6bb7y.vhd" -work altera_emif_arch_nf_180
# ddr4_4g_2000
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy_io_aux.sv" -work altera_emif_arch_nf_180
vcom "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_arch_nf_180_n4j75iy.vhd" -work altera_emif_arch_nf_180
# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama_io_aux.sv" -work altera_emif_arch_nf_180
vcom "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_arch_nf_180_7cl5ama.vhd" -work altera_emif_arch_nf_180
# ddr4_8g_2400
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top.sv" -work altera_emif_arch_nf_180
vlog -sv "$IP_DIR/../altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_io_aux.sv" -work altera_emif_arch_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
index 6a6fb2b579..0dc6055232 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_arch_nf_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
index 9e8e93ee02..71d21df766 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_emif_cal_slave_nf_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_emif_cal_slave_nf_180_efslyyq.vhd" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_emif_cal_slave_nf_180_efslyyq.vhd" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_emif_cal_slave_nf_180_efslyyq.vhd" -work altera_emif_cal_slave_nf_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_cal_slave_nf_180_efslyyq.vhd" -work altera_emif_cal_slave_nf_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/hdllib.cfg
index 56092a8285..abbd88a2b6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_emif_cal_slave_nf_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
index cff47b359f..a5c3c36590 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
@@ -31,10 +31,10 @@
vmap altera_eth_tse_180 ./work/
# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_eth_tse_180_dm7dxyq.vhd" -work altera_eth_tse_180
# tse_sgmii_lvds
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/../altera_eth_tse_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_eth_tse_180_zsww75y.vhd" -work altera_eth_tse_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/hdllib.cfg
index 06e083362f..dbd706bacf 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/hdllib.cfg
@@ -21,7 +21,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
index 9f48b1b749..ebfe3676cb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
@@ -28,6 +28,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_avalon_arbiter_180 ./work/
vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_180/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/hdllib.cfg
index dfd8b2b09d..c7ddc2cc43 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_avalon_arbiter_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
index 7253272d70..358035beda 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_mac_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/hdllib.cfg
index 3ca851ab1d..b5ac49ae69 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_mac_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
index 325af551d7..7bb7d7873e 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_nf_lvds_terminator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/hdllib.cfg
index 6cc184f5c6..0faae4f5e7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
index 15cf56df5c..01f18f5797 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_nf_phyip_terminator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/hdllib.cfg
index 20e2f82c82..5ca5479871 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
index 490a07462d..5f0cbdfbe7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_pcs_pma_nf_lvds_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/hdllib.cfg
index e32f89526d..efaa584853 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
index 55ca36b48b..c5d8719bef 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_pcs_pma_nf_phyip_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/hdllib.cfg
index 37eeea4205..9eeb5dab01 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
index 9b2f11d2d4..63926ceb2f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
@@ -31,13 +31,13 @@
vmap altera_iopll_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk25_altera_iopll_180_fp6fpla.vo" -work altera_iopll_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk125_altera_iopll_180_abkdtja.vo" -work altera_iopll_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_pll_clk200_altera_iopll_180_qkytlfy.vo" -work altera_iopll_180
# # Refreshing /home/hiemstra/git/hdl/build/unb2b/modelsim/ip_arria10_e1sg_jesd204b/work.ip_arria10_e1sg_jesd204b_rx_core_pll_200mhz(rtl)
@@ -48,6 +48,6 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
# ** Error (suppressible): (vsim-3584) /home/hiemstra/git/hdl/build/unb2b/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama.vo(155): Module parameter 'prot_mode' not found for override.
# Time: 0 fs Iteration: 0 Instance: /tb_tech_jesd204b/u_jesd204b/gen_ip_arria10_e1sg/u0/u_ip_arria10_e1sg_jesd204b/gen_jesd204b_rx/gen_jesd204b_rx_corepll_freqsel/u_ip_arria10_e1sg_jesd204b_rx_corepll_200MHz/iopll_0 File: /home/hiemstra/git/hdl/build/unb2b/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama.vo
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim"
vlog "$IP_DIR/../altera_iopll_180/sim/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz_altera_iopll_180_4sgpama.vo" -work altera_iopll_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/hdllib.cfg
index cd252f68f6..6516cce8a6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_iopll_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
index 369e946de1..376779b230 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_ip_col_if_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/hdllib.cfg
index b1a0d1270b..024a208baf 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_ip_col_if_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
index 845d83faa1..91cbbc1e60 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
@@ -30,12 +30,12 @@
vmap altera_jesd204_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
vcom "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_rx_200MHz_altera_jesd204_180_3rumeui.vhd" -work altera_jesd204_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
vcom "$IP_DIR/../altera_jesd204_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_jesd204_180_too2kia.vhd" -work altera_jesd204_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg
index fe8c51f3dd..358aee47eb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
index 116a846afa..b4a09da3dd 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
@@ -30,10 +30,10 @@
vmap altera_jesd204_phy_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
vcom "$IP_DIR/../altera_jesd204_phy_180/sim/ip_arria10_e1sg_jesd204b_rx_200MHz_altera_jesd204_phy_180_wv3zwea.vhd" -work altera_jesd204_phy_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
vcom "$IP_DIR/../altera_jesd204_phy_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_jesd204_phy_180_s336zrq.vhd" -work altera_jesd204_phy_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg
index fccfb8daff..f8876e64a4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
index bb1159b2e0..597e45ada3 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
@@ -30,7 +30,7 @@
vmap altera_jesd204_phy_adapter_xs_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
vlog "$IP_DIR/../altera_jesd204_phy_adapter_xs_180/sim/mentor/altera_jesd204_phy_adapter_xs.v" -work altera_jesd204_phy_adapter_xs_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg
index 703a6aa2e0..0f1de0165d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_phy_adapter_xs_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
index 93fceea38f..6b267b590f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
@@ -30,7 +30,7 @@
vmap altera_jesd204_rx_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_base.v" -work altera_jesd204_rx_180
vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_csr.v" -work altera_jesd204_rx_180
vlog "$IP_DIR/../altera_jesd204_rx_180/sim/mentor/altera_jesd204_rx_ctl.v" -work altera_jesd204_rx_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg
index c780bea065..abaf70661d 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
index 354a1a282c..4d4ba7db94 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
@@ -30,7 +30,7 @@
vmap altera_jesd204_rx_mlpcs_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_8b10b_dec.v" -work altera_jesd204_rx_mlpcs_180
vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_180/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_rx_mlpcs_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg
index 14bea68453..cfc479206a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_rx_mlpcs_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
index 6886f04bce..20cfae71a6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
@@ -31,7 +31,7 @@
vmap altera_jesd204_tx_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
vlog "$IP_DIR/../altera_jesd204_tx_180/sim/mentor/altera_jesd204_tx_base.v" -work altera_jesd204_tx_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg
index 427108eab8..23c41baba7 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
index 95fa227480..68f07f1a54 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
@@ -31,7 +31,7 @@
vmap altera_jesd204_tx_mlpcs_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_8b10b_enc.v" -work altera_jesd204_tx_mlpcs_180
vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_tx_mlpcs_180
vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_180/sim/mentor/altera_jesd204_pcfifo.v" -work altera_jesd204_tx_mlpcs_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg
index cf8d72f457..87b69774b9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jesd204_tx_mlpcs_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
index 74c891aeba..7855db26f8 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap altera_jtag_dc_streaming_180 ./work/
vlog "$IP_DIR/../altera_jtag_dc_streaming_180/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/hdllib.cfg
index 9ab2d1bf11..bad1021d85 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_jtag_dc_streaming_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
index 27e323677c..0638a7a952 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_lvds_180 ./work/
vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_og2byry.vhd" -work altera_lvds_180
vcom "$IP_DIR/../altera_lvds_180/sim/ip_arria10_e1sg_tse_sgmii_lvds_altera_lvds_180_zfbfxeq.vhd" -work altera_lvds_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/hdllib.cfg
index c9f081b5e9..7918f7e5b6 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
index c349496c42..763b278860 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vmap altera_lvds_core20_180 ./work/
vlog -sv "$IP_DIR/../altera_lvds_core20_180/sim/altera_lvds_core20.sv" -work altera_lvds_core20_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/hdllib.cfg
index 7c32b3d809..45552c10d2 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_lvds_core20_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
index d94285a791..80bd106da1 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_merlin_master_translator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/hdllib.cfg
index 2b22aa3b9b..0458c0d485 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_master_translator_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
index 5556de9e14..abeccdc264 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_merlin_slave_translator_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/hdllib.cfg
index 91f77c91d4..ef0408552a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_merlin_slave_translator_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
index 2b1c521473..260516ca23 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
@@ -30,16 +30,16 @@
#
vmap altera_mm_interconnect_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_4g_2000_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_ibrpcbq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_1600_altera_mm_interconnect_180_mtvmp4i.vhd" -work altera_mm_interconnect_180
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/../altera_mm_interconnect_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_mm_interconnect_180_7km4trq.vhd" -work altera_mm_interconnect_180
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/hdllib.cfg
index 73f5fa237c..90c3557716 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_mm_interconnect_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
index d884da7788..4923e9411f 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vmap altera_remote_update_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/hdllib.cfg
index 699861d088..d3736e725b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
index 3f761c4a64..27a2935517 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vmap altera_remote_update_core_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/hdllib.cfg
index 92dcbaea09..9aeb845fa9 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/hdllib.cfg
@@ -9,4 +9,4 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_remote_update_core_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
index 072c34aed3..56f7ad4cbb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vmap altera_reset_controller_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/hdllib.cfg
index 048e59748f..58c720a923 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_controller_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
index 1353d920fc..febef6eaa2 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
vmap altera_reset_sequencer_180 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim"
vlog "$IP_DIR/../altera_reset_sequencer_180/sim/mentor/altera_reset_controller.v" -work altera_reset_sequencer_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg
index 9efd339974..d60aa5a141 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_reset_sequencer_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
index 0a291e94b1..abf16a6330 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
vmap altera_common_sv_packages ./work/
vmap altera_xcvr_atx_pll_a10_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/hdllib.cfg
index 595a260842..6486c0dda2 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_atx_pll_a10_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
index 16078458ea..278e32120b 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
vmap altera_xcvr_fpll_a10_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/hdllib.cfg
index 06f182471a..05f9d5098a 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_fpll_a10_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
index 90bc5aa8c7..da4753a079 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap altera_xcvr_native_a10_180 ./work/
vmap altera_common_sv_packages ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
# common dependencies
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
@@ -68,41 +68,41 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_y6b7ffi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_24
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_24_altera_xcvr_native_a10_180_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_mhfwvwa.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_12
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_12_altera_xcvr_native_a10_180_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_fs3onwi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_4
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_4_altera_xcvr_native_a10_180_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_d2amdia.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r_3
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_3_altera_xcvr_native_a10_180_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_skxmbpy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# phy_10gbase_r
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_phy_10gbase_r_altera_xcvr_native_a10_180_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_nbxifma.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_tse_sgmii_gx_altera_xcvr_native_a10_180_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_k23srea.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# jesd204b rx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_180_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_vcpx3ja.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
# jesd204b tx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/ip_arria10_e1sg_jesd204b_tx_altera_xcvr_native_a10_180_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_180/sim/alt_xcvr_native_rcfg_opt_logic_q3qhp5a.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_180
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/hdllib.cfg
index eb5db3082a..8e2b4740c0 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_native_a10_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
index c99889b482..687d9bf2eb 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
vmap altera_xcvr_reset_control_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/hdllib.cfg
index fe27ceef66..f5e4652581 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altera_xcvr_reset_control_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
index ec2dcbbcdf..f9bc542473 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
@@ -29,11 +29,11 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
vmap altmult_complex_180 ./work/
vcom "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
vcom "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_27b_altmult_complex_180_ylvsosy.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/hdllib.cfg
index 215374a056..f90fb7bea4 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
index d1c2e5c5d8..79d78a02f2 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap channel_adapter_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/hdllib.cfg
index 553bb719ff..73a67fbf08 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/channel_adapter_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
index de74d47a27..dd0ebe9a69 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vmap timing_adapter_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/hdllib.cfg
index 342089f106..c9c52e6799 100644
--- a/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/altera_libraries/timing_adapter_180/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
index 73fa9937b3..3d395b250c 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_clkbuf_global/sim"
vcom "$IP_DIR/ip_arria10_e1sg_clkbuf_global.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
index 322c95752d..a196b03871 100644
--- a/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/clkbuf_global/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/clkbuf_global/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
index c9a33bbdfc..2e863c2d4b 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/complex_mult
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
index 45d5f65a6e..0ded9b559a 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
@@ -29,8 +29,8 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
vcom "$IP_DIR/ip_arria10_e1sg_complex_mult.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
vcom "$IP_DIR/ip_arria10_e1sg_complex_mult_27b.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
index 6debfcd8fe..338467998b 100644
--- a/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/complex_mult/hdllib.cfg
@@ -11,13 +11,13 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult_27b/ip_arria10_e1sg_complex_mult_27b.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_complex_mult_27b/ip_arria10_e1sg_complex_mult_27b.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/README.txt b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
index 1823e822ff..7ea3cfffa4 100755
--- a/libraries/technology/ip_arria10_e1sg/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddio
Contents:
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
index 5e3fcefa5e..0e0549cce0 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# OUTDATED AND NOT USED!!
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_in_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_180 ./work/
@@ -46,7 +46,7 @@ if {$IPMODEL=="PHY"} {
vcom "$IP_DIR/ip_arria10_ddio_in_1.vhd"
- set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddio_out_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_out_1_altera_gpio_core_180 ./work/
@@ -60,7 +60,7 @@ if {$IPMODEL=="PHY"} {
} else {
# This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
- set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/sim/"
+ set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10_e1sg/ddio/sim/"
vcom "$SIM_DIR/ip_arria10_e1sg_ddio_in_1.vhd"
vcom "$SIM_DIR/ip_arria10_e1sg_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
index 6fdd643351..7ded757226 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddio/hdllib.cfg
@@ -13,13 +13,13 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddio/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_in_1/ip_arria10_e1sg_ddio_in_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddio_out_1/ip_arria10_e1sg_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
index fa2a0fbf16..8b009fb307 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_16g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/copy_hex_files.tcl
index b6d7c0dbb9..2df1714974 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/hdllib.cfg
index 4c7c7b3043..9d2597334a 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
+ #$HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_16g_1600/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/ip_arria10_e1sg_ddr4_16g_1600.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_16g_1600/ip_arria10_e1sg_ddr4_16g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
index 7b57f32c77..45e98a1c47 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
index 47c09e91fb..12bfe4edd8 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
index c6034f2bd5..25e96f38fd 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_1600/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_1600/ip_arria10_e1sg_ddr4_4g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
index 2b8a534222..1650d44f51 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_4g_2000.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
index c41260fe48..b24051e068 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
index a22ea2e96a..1721b0eb35 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_4g_2000/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_4g_2000/ip_arria10_e1sg_ddr4_4g_2000.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
index fbbcfe7aac..2cfbbd059d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
index 8a8cad31d5..070ac6b40e 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
index bff7f43f64..e4d7e55c3d 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_1600/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_1600/ip_arria10_e1sg_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
index 6655a839f8..2638a04129 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
vcom "$IP_DIR/ip_arria10_e1sg_ddr4_8g_2400.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
index 48548cc80d..6a9ec1a2de 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
index b203d90d95..0d73d17460 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/README.txt b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
index 6db25b6412..bcf8b55de2 100755
--- a/libraries/technology/ip_arria10_e1sg/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/fifo
Contents:
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
index a4c21a5083..a708e80342 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_asmi_parallel/sim"
vcom "$IP_DIR/ip_arria10_e1sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
index 802d7bc9b6..9b31c2fc13 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/flash/asmi_parallel/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
index d721b04349..1f003afd9b 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_remote_update/sim"
vcom "$IP_DIR/ip_arria10_e1sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
index 64c28833bd..9ded3d1151 100644
--- a/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/flash/remote_update/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/flash/remote_update/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
index 1c55491d25..f93c3aa939 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
index 9ad42d4252..1360add5dd 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk125/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
index d62136904b..7d45343469 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e1sg_fractional_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
index 28bf7f6a78..7b9aa4a0ec 100644
--- a/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/fractional_pll_clk200/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
index fb6b4c779d..44dc6479f4 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
@@ -29,17 +29,17 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/sim"
vcom "$IP_DIR/ip_arria10_e1sg_jesd204b_rx_200MHz.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/sim"
vcom "$IP_DIR/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/sim"
vcom "$IP_DIR/ip_arria10_e1sg_jesd204b_rx_reset_seq.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/sim"
vcom "$IP_DIR/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_jesd204b_tx/sim"
vcom "$IP_DIR/ip_arria10_e1sg_jesd204b_tx.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
index e218af49fa..33d3183e33 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/hdllib.cfg
@@ -12,17 +12,17 @@ synth_files =
test_bench_files =
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/jesd204b/compile_ip.tcl
[modelsim_project_file]
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/ip_arria10_e1sg_jesd204b_rx_200MHz.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_tx/ip_arria10_e1sg_jesd204b_tx.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_200MHz/ip_arria10_e1sg_jesd204b_rx_200MHz.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e1sg_jesd204b_rx_core_pll_200MHz.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_reset_seq/ip_arria10_e1sg_jesd204b_rx_reset_seq.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_jesd204b_tx/ip_arria10_e1sg_jesd204b_tx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
index c775402d02..0f920fa60e 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/mac_10g
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
index 86cfa6cac3..1c211f6ce7 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mac_10g/sim"
vcom "$IP_DIR/ip_arria10_e1sg_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
index 508bbebf1f..f936983979 100644
--- a/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/mac_10g/hdllib.cfg
@@ -9,17 +9,17 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e1sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/mac_10g/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_mac_10g/ip_arria10_e1sg_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
index 82202caa75..8d098b26ce 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_mult_add4/sim"
vmap ip_arria10_e1sg_mult_add4 ./work/
vmap altera_mult_add_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
index 0aca429ea0..ea8fcb393b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
index 9af7dc8bc8..4bee4b5e5b 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r/ip_arria10_e1sg_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
index 4aa3d0288e..2736172286 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
index 0d284db59b..627972c121 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_12/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_12/ip_arria10_e1sg_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
index fa35c21f35..94616624b5 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
index f46a87107a..95ba59732e 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_24/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_24/ip_arria10_e1sg_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
index 81251469c6..3a060c4715 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
index bae65c0160..da507aaada 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_3/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_3/ip_arria10_e1sg_phy_10gbase_r_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
index e52b714299..31257d769e 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
index 05e6b863a6..0e8778478e 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_4/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_4/ip_arria10_e1sg_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
index 555bdfed73..1343afc3b5 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/sim"
vcom "$IP_DIR/ip_arria10_e1sg_phy_10gbase_r_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
index ea4dd7440b..6bd52a5a25 100644
--- a/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/phy_10gbase_r_48/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_phy_10gbase_r_48/ip_arria10_e1sg_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
index f6712cdd63..d18342e3f5 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
index 5bb0972c0c..550e96a1f9 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk125/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk125/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk125/ip_arria10_e1sg_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
index f7f3cec7ac..edfbbf4c07 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
index d745852618..282fcaa525 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk200/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk200/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk200/ip_arria10_e1sg_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
index 710e0dcc00..40eb599bd5 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_clk25/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
index c06945b319..cc5c323677 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_clk25/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/pll_clk25/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_clk25/ip_arria10_e1sg_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 2723100398..054104dc07 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/sim"
vcom "$IP_DIR/ip_arria10_e1sg_pll_xgmii_mac_clocks.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
index fb2761f881..97be02852a 100644
--- a/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/pll_xgmii_mac_clocks/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_pll_xgmii_mac_clocks/ip_arria10_e1sg_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/ram/README.txt b/libraries/technology/ip_arria10_e1sg/ram/README.txt
index 24ad4ab94e..bb10b06047 100755
--- a/libraries/technology/ip_arria10_e1sg/ram/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ram
Contents:
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
index 77ca49010c..f8fb076632 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_temp_sense/sim"
vmap altera_temp_sense_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
index 71ad52e9e4..00b0c605f5 100644
--- a/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/temp_sense/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
#modelsim_compile_ip_files =
-# $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
+# $HDL_WORK/libraries/technology/ip_arria10_e1sg/temp_sense/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
index fcb30bbd90..e62b1ca32f 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
index 30c1dbc1e5..3a524095ed 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_pll_10g/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_pll_10g/ip_arria10_e1sg_transceiver_pll_10g.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
index 076177e167..11105df2aa 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
index 42274baf39..5c73b7e94a 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_1/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_1/ip_arria10_e1sg_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
index aba40145fd..a708530bf8 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_12.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
index ae5ebcdb13..9e85b27173 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_12/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_12/ip_arria10_e1sg_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
index 70970628ba..87293d4a5f 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_24.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
index 6e0d258dfb..3e4bf12806 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_24/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_24/ip_arria10_e1sg_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
index 64f9f0b300..a1f71285b5 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
index 8a9a5c4f5f..69c5ad040c 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
index f939d89ec6..d8cfa66c84 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_4.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
index 6871a53037..4c64d9980e 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_4/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_4/ip_arria10_e1sg_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
index 6450d4dd24..cf074f0e12 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/sim"
vcom "$IP_DIR/ip_arria10_e1sg_transceiver_reset_controller_48.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
index f24fde1a35..127f8b08ae 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_48/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_transceiver_reset_controller_48/ip_arria10_e1sg_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
index fa105db173..8b20223537 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
-For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
index f195da2923..33ff4e89d5 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
index 6b6ad07b4c..3b3cd4c3a6 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_gx/ip_arria10_e1sg_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
index efe749e3a0..2272417d95 100755
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
-See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
index 3b2fffc3b6..bb52a542f9 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/ip_arria10_e1sg_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
index 0496ed8bd1..27b20a3b05 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/hdllib.cfg
@@ -13,12 +13,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
index 1be59a86e7..0d545f5608 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_voltage_sense/sim"
vmap ip_arria10_e1sg_voltage_sense ./work/
vmap altera_voltage_sensor_180 ./work/
diff --git a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
index a6cb5882e8..55c47eef16 100644
--- a/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e1sg/voltage_sense/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
[modelsim_project_file]
# There is no simulation model for the FPGA voltage sensor IP
#modelsim_compile_ip_files =
-# $RADIOHDL_WORK/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
+# $HDL_WORK/libraries/technology/ip_arria10_e1sg/voltage_sense/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
index bbaaa7d7bd..5fab512f1f 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
vmap alt_em10g32_1930 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg
index 4f6dac9d70..3df0b854b0 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_em10g32_1930/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
index 6a422a978d..5f7bc2d6f2 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
@@ -30,17 +30,17 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap alt_mem_if_jtag_master_191 ./work/
vcom "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_8g_1600_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191
#ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../alt_mem_if_jtag_master_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_alt_mem_if_jtag_master_191_rksoe3i.vhd" -work alt_mem_if_jtag_master_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
index 6bd31de18b..373f4f13c8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/alt_mem_if_jtag_master_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
index e58f06f587..89958dcb49 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
vmap altclkctrl_191 ./work/
vcom "$IP_DIR/../altclkctrl_191/sim/ip_arria10_e2sg_clkbuf_global_altclkctrl_191_njwbsri.vhd" -work altclkctrl_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/hdllib.cfg
index 869930dac5..900b436173 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altclkctrl_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
index 00bd880cea..bebfc84a70 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
vmap altera_asmi_parallel_1910 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
index cb81ea68e1..b55caa82d6 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_asmi_parallel_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
index a98ab0bd16..021361dd58 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
@@ -28,17 +28,17 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_avalon_mm_bridge_191 ./work/
vlog "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v" -work altera_avalon_mm_bridge_191
#ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_mm_bridge_191_x6qdesi.v" -work altera_avalon_mm_bridge_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_mm_bridge_191_x6qdesi.v" -work altera_avalon_mm_bridge_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg
index a61c85e5fd..b146a2e536 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/generated_tb/generated/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+ #$HDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/generated_tb/generated/sim/ip_arria10_e2sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_mm_bridge_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
index 87be9c3c25..6378d89b52 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
@@ -30,15 +30,15 @@
#
vmap altera_avalon_onchip_memory2_1920 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
#ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
# copy previous 'set' and 'vcom' lines to include more ddr4 variants
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg
index ef094f0caf..1f9f1929d3 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_onchip_memory2_1920/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
index e66734a9be..877ab950d0 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_avalon_packets_to_master_1910 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg
index 94aa088939..b5c2eb97a8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_packets_to_master_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
index 53adedc0d3..bb10bc6692 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
@@ -30,17 +30,17 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_avalon_sc_fifo_191 ./work/
vlog "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_sc_fifo_191_e5eqkcq.v" -work altera_avalon_sc_fifo_191
#ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vlog "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_sc_fifo_191_e5eqkcq.v" -work altera_avalon_sc_fifo_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog "$IP_DIR/../altera_avalon_sc_fifo_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_sc_fifo_191_e5eqkcq.v" -work altera_avalon_sc_fifo_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg
index 431d59b521..d3c83534c4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_sc_fifo_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
index 0e6cdc7f45..a3426d9909 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_bytes_to_packets_1910 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg
index 963c12636c..16af62b209 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_bytes_to_packets_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
index 98ea21838a..a0e16162bb 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_avalon_st_packets_to_bytes_1910 ./work/
vlog "$IP_DIR/../altera_avalon_st_packets_to_bytes_1910/sim/altera_avalon_st_packets_to_bytes.v" -work altera_avalon_st_packets_to_bytes_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
index dd502e7d10..7f851296a8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_avalon_st_packets_to_bytes_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
index 3c2347f5cf..4d9fd39c9c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
@@ -32,20 +32,20 @@
vmap altera_emif_arch_nf_191 ./work/
# ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy_top.sv" -work altera_emif_arch_nf_191
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy_io_aux.sv" -work altera_emif_arch_nf_191
vcom "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy.vhd" -work altera_emif_arch_nf_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_top.sv" -work altera_emif_arch_nf_191
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_io_aux.sv" -work altera_emif_arch_nf_191
vcom "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy.vhd" -work altera_emif_arch_nf_191
# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_top.sv" -work altera_emif_arch_nf_191
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_io_aux.sv" -work altera_emif_arch_nf_191
@@ -94,72 +94,72 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
vmap altera_reset_controller_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_controller.v" -work altera_reset_controller_191
vlog "$IP_DIR/../altera_reset_controller_191/sim/mentor/altera_reset_synchronizer.v" -work altera_reset_controller_191
vmap altera_mm_interconnect_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_3yb4cia.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd" -work altera_mm_interconnect_191
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_3yb4cia.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_monheay.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_dexdb4a.vhd" -work altera_mm_interconnect_191
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_3yb4cia.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_monheay.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_dexdb4a.vhd" -work altera_mm_interconnect_191
vmap altera_avalon_onchip_memory2_1920 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../altera_avalon_onchip_memory2_1920/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_onchip_memory2_1920_popesdq.vhd" -work altera_avalon_onchip_memory2_1920
vmap altera_avalon_mm_bridge_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_avalon_mm_bridge_191_x6qdesi.v" -work altera_avalon_mm_bridge_191
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_avalon_mm_bridge_191_x6qdesi.v" -work altera_avalon_mm_bridge_191
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog "$IP_DIR/../altera_avalon_mm_bridge_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_avalon_mm_bridge_191_x6qdesi.v" -work altera_avalon_mm_bridge_191
vmap altera_emif_cal_slave_nf_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
vmap altera_emif_1910 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_1910_jhcj6zy.vhd" -work altera_emif_1910
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_1910_rvperma.vhd" -work altera_emif_1910
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../altera_emif_1910/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_1910_3t6zvqq.vhd" -work altera_emif_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg
index 96efe3d56e..75b7420dd9 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
index 12bd8a8fab..68a13ded35 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
@@ -31,21 +31,21 @@
vmap altera_emif_arch_nf_191 ./work/
# ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy_top.sv" -work altera_emif_arch_nf_191
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy_io_aux.sv" -work altera_emif_arch_nf_191
vcom "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_arch_nf_191_ppinzjy.vhd" -work altera_emif_arch_nf_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_top.sv" -work altera_emif_arch_nf_191
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy_io_aux.sv" -work altera_emif_arch_nf_191
vcom "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_arch_nf_191_slbjghy.vhd" -work altera_emif_arch_nf_191
# ddr4_8g_1600
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_top.sv" -work altera_emif_arch_nf_191
vlog -sv "$IP_DIR/../altera_emif_arch_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_arch_nf_191_qssf3hq_io_aux.sv" -work altera_emif_arch_nf_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg
index 64324b44d8..a3f3cd3698 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_arch_nf_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
index 56bd8a7c21..59c175d3b6 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
@@ -31,15 +31,15 @@
vmap altera_emif_cal_slave_nf_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
#ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../altera_emif_cal_slave_nf_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_emif_cal_slave_nf_191_rmzieji.vhd" -work altera_emif_cal_slave_nf_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
index f8b87b4e79..c352940d5c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_emif_cal_slave_nf_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
index 95930d53ad..c6d4601317 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
@@ -31,9 +31,9 @@
vmap altera_eth_tse_1940 ./work/
# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/../altera_eth_tse_1940/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_eth_tse_1940_gpmdicy.vhd" -work altera_eth_tse_1940
# tse_sgmii_lvds
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/../altera_eth_tse_1940/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_eth_tse_1940_m7xbdka.vhd" -work altera_eth_tse_1940
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg
index 4b557fb62b..14db726367 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/hdllib.cfg
@@ -21,7 +21,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
index 9e546e6e0f..d917e61c35 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
@@ -28,6 +28,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_avalon_arbiter_1940 ./work/
vlog "$IP_DIR/../altera_eth_tse_avalon_arbiter_1940/sim/mentor/altera_eth_tse_avalon_arbiter.v" -work altera_eth_tse_avalon_arbiter_1940
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg
index 049eaf9ba4..585d9f8683 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_avalon_arbiter_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
index 96706c0c3f..aed3e1b91c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_mac_1940 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg
index 29fc00d681..c20fff2490 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_mac_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
index f22ce117ca..61f4579291 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_nf_lvds_terminator_1940 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg
index 01efe26fe3..03c93273a6 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_lvds_terminator_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
index a19f408746..5d0e40dc84 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_nf_phyip_terminator_1940 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg
index 6bc962ea4a..8dd291f50b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_nf_phyip_terminator_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
index 0c0ed04c18..27b587f453 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
vmap altera_eth_tse_pcs_pma_nf_lvds_1940 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg
index 15e2f2fc7c..130c99cb76 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_lvds_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
index e192256e38..fa922381c0 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
@@ -28,7 +28,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
vmap altera_eth_tse_pcs_pma_nf_phyip_1940 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg
index d2816a9060..b70e0a234a 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_eth_tse_pcs_pma_nf_phyip_1940/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
index 147ba350e4..9cfc4211b4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
@@ -30,16 +30,16 @@
vmap altera_iopll_1930 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
vlog "$IP_DIR/../altera_iopll_1930/sim/ip_arria10_e2sg_pll_clk25_altera_iopll_1930_4orwjna.vo" -work altera_iopll_1930
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
vlog "$IP_DIR/../altera_iopll_1930/sim/ip_arria10_e2sg_pll_clk125_altera_iopll_1930_rnfwfny.vo" -work altera_iopll_1930
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
vlog "$IP_DIR/../altera_iopll_1930/sim/ip_arria10_e2sg_pll_clk200_altera_iopll_1930_f63mvhq.vo" -work altera_iopll_1930
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/sim"
vlog "$IP_DIR/../altera_iopll_1930/sim/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz_altera_iopll_1930_ibzmqny.vo" -work altera_iopll_1930
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg
index c27a65e0dc..267debb7ca 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_iopll_1930/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
index 34e538bd85..f628b02f2b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
@@ -30,17 +30,17 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_ip_col_if_191 ./work/
vcom "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_ip_col_if_191_k6i7ubq.vhd" -work altera_ip_col_if_191
# ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_ip_col_if_191_k6i7ubq.vhd" -work altera_ip_col_if_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../altera_ip_col_if_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_ip_col_if_191_k6i7ubq.vhd" -work altera_ip_col_if_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
index 6b3ebc9cb7..998e657abd 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_ip_col_if_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
index 7ca664bc19..8884239d6d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
@@ -30,11 +30,11 @@
vmap altera_jesd204_1920 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
vcom "$IP_DIR/../altera_jesd204_1920/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_jesd204_1920_humwsma.vhd" -work altera_jesd204_1920
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
vcom "$IP_DIR/../altera_jesd204_1920/sim/ip_arria10_e2sg_jesd204b_tx_altera_jesd204_1920_xrjkkdy.vhd" -work altera_jesd204_1920
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg
index 7e2c7b6c99..a5d2dffcdc 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_1920/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
index 9fd2ce4a80..2a83b600c4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
@@ -30,10 +30,10 @@
vmap altera_jesd204_phy_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
vcom "$IP_DIR/../altera_jesd204_phy_191/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_jesd204_phy_191_qtzjdri.vhd" -work altera_jesd204_phy_191
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
vcom "$IP_DIR/../altera_jesd204_phy_191/sim/ip_arria10_e2sg_jesd204b_tx_altera_jesd204_phy_191_iu47x7q.vhd" -work altera_jesd204_phy_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg
index 7a3f243be3..0cef42c20a 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
index 24d021d788..be638256e0 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
@@ -30,7 +30,7 @@
vmap altera_jesd204_phy_adapter_xs_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
vlog "$IP_DIR/../altera_jesd204_phy_adapter_xs_191/sim/mentor/altera_jesd204_phy_adapter_xs.v" -work altera_jesd204_phy_adapter_xs_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg
index 019f8fa154..85d31379e2 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_phy_adapter_xs_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
index fda853dc06..4a9c9506db 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
@@ -30,7 +30,7 @@
vmap altera_jesd204_rx_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
vlog "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_base.v" -work altera_jesd204_rx_191
vlog "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_csr.v" -work altera_jesd204_rx_191
vlog "$IP_DIR/../altera_jesd204_rx_191/sim/mentor/altera_jesd204_rx_ctl.v" -work altera_jesd204_rx_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg
index f1cbfa6e1b..de7eeb1be7 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
index 7c98851c07..0cede8fb11 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
@@ -30,7 +30,7 @@
vmap altera_jesd204_rx_mlpcs_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_8b10b_dec.v" -work altera_jesd204_rx_mlpcs_191
vlog "$IP_DIR/../altera_jesd204_rx_mlpcs_191/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_rx_mlpcs_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg
index 1a66738823..c3911c4f9b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_rx_mlpcs_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
index 2dedec0639..f0d6789053 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
@@ -31,7 +31,7 @@
vmap altera_jesd204_tx_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
vlog "$IP_DIR/../altera_jesd204_tx_191/sim/mentor/altera_jesd204_tx_base.v" -work altera_jesd204_tx_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg
index 175fe361da..c213dc409d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
index 060df7feea..97381478a4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
@@ -31,7 +31,7 @@
vmap altera_jesd204_tx_mlpcs_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_8b10b_enc.v" -work altera_jesd204_tx_mlpcs_191
vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_mixed_width_dcfifo.v" -work altera_jesd204_tx_mlpcs_191
vlog "$IP_DIR/../altera_jesd204_tx_mlpcs_191/sim/mentor/altera_jesd204_pcfifo.v" -work altera_jesd204_tx_mlpcs_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg
index 27f636b09b..b9879ac843 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jesd204_tx_mlpcs_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
index 924628ab6f..8d3e1b4e18 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_jtag_dc_streaming_191 ./work/
vlog "$IP_DIR/../altera_jtag_dc_streaming_191/sim/altera_avalon_st_jtag_interface.v" -work altera_jtag_dc_streaming_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg
index 50e59bccc7..cec06d2e02 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_jtag_dc_streaming_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
index 83823e0425..069822f13e 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
vmap altera_lvds_1930 ./work/
vcom "$IP_DIR/../altera_lvds_1930/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_1930_7egaewa.vhd" -work altera_lvds_1930
vcom "$IP_DIR/../altera_lvds_1930/sim/ip_arria10_e2sg_tse_sgmii_lvds_altera_lvds_1930_w33qkcq.vhd" -work altera_lvds_1930
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg
index 73192d67a8..abee9b51f2 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_1930/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
index b2d60572fe..d3580dc299 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
@@ -27,7 +27,7 @@
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
vmap altera_lvds_core20_191 ./work/
vlog -sv "$IP_DIR/../altera_lvds_core20_191/sim/altera_lvds_core20.sv" -work altera_lvds_core20_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg
index 475ac60eb4..7eedc2e8b1 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_lvds_core20_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
index c98fe5bf24..9d24715fb0 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
@@ -28,16 +28,16 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_merlin_master_translator_191 ./work/
vlog -sv "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_master_translator_191_g7h47bq.sv" -work altera_merlin_master_translator_191
# ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vlog -sv "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_merlin_master_translator_191_g7h47bq.sv" -work altera_merlin_master_translator_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog -sv "$IP_DIR/../altera_merlin_master_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_merlin_master_translator_191_g7h47bq.sv" -work altera_merlin_master_translator_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg
index 96a1f18f72..d73f59d6e4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_master_translator_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
index 56f6eb803f..f0b3253108 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
@@ -29,16 +29,16 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_merlin_slave_translator_191 ./work/
vlog -sv "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_merlin_slave_translator_191_x56fcki.sv" -work altera_merlin_slave_translator_191
# ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vlog -sv "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_merlin_slave_translator_191_x56fcki.sv" -work altera_merlin_slave_translator_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog -sv "$IP_DIR/../altera_merlin_slave_translator_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_merlin_slave_translator_191_x56fcki.sv" -work altera_merlin_slave_translator_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg
index c3f96d2542..fc81ff2faa 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_merlin_slave_translator_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
index 7d2bdac347..492c5ae0c4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
@@ -31,18 +31,18 @@
vmap altera_mm_interconnect_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_3yb4cia.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_monheay.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_8g_1600_altera_mm_interconnect_191_dexdb4a.vhd" -work altera_mm_interconnect_191
#ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_3yb4cia.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_monheay.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_altera_mm_interconnect_191_dexdb4a.vhd" -work altera_mm_interconnect_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_3yb4cia.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_monheay.vhd" -work altera_mm_interconnect_191
vcom "$IP_DIR/../altera_mm_interconnect_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_altera_mm_interconnect_191_dexdb4a.vhd" -work altera_mm_interconnect_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
index 2ddb7be056..6fdd884a0f 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_mm_interconnect_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
index 674161ae5e..9b124aeee4 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
vmap altera_remote_update_1910 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
index a2f283a8ae..83a19e1b24 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/hdllib.cfg
@@ -11,5 +11,5 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
index 00107fb720..41bea969d2 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
vmap altera_remote_update_core_1910 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg
index 8e1035e075..40bf22c31b 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/hdllib.cfg
@@ -9,4 +9,4 @@ synth_files =
test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_remote_update_core_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
index 1f4efd6bea..54d6f0d11d 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap altera_reset_controller_191 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg
index fb7cfdeab2..94aa5e5886 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_controller_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
index 20acf8a3b7..5668f65951 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
@@ -30,7 +30,7 @@
#
vmap altera_reset_sequencer_191 ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/sim"
vlog "$IP_DIR/../altera_reset_sequencer_191/sim/mentor/altera_reset_controller.v" -work altera_reset_sequencer_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg
index 74ffede0c2..c97dcfbd0e 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_reset_sequencer_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
index 34e8546b79..9a48a1d3ec 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
vmap altera_common_sv_packages ./work/
vmap altera_xcvr_atx_pll_a10_191 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
index 8bc95d11ae..403fb40045 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_atx_pll_a10_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
index 93a8770a67..263063868e 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
vmap altera_xcvr_fpll_a10_191 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/hdllib.cfg
index 9d51eea5a3..55e602c9fc 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_fpll_a10_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
index e8a8b744ff..65bcc42ce7 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
@@ -32,7 +32,7 @@ vmap altera_xcvr_native_a10_191 ./work/
vmap altera_common_sv_packages ./work/
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
# common dependencies
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/altera_xcvr_native_a10_functions_h.sv" -work altera_common_sv_packages
@@ -68,41 +68,41 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_x2zy5gq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_24
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_24_altera_xcvr_native_a10_191_xj4rzbi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_xj4rzbi.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_12
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_12_altera_xcvr_native_a10_191_vvjuhsq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_vvjuhsq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_4
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_4_altera_xcvr_native_a10_191_nx522la.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_nx522la.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r_3
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_3_altera_xcvr_native_a10_191_ofoefcy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ofoefcy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# phy_10gbase_r
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_phy_10gbase_r_altera_xcvr_native_a10_191_ng5d5fy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_ng5d5fy.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# tse_sgmii_gx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_tse_sgmii_gx_altera_xcvr_native_a10_191_fbxkdmq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_fbxkdmq.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# jesd204b rx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_rx_200MHz_altera_xcvr_native_a10_191_pebno5q.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_pebno5q.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
# jesd204b tx
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/ip_arria10_e2sg_jesd204b_tx_altera_xcvr_native_a10_191_wjipjey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
vlog -sv "$IP_DIR/../altera_xcvr_native_a10_191/sim/alt_xcvr_native_rcfg_opt_logic_wjipjey.sv" -L altera_common_sv_packages -work altera_xcvr_native_a10_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg
index 534c0be3c2..cd422900db 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_native_a10_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
index 042ffaf536..e3253b9e54 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
vmap altera_xcvr_reset_control_191 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg
index 491e0f6336..2a93709c42 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/hdllib.cfg
@@ -11,6 +11,6 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altera_xcvr_reset_control_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
index 39828d81ea..142d72c907 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
@@ -29,12 +29,12 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
vmap altmult_complex_1910 ./work/
vcom "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_altmult_complex_1910_cumkcni.vhd" -work altmult_complex_1910
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
vcom "$IP_DIR/../altmult_complex_1910/sim/ip_arria10_e2sg_complex_mult_27b_altmult_complex_1910_ecifj3y.vhd" -work altmult_complex_1910
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg
index 3880a880c2..ae671bcf73 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/altmult_complex_1910/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
index f353879770..0f50ea7b02 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
@@ -30,7 +30,7 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap channel_adapter_191 ./work/
@@ -38,12 +38,12 @@ vmap channel_adapter_191 ./work/
vlog -sv "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_channel_adapter_191_uc27kqq.sv" -work channel_adapter_191
#ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vlog -sv "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_channel_adapter_191_cco4x3a.sv" -work channel_adapter_191
vlog -sv "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_channel_adapter_191_uc27kqq.sv" -work channel_adapter_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog -sv "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_channel_adapter_191_cco4x3a.sv" -work channel_adapter_191
vlog -sv "$IP_DIR/../channel_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_channel_adapter_191_uc27kqq.sv" -work channel_adapter_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg
index 88a5792a4c..5e364403a3 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/channel_adapter_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
index c339128849..607a591d1c 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
@@ -30,18 +30,18 @@
#
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vmap timing_adapter_191 ./work/
vlog -sv "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_8g_1600_timing_adapter_191_rrgemwi.sv" -work timing_adapter_191
#ddr4_16g_1600_64b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vlog -sv "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_64b_timing_adapter_191_rrgemwi.sv" -work timing_adapter_191
# ddr4_16g_1600_72b
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vlog -sv "$IP_DIR/../timing_adapter_191/sim/ip_arria10_e2sg_ddr4_16g_1600_72b_timing_adapter_191_rrgemwi.sv" -work timing_adapter_191
diff --git a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg
index c9632755d6..6596692db8 100644
--- a/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/hdllib.cfg
@@ -10,7 +10,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/altera_libraries/timing_adapter_191/compile_ip.tcl
diff --git a/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
index 1f8b03270d..0348ce4299 100644
--- a/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_clkbuf_global/sim"
vcom "$IP_DIR/ip_arria10_e2sg_clkbuf_global.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
index b2efd5ef0f..db471cadfb 100644
--- a/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/clkbuf_global/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/clkbuf_global/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_clkbuf_global/ip_arria10_e2sg_clkbuf_global.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_clkbuf_global/ip_arria10_e2sg_clkbuf_global.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt b/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt
index c9a33bbdfc..2e863c2d4b 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/complex_mult
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
index cc565f44e8..885e2180ad 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
@@ -29,9 +29,9 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult/sim"
vcom "$IP_DIR/ip_arria10_e2sg_complex_mult.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_complex_mult_27b/sim"
vcom "$IP_DIR/ip_arria10_e2sg_complex_mult_27b.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
index c2162613d9..bcfa7d31ab 100644
--- a/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/complex_mult/hdllib.cfg
@@ -11,13 +11,13 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/complex_mult/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult/ip_arria10_e2sg_complex_mult.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult_27b/ip_arria10_e2sg_complex_mult_27b.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult/ip_arria10_e2sg_complex_mult.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_complex_mult_27b/ip_arria10_e2sg_complex_mult_27b.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/README.txt b/libraries/technology/ip_arria10_e2sg/ddio/README.txt
index 1823e822ff..7ea3cfffa4 100755
--- a/libraries/technology/ip_arria10_e2sg/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddio
Contents:
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
index 47f7f739d8..dcdf127768 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
@@ -34,7 +34,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# OUTDATED AND NOT USED!!
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_in_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_in_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_in_1_altera_gpio_core_191 ./work/
@@ -46,7 +46,7 @@ if {$IPMODEL=="PHY"} {
vcom "$IP_DIR/ip_arria10_ddio_in_1.vhd"
- set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_out_1/sim"
+ set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddio_out_1/sim"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_ddio_out_1_altera_gpio_core_191 ./work/
@@ -60,7 +60,7 @@ if {$IPMODEL=="PHY"} {
} else {
# This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
- set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e2sg/ddio/sim/"
+ set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10_e2sg/ddio/sim/"
vcom "$SIM_DIR/ip_arria10_e2sg_ddio_in_1.vhd"
vcom "$SIM_DIR/ip_arria10_e2sg_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg
index de54715d17..6b69fa3fea 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddio/hdllib.cfg
@@ -13,13 +13,13 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddio/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_in_1/ip_arria10_e2sg_ddio_in_1.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_out_1/ip_arria10_e2sg_ddio_out_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_in_1/ip_arria10_e2sg_ddio_in_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddio_out_1/ip_arria10_e2sg_ddio_out_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
index e37e82f808..dd80bc54a4 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
vcom "$IP_DIR/ip_arria10_e2sg_ddr4_16g_1600_64b.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/copy_hex_files.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/copy_hex_files.tcl
index 7e60bb27c5..cce047a356 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/hdllib.cfg
index d7cb9b0f2e..72d7324ae7 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_64b/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/ip_arria10_e2sg_ddr4_16g_1600_64b.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_64b/ip_arria10_e2sg_ddr4_16g_1600_64b.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
index d021871f8c..c449e8db04 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
vcom "$IP_DIR/ip_arria10_e2sg_ddr4_16g_1600_72b.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/copy_hex_files.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/copy_hex_files.tcl
index 7b32ef5337..38ca19826b 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/hdllib.cfg
index 7b322559d7..588759f4af 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_16g_1600/ddr4_16g_1600_72b/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/ip_arria10_e2sg_ddr4_16g_1600_72b.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_16g_1600_72b/ip_arria10_e2sg_ddr4_16g_1600_72b.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
index d88b025be7..2b7d97f8b4 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
vcom "$IP_DIR/ip_arria10_e2sg_ddr4_8g_1600.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl
index 3cc009c6f5..26a2e26754 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
index eb13535a2f..54138be3e0 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/README.txt b/libraries/technology/ip_arria10_e2sg/fifo/README.txt
index 6db25b6412..bcf8b55de2 100755
--- a/libraries/technology/ip_arria10_e2sg/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/fifo
Contents:
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
index 923d3754c6..d14407ec43 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
@@ -29,7 +29,7 @@
vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_asmi_parallel/sim"
vcom "$IP_DIR/ip_arria10_e2sg_asmi_parallel.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
index bb9e88dd54..474a468c1e 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/hdllib.cfg
@@ -13,12 +13,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/flash/asmi_parallel/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_asmi_parallel/ip_arria10_e2sg_asmi_parallel.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_asmi_parallel/ip_arria10_e2sg_asmi_parallel.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
index a0166b1708..b09588eeed 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_remote_update/sim"
vcom "$IP_DIR/ip_arria10_e2sg_remote_update.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
index 7f228c3292..d699858547 100644
--- a/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/flash/remote_update/hdllib.cfg
@@ -13,12 +13,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/flash/remote_update/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_remote_update/ip_arria10_e2sg_remote_update.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_remote_update/ip_arria10_e2sg_remote_update.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
index 4fe3b4783e..4ac3d050ca 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e2sg_fractional_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
index 0ee356783a..9ee4652660 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk125/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/ip_arria10_e2sg_fractional_pll_clk125.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk125/ip_arria10_e2sg_fractional_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
index 4f8725a2e4..cf9bd07195 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e2sg_fractional_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
index 0b37db4eda..18add70cda 100644
--- a/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/fractional_pll_clk200/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/ip_arria10_e2sg_fractional_pll_clk200.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_fractional_pll_clk200/ip_arria10_e2sg_fractional_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
index b970b966a7..f26e8d39ef 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
@@ -29,18 +29,18 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/sim"
vcom "$IP_DIR/ip_arria10_e2sg_jesd204b_rx_200MHz.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/sim"
vcom "$IP_DIR/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/sim"
vcom "$IP_DIR/ip_arria10_e2sg_jesd204b_rx_reset_seq.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12/sim"
vcom "$IP_DIR/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.vhd"
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_jesd204b_tx/sim"
vcom "$IP_DIR/ip_arria10_e2sg_jesd204b_tx.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
index fd070965ac..0872ac3932 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/hdllib.cfg
@@ -11,17 +11,17 @@ synth_files =
test_bench_files =
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/jesd204b/compile_ip.tcl
[modelsim_project_file]
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/ip_arria10_e2sg_jesd204b_rx_200MHz.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/ip_arria10_e2sg_jesd204b_rx_reset_seq.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.qip
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_tx/ip_arria10_e2sg_jesd204b_tx.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_200MHz/ip_arria10_e2sg_jesd204b_rx_200MHz.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz/ip_arria10_e2sg_jesd204b_rx_core_pll_200MHz.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_reset_seq/ip_arria10_e2sg_jesd204b_rx_reset_seq.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12/ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_jesd204b_tx/ip_arria10_e2sg_jesd204b_tx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt b/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt
index c775402d02..0f920fa60e 100644
--- a/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/mac_10g
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
index f7f37290b0..aa5ec7b591 100644
--- a/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mac_10g/sim"
vcom "$IP_DIR/ip_arria10_e2sg_mac_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
index ed87d3019f..ccb711c226 100644
--- a/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/mac_10g/hdllib.cfg
@@ -9,17 +9,17 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e2sg_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/mac_10g/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_mac_10g/ip_arria10_e2sg_mac_10g.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_mac_10g/ip_arria10_e2sg_mac_10g.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
index ea16fe38cf..8c7deabdda 100644
--- a/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/mult_add4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mult_add4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_mult_add4/sim"
vmap ip_arria10_e2sg_mult_add4 ./work/
vmap altera_mult_add_1910 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
index 77ae9c3528..ea79c19262 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/sim"
vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
index b6e2620a30..59e6354d2e 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/ip_arria10_e2sg_phy_10gbase_r.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r/ip_arria10_e2sg_phy_10gbase_r.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
index e3603311eb..6171b4bbce 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/sim"
vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_12.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
index b211cea285..71711ff204 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_12/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/ip_arria10_e2sg_phy_10gbase_r_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_12/ip_arria10_e2sg_phy_10gbase_r_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
index c1b9278620..944729d211 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/sim"
vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_24.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
index d3d9782e02..7286071619 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_24/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/ip_arria10_e2sg_phy_10gbase_r_24.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_24/ip_arria10_e2sg_phy_10gbase_r_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
index 5e81bb41af..73e98d5057 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/sim"
vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_3.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
index 4f381244ec..c58d0c6956 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_3/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/ip_arria10_e2sg_phy_10gbase_r_3.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_3/ip_arria10_e2sg_phy_10gbase_r_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
index a969be29f8..66f765f185 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/sim"
vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_4.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
index 2f337692b2..0f1f0700d4 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_4/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/ip_arria10_e2sg_phy_10gbase_r_4.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_4/ip_arria10_e2sg_phy_10gbase_r_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
index 0cd5157ee4..955fb6426e 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/sim"
vcom "$IP_DIR/ip_arria10_e2sg_phy_10gbase_r_48.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
index 0f7ce6dd7d..861239db7d 100644
--- a/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/phy_10gbase_r_48/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/ip_arria10_e2sg_phy_10gbase_r_48.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_phy_10gbase_r_48/ip_arria10_e2sg_phy_10gbase_r_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
index d3104e52cf..1a3ce1dc14 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk125/sim"
vcom "$IP_DIR/ip_arria10_e2sg_pll_clk125.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
index 44ddc0d42f..7d067c8f00 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk125/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk125/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk125/ip_arria10_e2sg_pll_clk125.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk125/ip_arria10_e2sg_pll_clk125.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
index ef4a13259c..935e742e07 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
@@ -29,5 +29,5 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk200/sim"
vcom "$IP_DIR/ip_arria10_e2sg_pll_clk200.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
index b51d69c36e..f94c62b25f 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk200/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk200/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk200/ip_arria10_e2sg_pll_clk200.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk200/ip_arria10_e2sg_pll_clk200.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
index 284b7227b3..bfa6416fdc 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_clk25/sim"
vcom "$IP_DIR/ip_arria10_e2sg_pll_clk25.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
index b4643a3f39..46fb9069c1 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_clk25/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/pll_clk25/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk25/ip_arria10_e2sg_pll_clk25.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_clk25/ip_arria10_e2sg_pll_clk25.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
index 2b7ee9fed6..99a216a6d7 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/sim"
vcom "$IP_DIR/ip_arria10_e2sg_pll_xgmii_mac_clocks.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
index 4c9dbb43ed..dfe5343695 100644
--- a/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/pll_xgmii_mac_clocks/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/ip_arria10_e2sg_pll_xgmii_mac_clocks.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_pll_xgmii_mac_clocks/ip_arria10_e2sg_pll_xgmii_mac_clocks.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/ram/README.txt b/libraries/technology/ip_arria10_e2sg/ram/README.txt
index 24ad4ab94e..bb10b06047 100755
--- a/libraries/technology/ip_arria10_e2sg/ram/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ram
Contents:
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
index f7bf08e5ec..8734d79939 100644
--- a/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_temp_sense/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_temp_sense/sim"
vmap altera_temp_sense_1910 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
index 346ed99c79..d60dcd8cb3 100644
--- a/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/temp_sense/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
#modelsim_compile_ip_files =
-# $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
+# $HDL_WORK/libraries/technology/ip_arria10_e2sg/temp_sense/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_temp_sense/ip_arria10_e2sg_temp_sense.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_temp_sense/ip_arria10_e2sg_temp_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
index fb04e579cf..cff9d462dd 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/sim"
vcom "$IP_DIR/ip_arria10_e2sg_transceiver_pll_10g.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
index 3883ef2edc..da176b5e2d 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_pll_10g/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/ip_arria10_e2sg_transceiver_pll_10g.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_pll_10g/ip_arria10_e2sg_transceiver_pll_10g.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
index acd0d01bea..f7b9790eb8 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/sim"
vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_1.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
index 6d04b9ceda..afd333910f 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_1/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/ip_arria10_e2sg_transceiver_reset_controller_1.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_1/ip_arria10_e2sg_transceiver_reset_controller_1.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
index e5371e0872..07b0a76b7a 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/sim"
vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_12.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
index de8a07ce6b..729d6026b9 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_12/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/ip_arria10_e2sg_transceiver_reset_controller_12.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_12/ip_arria10_e2sg_transceiver_reset_controller_12.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
index 5bbfb9dc8a..a09ecb238f 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/sim"
vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_24.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
index 1769ca01f5..a51aa93ac3 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_24/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/ip_arria10_e2sg_transceiver_reset_controller_24.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_24/ip_arria10_e2sg_transceiver_reset_controller_24.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
index aebd7ffc43..dc4fd31164 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/sim"
vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_3.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
index a2612ca5c3..9bb94ac6eb 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_3/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/ip_arria10_e2sg_transceiver_reset_controller_3.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_3/ip_arria10_e2sg_transceiver_reset_controller_3.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
index a0dddbff50..0091266d77 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/sim"
vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_4.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
index 2854213ec4..a54de5d847 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_4/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/ip_arria10_e2sg_transceiver_reset_controller_4.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_4/ip_arria10_e2sg_transceiver_reset_controller_4.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
index bb2f21d04e..c3771cd87b 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/sim"
vcom "$IP_DIR/ip_arria10_e2sg_transceiver_reset_controller_48.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
index 4a07513526..0e53b9ead4 100644
--- a/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/hdllib.cfg
@@ -11,12 +11,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/transceiver_reset_controller_48/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/ip_arria10_e2sg_transceiver_reset_controller_48.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_transceiver_reset_controller_48/ip_arria10_e2sg_transceiver_reset_controller_48.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt
index fa105db173..8b20223537 100755
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
-For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
index 72131625fd..5d270f7373 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/sim"
vcom "$IP_DIR/ip_arria10_e2sg_tse_sgmii_gx.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
index e507db9acb..cd126f4a8e 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/ip_arria10_e2sg_tse_sgmii_gx.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_gx/ip_arria10_e2sg_tse_sgmii_gx.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt
index efe749e3a0..2272417d95 100755
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
-See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
index ec4f247a9c..0da01d1c74 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
@@ -29,6 +29,6 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/sim"
vcom "$IP_DIR/ip_arria10_e2sg_tse_sgmii_lvds.vhd"
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
index 25bd4f4555..22fcc1b2b1 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/hdllib.cfg
@@ -13,12 +13,12 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/ip_arria10_e2sg_tse_sgmii_lvds.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_tse_sgmii_lvds/ip_arria10_e2sg_tse_sgmii_lvds.qip
[generate_ip_libs]
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
index 1b8ecbf3fa..138997c714 100644
--- a/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
@@ -29,7 +29,7 @@
#vlib ./work/ ;# Assume library work already exist
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_voltage_sense/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e2sg_voltage_sense/sim"
vmap ip_arria10_e2sg_voltage_sense ./work/
vmap altera_voltage_sensor_1910 ./work/
diff --git a/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
index 6414fcd8bc..c8da4f7b01 100644
--- a/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e2sg/voltage_sense/hdllib.cfg
@@ -12,12 +12,12 @@ test_bench_files =
[modelsim_project_file]
# There is no simulation model for the FPGA voltage sensor IP
#modelsim_compile_ip_files =
-# $RADIOHDL_WORK/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
+# $HDL_WORK/libraries/technology/ip_arria10_e2sg/voltage_sense/compile_ip.tcl
[quartus_project_file]
quartus_qip_files =
- $RADIOHDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_voltage_sense/ip_arria10_e2sg_voltage_sense.qip
+ $HDL_BUILD_DIR/<buildset_name>/qsys-generate/ip_arria10_e2sg_voltage_sense/ip_arria10_e2sg_voltage_sense.qip
[generate_ip_libs]
qsys-generate_ip_files =
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
index bf8cd80c93..7ae5ccdb01 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
index 109d6d33f6..79113b1143 100644
--- a/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/clkbuf_global/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/clkbuf_global/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
index c9a33bbdfc..2e863c2d4b 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/complex_mult
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/complex_mult
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
index 9d3d778095..57832897c9 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
index a9a34dbda0..338c4d6556 100644
--- a/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/complex_mult/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/complex_mult/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/README.txt b/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
index 1823e822ff..7ea3cfffa4 100755
--- a/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ddio
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ddio
Contents:
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
index bf52569332..eaf469f3cd 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
@@ -26,7 +26,7 @@ set IPMODEL "SIM";
if {$IPMODEL=="PHY"} {
# This file is based on Qsys-generated file msim_setup.tcl.
- set IP_DIR "$env(RADIOHDL_BUILD_DIR)/"
+ set IP_DIR "$env(HDL_BUILD_DIR)/"
#vlib ./work/ ;# Assume library work already exists
vmap ip_arria10_e3sge3_ddio_in_1_altera_gpio_core_151 ./work/
@@ -52,7 +52,7 @@ if {$IPMODEL=="PHY"} {
} else {
# This file uses a behavioral model because the PHY model does not compile OK, see README.txt.
- set SIM_DIR "$env(RADIOHDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/sim/"
+ set SIM_DIR "$env(HDL_WORK)/libraries/technology/ip_arria10_e3sge3/ddio/sim/"
vcom "$SIM_DIR/ip_arria10_e3sge3_ddio_in_1.vhd"
vcom "$SIM_DIR/ip_arria10_e3sge3_ddio_out_1.vhd"
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
index 5c041edb86..b454aeb4e3 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddio/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
index e62b5e5b0e..f9daedf909 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
index ffac688997..960d695d93 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
index dd9a5269ec..5578d5083b 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_1600/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
index 5af5444873..4958df3351 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
index c7dc9753f6..9ee3836145 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
index e973cfc298..58da6ad396 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
index 9235dd757d..f1b453f200 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
index 50bcddb253..04c2a8b4be 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
index f8c58abd73..a2707c8733 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_1600/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
index 6ab71a395b..ce6a73617c 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
index 7017bd1680..aae9b7d9c1 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Qsys-generated file generated/sim/mentor/msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
index 61b0187261..3cab8b771d 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/ddr4_8g_2400/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
index 6db25b6412..bcf8b55de2 100755
--- a/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/fifo
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/fifo
Contents:
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
index bdfa521c2e..dca4f15724 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
vmap ip_arria10_e3sge3_asmi_parallel_altera_asmi_parallel_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
index 8158007cdb..47aa7b1f73 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/asmi_parallel/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
index 3ce459025c..74015b629d 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_core_151 ./work/
vmap ip_arria10_e3sge3_remote_update_altera_remote_update_151 ./work/
diff --git a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
index d86f360f53..81a791fca2 100644
--- a/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/flash/remote_update/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/flash/remote_update/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
index 644fcc2174..7e094e9376 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
index 3206621e21..a943ad1b82 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
index c74c228740..c0daa81c16 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
index 8d98ad13a4..16bc3c0bb0 100644
--- a/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/fractional_pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
index c775402d02..0f920fa60e 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/mac_10g
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/mac_10g
1) Porting
2) IP component
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
index 652e857266..5567b55fb3 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
@@ -26,8 +26,8 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
-set IP_TBDIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
+set IP_TBDIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
index 2395b80019..73453ccd6f 100644
--- a/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/mac_10g/hdllib.cfg
@@ -9,12 +9,12 @@ synth_files =
test_bench_files =
# The generated testbench is listed here to create a simulation configuration for it. However
# the tb is commented because it is not useful, see generate_ip.sh.
- #$RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
+ #$HDL_BUILD_DIR/sim/ip_arria10_e3sge3_mac_10g_tb.vhd
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/mac_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
index f4812de719..9f2c5442d7 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/compile_ip.tcl
@@ -25,7 +25,7 @@
# - vmap for the IP specific libraries and compile all IP source files into those libraries similar as in the msim_setup.tcl
# - replace QSYS_SIMDIR by IP_DIR
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
index bac46a3025..e27cf86d7f 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
index 8e7bc5b458..1666045e3f 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
index 845c5bc4dc..4d2d833dae 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
index 1f8b843ee0..af90b2ceab 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
index 52b235c6fc..26ba984cb5 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
index 189f755402..eca36fd33d 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
index a1a50b1517..76743709b4 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
index 16bfd7165f..83a8521a6e 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
index 55c73ea9af..f80ddb5a8f 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
index 7c697c6572..110de8fc61 100644
--- a/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/phy_10gbase_r_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
index 0f450fb1fb..cdad30ae36 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
index ed9baef7c2..125973f6df 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk125/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk125/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
index 4596b44c78..1e38e5900f 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
index ca6a0c6d8b..0ef6b5812b 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk200/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk200/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
index 6b08a6749e..fed8a5ff9a 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
index 77d805a510..935fac281b 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_clk25/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_clk25/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
index b165f8ec11..10417d22ca 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
index bb1bcd9a4f..dcdf033830 100644
--- a/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/pll_xgmii_mac_clocks/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/README.txt b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
index 24ad4ab94e..bb10b06047 100755
--- a/libraries/technology/ip_arria10_e3sge3/ram/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/ram/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/ram
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/ram
Contents:
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
index 5453478c58..350a3674c8 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
index 8f96a5f7bb..d843b8899a 100644
--- a/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/temp_sense/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
#modelsim_compile_ip_files =
-# $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
+# $HDL_WORK/libraries/technology/ip_arria10_e3sge3/temp_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
index fb2a92dad8..e16ab1bb84 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
index afd34643a6..c989e42aca 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_pll_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
index 54b0b19176..824d03bc0c 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
index f6fbacfad7..8f02442286 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_1/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
index ad26deea93..b674c73aa8 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
index a0f8d7cfba..88b05a011d 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_12/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
index a1afcf2942..d9cbccb139 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
index a1b6720a80..b6a376782f 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_24/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
index fb291b27e4..f2d0fa88e7 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
index 79a61988aa..9ce9710164 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_4/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
index 4141448189..84ad7eb848 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
index fddd592bd0..9ac085cabd 100644
--- a/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/transceiver_reset_controller_48/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
index fa105db173..8b20223537 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/README.txt
@@ -1,8 +1,8 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
+README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_gx
The ip_arria10_tse_sgmii_gx IP was ported to Quartus 14.0a10 for Arria10 by creating it in Qsys using the same parameter settings as the ip_arria10_tse_sgmii_lvds, but with GX IO.
The tb_ip_arria10_tse_sgmii_gx.vhd verifies the DUT and simulates OK.
-For more information see: $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
+For more information see: $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds/README.txt
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
index 124ced04c4..216ad6395e 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
index 9745670627..b914d37c02 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
index efe749e3a0..2272417d95 100755
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/README.txt
@@ -1,4 +1,4 @@
-README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
+README.txt for $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds
-See README.txt for $RADIOHDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
+See README.txt for $HDL_WORK/libraries/technology/ip_arria10/tse_sgmii_lvds
\ No newline at end of file
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
index f6ae1988b3..add9457301 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
@@ -26,7 +26,7 @@
# - hdllib.cfg: add this compile_ip.tcl to the modelsim_compile_ip_files key in the hdllib.cfg
# - hdllib.cfg: the values for modelsim_search_libraries key in the hdllib.cfg follow from altera libraries vmap section in the msim_setup.tcl
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
index 1f2692dc30..48b8e5d73d 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
index 2e88d7082a..090df9c5c9 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
@@ -26,7 +26,7 @@
# - replace QSYS_SIMDIR by IP_DIR
# - if the testbench is also generated with QSYS then only the IP_TBDIR files are needed, because these also contain the source files.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/sim"
#vlib ./work/ ;# Assume library work already exists
diff --git a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
index 77801114c9..96e7557c6b 100644
--- a/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
+++ b/libraries/technology/ip_arria10_e3sge3/voltage_sense/hdllib.cfg
@@ -12,7 +12,7 @@ test_bench_files =
[modelsim_project_file]
# There is no simulation model for the FPGA voltage sensor IP
#modelsim_compile_ip_files =
-# $RADIOHDL_WORK/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
+# $HDL_WORK/libraries/technology/ip_arria10_e3sge3/voltage_sense/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
index a2129d9a99..f3d535487c 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
@@ -23,7 +23,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
# Get the memory model for the uphy_4g_* from the ip_stratixiv_ddr3_uphy_4g_800_master example design
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_example_design"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
index 4b428db963..d8233db8ea 100644
--- a/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_mem_model/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_mem_model/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
index 0cd94954d8..0cba85661d 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
index d73de176a4..c62e33e654 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_16g_dual_rank_800_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
index 56142bcee0..098694698b 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_16g_dual_rank_800/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
index 182467d01b..0130afea23 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
index f3f0232211..aae001963a 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
index adec7b0329..7a6d61ba17 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
index b248f5b52c..100507af6a 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
index 16afa27153..96244d1526 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
index 8391e40fd9..84368ca1a7 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/hdllib.cfg
@@ -11,7 +11,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_slave/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
index 3941d3de8c..84678948ce 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
index 0e72fc7b53..6a06571581 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
index e59e8b5ca0..b1ea4716a9 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_master/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
index 59118cab74..ca5ef73e86 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
index 3f69d05466..755278c849 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
@@ -22,7 +22,7 @@
# This file is based on Megawizard-generated file msim_setup.tcl.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave_sim"
# Copy ROM/RAM files to simulation directory
if {[file isdirectory $IP_DIR]} {
diff --git a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
index 806cd417be..c2bc27298a 100644
--- a/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/hdllib.cfg
@@ -11,8 +11,8 @@ test_bench_files =
[modelsim_project_file]
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/ddr3_uphy_4g_single_rank_800_slave/copy_hex_files.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/flash/hdllib.cfg b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
index 31d0dceb88..a6abdf612b 100644
--- a/libraries/technology/ip_stratixiv/flash/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/flash/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
[modelsim_project_file]
modelsim_copy_files =
- $RADIOHDL_WORK/libraries/external/numonyx_m25p128/NU_M25P128_V10/sim/memory_file .
+ $HDL_WORK/libraries/external/numonyx_m25p128/NU_M25P128_V10/sim/memory_file .
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
index 1a23512475..8133ccc7f4 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
@@ -24,7 +24,7 @@
# file msim_setup.tcl.
# tr_xaui is the first module I did this for.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_mac_10g_sim"
#vlib ./work/ ;# Assume library work already exists
#vmap work ./work/
diff --git a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
index 47e15241a4..6ac6b58969 100644
--- a/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/mac_10g/hdllib.cfg
@@ -13,7 +13,7 @@ test_bench_files =
modelsim_copy_files =
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/mac_10g/compile_ip.tcl
[quartus_project_file]
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
index 72ba643281..3318814203 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
@@ -27,7 +27,7 @@
# correct compile order).
# EK: The model files in phy_xaui_0_sim/ are suitable for all hard xaui IP variants.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_0_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
index fb8eca101f..7e223040ac 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+++ b/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
@@ -27,7 +27,7 @@
# correct compile order). Bonus of this is also that there will be no errors
# when making all_mod without having run the XAUI megawizard first.
-set IP_DIR "$env(RADIOHDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
+set IP_DIR "$env(HDL_BUILD_DIR)/unb1/qmegawiz/ip_stratixiv_phy_xaui_soft_sim"
#vlib ./work/ ;# EK: Assume library work already exists
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
index ac4ee7014d..f8e6880212 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
+++ b/libraries/technology/ip_stratixiv/phy_xaui/hdllib.cfg
@@ -21,8 +21,8 @@ modelsim_copy_files =
wave_tb_ip_stratixiv_phy_xaui_ppm.do .
modelsim_compile_ip_files =
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
- $RADIOHDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip.tcl
+ $HDL_WORK/libraries/technology/ip_stratixiv/phy_xaui/compile_ip_soft.tcl
[quartus_project_file]
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index 2455289038..3ecd647ba5 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -52,7 +52,7 @@ PACKAGE tech_mac_10g_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Copied from entity $RADIOHDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
+ -- Copied from entity $HDL_BUILD_DIR/ip_stratixiv_mac_10g_sim/ip_stratixiv_mac_10g.vhd
COMPONENT ip_stratixiv_mac_10g IS
PORT (
csr_clk_clk : in std_logic := '0'; -- csr_clk.clk
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index ec3f497a8e..6d568f4569 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -31,7 +31,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_stratixiv
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_lvds/ip_stratixiv_tse_sgmii_lvds.vhd
COMPONENT ip_stratixiv_tse_sgmii_lvds IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -78,7 +78,7 @@ PACKAGE tech_tse_component_pkg IS
);
END COMPONENT;
- -- Copied from $RADIOHDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx.vhd
+ -- Copied from $HDL_WORK/libraries/technology/ip_stratixiv/tse_sgmii_gx/ip_stratixiv_tse_sgmii_gx.vhd
COMPONENT ip_stratixiv_tse_sgmii_gx IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
@@ -147,7 +147,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_tse_sgmii_lvds IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -198,7 +198,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
COMPONENT ip_arria10_tse_sgmii_gx IS
PORT (
clk : in std_logic := '0'; -- control_port_clock_connection.clk
@@ -265,7 +265,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -316,7 +316,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e3sge3_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -383,7 +383,7 @@ PACKAGE tech_tse_component_pkg IS
-- ip_arria10_e1sg
------------------------------------------------------------------------------
- -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_lvds.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_lvds IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
@@ -434,7 +434,7 @@ PACKAGE tech_tse_component_pkg IS
END COMPONENT;
- -- Copied from $RADIOHDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
+ -- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
COMPONENT ip_arria10_e1sg_tse_sgmii_gx IS
PORT (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
--
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