diff --git a/libraries/technology/eth_10g/hdllib.cfg b/libraries/technology/eth_10g/hdllib.cfg
index 74cf4140bbd2d4975e0b8943b99999965133227a..d3653813d89d74ccc4e11a449eb79a6f742684b7 100644
--- a/libraries/technology/eth_10g/hdllib.cfg
+++ b/libraries/technology/eth_10g/hdllib.cfg
@@ -1,13 +1,13 @@
hdl_lib_name = tech_eth_10g
hdl_library_clause_name = tech_eth_10g_lib
-hdl_lib_uses = technology tech_pll tech_mac_10g tech_10gbase_r common dp
+hdl_lib_uses = technology tech_pll tech_mac_10g tech_10gbase_r tech_xaui common dp
hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
synth_files =
- #tech_eth_10g_stratixiv.vhd
+ tech_eth_10g_stratixiv.vhd
tech_eth_10g_arria10.vhd
tech_eth_10g.vhd
@@ -16,9 +16,5 @@ test_bench_files =
tb_tech_eth_10g_ppm.vhd
modelsim_search_libraries =
- altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
- altera lpm sgate altera_mf altera_lnsim twentynm twentynm_hssi twentynm_hip
-
-modelsim_copy_files =
- #wave_tb_tech_eth_10gbase_r.do .
-
\ No newline at end of file
+ altera_ver lpm_ver sgate_ver altera_mf_ver altera_lnsim_ver stratixiv_ver stratixiv_hssi_ver stratixiv_pcie_hip_ver twentynm_ver twentynm_hssi_ver twentynm_hip_ver
+ altera lpm sgate altera_mf altera_lnsim stratixiv stratixiv_hssi stratixiv_pcie_hip twentynm twentynm_hssi twentynm_hip
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
index f032d16d45d26db1c1d4a78933dfe40729f05316..bd414709a93247e6aaa06fa7dc1c1c5bf9be423b 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
@@ -47,15 +47,20 @@ ENTITY tb_tech_eth_10g IS
-- Test bench control parameters
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_tech_pll_clk_644_period : TIME := tech_pll_clk_644_period;
+ g_clk_644_period : TIME := tech_pll_clk_644_period;
+ g_clk_156_period : TIME := 6.4 ns;
g_data_type : NATURAL := c_tb_tech_mac_10g_data_type_symbols;
g_verify_link_recovery : BOOLEAN := TRUE;
g_link_status_check : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
- g_use_rx_serial_in : BOOLEAN := FALSE
+ g_use_serial_rx_in : BOOLEAN := FALSE
);
PORT (
- tx_serial_out : OUT STD_LOGIC;
- rx_serial_in : IN STD_LOGIC
+ -- PHY 10gbase_r
+ serial_tx_out : OUT STD_LOGIC; -- 1 lane
+ serial_rx_in : IN STD_LOGIC;
+ -- PHY XAUI
+ xaui_tx_out : OUT STD_LOGIC_VECTOR(c_nof_xaui_lanes-1 DOWNTO 0); -- 4 lanes
+ xaui_rx_in : IN STD_LOGIC_VECTOR(c_nof_xaui_lanes-1 DOWNTO 0)
);
END tb_tech_eth_10g;
@@ -64,7 +69,7 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
CONSTANT phy_delay : TIME := 0 ns;
- CONSTANT c_phy_loopback : BOOLEAN := NOT g_use_rx_serial_in;
+ CONSTANT c_phy_loopback : BOOLEAN := NOT g_use_serial_rx_in;
CONSTANT c_st_loopback : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
CONSTANT c_rl : NATURAL := 1;
CONSTANT c_nof_tx_not_valid : NATURAL := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
@@ -94,11 +99,30 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
SIGNAL tb_end : STD_LOGIC := '0';
SIGNAL mm_clk : STD_LOGIC := '0'; -- memory-mapped bus clock
SIGNAL mm_rst : STD_LOGIC; -- reset synchronous with mm_clk
- SIGNAL tr_ref_clk_644 : STD_LOGIC := '1'; -- 10base_r reference clock
+
+ -- . 10base_r clocks
+ SIGNAL tr_ref_clk_644 : STD_LOGIC := '1';
SIGNAL clk_312 : STD_LOGIC;
SIGNAL clk_156 : STD_LOGIC;
SIGNAL rst_156 : STD_LOGIC;
+ -- . XAUI clocks
+ SIGNAL tr_ref_clk_156 : STD_LOGIC := '1';
+ SIGNAL tx_rst_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL rx_clk_arr_out : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL rx_rst_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+ -- . Test bench top level clocks
+ SIGNAL tb_ref_clk_644 : STD_LOGIC;
+ SIGNAL tb_ref_clk_156 : STD_LOGIC;
+ SIGNAL tb_clk_312 : STD_LOGIC;
+ SIGNAL tb_clk_156 : STD_LOGIC;
+ SIGNAL tb_rst_156 : STD_LOGIC;
+ SIGNAL tb_tx_clk : STD_LOGIC;
+ SIGNAL tb_tx_rst : STD_LOGIC;
+ SIGNAL tb_rx_clk : STD_LOGIC;
+ SIGNAL tb_rx_rst : STD_LOGIC;
+
-- 10G MAC control interface
SIGNAL mm_init : STD_LOGIC := '1';
SIGNAL mm_mosi : t_mem_mosi;
@@ -123,12 +147,17 @@ ARCHITECTURE tb OF tb_tech_eth_10g IS
SIGNAL rx_sosi_arr : t_dp_sosi_arr(0 DOWNTO 0);
SIGNAL rx_sosi_data : STD_LOGIC_VECTOR(c_tech_mac_10g_data_w-1 DOWNTO 0); -- 64 bit
- -- 10G PHY serial interface
- SIGNAL tx_serial_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
- SIGNAL rx_serial_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ -- PHY serial IO
+ -- . 10GBASE-R (single lane)
+ SIGNAL serial_tx_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL serial_rx_arr : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ -- . XAUI (four lanes)
+ SIGNAL xaui_tx_arr : t_xaui_arr(0 DOWNTO 0);
+ SIGNAL xaui_rx_arr : t_xaui_arr(0 DOWNTO 0);
+
-- Model a serial link fault
- SIGNAL link_fault : STD_LOGIC;
+ SIGNAL link_fault : STD_LOGIC;
-- Verification
SIGNAL tx_pkt_cnt : NATURAL := 0;
@@ -173,7 +202,7 @@ BEGIN
PORT MAP (
mm_init => mm_init,
total_header => total_header,
- clk_156 => clk_156,
+ clk_156 => tb_tx_clk,
tx_siso => tx_siso,
tx_sosi => tx_sosi,
link_fault => link_fault,
@@ -187,7 +216,8 @@ BEGIN
rx_siso_arr(0) <= rx_siso;
rx_sosi <= rx_sosi_arr(0);
- tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_tech_pll_clk_644_period/2;
+ tr_ref_clk_644 <= NOT tr_ref_clk_644 AFTER g_clk_644_period/2;
+ tr_ref_clk_156 <= NOT tr_ref_clk_156 AFTER g_clk_156_period/2;
pll : ENTITY tech_pll_lib.tech_pll_xgmii_mac_clocks
GENERIC MAP (
@@ -200,7 +230,25 @@ BEGIN
rst_156 => rst_156,
rst_312 => OPEN
);
+
+ -- Connect the clocks from test bench top level (down such that they have their rising_edge() aligned without any delta-delay)
+ gen_tb_clocks_xaui : IF g_technology=c_tech_stratixiv GENERATE
+ tb_ref_clk_156 <= tr_ref_clk_156;
+ tb_tx_clk <= tr_ref_clk_156;
+ tb_rx_clk <= rx_clk_arr_out(0);
+ tb_tx_rst <= tx_rst_arr(0);
+ tb_rx_rst <= rx_rst_arr(0);
+ END GENERATE;
+ gen_tb_clocks_10gbase_r : IF g_technology=c_tech_arria10 GENERATE
+ tb_ref_clk_644 <= tr_ref_clk_644;
+ tb_clk_312 <= clk_312;
+ tb_clk_156 <= clk_156;
+ tb_rst_156 <= rst_156;
+ tb_tx_clk <= clk_156;
+ tb_rx_clk <= clk_156;
+ END GENERATE;
+
no_dut : IF c_st_loopback=TRUE GENERATE
rx_sosi <= tx_sosi;
tx_siso <= rx_siso;
@@ -218,7 +266,8 @@ BEGIN
)
PORT MAP (
-- Transceiver PLL reference clock
- tr_ref_clk_644 => tr_ref_clk_644,
+ tr_ref_clk_644 => tb_ref_clk_644,
+ tr_ref_clk_156 => tb_ref_clk_156,
-- MM
mm_clk => mm_clk,
@@ -228,37 +277,57 @@ BEGIN
mac_miso => mm_miso,
-- Clocks
- clk_312 => clk_312,
- clk_156 => clk_156, -- 156.25 MHz local reference
- rst_156 => rst_156,
+ -- . 10GBASE-R
+ clk_312 => tb_clk_312,
+ clk_156 => tb_clk_156, -- 156.25 MHz local reference
+ rst_156 => tb_rst_156,
+
+ -- . XAUI
+ tx_clk_arr(0) => tb_tx_clk, -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ tx_rst_arr => tx_rst_arr,
+ rx_clk_arr_out => rx_clk_arr_out,
+ rx_clk_arr_in(0) => tb_rx_clk, -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_rst_arr => rx_rst_arr,
-- ST
- tx_snk_in_arr => tx_sosi_arr, -- 64 bit data @ clk_156
+ tx_snk_in_arr => tx_sosi_arr, -- 64 bit data @ 156 tb_tx_clk
tx_snk_out_arr => tx_siso_arr,
- rx_src_out_arr => rx_sosi_arr, -- 64 bit data @ clk_156
+ rx_src_out_arr => rx_sosi_arr, -- 64 bit data @ 156 tb_rx_clk
rx_src_in_arr => rx_siso_arr,
- -- Serial
- tx_serial_arr => tx_serial_arr,
- rx_serial_arr => rx_serial_arr
+ -- PHY serial IO
+ -- . 10GBASE-R (single lane)
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr,
+
+ -- . XAUI (four lanes)
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr
);
END GENERATE;
+ xaui_rx_arr <= xaui_tx_arr;
+
u_link_connect : ENTITY tech_mac_10g_lib.tb_tech_mac_10g_link_connect
GENERIC MAP (
g_loopback => c_phy_loopback, -- default TRUE for loopback tx to rx, else use FALSE to connect tx-tx, rx-rx between two tb devices
g_link_delay => phy_delay
)
PORT MAP (
- -- Serial layer connect
link_fault => link_fault, -- when '1' then forces rx_serial_arr(0)='0'
- tx_serial_arr => tx_serial_arr,
- rx_serial_arr => rx_serial_arr, -- connects to delayed tx_serial_arr(0) when g_loopback=TRUE else to rx_serial_in
- -- . external connect
- tx_serial_out => tx_serial_out, -- connects to delayed tx_serial_arr(0)
- rx_serial_in => rx_serial_in -- used when g_loopback=FALSE
+ -- 10GBASE-R serial layer connect
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr, -- connects to delayed tx_serial_arr(0) when g_loopback=TRUE else to rx_serial_in
+ serial_tx_out => serial_tx_out, -- connects to delayed tx_serial_arr(0)
+ serial_rx_in => serial_rx_in, -- used when g_loopback=FALSE
+
+ -- XAUI serial layer connect
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr, -- connects to delayed xaui_tx_arr(0) when g_loopback=TRUE else to xaui_rx_in
+ xaui_tx_out => xaui_tx_out, -- connects to delayed xaui_tx_arr(0)
+ xaui_rx_in => xaui_rx_in -- used when g_loopback=FALSE
);
-- Packet receiver
@@ -269,7 +338,7 @@ BEGIN
PORT MAP (
mm_init => mm_init,
total_header => total_header,
- clk_156 => clk_156,
+ clk_156 => tb_rx_clk,
rx_sosi => rx_sosi,
rx_siso => rx_siso,
rx_toggle => rx_toggle
@@ -282,9 +351,9 @@ BEGIN
g_pkt_length_arr => c_pkt_length_arr
)
PORT MAP (
- tx_clk_156 => clk_156,
+ tx_clk_156 => tb_tx_clk,
tx_sosi => tx_sosi,
- rx_clk_156 => clk_156,
+ rx_clk_156 => tb_rx_clk,
rx_sosi => rx_sosi
);
@@ -293,9 +362,9 @@ BEGIN
g_nof_pkt => c_nof_pkt
)
PORT MAP (
- tx_clk_156 => clk_156,
+ tx_clk_156 => tb_tx_clk,
tx_sosi => tx_sosi,
- rx_clk_156 => clk_156,
+ rx_clk_156 => tb_rx_clk,
rx_sosi => rx_sosi,
tx_pkt_cnt => tx_pkt_cnt,
rx_pkt_cnt => rx_pkt_cnt,
@@ -305,8 +374,8 @@ BEGIN
p_tb_end : PROCESS
BEGIN
WAIT UNTIL rx_end='1';
- proc_common_wait_some_cycles(clk_156, 100);
- --proc_common_wait_some_cycles(clk_156, 10000); -- uncomment to simulate somewhat longer without tx packet data
+ proc_common_wait_some_cycles(tb_tx_clk, 100);
+ --proc_common_wait_some_cycles(tb_tx_clk, 10000); -- uncomment to simulate somewhat longer without tx packet data
-- Stop the simulation
tb_end <= '1';
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
index c4f8f1e772c1d1557bfae113d3ce9fe7d0c046bf..7ec75eab8874761711e29f185ad3915711a77653 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
@@ -27,55 +27,74 @@
-- and both tb_tech_eth_10g instances send the same and expect the same.
-- Remarks:
-- . For c_tech_arria10 the test fails when g_nof_10ppm /= 0 (erko, 21 nov 2014)
+-- . For c_tech_stratixiv the test fails when g_nof_10ppm /= 0 (erko, 5 dec 2014)
-- Usage:
-- > as 16
-- > run -all
-LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib;
+LIBRARY IEEE, technology_lib, tech_pll_lib, tech_mac_10g_lib, common_lib;
USE IEEE.std_logic_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
USE tech_pll_lib.tech_pll_component_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
ENTITY tb_tech_eth_10g_ppm IS
-- Test bench control parameters
GENERIC (
g_technology : NATURAL := c_tech_select_default;
- g_nof_10ppm : INTEGER := 0 -- use /= 0 to verify XO ppm offset between two devices
+ g_nof_10ppm : INTEGER := 1 -- use /= 0 to verify XO ppm offset between two devices
);
END tb_tech_eth_10g_ppm;
ARCHITECTURE tb OF tb_tech_eth_10g_ppm IS
- SIGNAL tx_serial_0 : STD_LOGIC;
- SIGNAL tx_serial_1 : STD_LOGIC;
+ -- PHY 10gbase_r
+ SIGNAL serial_tx_0 : STD_LOGIC; -- 1 lane
+ SIGNAL serial_tx_1 : STD_LOGIC;
+ -- PHY XAUI
+ SIGNAL xaui_tx_0 : STD_LOGIC_VECTOR(c_nof_xaui_lanes-1 DOWNTO 0); -- 4 lanes
+ SIGNAL xaui_tx_1 : STD_LOGIC_VECTOR(c_nof_xaui_lanes-1 DOWNTO 0);
+
BEGIN
u_tb_tech_eth_10g_0 : ENTITY work.tb_tech_eth_10g
GENERIC MAP (
g_technology => g_technology,
- g_tech_pll_clk_644_period => tech_pll_clk_644_period,
+ g_clk_644_period => tech_pll_clk_644_period,
+ g_clk_156_period => 6.4 ns,
g_verify_link_recovery => FALSE,
g_link_status_check => "11",
- g_use_rx_serial_in => TRUE
+ g_use_serial_rx_in => TRUE
)
PORT MAP (
- tx_serial_out => tx_serial_0,
- rx_serial_in => tx_serial_1
+ -- PHY 10gbase_r
+ serial_tx_out => serial_tx_0,
+ serial_rx_in => serial_tx_1,
+
+ -- PHY XAUI
+ xaui_tx_out => xaui_tx_0,
+ xaui_rx_in => xaui_tx_1
);
u_tb_tech_eth_10g_1 : ENTITY work.tb_tech_eth_10g
GENERIC MAP (
g_technology => g_technology,
- g_tech_pll_clk_644_period => tech_pll_clk_644_period + tech_pll_clk_644_10ppm * g_nof_10ppm,
+ g_clk_644_period => tech_pll_clk_644_period + tech_pll_clk_644_10ppm * g_nof_10ppm,
+ g_clk_156_period => 6.4 ns + 64 fs * g_nof_10ppm,
g_verify_link_recovery => FALSE,
g_link_status_check => "11",
- g_use_rx_serial_in => TRUE
+ g_use_serial_rx_in => TRUE
)
PORT MAP (
- tx_serial_out => tx_serial_1,
- rx_serial_in => tx_serial_0
+ -- PHY 10gbase_r
+ serial_tx_out => serial_tx_1,
+ serial_rx_in => serial_tx_0,
+
+ -- PHY XAUI
+ xaui_tx_out => xaui_tx_1,
+ xaui_rx_in => xaui_tx_0
);
END tb;
diff --git a/libraries/technology/eth_10g/tech_eth_10g.vhd b/libraries/technology/eth_10g/tech_eth_10g.vhd
index a1c8a87b8c1ba69a4d20f3b2e037061c3e657761..f2037baea1eba75d1b831865ccf0a6688dc2a91b 100644
--- a/libraries/technology/eth_10g/tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g.vhd
@@ -28,8 +28,8 @@
-- . For c_tech_arria10:
-- __________________
-- | |
--- tx_snk --->|tech_ |---> tx_serial
--- rx_src <---|eth_10g_arria10 |<--- rx_serial
+-- tx_snk --->|tech_ |---> serial_tx
+-- rx_src <---|eth_10g_arria10 |<--- serial_rx
-- |________________|
-- |
-- |
@@ -57,42 +57,99 @@ ENTITY tech_eth_10g IS
PORT (
-- Transceiver PLL reference clock
tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
+ tr_ref_clk_156 : IN STD_LOGIC := '0'; -- 156.25 MHz for XAUI
+
+ -- Calibration & reconfig clock
+ cal_rec_clk : IN STD_LOGIC := '0'; -- for XAUI;
+
+ -- Data clocks and reset
+ -- . 10GBASE-R
+ clk_312 : IN STD_LOGIC := '0';
+ clk_156 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
+
+ -- . XAUI
+ tx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0'); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ rx_clk_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ rx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0'); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
-- MM
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
- mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR), aggregated for all g_nof_channels
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR), aggregated for all g_nof_channels
mac_miso : OUT t_mem_miso;
- -- Clocks
- clk_312 : IN STD_LOGIC := '0';
- clk_156 : IN STD_LOGIC := '0';
- rst_156 : IN STD_LOGIC := '0';
+ xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- XAUI control
+ xaui_miso : OUT t_mem_miso;
-- ST
- tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ 156 MHz
tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
- rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ 156 MHz
rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
- -- Serial
- tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0')
+ -- PHY serial IO
+ -- . 10GBASE-R (single lane)
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0');
+
+ -- . XAUI (four lanes)
+ xaui_tx_arr : OUT t_xaui_arr(g_nof_channels-1 DOWNTO 0);
+ xaui_rx_arr : IN t_xaui_arr(g_nof_channels-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'))
);
END tech_eth_10g;
ARCHITECTURE str OF tech_eth_10g IS
-
- -- MAG_10G control status registers
- SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
- SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-
BEGIN
gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+ u0 : ENTITY work.tech_eth_10g_stratixiv
+ GENERIC MAP (
+ g_sim => g_sim,
+ g_nof_channels => g_nof_channels,
+ g_link_status_check => g_link_status_check,
+ g_pre_header_padding => g_pre_header_padding
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 => tr_ref_clk_156,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => cal_rec_clk,
+
+ -- Data clocks
+ tx_clk_arr => tx_clk_arr,
+ tx_rst_arr => tx_rst_arr,
+ rx_clk_arr_out => rx_clk_arr_out,
+ rx_clk_arr_in => rx_clk_arr_in,
+ rx_rst_arr => rx_rst_arr,
+
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
+
+ xaui_mosi => xaui_mosi,
+ xaui_miso => xaui_miso,
+
+ -- ST
+ tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ clk_156
+ tx_snk_out_arr => tx_snk_out_arr,
+
+ rx_src_out_arr => rx_src_out_arr, -- 64 bit data @ clk_156
+ rx_src_in_arr => rx_src_in_arr,
+
+ -- Serial IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr
+ );
END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
@@ -107,17 +164,17 @@ BEGIN
-- Transceiver PLL reference clock
tr_ref_clk_644 => tr_ref_clk_644,
+ -- Data clocks
+ clk_312 => clk_312,
+ clk_156 => clk_156,
+ rst_156 => rst_156,
+
-- MM
mm_clk => mm_clk,
mm_rst => mm_rst,
- mac_mosi_arr => mac_mosi_arr,
- mac_miso_arr => mac_miso_arr,
-
- -- Clocks
- clk_312 => clk_312,
- clk_156 => clk_156,
- rst_156 => rst_156,
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
-- ST
tx_snk_in_arr => tx_snk_in_arr, -- 64 bit data @ clk_156
@@ -127,24 +184,9 @@ BEGIN
rx_src_in_arr => rx_src_in_arr,
-- Serial
- tx_serial_arr => tx_serial_arr,
- rx_serial_arr => rx_serial_arr
+ serial_tx_arr => serial_tx_arr,
+ serial_rx_arr => serial_rx_arr
);
END GENERATE;
- -----------------------------------------------------------------------------
- -- MM bus mux
- -----------------------------------------------------------------------------
- u_common_mem_mux : ENTITY common_lib.common_mem_mux
- GENERIC MAP (
- g_nof_mosi => g_nof_channels,
- g_mult_addr_w => func_tech_mac_10g_csr_addr_w(g_technology)
- )
- PORT MAP (
- mosi => mac_mosi,
- miso => mac_miso,
- mosi_arr => mac_mosi_arr,
- miso_arr => mac_miso_arr
- );
-
END str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
index 7a2601ad45c1485d3e5b2b332f8ccdff3f297452..77e0365058ec4dccda0f4ff3098cc5072790e785 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
@@ -22,17 +22,42 @@
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10
--- Description:
--- XGMII
--- _________ ____________
--- | | | |
--- tx_snk --->|tech_ |-------|tech_ |---> tx_serial
--- rx_src <---|mac_10g| |10gbase_r |<--- rx_serial
--- |_______| |__________|
--- |
--- |
--- mac_mm
+-- Description
+--
+-- The clocks come from an external central fPLL:
--
+-- tx_ref_clk_644 --> fPLL --> clk_312
+-- clk_156, rst_156
+-- Blockdiagram:
+--
+-- 312 156 644
+-- _________ | | | ____________
+-- | | | | | | |
+-- | |<--/ | \-->| |
+-- | |<-----+----->| |
+-- | | | |
+-- | | XGMII | |
+-- tx_snk --->|tech_ |------------>|tech_ |---> serial_tx
+-- rx_src <---|mac_10g|<------------|10gbase_r |<--- serial_rx
+-- | | | |
+-- |_______|--\ /--|__________|
+-- | | |
+-- mac_mm | |
+-- | v
+-- ( v xgmii_tx_ready)
+-- tx_snk_out.xon <--(xgmii_link_status[1:0])
+--
+-- When the xgmii_tx_ready from the 10gbase_r and the xgmii_link_status from
+-- the mac_10g are both be OK then the tx_snk.xon is asserted to allow the
+-- user data transmission.
+-- The tb_tech_eth_10g reveals that xgmii_tx_ready goes high after some power
+-- up time and then remains active independent of link_fault. A link fault
+-- eg. due to rx disconnect is detected by xgmii_link_status:
+-- 0 = OK
+-- 1 = local fault
+-- 2 = remote fault
+-- Hence when the xgmii_link_status is OK then the other side is also OK so
+-- then it is also appropriate to release tx_snk.xon.
LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_10gbase_r_lib, tech_mac_10g_lib;
USE IEEE.STD_LOGIC_1164.ALL;
@@ -54,17 +79,17 @@ ENTITY tech_eth_10g_arria10 IS
-- Transceiver PLL reference clock
tr_ref_clk_644 : IN STD_LOGIC := '0'; -- 644.531250 MHz for 10GBASE-R
+ -- Data clocks
+ clk_312 : IN STD_LOGIC := '0';
+ clk_156 : IN STD_LOGIC := '0';
+ rst_156 : IN STD_LOGIC := '0';
+
-- MM
mm_clk : IN STD_LOGIC;
mm_rst : IN STD_LOGIC;
- mac_mosi_arr : IN t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0); -- MAG_10G (CSR)
- mac_miso_arr : OUT t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
-
- -- Clocks
- clk_312 : IN STD_LOGIC := '0';
- clk_156 : IN STD_LOGIC := '0';
- rst_156 : IN STD_LOGIC := '0';
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
-- ST
tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ clk_156
@@ -74,14 +99,18 @@ ENTITY tech_eth_10g_arria10 IS
rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
-- Serial
- tx_serial_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
- rx_serial_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0) := (OTHERS=>'0')
+ serial_tx_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ serial_rx_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0)
);
END tech_eth_10g_arria10;
ARCHITECTURE str OF tech_eth_10g_arria10 IS
+ -- MAG_10G control status registers
+ SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
+
-- XON control
SIGNAL mac_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
@@ -139,7 +168,7 @@ BEGIN
xgmii_tx_data => xgmii_tx_dc_arr(I),
xgmii_rx_data => xgmii_rx_dc_arr(I)
);
- END GENERATE;
+ END GENERATE;
u_tech_10gbase_r: ENTITY tech_10gbase_r_lib.tech_10gbase_r
GENERIC MAP (
@@ -157,12 +186,28 @@ BEGIN
-- XGMII interface
xgmii_tx_ready_arr => xgmii_tx_ready_arr,
+ xgmii_rx_ready_arr => OPEN,
xgmii_tx_dc_arr => xgmii_tx_dc_arr,
xgmii_rx_dc_arr => xgmii_rx_dc_arr,
-- PHY serial IO
- tx_serial_arr => tx_serial_arr,
- rx_serial_arr => rx_serial_arr
+ tx_serial_arr => serial_tx_arr,
+ rx_serial_arr => serial_rx_arr
);
+ -----------------------------------------------------------------------------
+ -- MM bus mux
+ -----------------------------------------------------------------------------
+ u_common_mem_mux : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_channels,
+ g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_arria10)
+ )
+ PORT MAP (
+ mosi => mac_mosi,
+ miso => mac_miso,
+ mosi_arr => mac_mosi_arr,
+ miso_arr => mac_miso_arr
+ );
+
END str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..318e33204f6e6061d5b56b90ddad03e6b5632fd8
--- /dev/null
+++ b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
@@ -0,0 +1,237 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+
+-- Purpose: Combine mac_10g and xaui for c_tech_stratixiv
+-- Description:
+-- The clocks come from an external central fPLL:
+--
+-- Blockdiagram:
+--
+-- ref
+-- 156 156
+-- _________ | | ____________
+-- | | | | | |
+-- | | | \-->| |
+-- | |<-----+----->| |
+-- | | | |
+-- | | XGMII | |
+-- tx_snk --->|tech_ |------------>|tech_ |---> xaui_tx[3:0]
+-- rx_src <---|mac_10g|<------------|xaui |<--- xaui_rx[3:0]
+-- | | | |
+-- |_______|--\ /--|__________|
+-- | | |
+-- mac_mm | |
+-- | v
+-- ( v xgmii_tx_ready)
+-- tx_snk_out.xon <--(xgmii_link_status[1:0])
+--
+
+LIBRARY IEEE, common_lib, dp_lib, technology_lib, tech_xaui_lib, tech_mac_10g_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_interface_layers_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE tech_mac_10g_lib.tech_mac_10g_component_pkg.ALL;
+
+ENTITY tech_eth_10g_stratixiv IS
+ GENERIC (
+ g_sim : BOOLEAN := FALSE;
+ g_nof_channels : NATURAL := 1;
+ g_link_status_check : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0) := "11";
+ g_pre_header_padding : BOOLEAN := FALSE
+ );
+ PORT (
+ -- Transceiver PLL reference clock
+ tr_ref_clk_156 : IN STD_LOGIC; -- 156.25 MHz for XAUI
+
+ -- Calibration & reconfig clock
+ cal_rec_clk : IN STD_LOGIC;
+
+ -- Data clocks
+ tx_clk_arr : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 156.25 MHz, externally connect tr_ref_clk_156 to tx_clk_arr or connect rx_clk_arr to tx_clk_arr
+ tx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ rx_clk_arr_out : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ rx_clk_arr_in : IN STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- externally connect to rx_clk_arr_out to avoid clock delta-delay
+ rx_rst_arr : OUT STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+
+ -- MM
+ mm_clk : IN STD_LOGIC;
+ mm_rst : IN STD_LOGIC;
+
+ mac_mosi : IN t_mem_mosi; -- MAG_10G (CSR)
+ mac_miso : OUT t_mem_miso;
+
+ xaui_mosi : IN t_mem_mosi := c_mem_mosi_rst; -- XAUI control
+ xaui_miso : OUT t_mem_miso;
+
+ -- ST
+ tx_snk_in_arr : IN t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ 156 MHz tx_clk_arr
+ tx_snk_out_arr : OUT t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ rx_src_out_arr : OUT t_dp_sosi_arr(g_nof_channels-1 DOWNTO 0); -- 64 bit data @ 156 MHz rx_clk_arr_in
+ rx_src_in_arr : IN t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- XAUI serial IO
+ xaui_tx_arr : OUT t_xaui_arr(g_nof_channels-1 DOWNTO 0);
+ xaui_rx_arr : IN t_xaui_arr(g_nof_channels-1 DOWNTO 0)
+ );
+END tech_eth_10g_stratixiv;
+
+
+ARCHITECTURE str OF tech_eth_10g_stratixiv IS
+
+ -- MAG_10G control status registers
+ SIGNAL mac_mosi_arr : t_mem_mosi_arr(g_nof_channels-1 DOWNTO 0);
+ SIGNAL mac_miso_arr : t_mem_miso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- ST
+ SIGNAL i_tx_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+ SIGNAL i_rx_rst_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0);
+
+ SIGNAL txc_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- tx_ready in tx_clk_arr domain, can be used for xon flow control
+ SIGNAL rxc_rx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- rx_ready in rx_clk_arr domain, typically leave not connected
+
+ SIGNAL txc_rx_channelaligned_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- rx_channelaligned in tx_clk_arr domain, from PHY XAUI, indicates
+ -- that all 4 RX channels are aligned when asserted
+
+ -- XON control
+ SIGNAL mac_snk_out_arr : t_dp_siso_arr(g_nof_channels-1 DOWNTO 0);
+
+ -- XGMII
+ SIGNAL xgmii_link_status_arr : t_tech_mac_10g_xgmii_status_arr(g_nof_channels-1 DOWNTO 0); -- 2 bit, from MAC_10g
+ SIGNAL xgmii_tx_ready_arr : STD_LOGIC_VECTOR(g_nof_channels-1 DOWNTO 0); -- 1 bit, from PHY XAUI
+ SIGNAL xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+ SIGNAL xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels-1 DOWNTO 0); -- 72 bit
+
+BEGIN
+
+ -- Clocks and reset
+ tx_rst_arr <= i_tx_rst_arr;
+ rx_rst_arr <= i_rx_rst_arr;
+
+ i_tx_rst_arr <= NOT txc_tx_ready_arr;
+ i_rx_rst_arr <= NOT rxc_rx_ready_arr;
+
+ xgmii_tx_ready_arr <= txc_tx_ready_arr;
+
+ gen_mac : FOR I IN 0 TO g_nof_channels-1 GENERATE
+
+ tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
+
+ p_xon_flow_control : PROCESS(tx_clk_arr)
+ VARIABLE v_xgmii_link_status : STD_LOGIC_VECTOR(c_tech_mac_10g_link_status_w-1 DOWNTO 0);
+ BEGIN
+ IF rising_edge(tx_clk_arr(I)) THEN
+ tx_snk_out_arr(I).xon <= '0';
+ v_xgmii_link_status := xgmii_link_status_arr(I) AND g_link_status_check; -- use mask to check Tx, Rx, both or none.
+ IF xgmii_tx_ready_arr(I)='1' AND v_xgmii_link_status="00" THEN
+ tx_snk_out_arr(I).xon <= '1'; -- XON when Tx PHY is ready and XGMII is ok
+ END IF;
+ END IF;
+ END PROCESS;
+
+ u_tech_mac_10g : ENTITY tech_mac_10g_lib.tech_mac_10g
+ GENERIC MAP (
+ g_technology => c_tech_stratixiv,
+ g_pre_header_padding => g_pre_header_padding
+ )
+ PORT MAP (
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+ csr_mosi => mac_mosi_arr(I),
+ csr_miso => mac_miso_arr(I),
+
+ -- ST
+ tx_clk_156 => tx_clk_arr(I),
+ tx_rst => i_tx_rst_arr(I),
+ tx_snk_in => tx_snk_in_arr(I), -- 64 bit data
+ tx_snk_out => mac_snk_out_arr(I),
+
+ rx_clk_156 => rx_clk_arr_in(I),
+ rx_rst => i_rx_rst_arr(I),
+ rx_src_out => rx_src_out_arr(I), -- 64 bit data
+ rx_src_in => rx_src_in_arr(I),
+
+ -- XGMII
+ xgmii_link_status => xgmii_link_status_arr(I),
+ xgmii_tx_data => xgmii_tx_dc_arr(I),
+ xgmii_rx_data => xgmii_rx_dc_arr(I)
+ );
+ END GENERATE;
+
+ u_tech_xaui: ENTITY tech_xaui_lib.tech_xaui
+ GENERIC MAP (
+ g_technology => c_tech_stratixiv,
+ g_nof_xaui => g_nof_channels -- Up to 3 (hard XAUI only) supported
+ )
+ PORT MAP (
+ -- Transceiver PLL reference clock
+ tr_clk => tr_ref_clk_156,
+
+ -- Calibration & reconfig clock
+ cal_rec_clk => cal_rec_clk,
+
+ -- MM interface
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
+
+ xaui_mosi => xaui_mosi,
+ xaui_miso => xaui_miso,
+
+ -- XGMII interface
+ tx_clk_arr => tx_clk_arr,
+ rx_clk_arr_out => rx_clk_arr_out,
+ rx_clk_arr_in => rx_clk_arr_in,
+
+ txc_tx_ready_arr => txc_tx_ready_arr, -- tx_ready in tx_clk_arr domain, can be used for xon flow control
+ rxc_rx_ready_arr => rxc_rx_ready_arr, -- rx_ready in rx_clk_arr domain, typically leave not connected
+
+ txc_rx_channelaligned_arr => txc_rx_channelaligned_arr, -- rx_channelaligned in tx_clk_arr domain, indicates that all 4 RX channels are aligned when asserted
+
+ xgmii_tx_dc_arr => xgmii_tx_dc_arr,
+ xgmii_rx_dc_arr => xgmii_rx_dc_arr,
+
+ -- XAUI serial IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr
+ );
+
+ -----------------------------------------------------------------------------
+ -- MM bus mux
+ -----------------------------------------------------------------------------
+ u_common_mem_mux : ENTITY common_lib.common_mem_mux
+ GENERIC MAP (
+ g_nof_mosi => g_nof_channels,
+ g_mult_addr_w => func_tech_mac_10g_csr_addr_w(c_tech_stratixiv)
+ )
+ PORT MAP (
+ mosi => mac_mosi,
+ miso => mac_miso,
+ mosi_arr => mac_mosi_arr,
+ miso_arr => mac_miso_arr
+ );
+
+END str;